Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: hisilicon/zip - save capability registers in probe process
Pre-store the valid value of the zip alg support related capability
register in hisi_zip_qm_init(), which will be called by hisi_zip_probe().
It can reduce the number of capability register queries and avoid
obtaining incorrect values in abnormal scenarios, such as reset failed
and the memory space disabled.
Fixes: db700974b69d ("crypto: hisilicon/zip - support zip capability")
Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Zhiqi Song
and committed by
Herbert Xu
2ff0ad84
f1115b00
+60
-13
+60
-13
drivers/crypto/hisilicon/zip/zip_main.c
+60
-13
drivers/crypto/hisilicon/zip/zip_main.c
···
249
249
{ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}
250
250
};
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+
enum zip_pre_store_cap_idx {
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+
ZIP_CORE_NUM_CAP_IDX = 0x0,
254
+
ZIP_CLUSTER_COMP_NUM_CAP_IDX,
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ZIP_CLUSTER_DECOMP_NUM_CAP_IDX,
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+
ZIP_DECOMP_ENABLE_BITMAP_IDX,
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+
ZIP_COMP_ENABLE_BITMAP_IDX,
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+
ZIP_DRV_ALG_BITMAP_IDX,
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ZIP_DEV_ALG_BITMAP_IDX,
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+
};
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+
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+
static const u32 zip_pre_store_caps[] = {
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ZIP_CORE_NUM_CAP,
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+
ZIP_CLUSTER_COMP_NUM_CAP,
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+
ZIP_CLUSTER_DECOMP_NUM_CAP,
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+
ZIP_DECOMP_ENABLE_BITMAP,
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+
ZIP_COMP_ENABLE_BITMAP,
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ZIP_DRV_ALG_BITMAP,
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ZIP_DEV_ALG_BITMAP,
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+
};
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+
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enum {
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HZIP_COMP_CORE0,
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HZIP_COMP_CORE1,
···
463
443
{
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u32 cap_val;
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-
cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver);
446
+
cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val;
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if ((alg & cap_val) == alg)
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return true;
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449
···
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568
}
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569
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/* let's open all compression/decompression cores */
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-
dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
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-
ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver);
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-
comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
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-
ZIP_COMP_ENABLE_BITMAP, qm->cap_ver);
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+
dcomp_bm = qm->cap_tables.dev_cap_table[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val;
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+
comp_bm = qm->cap_tables.dev_cap_table[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val;
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writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);
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/* enable sqc,cqc writeback */
···
816
798
char buf[HZIP_BUF_SIZE];
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int i;
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-
zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);
820
-
zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,
821
-
qm->cap_ver);
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+
zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;
802
+
zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;
822
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823
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for (i = 0; i < zip_core_num; i++) {
824
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if (i < zip_comp_core_num)
···
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u32 zip_core_num;
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int i, j, idx;
961
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962
-
zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);
945
+
zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;
963
946
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debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num,
965
948
sizeof(unsigned int), GFP_KERNEL);
···
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998
hzip_com_dfx_regs[i].name, debug->last_words[i], val);
1016
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}
1017
1000
1018
-
zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);
1019
-
zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,
1020
-
qm->cap_ver);
1001
+
zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val;
1002
+
zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;
1003
+
1021
1004
for (i = 0; i < zip_core_num; i++) {
1022
1005
if (i < zip_comp_core_num)
1023
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scnprintf(buf, sizeof(buf), "Comp_core-%d", i);
···
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1156
return ret;
1174
1157
}
1175
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1159
+
static int zip_pre_store_cap_reg(struct hisi_qm *qm)
1160
+
{
1161
+
struct hisi_qm_cap_record *zip_cap;
1162
+
struct pci_dev *pdev = qm->pdev;
1163
+
size_t i, size;
1164
+
1165
+
size = ARRAY_SIZE(zip_pre_store_caps);
1166
+
zip_cap = devm_kzalloc(&pdev->dev, sizeof(*zip_cap) * size, GFP_KERNEL);
1167
+
if (!zip_cap)
1168
+
return -ENOMEM;
1169
+
1170
+
for (i = 0; i < size; i++) {
1171
+
zip_cap[i].type = zip_pre_store_caps[i];
1172
+
zip_cap[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info,
1173
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zip_pre_store_caps[i], qm->cap_ver);
1174
+
}
1175
+
1176
+
qm->cap_tables.dev_cap_table = zip_cap;
1177
+
1178
+
return 0;
1179
+
}
1180
+
1176
1181
static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1177
1182
{
1178
1183
u64 alg_msk;
···
1233
1194
return ret;
1234
1195
}
1235
1196
1236
-
alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver);
1197
+
/* Fetch and save the value of capability registers */
1198
+
ret = zip_pre_store_cap_reg(qm);
1199
+
if (ret) {
1200
+
pci_err(qm->pdev, "Failed to pre-store capability registers!\n");
1201
+
hisi_qm_uninit(qm);
1202
+
return ret;
1203
+
}
1204
+
1205
+
alg_msk = qm->cap_tables.dev_cap_table[ZIP_DEV_ALG_BITMAP_IDX].cap_val;
1237
1206
ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));
1238
1207
if (ret) {
1239
1208
pci_err(qm->pdev, "Failed to set zip algs!\n");