Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: hisilicon/sec2 - save capability registers in probe process
Pre-store the valid value of the sec alg support related capability
register in sec_qm_init(), which will be called by probe process.
It can reduce the number of capability register queries and avoid
obtaining incorrect values in abnormal scenarios, such as reset
failed and the memory space disabled.
Fixes: 921715b6b782 ("crypto: hisilicon/sec - get algorithm bitmap from registers")
Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Zhiqi Song
and committed by
Herbert Xu
f1115b00
cf8b5156
+55
-5
+7
drivers/crypto/hisilicon/sec2/sec.h
+7
drivers/crypto/hisilicon/sec2/sec.h
···
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SEC_CORE4_ALG_BITMAP_HIGH,
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};
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+
enum sec_cap_reg_record_idx {
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+
SEC_DRV_ALG_BITMAP_LOW_IDX = 0x0,
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+
SEC_DRV_ALG_BITMAP_HIGH_IDX,
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+
SEC_DEV_ALG_BITMAP_LOW_IDX,
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+
SEC_DEV_ALG_BITMAP_HIGH_IDX,
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+
};
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+
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void sec_destroy_qps(struct hisi_qp **qps, int qp_num);
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struct hisi_qp **sec_create_qps(void);
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int sec_register_to_crypto(struct hisi_qm *qm);
+8
-2
drivers/crypto/hisilicon/sec2/sec_crypto.c
+8
-2
drivers/crypto/hisilicon/sec2/sec_crypto.c
···
2547
2547
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2548
int sec_register_to_crypto(struct hisi_qm *qm)
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2549
{
2550
-
u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW);
2550
+
u64 alg_mask;
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int ret = 0;
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+
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+
alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX,
2554
+
SEC_DRV_ALG_BITMAP_LOW_IDX);
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mutex_lock(&sec_algs_lock);
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if (sec_available_devs) {
···
2581
2578
2582
2579
void sec_unregister_from_crypto(struct hisi_qm *qm)
2583
2580
{
2584
-
u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW);
2581
+
u64 alg_mask;
2582
+
2583
+
alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX,
2584
+
SEC_DRV_ALG_BITMAP_LOW_IDX);
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mutex_lock(&sec_algs_lock);
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if (--sec_available_devs)
+40
-3
drivers/crypto/hisilicon/sec2/sec_main.c
+40
-3
drivers/crypto/hisilicon/sec2/sec_main.c
···
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{SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
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};
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+
static const u32 sec_pre_store_caps[] = {
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SEC_DRV_ALG_BITMAP_LOW,
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SEC_DRV_ALG_BITMAP_HIGH,
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SEC_DEV_ALG_BITMAP_LOW,
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SEC_DEV_ALG_BITMAP_HIGH,
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+
};
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+
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static const struct qm_dev_alg sec_dev_algs[] = { {
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.alg_msk = SEC_CIPHER_BITMAP,
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.alg = "cipher\n",
···
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{
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u32 cap_val_h, cap_val_l;
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-
cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver);
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-
cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver);
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+
cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val;
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+
cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val;
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return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;
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}
···
1078
1071
return ret;
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}
1080
1073
1074
+
static int sec_pre_store_cap_reg(struct hisi_qm *qm)
1075
+
{
1076
+
struct hisi_qm_cap_record *sec_cap;
1077
+
struct pci_dev *pdev = qm->pdev;
1078
+
size_t i, size;
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+
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+
size = ARRAY_SIZE(sec_pre_store_caps);
1081
+
sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL);
1082
+
if (!sec_cap)
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+
return -ENOMEM;
1084
+
1085
+
for (i = 0; i < size; i++) {
1086
+
sec_cap[i].type = sec_pre_store_caps[i];
1087
+
sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info,
1088
+
sec_pre_store_caps[i], qm->cap_ver);
1089
+
}
1090
+
1091
+
qm->cap_tables.dev_cap_table = sec_cap;
1092
+
1093
+
return 0;
1094
+
}
1095
+
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static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1082
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{
1083
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u64 alg_msk;
···
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1108
return ret;
1138
1109
}
1139
1110
1140
-
alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);
1111
+
/* Fetch and save the value of capability registers */
1112
+
ret = sec_pre_store_cap_reg(qm);
1113
+
if (ret) {
1114
+
pci_err(qm->pdev, "Failed to pre-store capability registers!\n");
1115
+
hisi_qm_uninit(qm);
1116
+
return ret;
1117
+
}
1118
+
1119
+
alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX);
1141
1120
ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));
1142
1121
if (ret) {
1143
1122
pci_err(qm->pdev, "Failed to set sec algs!\n");