Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and 'clk-rate-exclusive' into clk-next
- Increase dev_id len for clkdev lookups
* clk-samsung: (25 commits)
clk: samsung: Add CPU clock support for Exynos850
clk: samsung: Pass mask to wait_until_mux_stable()
clk: samsung: Keep register offsets in chip specific structure
clk: samsung: Keep CPU clock chip specific data in a dedicated struct
clk: samsung: Pass register layout type explicitly to CLK_CPU()
clk: samsung: Pass actual CPU clock registers base to CPU_CLK()
clk: samsung: Group CPU clock functions by chip
clk: samsung: Use single CPU clock notifier callback for all chips
clk: samsung: Reduce params count in exynos_register_cpu_clock()
clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
clk: samsung: Improve clk-cpu.c style
dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
clk: samsung: gs101: add support for cmu_peric1
clk: samsung: gs101: drop extra empty line
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
clk: samsung: exynos850: Propagate SPI IPCLK rate change
clk: samsung: gs101: gpio_peric0_pclk needs to be kept on
clk: samsung: exynos850: Add PDMA clocks
dt-bindings: clock: tesla,fsd: Fix spelling mistake
clk: samsung: gs101: add support for cmu_peric0
...
* clk-imx:
clk: imx: imx8mp: Fix SAI_MCLK_SEL definition
clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev()
clk: imx: composite-8m: Delete two unnecessary initialisations in __imx8m_clk_hw_composite()
clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() after error detection
* clk-rockchip:
clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent
clk: rockchip: rk3588: use linked clock ID for GATE_LINK
clk: rockchip: rk3588: fix indent
clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
dt-bindings: clock: rk3588: drop CLK_NR_CLKS
clk: rockchip: rk3588: fix CLK_NR_CLKS usage
clk: rockchip: rk3568: Add PLL rate for 128MHz
* clk-clkdev:
clkdev: Update clkdev id usage to allow for longer names
* clk-rate-exclusive:
clk: Add a devm variant of clk_rate_exclusive_get()
+1775
-301
+28
-4
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+28
-4
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
···
30
30
- google,gs101-cmu-top
31
31
- google,gs101-cmu-apm
32
32
- google,gs101-cmu-misc
33
+
- google,gs101-cmu-peric0
34
+
- google,gs101-cmu-peric1
33
35
34
36
clocks:
35
37
minItems: 1
36
-
maxItems: 2
38
+
maxItems: 3
37
39
38
40
clock-names:
39
41
minItems: 1
40
-
maxItems: 2
42
+
maxItems: 3
41
43
42
44
"#clock-cells":
43
45
const: 1
···
87
85
88
86
clock-names:
89
87
items:
90
-
- const: dout_cmu_misc_bus
91
-
- const: dout_cmu_misc_sss
88
+
- const: bus
89
+
- const: sss
90
+
91
+
- if:
92
+
properties:
93
+
compatible:
94
+
contains:
95
+
enum:
96
+
- google,gs101-cmu-peric0
97
+
- google,gs101-cmu-peric1
98
+
99
+
then:
100
+
properties:
101
+
clocks:
102
+
items:
103
+
- description: External reference clock (24.576 MHz)
104
+
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
105
+
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
106
+
107
+
clock-names:
108
+
items:
109
+
- const: oscclk
110
+
- const: bus
111
+
- const: ip
92
112
93
113
additionalProperties: false
94
114
+42
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+42
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
···
36
36
- samsung,exynos850-cmu-aud
37
37
- samsung,exynos850-cmu-cmgp
38
38
- samsung,exynos850-cmu-core
39
+
- samsung,exynos850-cmu-cpucl0
40
+
- samsung,exynos850-cmu-cpucl1
39
41
- samsung,exynos850-cmu-dpu
40
42
- samsung,exynos850-cmu-g3d
41
43
- samsung,exynos850-cmu-hsi
···
153
151
- const: dout_core_cci
154
152
- const: dout_core_mmc_embd
155
153
- const: dout_core_sss
154
+
155
+
- if:
156
+
properties:
157
+
compatible:
158
+
contains:
159
+
const: samsung,exynos850-cmu-cpucl0
160
+
161
+
then:
162
+
properties:
163
+
clocks:
164
+
items:
165
+
- description: External reference clock (26 MHz)
166
+
- description: CPUCL0 switch clock (from CMU_TOP)
167
+
- description: CPUCL0 debug clock (from CMU_TOP)
168
+
169
+
clock-names:
170
+
items:
171
+
- const: oscclk
172
+
- const: dout_cpucl0_switch
173
+
- const: dout_cpucl0_dbg
174
+
175
+
- if:
176
+
properties:
177
+
compatible:
178
+
contains:
179
+
const: samsung,exynos850-cmu-cpucl1
180
+
181
+
then:
182
+
properties:
183
+
clocks:
184
+
items:
185
+
- description: External reference clock (26 MHz)
186
+
- description: CPUCL1 switch clock (from CMU_TOP)
187
+
- description: CPUCL1 debug clock (from CMU_TOP)
188
+
189
+
clock-names:
190
+
items:
191
+
- const: oscclk
192
+
- const: dout_cpucl1_switch
193
+
- const: dout_cpucl1_dbg
156
194
157
195
- if:
158
196
properties:
+1
-1
Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
+1
-1
Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
···
12
12
13
13
description: |
14
14
FSD clock controller consist of several clock management unit
15
-
(CMU), which generates clocks for various inteernal SoC blocks.
15
+
(CMU), which generates clocks for various internal SoC blocks.
16
16
The root clock comes from external OSC clock (24 MHz).
17
17
18
18
All available clocks are defined as preprocessor macros in
+19
drivers/clk/clk.c
+19
drivers/clk/clk.c
···
942
942
}
943
943
EXPORT_SYMBOL_GPL(clk_rate_exclusive_get);
944
944
945
+
static void devm_clk_rate_exclusive_put(void *data)
946
+
{
947
+
struct clk *clk = data;
948
+
949
+
clk_rate_exclusive_put(clk);
950
+
}
951
+
952
+
int devm_clk_rate_exclusive_get(struct device *dev, struct clk *clk)
953
+
{
954
+
int ret;
955
+
956
+
ret = clk_rate_exclusive_get(clk);
957
+
if (ret)
958
+
return ret;
959
+
960
+
return devm_add_action_or_reset(dev, devm_clk_rate_exclusive_put, clk);
961
+
}
962
+
EXPORT_SYMBOL_GPL(devm_clk_rate_exclusive_get);
963
+
945
964
static void clk_core_unprepare(struct clk_core *core)
946
965
{
947
966
lockdep_assert_held(&prepare_lock);
+1
-1
drivers/clk/clkdev.c
+1
-1
drivers/clk/clkdev.c
+9
-7
drivers/clk/imx/clk-composite-8m.c
+9
-7
drivers/clk/imx/clk-composite-8m.c
···
212
212
{
213
213
struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
214
214
struct clk_hw *div_hw, *gate_hw = NULL;
215
-
struct clk_divider *div = NULL;
215
+
struct clk_divider *div;
216
216
struct clk_gate *gate = NULL;
217
-
struct clk_mux *mux = NULL;
217
+
struct clk_mux *mux;
218
218
const struct clk_ops *divider_ops;
219
219
const struct clk_ops *mux_ops;
220
220
221
221
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
222
222
if (!mux)
223
-
goto fail;
223
+
return ERR_CAST(hw);
224
224
225
225
mux_hw = &mux->hw;
226
226
mux->reg = reg;
···
230
230
231
231
div = kzalloc(sizeof(*div), GFP_KERNEL);
232
232
if (!div)
233
-
goto fail;
233
+
goto free_mux;
234
234
235
235
div_hw = &div->hw;
236
236
div->reg = reg;
···
260
260
if (!mcore_booted) {
261
261
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
262
262
if (!gate)
263
-
goto fail;
263
+
goto free_div;
264
264
265
265
gate_hw = &gate->hw;
266
266
gate->reg = reg;
···
272
272
mux_hw, mux_ops, div_hw,
273
273
divider_ops, gate_hw, &clk_gate_ops, flags);
274
274
if (IS_ERR(hw))
275
-
goto fail;
275
+
goto free_gate;
276
276
277
277
return hw;
278
278
279
-
fail:
279
+
free_gate:
280
280
kfree(gate);
281
+
free_div:
281
282
kfree(div);
283
+
free_mux:
282
284
kfree(mux);
283
285
return ERR_CAST(hw);
284
286
}
+8
-3
drivers/clk/imx/clk-imx8mp-audiomix.c
+8
-3
drivers/clk/imx/clk-imx8mp-audiomix.c
···
18
18
19
19
#define CLKEN0 0x000
20
20
#define CLKEN1 0x004
21
-
#define SAI_MCLK_SEL(n) (0x300 + 4 * (n)) /* n in 0..5 */
21
+
#define SAI1_MCLK_SEL 0x300
22
+
#define SAI2_MCLK_SEL 0x304
23
+
#define SAI3_MCLK_SEL 0x308
24
+
#define SAI5_MCLK_SEL 0x30C
25
+
#define SAI6_MCLK_SEL 0x310
26
+
#define SAI7_MCLK_SEL 0x314
22
27
#define PDM_SEL 0x318
23
28
#define SAI_PLL_GNRL_CTL 0x400
24
29
···
100
95
IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {}, \
101
96
clk_imx8mp_audiomix_sai##n##_mclk1_parents, \
102
97
ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
103
-
SAI_MCLK_SEL(n), 1, 0 \
98
+
SAI##n##_MCLK_SEL, 1, 0 \
104
99
}, { \
105
100
"sai"__stringify(n)"_mclk2_sel", \
106
101
IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {}, \
107
102
clk_imx8mp_audiomix_sai_mclk2_parents, \
108
103
ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents), \
109
-
SAI_MCLK_SEL(n), 4, 1 \
104
+
SAI##n##_MCLK_SEL, 4, 1 \
110
105
}, { \
111
106
"sai"__stringify(n)"_ipg_cg", \
112
107
IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG, \
+10
-12
drivers/clk/imx/clk-scu.c
+10
-12
drivers/clk/imx/clk-scu.c
···
712
712
}
713
713
714
714
ret = platform_device_add_data(pdev, &clk, sizeof(clk));
715
-
if (ret) {
716
-
platform_device_put(pdev);
717
-
return ERR_PTR(ret);
718
-
}
715
+
if (ret)
716
+
goto put_device;
719
717
720
718
ret = driver_set_override(&pdev->dev, &pdev->driver_override,
721
719
"imx-scu-clk", strlen("imx-scu-clk"));
722
-
if (ret) {
723
-
platform_device_put(pdev);
724
-
return ERR_PTR(ret);
725
-
}
720
+
if (ret)
721
+
goto put_device;
726
722
727
723
ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);
728
724
if (ret)
···
726
730
name, ret);
727
731
728
732
ret = platform_device_add(pdev);
729
-
if (ret) {
730
-
platform_device_put(pdev);
731
-
return ERR_PTR(ret);
732
-
}
733
+
if (ret)
734
+
goto put_device;
733
735
734
736
/* For API backwards compatiblilty, simply return NULL for success */
735
737
return NULL;
738
+
739
+
put_device:
740
+
platform_device_put(pdev);
741
+
return ERR_PTR(ret);
736
742
}
737
743
738
744
void imx_clk_scu_unregister(void)
+3
-3
drivers/clk/rockchip/clk-rk3399.c
+3
-3
drivers/clk/rockchip/clk-rk3399.c
···
597
597
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
598
598
RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
599
599
RK3399_CLKGATE_CON(8), 3, GFLAGS),
600
-
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
600
+
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
601
601
RK3399_CLKSEL_CON(96), 0,
602
602
RK3399_CLKGATE_CON(8), 4, GFLAGS,
603
603
&rk3399_i2s0_fracmux),
···
607
607
COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
608
608
RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
609
609
RK3399_CLKGATE_CON(8), 6, GFLAGS),
610
-
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
610
+
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
611
611
RK3399_CLKSEL_CON(97), 0,
612
612
RK3399_CLKGATE_CON(8), 7, GFLAGS,
613
613
&rk3399_i2s1_fracmux),
···
617
617
COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
618
618
RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
619
619
RK3399_CLKGATE_CON(8), 9, GFLAGS),
620
-
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
620
+
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
621
621
RK3399_CLKSEL_CON(98), 0,
622
622
RK3399_CLKGATE_CON(8), 10, GFLAGS,
623
623
&rk3399_i2s2_fracmux),
+1
drivers/clk/rockchip/clk-rk3568.c
+1
drivers/clk/rockchip/clk-rk3568.c
···
78
78
RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
79
79
RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
80
80
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
81
+
RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),
81
82
RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
82
83
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
83
84
RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),
+28
-27
drivers/clk/rockchip/clk-rk3588.c
+28
-27
drivers/clk/rockchip/clk-rk3588.c
···
29
29
* power, but avoids leaking implementation details into DT or hanging the
30
30
* system.
31
31
*/
32
-
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
32
+
#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
33
33
GATE(_id, cname, pname, f, o, b, gf)
34
34
#define RK3588_LINKED_CLK CLK_IS_CRITICAL
35
35
···
1004
1004
GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
1005
1005
RK3588_CLKGATE_CON(16), 12, GFLAGS),
1006
1006
GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
1007
-
RK3588_CLKGATE_CON(16), 13, GFLAGS),
1007
+
RK3588_CLKGATE_CON(16), 13, GFLAGS),
1008
1008
GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
1009
1009
RK3588_CLKGATE_CON(19), 3, GFLAGS),
1010
1010
GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
···
1851
1851
RK3588_CLKGATE_CON(56), 0, GFLAGS),
1852
1852
GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
1853
1853
RK3588_CLKGATE_CON(56), 1, GFLAGS),
1854
-
GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
1855
-
RK3588_CLKGATE_CON(55), 10, GFLAGS),
1856
1854
COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
1857
1855
RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
1858
1856
RK3588_CLKGATE_CON(56), 11, GFLAGS),
···
1996
1998
RK3588_CLKGATE_CON(60), 9, GFLAGS),
1997
1999
GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
1998
2000
RK3588_CLKGATE_CON(60), 10, GFLAGS),
1999
-
GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
2000
-
RK3588_CLKGATE_CON(59), 12, GFLAGS),
2001
2001
GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
2002
2002
RK3588_CLKGATE_CON(59), 14, GFLAGS),
2003
2003
GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
···
2429
2433
GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
2430
2434
RK3588_CLKGATE_CON(68), 2, GFLAGS),
2431
2435
2432
-
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
2433
-
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
2434
-
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
2435
-
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
2436
-
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
2437
-
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
2438
-
GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
2439
-
GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
2440
-
GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
2441
-
GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
2442
-
GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
2443
-
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
2444
-
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
2445
-
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
2446
-
GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
2447
-
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
2448
-
GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
2449
-
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
2450
-
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
2451
-
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
2436
+
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
2437
+
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
2438
+
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
2439
+
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
2440
+
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
2441
+
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
2442
+
GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
2443
+
GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
2444
+
GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
2445
+
GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
2446
+
GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
2447
+
GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
2448
+
GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
2449
+
GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
2450
+
GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
2451
+
GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
2452
+
GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
2453
+
GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
2454
+
GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
2455
+
GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
2456
+
GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
2457
+
GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
2452
2458
};
2453
2459
2454
2460
static void __init rk3588_clk_init(struct device_node *np)
2455
2461
{
2456
2462
struct rockchip_clk_provider *ctx;
2463
+
unsigned long clk_nr_clks;
2457
2464
void __iomem *reg_base;
2458
2465
2466
+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
2467
+
ARRAY_SIZE(rk3588_clk_branches)) + 1;
2459
2468
reg_base = of_iomap(np, 0);
2460
2469
if (!reg_base) {
2461
2470
pr_err("%s: could not map cru region\n", __func__);
2462
2471
return;
2463
2472
}
2464
2473
2465
-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
2474
+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
2466
2475
if (IS_ERR(ctx)) {
2467
2476
pr_err("%s: rockchip clk init failed\n", __func__);
2468
2477
iounmap(reg_base);
+17
drivers/clk/rockchip/clk.c
+17
drivers/clk/rockchip/clk.c
···
429
429
}
430
430
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
431
431
432
+
unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
433
+
unsigned int nr_clk)
434
+
{
435
+
unsigned long max = 0;
436
+
unsigned int idx;
437
+
438
+
for (idx = 0; idx < nr_clk; idx++, list++) {
439
+
if (list->id > max)
440
+
max = list->id;
441
+
if (list->child && list->child->id > max)
442
+
max = list->id;
443
+
}
444
+
445
+
return max;
446
+
}
447
+
EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
448
+
432
449
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
433
450
struct rockchip_clk_branch *list,
434
451
unsigned int nr_clk)
+2
drivers/clk/rockchip/clk.h
+2
drivers/clk/rockchip/clk.h
···
973
973
void __iomem *base, unsigned long nr_clks);
974
974
void rockchip_clk_of_add_provider(struct device_node *np,
975
975
struct rockchip_clk_provider *ctx);
976
+
unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
977
+
unsigned int nr_clk);
976
978
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
977
979
struct rockchip_clk_branch *list,
978
980
unsigned int nr_clk);
+400
-164
drivers/clk/samsung/clk-cpu.c
+400
-164
drivers/clk/samsung/clk-cpu.c
···
16
16
* of the SoC or supplied after the SoC characterization.
17
17
*
18
18
* The below implementation of the CPU clock allows the rate changes of the CPU
19
-
* clock and the corresponding rate changes of the auxillary clocks of the CPU
19
+
* clock and the corresponding rate changes of the auxiliary clocks of the CPU
20
20
* domain. The platform clock driver provides a clock register configuration
21
21
* for each configurable rate which is then used to program the clock hardware
22
-
* registers to acheive a fast co-oridinated rate change for all the CPU domain
22
+
* registers to achieve a fast coordinated rate change for all the CPU domain
23
23
* clocks.
24
24
*
25
25
* On a rate change request for the CPU clock, the rate change is propagated
26
-
* upto the PLL supplying the clock to the CPU domain clock blocks. While the
26
+
* up to the PLL supplying the clock to the CPU domain clock blocks. While the
27
27
* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
28
28
* alternate clock source. If required, the alternate clock source is divided
29
29
* down in order to keep the output clock rate within the previous OPP limits.
30
-
*/
30
+
*/
31
31
32
+
#include <linux/delay.h>
32
33
#include <linux/errno.h>
33
34
#include <linux/io.h>
34
35
#include <linux/slab.h>
35
36
#include <linux/clk.h>
36
37
#include <linux/clk-provider.h>
38
+
39
+
#include "clk.h"
37
40
#include "clk-cpu.h"
38
41
39
-
#define E4210_SRC_CPU 0x0
40
-
#define E4210_STAT_CPU 0x200
41
-
#define E4210_DIV_CPU0 0x300
42
-
#define E4210_DIV_CPU1 0x304
43
-
#define E4210_DIV_STAT_CPU0 0x400
44
-
#define E4210_DIV_STAT_CPU1 0x404
42
+
struct exynos_cpuclk;
45
43
46
-
#define E5433_MUX_SEL2 0x008
47
-
#define E5433_MUX_STAT2 0x208
48
-
#define E5433_DIV_CPU0 0x400
49
-
#define E5433_DIV_CPU1 0x404
50
-
#define E5433_DIV_STAT_CPU0 0x500
51
-
#define E5433_DIV_STAT_CPU1 0x504
44
+
typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
45
+
struct exynos_cpuclk *cpuclk);
52
46
53
-
#define E4210_DIV0_RATIO0_MASK 0x7
54
-
#define E4210_DIV1_HPM_MASK (0x7 << 4)
55
-
#define E4210_DIV1_COPY_MASK (0x7 << 0)
56
-
#define E4210_MUX_HPM_MASK (1 << 20)
57
-
#define E4210_DIV0_ATB_SHIFT 16
58
-
#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
47
+
/**
48
+
* struct exynos_cpuclk_regs - Register offsets for CPU related clocks
49
+
* @mux_sel: offset of CPU MUX_SEL register (for selecting MUX clock parent)
50
+
* @mux_stat: offset of CPU MUX_STAT register (for checking MUX clock status)
51
+
* @div_cpu0: offset of CPU DIV0 register (for modifying divider values)
52
+
* @div_cpu1: offset of CPU DIV1 register (for modifying divider values)
53
+
* @div_stat_cpu0: offset of CPU DIV0_STAT register (for checking DIV status)
54
+
* @div_stat_cpu1: offset of CPU DIV1_STAT register (for checking DIV status)
55
+
* @mux: offset of MUX register for choosing CPU clock source
56
+
* @divs: offsets of DIV registers (ACLK, ATCLK, PCLKDBG and PERIPHCLK)
57
+
*/
58
+
struct exynos_cpuclk_regs {
59
+
u32 mux_sel;
60
+
u32 mux_stat;
61
+
u32 div_cpu0;
62
+
u32 div_cpu1;
63
+
u32 div_stat_cpu0;
64
+
u32 div_stat_cpu1;
59
65
66
+
u32 mux;
67
+
u32 divs[4];
68
+
};
69
+
70
+
/**
71
+
* struct exynos_cpuclk_chip - Chip specific data for CPU clock
72
+
* @regs: register offsets for CPU related clocks
73
+
* @pre_rate_cb: callback to run before CPU clock rate change
74
+
* @post_rate_cb: callback to run after CPU clock rate change
75
+
*/
76
+
struct exynos_cpuclk_chip {
77
+
const struct exynos_cpuclk_regs *regs;
78
+
exynos_rate_change_fn_t pre_rate_cb;
79
+
exynos_rate_change_fn_t post_rate_cb;
80
+
};
81
+
82
+
/**
83
+
* struct exynos_cpuclk - information about clock supplied to a CPU core
84
+
* @hw: handle between CCF and CPU clock
85
+
* @alt_parent: alternate parent clock to use when switching the speed
86
+
* of the primary parent clock
87
+
* @base: start address of the CPU clock registers block
88
+
* @lock: cpu clock domain register access lock
89
+
* @cfg: cpu clock rate configuration data
90
+
* @num_cfgs: number of array elements in @cfg array
91
+
* @clk_nb: clock notifier registered for changes in clock speed of the
92
+
* primary parent clock
93
+
* @flags: configuration flags for the CPU clock
94
+
* @chip: chip-specific data for the CPU clock
95
+
*
96
+
* This structure holds information required for programming the CPU clock for
97
+
* various clock speeds.
98
+
*/
99
+
struct exynos_cpuclk {
100
+
struct clk_hw hw;
101
+
const struct clk_hw *alt_parent;
102
+
void __iomem *base;
103
+
spinlock_t *lock;
104
+
const struct exynos_cpuclk_cfg_data *cfg;
105
+
const unsigned long num_cfgs;
106
+
struct notifier_block clk_nb;
107
+
unsigned long flags;
108
+
const struct exynos_cpuclk_chip *chip;
109
+
};
110
+
111
+
/* ---- Common code --------------------------------------------------------- */
112
+
113
+
/* Divider stabilization time, msec */
114
+
#define MAX_STAB_TIME 10
60
115
#define MAX_DIV 8
61
-
#define DIV_MASK 7
62
-
#define DIV_MASK_ALL 0xffffffff
63
-
#define MUX_MASK 7
116
+
#define DIV_MASK GENMASK(2, 0)
117
+
#define DIV_MASK_ALL GENMASK(31, 0)
118
+
#define MUX_MASK GENMASK(2, 0)
64
119
65
120
/*
66
121
* Helper function to wait until divider(s) have stabilized after the divider
···
123
68
*/
124
69
static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
125
70
{
126
-
unsigned long timeout = jiffies + msecs_to_jiffies(10);
71
+
unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
127
72
128
73
do {
129
74
if (!(readl(div_reg) & mask))
···
141
86
* value was changed.
142
87
*/
143
88
static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
144
-
unsigned long mux_value)
89
+
unsigned long mask, unsigned long mux_value)
145
90
{
146
-
unsigned long timeout = jiffies + msecs_to_jiffies(10);
91
+
unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
147
92
148
93
do {
149
-
if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
94
+
if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
150
95
return;
151
96
} while (time_before(jiffies, timeout));
152
97
153
-
if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
98
+
if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
154
99
return;
155
100
156
101
pr_err("%s: re-parenting mux timed-out\n", __func__);
157
102
}
158
-
159
-
/* common round rate callback useable for all types of CPU clocks */
160
-
static long exynos_cpuclk_round_rate(struct clk_hw *hw,
161
-
unsigned long drate, unsigned long *prate)
162
-
{
163
-
struct clk_hw *parent = clk_hw_get_parent(hw);
164
-
*prate = clk_hw_round_rate(parent, drate);
165
-
return *prate;
166
-
}
167
-
168
-
/* common recalc rate callback useable for all types of CPU clocks */
169
-
static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
170
-
unsigned long parent_rate)
171
-
{
172
-
/*
173
-
* The CPU clock output (armclk) rate is the same as its parent
174
-
* rate. Although there exist certain dividers inside the CPU
175
-
* clock block that could be used to divide the parent clock,
176
-
* the driver does not make use of them currently, except during
177
-
* frequency transitions.
178
-
*/
179
-
return parent_rate;
180
-
}
181
-
182
-
static const struct clk_ops exynos_cpuclk_clk_ops = {
183
-
.recalc_rate = exynos_cpuclk_recalc_rate,
184
-
.round_rate = exynos_cpuclk_round_rate,
185
-
};
186
103
187
104
/*
188
105
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
189
106
* div and mask contain the divider value and the register bit mask of the
190
107
* dividers to be programmed.
191
108
*/
192
-
static void exynos_set_safe_div(void __iomem *base, unsigned long div,
193
-
unsigned long mask)
109
+
static void exynos_set_safe_div(struct exynos_cpuclk *cpuclk, unsigned long div,
110
+
unsigned long mask)
194
111
{
112
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
113
+
void __iomem *base = cpuclk->base;
195
114
unsigned long div0;
196
115
197
-
div0 = readl(base + E4210_DIV_CPU0);
116
+
div0 = readl(base + regs->div_cpu0);
198
117
div0 = (div0 & ~mask) | (div & mask);
199
-
writel(div0, base + E4210_DIV_CPU0);
200
-
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
118
+
writel(div0, base + regs->div_cpu0);
119
+
wait_until_divider_stable(base + regs->div_stat_cpu0, mask);
201
120
}
121
+
122
+
/* ---- Exynos 3/4/5 -------------------------------------------------------- */
123
+
124
+
#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
125
+
#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
126
+
#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
127
+
#define E4210_MUX_HPM_MASK BIT(20)
128
+
#define E4210_DIV0_ATB_SHIFT 16
129
+
#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
130
+
131
+
static const struct exynos_cpuclk_regs e4210_cpuclk_regs = {
132
+
.mux_sel = 0x200,
133
+
.mux_stat = 0x400,
134
+
.div_cpu0 = 0x500,
135
+
.div_cpu1 = 0x504,
136
+
.div_stat_cpu0 = 0x600,
137
+
.div_stat_cpu1 = 0x604,
138
+
};
202
139
203
140
/* handler for pre-rate change notification from parent clock */
204
141
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
205
-
struct exynos_cpuclk *cpuclk, void __iomem *base)
142
+
struct exynos_cpuclk *cpuclk)
206
143
{
207
144
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
145
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
146
+
void __iomem *base = cpuclk->base;
208
147
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
209
-
unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
210
148
unsigned long div0, div1 = 0, mux_reg;
211
149
unsigned long flags;
212
150
···
220
172
div0 = cfg_data->div0;
221
173
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
222
174
div1 = cfg_data->div1;
223
-
if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
224
-
div1 = readl(base + E4210_DIV_CPU1) &
175
+
if (readl(base + regs->mux_sel) & E4210_MUX_HPM_MASK)
176
+
div1 = readl(base + regs->div_cpu1) &
225
177
(E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
226
178
}
227
179
···
235
187
*/
236
188
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
237
189
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
190
+
unsigned long alt_div, alt_div_mask = DIV_MASK;
238
191
239
192
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
240
193
WARN_ON(alt_div >= MAX_DIV);
···
248
199
alt_div |= E4210_DIV0_ATB_MASK;
249
200
alt_div_mask |= E4210_DIV0_ATB_MASK;
250
201
}
251
-
exynos_set_safe_div(base, alt_div, alt_div_mask);
202
+
exynos_set_safe_div(cpuclk, alt_div, alt_div_mask);
252
203
div0 |= alt_div;
253
204
}
254
205
255
206
/* select sclk_mpll as the alternate parent */
256
-
mux_reg = readl(base + E4210_SRC_CPU);
257
-
writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
258
-
wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
207
+
mux_reg = readl(base + regs->mux_sel);
208
+
writel(mux_reg | (1 << 16), base + regs->mux_sel);
209
+
wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2);
259
210
260
211
/* alternate parent is active now. set the dividers */
261
-
writel(div0, base + E4210_DIV_CPU0);
262
-
wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
212
+
writel(div0, base + regs->div_cpu0);
213
+
wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
263
214
264
215
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
265
-
writel(div1, base + E4210_DIV_CPU1);
266
-
wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
267
-
DIV_MASK_ALL);
216
+
writel(div1, base + regs->div_cpu1);
217
+
wait_until_divider_stable(base + regs->div_stat_cpu1,
218
+
DIV_MASK_ALL);
268
219
}
269
220
270
221
spin_unlock_irqrestore(cpuclk->lock, flags);
···
273
224
274
225
/* handler for post-rate change notification from parent clock */
275
226
static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
276
-
struct exynos_cpuclk *cpuclk, void __iomem *base)
227
+
struct exynos_cpuclk *cpuclk)
277
228
{
278
229
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
230
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
231
+
void __iomem *base = cpuclk->base;
279
232
unsigned long div = 0, div_mask = DIV_MASK;
280
233
unsigned long mux_reg;
281
234
unsigned long flags;
···
294
243
spin_lock_irqsave(cpuclk->lock, flags);
295
244
296
245
/* select mout_apll as the alternate parent */
297
-
mux_reg = readl(base + E4210_SRC_CPU);
298
-
writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
299
-
wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
246
+
mux_reg = readl(base + regs->mux_sel);
247
+
writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
248
+
wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1);
300
249
301
250
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
302
251
div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
303
252
div_mask |= E4210_DIV0_ATB_MASK;
304
253
}
305
254
306
-
exynos_set_safe_div(base, div, div_mask);
255
+
exynos_set_safe_div(cpuclk, div, div_mask);
307
256
spin_unlock_irqrestore(cpuclk->lock, flags);
308
257
return 0;
309
258
}
310
259
311
-
/*
312
-
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
313
-
* div and mask contain the divider value and the register bit mask of the
314
-
* dividers to be programmed.
315
-
*/
316
-
static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
317
-
unsigned long mask)
318
-
{
319
-
unsigned long div0;
260
+
/* ---- Exynos5433 ---------------------------------------------------------- */
320
261
321
-
div0 = readl(base + E5433_DIV_CPU0);
322
-
div0 = (div0 & ~mask) | (div & mask);
323
-
writel(div0, base + E5433_DIV_CPU0);
324
-
wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
325
-
}
262
+
static const struct exynos_cpuclk_regs e5433_cpuclk_regs = {
263
+
.mux_sel = 0x208,
264
+
.mux_stat = 0x408,
265
+
.div_cpu0 = 0x600,
266
+
.div_cpu1 = 0x604,
267
+
.div_stat_cpu0 = 0x700,
268
+
.div_stat_cpu1 = 0x704,
269
+
};
326
270
327
271
/* handler for pre-rate change notification from parent clock */
328
272
static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
329
-
struct exynos_cpuclk *cpuclk, void __iomem *base)
273
+
struct exynos_cpuclk *cpuclk)
330
274
{
331
275
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
276
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
277
+
void __iomem *base = cpuclk->base;
332
278
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
333
-
unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
334
279
unsigned long div0, div1 = 0, mux_reg;
335
280
unsigned long flags;
336
281
···
356
309
*/
357
310
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
358
311
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
312
+
unsigned long alt_div, alt_div_mask = DIV_MASK;
359
313
360
314
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
361
315
WARN_ON(alt_div >= MAX_DIV);
362
316
363
-
exynos5433_set_safe_div(base, alt_div, alt_div_mask);
317
+
exynos_set_safe_div(cpuclk, alt_div, alt_div_mask);
364
318
div0 |= alt_div;
365
319
}
366
320
367
321
/* select the alternate parent */
368
-
mux_reg = readl(base + E5433_MUX_SEL2);
369
-
writel(mux_reg | 1, base + E5433_MUX_SEL2);
370
-
wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
322
+
mux_reg = readl(base + regs->mux_sel);
323
+
writel(mux_reg | 1, base + regs->mux_sel);
324
+
wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2);
371
325
372
326
/* alternate parent is active now. set the dividers */
373
-
writel(div0, base + E5433_DIV_CPU0);
374
-
wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
327
+
writel(div0, base + regs->div_cpu0);
328
+
wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
375
329
376
-
writel(div1, base + E5433_DIV_CPU1);
377
-
wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
330
+
writel(div1, base + regs->div_cpu1);
331
+
wait_until_divider_stable(base + regs->div_stat_cpu1, DIV_MASK_ALL);
378
332
379
333
spin_unlock_irqrestore(cpuclk->lock, flags);
380
334
return 0;
···
383
335
384
336
/* handler for post-rate change notification from parent clock */
385
337
static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
386
-
struct exynos_cpuclk *cpuclk, void __iomem *base)
338
+
struct exynos_cpuclk *cpuclk)
387
339
{
340
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
341
+
void __iomem *base = cpuclk->base;
388
342
unsigned long div = 0, div_mask = DIV_MASK;
389
343
unsigned long mux_reg;
390
344
unsigned long flags;
···
394
344
spin_lock_irqsave(cpuclk->lock, flags);
395
345
396
346
/* select apll as the alternate parent */
397
-
mux_reg = readl(base + E5433_MUX_SEL2);
398
-
writel(mux_reg & ~1, base + E5433_MUX_SEL2);
399
-
wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
347
+
mux_reg = readl(base + regs->mux_sel);
348
+
writel(mux_reg & ~1, base + regs->mux_sel);
349
+
wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1);
400
350
401
-
exynos5433_set_safe_div(base, div, div_mask);
351
+
exynos_set_safe_div(cpuclk, div, div_mask);
402
352
spin_unlock_irqrestore(cpuclk->lock, flags);
403
353
return 0;
404
354
}
355
+
356
+
/* ---- Exynos850 ----------------------------------------------------------- */
357
+
358
+
#define E850_DIV_RATIO_MASK GENMASK(3, 0)
359
+
#define E850_BUSY_MASK BIT(16)
360
+
361
+
/* Max time for divider or mux to stabilize, usec */
362
+
#define E850_DIV_MUX_STAB_TIME 100
363
+
/* OSCCLK clock rate, Hz */
364
+
#define E850_OSCCLK (26 * MHZ)
365
+
366
+
static const struct exynos_cpuclk_regs e850cl0_cpuclk_regs = {
367
+
.mux = 0x100c,
368
+
.divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
369
+
};
370
+
371
+
static const struct exynos_cpuclk_regs e850cl1_cpuclk_regs = {
372
+
.mux = 0x1000,
373
+
.divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
374
+
};
375
+
376
+
/*
377
+
* Set alternate parent rate to "rate" value or less.
378
+
*
379
+
* rate: Desired alt_parent rate, or 0 for max alt_parent rate
380
+
*
381
+
* Exynos850 doesn't have CPU clock divider in CMU_CPUCLx block (CMUREF divider
382
+
* doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used
383
+
* instead to adjust alternate parent speed.
384
+
*
385
+
* It's possible to use clk_set_max_rate() instead of this function, but it
386
+
* would set overly pessimistic rate values to alternate parent.
387
+
*/
388
+
static int exynos850_alt_parent_set_max_rate(const struct clk_hw *alt_parent,
389
+
unsigned long rate)
390
+
{
391
+
struct clk_hw *clk_div, *clk_divp;
392
+
unsigned long divp_rate, div_rate, div;
393
+
int ret;
394
+
395
+
/* Divider from CMU_TOP */
396
+
clk_div = clk_hw_get_parent(alt_parent);
397
+
if (!clk_div)
398
+
return -ENOENT;
399
+
/* Divider's parent from CMU_TOP */
400
+
clk_divp = clk_hw_get_parent(clk_div);
401
+
if (!clk_divp)
402
+
return -ENOENT;
403
+
/* Divider input rate */
404
+
divp_rate = clk_hw_get_rate(clk_divp);
405
+
if (!divp_rate)
406
+
return -EINVAL;
407
+
408
+
/* Calculate new alt_parent rate for integer divider value */
409
+
if (rate == 0)
410
+
div = 1;
411
+
else
412
+
div = DIV_ROUND_UP(divp_rate, rate);
413
+
div_rate = DIV_ROUND_UP(divp_rate, div);
414
+
WARN_ON(div >= MAX_DIV);
415
+
416
+
/* alt_parent will propagate this change up to the divider */
417
+
ret = clk_set_rate(alt_parent->clk, div_rate);
418
+
if (ret)
419
+
return ret;
420
+
udelay(E850_DIV_MUX_STAB_TIME);
421
+
422
+
return 0;
423
+
}
424
+
425
+
/* Handler for pre-rate change notification from parent clock */
426
+
static int exynos850_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
427
+
struct exynos_cpuclk *cpuclk)
428
+
{
429
+
const unsigned int shifts[4] = { 16, 12, 8, 4 }; /* E850_CPU_DIV0() */
430
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
431
+
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
432
+
const struct clk_hw *alt_parent = cpuclk->alt_parent;
433
+
void __iomem *base = cpuclk->base;
434
+
unsigned long alt_prate = clk_hw_get_rate(alt_parent);
435
+
unsigned long flags;
436
+
u32 mux_reg;
437
+
size_t i;
438
+
int ret;
439
+
440
+
/* No actions are needed when switching to or from OSCCLK parent */
441
+
if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
442
+
return 0;
443
+
444
+
/* Find out the divider values to use for clock data */
445
+
while ((cfg_data->prate * 1000) != ndata->new_rate) {
446
+
if (cfg_data->prate == 0)
447
+
return -EINVAL;
448
+
cfg_data++;
449
+
}
450
+
451
+
/*
452
+
* If the old parent clock speed is less than the clock speed of
453
+
* the alternate parent, then it should be ensured that at no point
454
+
* the armclk speed is more than the old_prate until the dividers are
455
+
* set. Also workaround the issue of the dividers being set to lower
456
+
* values before the parent clock speed is set to new lower speed
457
+
* (this can result in too high speed of armclk output clocks).
458
+
*/
459
+
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
460
+
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
461
+
462
+
ret = exynos850_alt_parent_set_max_rate(alt_parent, tmp_rate);
463
+
if (ret)
464
+
return ret;
465
+
}
466
+
467
+
spin_lock_irqsave(cpuclk->lock, flags);
468
+
469
+
/* Select the alternate parent */
470
+
mux_reg = readl(base + regs->mux);
471
+
writel(mux_reg | 1, base + regs->mux);
472
+
wait_until_mux_stable(base + regs->mux, 16, 1, 0);
473
+
474
+
/* Alternate parent is active now. Set the dividers */
475
+
for (i = 0; i < ARRAY_SIZE(shifts); ++i) {
476
+
unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf;
477
+
u32 val;
478
+
479
+
val = readl(base + regs->divs[i]);
480
+
val = (val & ~E850_DIV_RATIO_MASK) | div;
481
+
writel(val, base + regs->divs[i]);
482
+
wait_until_divider_stable(base + regs->divs[i], E850_BUSY_MASK);
483
+
}
484
+
485
+
spin_unlock_irqrestore(cpuclk->lock, flags);
486
+
487
+
return 0;
488
+
}
489
+
490
+
/* Handler for post-rate change notification from parent clock */
491
+
static int exynos850_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
492
+
struct exynos_cpuclk *cpuclk)
493
+
{
494
+
const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
495
+
const struct clk_hw *alt_parent = cpuclk->alt_parent;
496
+
void __iomem *base = cpuclk->base;
497
+
unsigned long flags;
498
+
u32 mux_reg;
499
+
500
+
/* No actions are needed when switching to or from OSCCLK parent */
501
+
if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
502
+
return 0;
503
+
504
+
spin_lock_irqsave(cpuclk->lock, flags);
505
+
506
+
/* Select main parent (PLL) for mux */
507
+
mux_reg = readl(base + regs->mux);
508
+
writel(mux_reg & ~1, base + regs->mux);
509
+
wait_until_mux_stable(base + regs->mux, 16, 1, 0);
510
+
511
+
spin_unlock_irqrestore(cpuclk->lock, flags);
512
+
513
+
/* Set alt_parent rate back to max */
514
+
return exynos850_alt_parent_set_max_rate(alt_parent, 0);
515
+
}
516
+
517
+
/* -------------------------------------------------------------------------- */
518
+
519
+
/* Common round rate callback usable for all types of CPU clocks */
520
+
static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
521
+
unsigned long *prate)
522
+
{
523
+
struct clk_hw *parent = clk_hw_get_parent(hw);
524
+
*prate = clk_hw_round_rate(parent, drate);
525
+
return *prate;
526
+
}
527
+
528
+
/* Common recalc rate callback usable for all types of CPU clocks */
529
+
static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
530
+
unsigned long parent_rate)
531
+
{
532
+
/*
533
+
* The CPU clock output (armclk) rate is the same as its parent
534
+
* rate. Although there exist certain dividers inside the CPU
535
+
* clock block that could be used to divide the parent clock,
536
+
* the driver does not make use of them currently, except during
537
+
* frequency transitions.
538
+
*/
539
+
return parent_rate;
540
+
}
541
+
542
+
static const struct clk_ops exynos_cpuclk_clk_ops = {
543
+
.recalc_rate = exynos_cpuclk_recalc_rate,
544
+
.round_rate = exynos_cpuclk_round_rate,
545
+
};
405
546
406
547
/*
407
548
* This notifier function is called for the pre-rate and post-rate change
408
549
* notifications of the parent clock of cpuclk.
409
550
*/
410
551
static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
411
-
unsigned long event, void *data)
552
+
unsigned long event, void *data)
412
553
{
413
554
struct clk_notifier_data *ndata = data;
414
555
struct exynos_cpuclk *cpuclk;
415
-
void __iomem *base;
416
556
int err = 0;
417
557
418
558
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
419
-
base = cpuclk->ctrl_base;
420
559
421
560
if (event == PRE_RATE_CHANGE)
422
-
err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
561
+
err = cpuclk->chip->pre_rate_cb(ndata, cpuclk);
423
562
else if (event == POST_RATE_CHANGE)
424
-
err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
563
+
err = cpuclk->chip->post_rate_cb(ndata, cpuclk);
425
564
426
565
return notifier_from_errno(err);
427
566
}
428
567
429
-
/*
430
-
* This notifier function is called for the pre-rate and post-rate change
431
-
* notifications of the parent clock of cpuclk.
432
-
*/
433
-
static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
434
-
unsigned long event, void *data)
435
-
{
436
-
struct clk_notifier_data *ndata = data;
437
-
struct exynos_cpuclk *cpuclk;
438
-
void __iomem *base;
439
-
int err = 0;
440
-
441
-
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
442
-
base = cpuclk->ctrl_base;
443
-
444
-
if (event == PRE_RATE_CHANGE)
445
-
err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
446
-
else if (event == POST_RATE_CHANGE)
447
-
err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
448
-
449
-
return notifier_from_errno(err);
450
-
}
568
+
static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = {
569
+
[CPUCLK_LAYOUT_E4210] = {
570
+
.regs = &e4210_cpuclk_regs,
571
+
.pre_rate_cb = exynos_cpuclk_pre_rate_change,
572
+
.post_rate_cb = exynos_cpuclk_post_rate_change,
573
+
},
574
+
[CPUCLK_LAYOUT_E5433] = {
575
+
.regs = &e5433_cpuclk_regs,
576
+
.pre_rate_cb = exynos5433_cpuclk_pre_rate_change,
577
+
.post_rate_cb = exynos5433_cpuclk_post_rate_change,
578
+
},
579
+
[CPUCLK_LAYOUT_E850_CL0] = {
580
+
.regs = &e850cl0_cpuclk_regs,
581
+
.pre_rate_cb = exynos850_cpuclk_pre_rate_change,
582
+
.post_rate_cb = exynos850_cpuclk_post_rate_change,
583
+
},
584
+
[CPUCLK_LAYOUT_E850_CL1] = {
585
+
.regs = &e850cl1_cpuclk_regs,
586
+
.pre_rate_cb = exynos850_cpuclk_pre_rate_change,
587
+
.post_rate_cb = exynos850_cpuclk_post_rate_change,
588
+
},
589
+
};
451
590
452
591
/* helper function to register a CPU clock */
453
592
static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
454
-
unsigned int lookup_id, const char *name,
455
-
const struct clk_hw *parent, const struct clk_hw *alt_parent,
456
-
unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
457
-
unsigned long num_cfgs, unsigned long flags)
593
+
const struct samsung_cpu_clock *clk_data)
458
594
{
595
+
const struct clk_hw *parent, *alt_parent;
596
+
struct clk_hw **hws;
459
597
struct exynos_cpuclk *cpuclk;
460
598
struct clk_init_data init;
461
599
const char *parent_name;
600
+
unsigned int num_cfgs;
462
601
int ret = 0;
463
602
603
+
hws = ctx->clk_data.hws;
604
+
parent = hws[clk_data->parent_id];
605
+
alt_parent = hws[clk_data->alt_parent_id];
464
606
if (IS_ERR(parent) || IS_ERR(alt_parent)) {
465
607
pr_err("%s: invalid parent clock(s)\n", __func__);
466
608
return -EINVAL;
···
664
422
665
423
parent_name = clk_hw_get_name(parent);
666
424
667
-
init.name = name;
425
+
init.name = clk_data->name;
668
426
init.flags = CLK_SET_RATE_PARENT;
669
427
init.parent_names = &parent_name;
670
428
init.num_parents = 1;
···
672
430
673
431
cpuclk->alt_parent = alt_parent;
674
432
cpuclk->hw.init = &init;
675
-
cpuclk->ctrl_base = ctx->reg_base + offset;
433
+
cpuclk->base = ctx->reg_base + clk_data->offset;
676
434
cpuclk->lock = &ctx->lock;
677
-
cpuclk->flags = flags;
678
-
if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
679
-
cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
680
-
else
681
-
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
682
-
435
+
cpuclk->flags = clk_data->flags;
436
+
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
437
+
cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout];
683
438
684
439
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
685
440
if (ret) {
686
441
pr_err("%s: failed to register clock notifier for %s\n",
687
-
__func__, name);
442
+
__func__, clk_data->name);
688
443
goto free_cpuclk;
689
444
}
690
445
691
-
cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
446
+
/* Find count of configuration rates in cfg */
447
+
for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; )
448
+
num_cfgs++;
449
+
450
+
cpuclk->cfg = kmemdup(clk_data->cfg, sizeof(*clk_data->cfg) * num_cfgs,
451
+
GFP_KERNEL);
692
452
if (!cpuclk->cfg) {
693
453
ret = -ENOMEM;
694
454
goto unregister_clk_nb;
···
698
454
699
455
ret = clk_hw_register(NULL, &cpuclk->hw);
700
456
if (ret) {
701
-
pr_err("%s: could not register cpuclk %s\n", __func__, name);
457
+
pr_err("%s: could not register cpuclk %s\n", __func__,
458
+
clk_data->name);
702
459
goto free_cpuclk_data;
703
460
}
704
461
705
-
samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);
462
+
samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id);
706
463
return 0;
707
464
708
465
free_cpuclk_data:
···
719
474
const struct samsung_cpu_clock *list, unsigned int nr_clk)
720
475
{
721
476
unsigned int idx;
722
-
unsigned int num_cfgs;
723
-
struct clk_hw **hws = ctx->clk_data.hws;
724
477
725
-
for (idx = 0; idx < nr_clk; idx++, list++) {
726
-
/* find count of configuration rates in cfg */
727
-
for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )
728
-
num_cfgs++;
729
-
730
-
exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],
731
-
hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,
732
-
list->flags);
733
-
}
478
+
for (idx = 0; idx < nr_clk; idx++)
479
+
exynos_register_cpu_clock(ctx, &list[idx]);
734
480
}
+18
-35
drivers/clk/samsung/clk-cpu.h
+18
-35
drivers/clk/samsung/clk-cpu.h
···
8
8
#ifndef __SAMSUNG_CLK_CPU_H
9
9
#define __SAMSUNG_CLK_CPU_H
10
10
11
-
#include "clk.h"
11
+
/* The CPU clock registers have DIV1 configuration register */
12
+
#define CLK_CPU_HAS_DIV1 BIT(0)
13
+
/* When ALT parent is active, debug clocks need safe divider values */
14
+
#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1)
15
+
16
+
/**
17
+
* enum exynos_cpuclk_layout - CPU clock registers layout compatibility
18
+
* @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout
19
+
* @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout
20
+
* @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout
21
+
* @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout
22
+
*/
23
+
enum exynos_cpuclk_layout {
24
+
CPUCLK_LAYOUT_E4210,
25
+
CPUCLK_LAYOUT_E5433,
26
+
CPUCLK_LAYOUT_E850_CL0,
27
+
CPUCLK_LAYOUT_E850_CL1,
28
+
};
12
29
13
30
/**
14
31
* struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
···
43
26
unsigned long prate;
44
27
unsigned long div0;
45
28
unsigned long div1;
46
-
};
47
-
48
-
/**
49
-
* struct exynos_cpuclk - information about clock supplied to a CPU core
50
-
* @hw: handle between CCF and CPU clock
51
-
* @alt_parent: alternate parent clock to use when switching the speed
52
-
* of the primary parent clock
53
-
* @ctrl_base: base address of the clock controller
54
-
* @lock: cpu clock domain register access lock
55
-
* @cfg: cpu clock rate configuration data
56
-
* @num_cfgs: number of array elements in @cfg array
57
-
* @clk_nb: clock notifier registered for changes in clock speed of the
58
-
* primary parent clock
59
-
* @flags: configuration flags for the CPU clock
60
-
*
61
-
* This structure holds information required for programming the CPU clock for
62
-
* various clock speeds.
63
-
*/
64
-
struct exynos_cpuclk {
65
-
struct clk_hw hw;
66
-
const struct clk_hw *alt_parent;
67
-
void __iomem *ctrl_base;
68
-
spinlock_t *lock;
69
-
const struct exynos_cpuclk_cfg_data *cfg;
70
-
const unsigned long num_cfgs;
71
-
struct notifier_block clk_nb;
72
-
unsigned long flags;
73
-
74
-
/* The CPU clock registers have DIV1 configuration register */
75
-
#define CLK_CPU_HAS_DIV1 (1 << 0)
76
-
/* When ALT parent is active, debug clocks need safe divider values */
77
-
#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
78
-
/* The CPU clock registers have Exynos5433-compatible layout */
79
-
#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
80
29
};
81
30
82
31
#endif /* __SAMSUNG_CLK_CPU_H */
+1
-1
drivers/clk/samsung/clk-exynos3250.c
+1
-1
drivers/clk/samsung/clk-exynos3250.c
···
775
775
776
776
static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
777
777
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
778
-
CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
778
+
CLK_CPU_HAS_DIV1, 0x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d),
779
779
};
780
780
781
781
static void __init exynos3_core_down_clock(void __iomem *reg_base)
+6
-3
drivers/clk/samsung/clk-exynos4.c
+6
-3
drivers/clk/samsung/clk-exynos4.c
···
1252
1252
1253
1253
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
1254
1254
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
1255
-
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
1255
+
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
1256
+
CPUCLK_LAYOUT_E4210, e4210_armclk_d),
1256
1257
};
1257
1258
1258
1259
static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {
1259
1260
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
1260
-
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d),
1261
+
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
1262
+
CPUCLK_LAYOUT_E4210, e4212_armclk_d),
1261
1263
};
1262
1264
1263
1265
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
1264
1266
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
1265
-
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
1267
+
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
1268
+
CPUCLK_LAYOUT_E4210, e4412_armclk_d),
1266
1269
};
1267
1270
1268
1271
/* register exynos4 clocks */
+3
-2
drivers/clk/samsung/clk-exynos5250.c
+3
-2
drivers/clk/samsung/clk-exynos5250.c
···
776
776
};
777
777
778
778
static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
779
-
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
780
-
exynos5250_armclk_d),
779
+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL,
780
+
CLK_CPU_HAS_DIV1, 0x0, CPUCLK_LAYOUT_E4210,
781
+
exynos5250_armclk_d),
781
782
};
782
783
783
784
static const struct of_device_id ext_clk_match[] __initconst = {
+8
-8
drivers/clk/samsung/clk-exynos5420.c
+8
-8
drivers/clk/samsung/clk-exynos5420.c
···
1555
1555
};
1556
1556
1557
1557
static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
1558
-
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
1559
-
exynos5420_eglclk_d),
1560
-
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
1561
-
exynos5420_kfcclk_d),
1558
+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1559
+
0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d),
1560
+
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1561
+
0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1562
1562
};
1563
1563
1564
1564
static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
1565
-
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
1566
-
exynos5800_eglclk_d),
1567
-
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
1568
-
exynos5420_kfcclk_d),
1565
+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
1566
+
0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d),
1567
+
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
1568
+
0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
1569
1569
};
1570
1570
1571
1571
static const struct of_device_id ext_clk_match[] __initconst = {
+4
-6
drivers/clk/samsung/clk-exynos5433.c
+4
-6
drivers/clk/samsung/clk-exynos5433.c
···
3700
3700
3701
3701
static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
3702
3702
CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
3703
-
CLK_MOUT_BUS_PLL_APOLLO_USER,
3704
-
CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
3705
-
exynos5433_apolloclk_d),
3703
+
CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0,
3704
+
CPUCLK_LAYOUT_E5433, exynos5433_apolloclk_d),
3706
3705
};
3707
3706
3708
3707
static const struct samsung_cmu_info apollo_cmu_info __initconst = {
···
3944
3945
3945
3946
static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
3946
3947
CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
3947
-
CLK_MOUT_BUS_PLL_ATLAS_USER,
3948
-
CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
3949
-
exynos5433_atlasclk_d),
3948
+
CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0,
3949
+
CPUCLK_LAYOUT_E5433, exynos5433_atlasclk_d),
3950
3950
};
3951
3951
3952
3952
static const struct samsung_cmu_info atlas_cmu_info __initconst = {
+26
-17
drivers/clk/samsung/clk-exynos850.c
+26
-17
drivers/clk/samsung/clk-exynos850.c
···
26
26
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
27
27
#define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
28
28
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
29
-
#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
29
+
#define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1)
30
30
#define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
31
31
32
32
/* ---- CMU_TOP ------------------------------------------------------------- */
···
605
605
606
606
static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
607
607
GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
608
-
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
608
+
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0),
609
609
GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
610
610
"mout_clkcmu_chub_bus",
611
611
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
···
974
974
static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
975
975
MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
976
976
CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
977
-
MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
978
-
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
979
-
MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
980
-
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
977
+
MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
978
+
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0),
979
+
MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
980
+
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0),
981
981
};
982
982
983
983
static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
984
984
DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
985
985
CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
986
-
DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
987
-
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
988
-
DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
989
-
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
986
+
DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
987
+
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),
988
+
DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
989
+
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0),
990
990
};
991
991
992
992
static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
···
1001
1001
"gout_clkcmu_cmgp_bus",
1002
1002
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1003
1003
GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
1004
-
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
1004
+
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1005
1005
GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
1006
1006
"gout_clkcmu_cmgp_bus",
1007
1007
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
1008
1008
GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
1009
-
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
1009
+
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1010
1010
GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
1011
1011
"gout_clkcmu_cmgp_bus",
1012
1012
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
···
1557
1557
mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
1558
1558
MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
1559
1559
mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
1560
-
MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p,
1561
-
PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1),
1560
+
MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user",
1561
+
mout_peri_spi_user_p, PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1,
1562
+
CLK_SET_RATE_PARENT, 0),
1562
1563
};
1563
1564
1564
1565
static const struct samsung_div_clock peri_div_clks[] __initconst = {
···
1569
1568
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
1570
1569
DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
1571
1570
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
1572
-
DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
1573
-
CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
1571
+
DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
1572
+
CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0),
1574
1573
};
1575
1574
1576
1575
static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
···
1612
1611
"mout_peri_bus_user",
1613
1612
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
1614
1613
GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
1615
-
CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
1614
+
CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1616
1615
GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
1617
1616
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
1618
1617
GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
···
1668
1667
#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
1669
1668
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
1670
1669
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
1670
+
#define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK 0x20f0
1671
+
#define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK 0x2124
1671
1672
#define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
1672
1673
#define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
1673
1674
#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
···
1686
1683
CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
1687
1684
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
1688
1685
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
1686
+
CLK_CON_GAT_GOUT_CORE_PDMA_ACLK,
1687
+
CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK,
1689
1688
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
1690
1689
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
1691
1690
CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
···
1731
1726
GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
1732
1727
"mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
1733
1728
21, CLK_SET_RATE_PARENT, 0),
1729
+
GATE(CLK_GOUT_PDMA_CORE_ACLK, "gout_pdma_core_aclk",
1730
+
"mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0),
1731
+
GATE(CLK_GOUT_SPDMA_CORE_ACLK, "gout_spdma_core_aclk",
1732
+
"mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0),
1734
1733
GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
1735
1734
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
1736
1735
GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
+938
-4
drivers/clk/samsung/clk-gs101.c
+938
-4
drivers/clk/samsung/clk-gs101.c
···
20
20
#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
21
21
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
22
22
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
23
+
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
24
+
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
23
25
24
26
/* ---- CMU_TOP ------------------------------------------------------------- */
25
27
26
28
/* Register Offset definitions for CMU_TOP (0x1e080000) */
27
-
28
29
#define PLL_LOCKTIME_PLL_SHARED0 0x0000
29
30
#define PLL_LOCKTIME_PLL_SHARED1 0x0004
30
31
#define PLL_LOCKTIME_PLL_SHARED2 0x0008
···
2476
2475
.nr_clk_ids = CLKS_NR_MISC,
2477
2476
.clk_regs = misc_clk_regs,
2478
2477
.nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
2479
-
.clk_name = "dout_cmu_misc_bus",
2478
+
.clk_name = "bus",
2479
+
};
2480
+
2481
+
static void __init gs101_cmu_misc_init(struct device_node *np)
2482
+
{
2483
+
exynos_arm64_register_cmu(NULL, np, &misc_cmu_info);
2484
+
}
2485
+
2486
+
/* Register CMU_MISC early, as it's needed for MCT timer */
2487
+
CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc",
2488
+
gs101_cmu_misc_init);
2489
+
2490
+
/* ---- CMU_PERIC0 ---------------------------------------------------------- */
2491
+
2492
+
/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
2493
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
2494
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
2495
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610
2496
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614
2497
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620
2498
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624
2499
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640
2500
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644
2501
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650
2502
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654
2503
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660
2504
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664
2505
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670
2506
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674
2507
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680
2508
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684
2509
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690
2510
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694
2511
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0
2512
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4
2513
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0
2514
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4
2515
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0
2516
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4
2517
+
#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800
2518
+
#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810
2519
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
2520
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804
2521
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c
2522
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810
2523
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814
2524
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820
2525
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824
2526
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828
2527
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c
2528
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830
2529
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834
2530
+
#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000
2531
+
#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
2532
+
#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
2533
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
2534
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010
2535
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014
2536
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018
2537
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c
2538
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020
2539
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024
2540
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028
2541
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c
2542
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030
2543
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034
2544
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038
2545
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c
2546
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040
2547
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044
2548
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048
2549
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c
2550
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050
2551
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054
2552
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058
2553
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c
2554
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060
2555
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064
2556
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068
2557
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c
2558
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070
2559
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074
2560
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078
2561
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c
2562
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080
2563
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084
2564
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088
2565
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c
2566
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090
2567
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094
2568
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098
2569
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c
2570
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4
2571
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8
2572
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0
2573
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
2574
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8
2575
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc
2576
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4
2577
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8
2578
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc
2579
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0
2580
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4
2581
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8
2582
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc
2583
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0
2584
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4
2585
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8
2586
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000
2587
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004
2588
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008
2589
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c
2590
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010
2591
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014
2592
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018
2593
+
#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c
2594
+
#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020
2595
+
#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024
2596
+
#define QCH_CON_GPC_PERIC0_QCH 0x3028
2597
+
#define QCH_CON_GPIO_PERIC0_QCH 0x302c
2598
+
#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030
2599
+
#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034
2600
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038
2601
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c
2602
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040
2603
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044
2604
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048
2605
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c
2606
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050
2607
+
#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054
2608
+
#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058
2609
+
#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c
2610
+
#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060
2611
+
#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064
2612
+
#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068
2613
+
#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c
2614
+
#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070
2615
+
#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074
2616
+
#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078
2617
+
#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c
2618
+
#define QCH_CON_SYSREG_PERIC0_QCH 0x3080
2619
+
#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00
2620
+
2621
+
static const unsigned long peric0_clk_regs[] __initconst = {
2622
+
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
2623
+
PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
2624
+
PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER,
2625
+
PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER,
2626
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER,
2627
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER,
2628
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
2629
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
2630
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER,
2631
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER,
2632
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER,
2633
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER,
2634
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER,
2635
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER,
2636
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER,
2637
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER,
2638
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER,
2639
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER,
2640
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER,
2641
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER,
2642
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER,
2643
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER,
2644
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER,
2645
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER,
2646
+
PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
2647
+
CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0,
2648
+
CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
2649
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART,
2650
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
2651
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI,
2652
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI,
2653
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI,
2654
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI,
2655
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI,
2656
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
2657
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
2658
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI,
2659
+
CLK_CON_BUF_CLKBUF_PERIC0_IP,
2660
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
2661
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
2662
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
2663
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
2664
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
2665
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
2666
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
2667
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
2668
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
2669
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
2670
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
2671
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
2672
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
2673
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
2674
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
2675
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
2676
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
2677
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
2678
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
2679
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
2680
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
2681
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
2682
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
2683
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
2684
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
2685
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
2686
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
2687
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
2688
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
2689
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
2690
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
2691
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
2692
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
2693
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
2694
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
2695
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
2696
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
2697
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
2698
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
2699
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
2700
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
2701
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
2702
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
2703
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
2704
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
2705
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
2706
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
2707
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
2708
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
2709
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
2710
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
2711
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
2712
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
2713
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
2714
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
2715
+
DMYQCH_CON_PERIC0_TOP0_QCH_S1,
2716
+
DMYQCH_CON_PERIC0_TOP0_QCH_S2,
2717
+
DMYQCH_CON_PERIC0_TOP0_QCH_S3,
2718
+
DMYQCH_CON_PERIC0_TOP0_QCH_S4,
2719
+
DMYQCH_CON_PERIC0_TOP0_QCH_S5,
2720
+
DMYQCH_CON_PERIC0_TOP0_QCH_S6,
2721
+
DMYQCH_CON_PERIC0_TOP0_QCH_S7,
2722
+
DMYQCH_CON_PERIC0_TOP0_QCH_S8,
2723
+
PCH_CON_LHM_AXI_P_PERIC0_PCH,
2724
+
QCH_CON_D_TZPC_PERIC0_QCH,
2725
+
QCH_CON_GPC_PERIC0_QCH,
2726
+
QCH_CON_GPIO_PERIC0_QCH,
2727
+
QCH_CON_LHM_AXI_P_PERIC0_QCH,
2728
+
QCH_CON_PERIC0_CMU_PERIC0_QCH,
2729
+
QCH_CON_PERIC0_TOP0_QCH_I3C1,
2730
+
QCH_CON_PERIC0_TOP0_QCH_I3C2,
2731
+
QCH_CON_PERIC0_TOP0_QCH_I3C3,
2732
+
QCH_CON_PERIC0_TOP0_QCH_I3C4,
2733
+
QCH_CON_PERIC0_TOP0_QCH_I3C5,
2734
+
QCH_CON_PERIC0_TOP0_QCH_I3C6,
2735
+
QCH_CON_PERIC0_TOP0_QCH_I3C7,
2736
+
QCH_CON_PERIC0_TOP0_QCH_I3C8,
2737
+
QCH_CON_PERIC0_TOP0_QCH_USI1_USI,
2738
+
QCH_CON_PERIC0_TOP0_QCH_USI2_USI,
2739
+
QCH_CON_PERIC0_TOP0_QCH_USI3_USI,
2740
+
QCH_CON_PERIC0_TOP0_QCH_USI4_USI,
2741
+
QCH_CON_PERIC0_TOP0_QCH_USI5_USI,
2742
+
QCH_CON_PERIC0_TOP0_QCH_USI6_USI,
2743
+
QCH_CON_PERIC0_TOP0_QCH_USI7_USI,
2744
+
QCH_CON_PERIC0_TOP0_QCH_USI8_USI,
2745
+
QCH_CON_PERIC0_TOP1_QCH_USI0_UART,
2746
+
QCH_CON_PERIC0_TOP1_QCH_USI14_UART,
2747
+
QCH_CON_SYSREG_PERIC0_QCH,
2748
+
QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0,
2749
+
};
2750
+
2751
+
/* List of parent clocks for Muxes in CMU_PERIC0 */
2752
+
PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
2753
+
PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
2754
+
PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
2755
+
PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
2756
+
2757
+
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
2758
+
MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
2759
+
mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
2760
+
MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user",
2761
+
mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1),
2762
+
MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
2763
+
"mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
2764
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
2765
+
MUX(CLK_MOUT_PERIC0_USI14_USI_USER,
2766
+
"mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
2767
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
2768
+
MUX(CLK_MOUT_PERIC0_USI1_USI_USER,
2769
+
"mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
2770
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
2771
+
MUX(CLK_MOUT_PERIC0_USI2_USI_USER,
2772
+
"mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
2773
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
2774
+
MUX(CLK_MOUT_PERIC0_USI3_USI_USER,
2775
+
"mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
2776
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
2777
+
MUX(CLK_MOUT_PERIC0_USI4_USI_USER,
2778
+
"mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
2779
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
2780
+
MUX(CLK_MOUT_PERIC0_USI5_USI_USER,
2781
+
"mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
2782
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
2783
+
MUX(CLK_MOUT_PERIC0_USI6_USI_USER,
2784
+
"mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
2785
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
2786
+
MUX(CLK_MOUT_PERIC0_USI7_USI_USER,
2787
+
"mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
2788
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
2789
+
MUX(CLK_MOUT_PERIC0_USI8_USI_USER,
2790
+
"mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
2791
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
2792
+
};
2793
+
2794
+
static const struct samsung_div_clock peric0_div_clks[] __initconst = {
2795
+
DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user",
2796
+
CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
2797
+
DIV(CLK_DOUT_PERIC0_USI0_UART,
2798
+
"dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
2799
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
2800
+
DIV(CLK_DOUT_PERIC0_USI14_USI,
2801
+
"dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
2802
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4),
2803
+
DIV(CLK_DOUT_PERIC0_USI1_USI,
2804
+
"dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
2805
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4),
2806
+
DIV(CLK_DOUT_PERIC0_USI2_USI,
2807
+
"dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
2808
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4),
2809
+
DIV(CLK_DOUT_PERIC0_USI3_USI,
2810
+
"dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
2811
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4),
2812
+
DIV(CLK_DOUT_PERIC0_USI4_USI,
2813
+
"dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
2814
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4),
2815
+
DIV(CLK_DOUT_PERIC0_USI5_USI,
2816
+
"dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
2817
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4),
2818
+
DIV(CLK_DOUT_PERIC0_USI6_USI,
2819
+
"dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
2820
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4),
2821
+
DIV(CLK_DOUT_PERIC0_USI7_USI,
2822
+
"dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
2823
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4),
2824
+
DIV(CLK_DOUT_PERIC0_USI8_USI,
2825
+
"dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
2826
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4),
2827
+
};
2828
+
2829
+
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
2830
+
/* Disabling this clock makes the system hang. Mark the clock as critical. */
2831
+
GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
2832
+
"gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
2833
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
2834
+
21, CLK_IS_CRITICAL, 0),
2835
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK,
2836
+
"gout_peric0_clk_peric0_oscclk_clk", "oscclk",
2837
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
2838
+
21, 0, 0),
2839
+
GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK,
2840
+
"gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user",
2841
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
2842
+
21, 0, 0),
2843
+
GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK,
2844
+
"gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user",
2845
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
2846
+
21, 0, 0),
2847
+
GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK,
2848
+
"gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user",
2849
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
2850
+
21, CLK_IGNORE_UNUSED, 0),
2851
+
/* Disabling this clock makes the system hang. Mark the clock as critical. */
2852
+
GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
2853
+
"gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user",
2854
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
2855
+
21, CLK_IS_CRITICAL, 0),
2856
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
2857
+
"gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
2858
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
2859
+
21, 0, 0),
2860
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
2861
+
"gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
2862
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
2863
+
21, 0, 0),
2864
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
2865
+
"gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
2866
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
2867
+
21, 0, 0),
2868
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11,
2869
+
"gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c",
2870
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
2871
+
21, 0, 0),
2872
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12,
2873
+
"gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c",
2874
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
2875
+
21, 0, 0),
2876
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13,
2877
+
"gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c",
2878
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
2879
+
21, 0, 0),
2880
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14,
2881
+
"gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c",
2882
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
2883
+
21, 0, 0),
2884
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15,
2885
+
"gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c",
2886
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
2887
+
21, 0, 0),
2888
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
2889
+
"gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
2890
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
2891
+
21, 0, 0),
2892
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
2893
+
"gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
2894
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
2895
+
21, 0, 0),
2896
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
2897
+
"gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
2898
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
2899
+
21, 0, 0),
2900
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
2901
+
"gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
2902
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
2903
+
21, 0, 0),
2904
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
2905
+
"gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
2906
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
2907
+
21, 0, 0),
2908
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
2909
+
"gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
2910
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
2911
+
21, 0, 0),
2912
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
2913
+
"gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
2914
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
2915
+
21, 0, 0),
2916
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9,
2917
+
"gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c",
2918
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
2919
+
21, 0, 0),
2920
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0,
2921
+
"gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user",
2922
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
2923
+
21, 0, 0),
2924
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1,
2925
+
"gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user",
2926
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
2927
+
21, 0, 0),
2928
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10,
2929
+
"gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user",
2930
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
2931
+
21, 0, 0),
2932
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11,
2933
+
"gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user",
2934
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
2935
+
21, 0, 0),
2936
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12,
2937
+
"gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user",
2938
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
2939
+
21, 0, 0),
2940
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13,
2941
+
"gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user",
2942
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
2943
+
21, 0, 0),
2944
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14,
2945
+
"gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user",
2946
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
2947
+
21, 0, 0),
2948
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15,
2949
+
"gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user",
2950
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
2951
+
21, 0, 0),
2952
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2,
2953
+
"gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user",
2954
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
2955
+
21, 0, 0),
2956
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3,
2957
+
"gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user",
2958
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
2959
+
21, 0, 0),
2960
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4,
2961
+
"gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user",
2962
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
2963
+
21, 0, 0),
2964
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5,
2965
+
"gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user",
2966
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
2967
+
21, 0, 0),
2968
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6,
2969
+
"gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user",
2970
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
2971
+
21, 0, 0),
2972
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7,
2973
+
"gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user",
2974
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
2975
+
21, 0, 0),
2976
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8,
2977
+
"gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user",
2978
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
2979
+
21, 0, 0),
2980
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9,
2981
+
"gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user",
2982
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
2983
+
21, 0, 0),
2984
+
/* Disabling this clock makes the system hang. Mark the clock as critical. */
2985
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
2986
+
"gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart",
2987
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
2988
+
21, CLK_IS_CRITICAL, 0),
2989
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
2990
+
"gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
2991
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
2992
+
21, 0, 0),
2993
+
/* Disabling this clock makes the system hang. Mark the clock as critical. */
2994
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
2995
+
"gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
2996
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
2997
+
21, CLK_IS_CRITICAL, 0),
2998
+
GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
2999
+
"gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user",
3000
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
3001
+
21, 0, 0),
3002
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK,
3003
+
"gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user",
3004
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
3005
+
21, 0, 0),
3006
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK,
3007
+
"gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c",
3008
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
3009
+
21, 0, 0),
3010
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK,
3011
+
"gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart",
3012
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
3013
+
21, 0, 0),
3014
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK,
3015
+
"gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi",
3016
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
3017
+
21, 0, 0),
3018
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK,
3019
+
"gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi",
3020
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
3021
+
21, 0, 0),
3022
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK,
3023
+
"gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi",
3024
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
3025
+
21, 0, 0),
3026
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK,
3027
+
"gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi",
3028
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
3029
+
21, 0, 0),
3030
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK,
3031
+
"gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi",
3032
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
3033
+
21, 0, 0),
3034
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK,
3035
+
"gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi",
3036
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
3037
+
21, 0, 0),
3038
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK,
3039
+
"gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi",
3040
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
3041
+
21, 0, 0),
3042
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK,
3043
+
"gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi",
3044
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
3045
+
21, 0, 0),
3046
+
GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK,
3047
+
"gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi",
3048
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
3049
+
21, 0, 0),
3050
+
GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
3051
+
"gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user",
3052
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
3053
+
21, 0, 0),
3054
+
};
3055
+
3056
+
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
3057
+
.mux_clks = peric0_mux_clks,
3058
+
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
3059
+
.div_clks = peric0_div_clks,
3060
+
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
3061
+
.gate_clks = peric0_gate_clks,
3062
+
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
3063
+
.nr_clk_ids = CLKS_NR_PERIC0,
3064
+
.clk_regs = peric0_clk_regs,
3065
+
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
3066
+
.clk_name = "bus",
3067
+
};
3068
+
3069
+
/* ---- CMU_PERIC1 ---------------------------------------------------------- */
3070
+
3071
+
/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
3072
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
3073
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
3074
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
3075
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
3076
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
3077
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
3078
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
3079
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
3080
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
3081
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
3082
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
3083
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
3084
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
3085
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
3086
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
3087
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
3088
+
#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
3089
+
#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
3090
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
3091
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
3092
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
3093
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
3094
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
3095
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
3096
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
3097
+
#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
3098
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
3099
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
3100
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
3101
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
3102
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
3103
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
3104
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
3105
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
3106
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
3107
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
3108
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
3109
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
3110
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
3111
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
3112
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
3113
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
3114
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
3115
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
3116
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
3117
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
3118
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
3119
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
3120
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
3121
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
3122
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
3123
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
3124
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
3125
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
3126
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
3127
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
3128
+
#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
3129
+
#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
3130
+
#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
3131
+
#define QCH_CON_GPC_PERIC1_QCH 0x300c
3132
+
#define QCH_CON_GPIO_PERIC1_QCH 0x3010
3133
+
#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
3134
+
#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
3135
+
#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
3136
+
#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
3137
+
#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
3138
+
#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
3139
+
#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
3140
+
#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
3141
+
#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
3142
+
#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
3143
+
#define QCH_CON_SYSREG_PERIC1_QCH 0x303c
3144
+
#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
3145
+
3146
+
static const unsigned long peric1_clk_regs[] __initconst = {
3147
+
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
3148
+
PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
3149
+
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,
3150
+
PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,
3151
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,
3152
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,
3153
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
3154
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
3155
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
3156
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
3157
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
3158
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
3159
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,
3160
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,
3161
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,
3162
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,
3163
+
PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
3164
+
CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
3165
+
CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
3166
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,
3167
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
3168
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
3169
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
3170
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
3171
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,
3172
+
CLK_CON_BUF_CLKBUF_PERIC1_IP,
3173
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
3174
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
3175
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
3176
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
3177
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
3178
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
3179
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
3180
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
3181
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
3182
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
3183
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
3184
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
3185
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
3186
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
3187
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
3188
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
3189
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
3190
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
3191
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
3192
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
3193
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
3194
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
3195
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
3196
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
3197
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
3198
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
3199
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
3200
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
3201
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
3202
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
3203
+
DMYQCH_CON_PERIC1_TOP0_QCH_S,
3204
+
PCH_CON_LHM_AXI_P_PERIC1_PCH,
3205
+
QCH_CON_D_TZPC_PERIC1_QCH,
3206
+
QCH_CON_GPC_PERIC1_QCH,
3207
+
QCH_CON_GPIO_PERIC1_QCH,
3208
+
QCH_CON_LHM_AXI_P_PERIC1_QCH,
3209
+
QCH_CON_PERIC1_CMU_PERIC1_QCH,
3210
+
QCH_CON_PERIC1_TOP0_QCH_I3C0,
3211
+
QCH_CON_PERIC1_TOP0_QCH_PWM,
3212
+
QCH_CON_PERIC1_TOP0_QCH_USI0_USI,
3213
+
QCH_CON_PERIC1_TOP0_QCH_USI10_USI,
3214
+
QCH_CON_PERIC1_TOP0_QCH_USI11_USI,
3215
+
QCH_CON_PERIC1_TOP0_QCH_USI12_USI,
3216
+
QCH_CON_PERIC1_TOP0_QCH_USI13_USI,
3217
+
QCH_CON_PERIC1_TOP0_QCH_USI9_USI,
3218
+
QCH_CON_SYSREG_PERIC1_QCH,
3219
+
QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,
3220
+
};
3221
+
3222
+
/* List of parent clocks for Muxes in CMU_PERIC1 */
3223
+
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
3224
+
PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
3225
+
3226
+
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
3227
+
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
3228
+
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
3229
+
MUX(CLK_MOUT_PERIC1_I3C_USER,
3230
+
"mout_peric1_i3c_user", mout_peric1_nonbususer_p,
3231
+
PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
3232
+
MUX(CLK_MOUT_PERIC1_USI0_USI_USER,
3233
+
"mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
3234
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
3235
+
MUX(CLK_MOUT_PERIC1_USI10_USI_USER,
3236
+
"mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
3237
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
3238
+
MUX(CLK_MOUT_PERIC1_USI11_USI_USER,
3239
+
"mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
3240
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
3241
+
MUX(CLK_MOUT_PERIC1_USI12_USI_USER,
3242
+
"mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
3243
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
3244
+
MUX(CLK_MOUT_PERIC1_USI13_USI_USER,
3245
+
"mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
3246
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
3247
+
MUX(CLK_MOUT_PERIC1_USI9_USI_USER,
3248
+
"mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
3249
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
3250
+
};
3251
+
3252
+
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
3253
+
DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
3254
+
CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
3255
+
DIV(CLK_DOUT_PERIC1_USI0_USI,
3256
+
"dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
3257
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),
3258
+
DIV(CLK_DOUT_PERIC1_USI10_USI,
3259
+
"dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
3260
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),
3261
+
DIV(CLK_DOUT_PERIC1_USI11_USI,
3262
+
"dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
3263
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),
3264
+
DIV(CLK_DOUT_PERIC1_USI12_USI,
3265
+
"dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
3266
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),
3267
+
DIV(CLK_DOUT_PERIC1_USI13_USI,
3268
+
"dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
3269
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),
3270
+
DIV(CLK_DOUT_PERIC1_USI9_USI,
3271
+
"dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
3272
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),
3273
+
};
3274
+
3275
+
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
3276
+
GATE(CLK_GOUT_PERIC1_PCLK,
3277
+
"gout_peric1_peric1_pclk", "mout_peric1_bus_user",
3278
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
3279
+
21, CLK_IS_CRITICAL, 0),
3280
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
3281
+
"gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",
3282
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
3283
+
21, 0, 0),
3284
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
3285
+
"gout_peric1_clk_peric1_oscclk_clk", "oscclk",
3286
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
3287
+
21, 0, 0),
3288
+
GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
3289
+
"gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",
3290
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
3291
+
21, 0, 0),
3292
+
GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
3293
+
"gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",
3294
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
3295
+
21, 0, 0),
3296
+
GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
3297
+
"gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
3298
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
3299
+
21, CLK_IGNORE_UNUSED, 0),
3300
+
GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
3301
+
"gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
3302
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
3303
+
21, CLK_IS_CRITICAL, 0),
3304
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
3305
+
"gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
3306
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
3307
+
21, 0, 0),
3308
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
3309
+
"gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
3310
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
3311
+
21, 0, 0),
3312
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
3313
+
"gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
3314
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
3315
+
21, 0, 0),
3316
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
3317
+
"gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
3318
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
3319
+
21, 0, 0),
3320
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
3321
+
"gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
3322
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
3323
+
21, 0, 0),
3324
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
3325
+
"gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
3326
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
3327
+
21, 0, 0),
3328
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
3329
+
"gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
3330
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
3331
+
21, 0, 0),
3332
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
3333
+
"gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",
3334
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
3335
+
21, 0, 0),
3336
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
3337
+
"gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",
3338
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
3339
+
21, 0, 0),
3340
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
3341
+
"gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",
3342
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
3343
+
21, 0, 0),
3344
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
3345
+
"gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",
3346
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
3347
+
21, 0, 0),
3348
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
3349
+
"gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",
3350
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
3351
+
21, 0, 0),
3352
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
3353
+
"gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",
3354
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
3355
+
21, 0, 0),
3356
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
3357
+
"gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",
3358
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
3359
+
21, 0, 0),
3360
+
GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
3361
+
"gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",
3362
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
3363
+
21, 0, 0),
3364
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
3365
+
"gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",
3366
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
3367
+
21, 0, 0),
3368
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
3369
+
"gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",
3370
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
3371
+
21, 0, 0),
3372
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
3373
+
"gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",
3374
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
3375
+
21, 0, 0),
3376
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
3377
+
"gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",
3378
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
3379
+
21, 0, 0),
3380
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
3381
+
"gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",
3382
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
3383
+
21, 0, 0),
3384
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
3385
+
"gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",
3386
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
3387
+
21, 0, 0),
3388
+
GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
3389
+
"gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",
3390
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
3391
+
21, 0, 0),
3392
+
GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
3393
+
"gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
3394
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
3395
+
21, 0, 0),
3396
+
};
3397
+
3398
+
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
3399
+
.mux_clks = peric1_mux_clks,
3400
+
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
3401
+
.div_clks = peric1_div_clks,
3402
+
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
3403
+
.gate_clks = peric1_gate_clks,
3404
+
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
3405
+
.nr_clk_ids = CLKS_NR_PERIC1,
3406
+
.clk_regs = peric1_clk_regs,
3407
+
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
3408
+
.clk_name = "bus",
2480
3409
};
2481
3410
2482
3411
/* ---- platform_driver ----------------------------------------------------- */
···
3427
2496
.compatible = "google,gs101-cmu-apm",
3428
2497
.data = &apm_cmu_info,
3429
2498
}, {
3430
-
.compatible = "google,gs101-cmu-misc",
3431
-
.data = &misc_cmu_info,
2499
+
.compatible = "google,gs101-cmu-peric0",
2500
+
.data = &peric0_cmu_info,
2501
+
}, {
2502
+
.compatible = "google,gs101-cmu-peric1",
2503
+
.data = &peric1_cmu_info,
3432
2504
}, {
3433
2505
},
3434
2506
};
+4
-1
drivers/clk/samsung/clk.h
+4
-1
drivers/clk/samsung/clk.h
···
12
12
13
13
#include <linux/clk-provider.h>
14
14
#include "clk-pll.h"
15
+
#include "clk-cpu.h"
15
16
16
17
/**
17
18
* struct samsung_clk_provider - information about clock provider
···
283
282
unsigned int alt_parent_id;
284
283
unsigned long flags;
285
284
int offset;
285
+
enum exynos_cpuclk_layout reg_layout;
286
286
const struct exynos_cpuclk_cfg_data *cfg;
287
287
};
288
288
289
-
#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _cfg) \
289
+
#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _layout, _cfg) \
290
290
{ \
291
291
.id = _id, \
292
292
.name = _name, \
···
295
293
.alt_parent_id = _apid, \
296
294
.flags = _flags, \
297
295
.offset = _offset, \
296
+
.reg_layout = _layout, \
298
297
.cfg = _cfg, \
299
298
}
300
299
+56
include/dt-bindings/clock/exynos850.h
+56
include/dt-bindings/clock/exynos850.h
···
88
88
#define CLK_MOUT_G3D_SWITCH 76
89
89
#define CLK_GOUT_G3D_SWITCH 77
90
90
#define CLK_DOUT_G3D_SWITCH 78
91
+
#define CLK_MOUT_CPUCL0_DBG 79
92
+
#define CLK_MOUT_CPUCL0_SWITCH 80
93
+
#define CLK_GOUT_CPUCL0_DBG 81
94
+
#define CLK_GOUT_CPUCL0_SWITCH 82
95
+
#define CLK_DOUT_CPUCL0_DBG 83
96
+
#define CLK_DOUT_CPUCL0_SWITCH 84
97
+
#define CLK_MOUT_CPUCL1_DBG 85
98
+
#define CLK_MOUT_CPUCL1_SWITCH 86
99
+
#define CLK_GOUT_CPUCL1_DBG 87
100
+
#define CLK_GOUT_CPUCL1_SWITCH 88
101
+
#define CLK_DOUT_CPUCL1_DBG 89
102
+
#define CLK_DOUT_CPUCL1_SWITCH 90
91
103
92
104
/* CMU_APM */
93
105
#define CLK_RCO_I3C_PMIC 1
···
206
194
#define CLK_GOUT_CMGP_USI1_IPCLK 13
207
195
#define CLK_GOUT_CMGP_USI1_PCLK 14
208
196
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
197
+
198
+
/* CMU_CPUCL0 */
199
+
#define CLK_FOUT_CPUCL0_PLL 1
200
+
#define CLK_MOUT_PLL_CPUCL0 2
201
+
#define CLK_MOUT_CPUCL0_SWITCH_USER 3
202
+
#define CLK_MOUT_CPUCL0_DBG_USER 4
203
+
#define CLK_MOUT_CPUCL0_PLL 5
204
+
#define CLK_DOUT_CPUCL0_CPU 6
205
+
#define CLK_DOUT_CPUCL0_CMUREF 7
206
+
#define CLK_DOUT_CPUCL0_PCLK 8
207
+
#define CLK_DOUT_CLUSTER0_ACLK 9
208
+
#define CLK_DOUT_CLUSTER0_ATCLK 10
209
+
#define CLK_DOUT_CLUSTER0_PCLKDBG 11
210
+
#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
211
+
#define CLK_GOUT_CLUSTER0_ATCLK 13
212
+
#define CLK_GOUT_CLUSTER0_PCLK 14
213
+
#define CLK_GOUT_CLUSTER0_PERIPHCLK 15
214
+
#define CLK_GOUT_CLUSTER0_SCLK 16
215
+
#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17
216
+
#define CLK_GOUT_CLUSTER0_CPU 18
217
+
#define CLK_CLUSTER0_SCLK 19
218
+
219
+
/* CMU_CPUCL1 */
220
+
#define CLK_FOUT_CPUCL1_PLL 1
221
+
#define CLK_MOUT_PLL_CPUCL1 2
222
+
#define CLK_MOUT_CPUCL1_SWITCH_USER 3
223
+
#define CLK_MOUT_CPUCL1_DBG_USER 4
224
+
#define CLK_MOUT_CPUCL1_PLL 5
225
+
#define CLK_DOUT_CPUCL1_CPU 6
226
+
#define CLK_DOUT_CPUCL1_CMUREF 7
227
+
#define CLK_DOUT_CPUCL1_PCLK 8
228
+
#define CLK_DOUT_CLUSTER1_ACLK 9
229
+
#define CLK_DOUT_CLUSTER1_ATCLK 10
230
+
#define CLK_DOUT_CLUSTER1_PCLKDBG 11
231
+
#define CLK_DOUT_CLUSTER1_PERIPHCLK 12
232
+
#define CLK_GOUT_CLUSTER1_ATCLK 13
233
+
#define CLK_GOUT_CLUSTER1_PCLK 14
234
+
#define CLK_GOUT_CLUSTER1_PERIPHCLK 15
235
+
#define CLK_GOUT_CLUSTER1_SCLK 16
236
+
#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17
237
+
#define CLK_GOUT_CLUSTER1_CPU 18
238
+
#define CLK_CLUSTER1_SCLK 19
209
239
210
240
/* CMU_G3D */
211
241
#define CLK_FOUT_G3D_PLL 1
···
374
320
#define CLK_GOUT_SSS_PCLK 12
375
321
#define CLK_GOUT_GPIO_CORE_PCLK 13
376
322
#define CLK_GOUT_SYSREG_CORE_PCLK 14
323
+
#define CLK_GOUT_PDMA_CORE_ACLK 15
324
+
#define CLK_GOUT_SPDMA_CORE_ACLK 16
377
325
378
326
/* CMU_DPU */
379
327
#define CLK_MOUT_DPU_USER 1
+129
include/dt-bindings/clock/google,gs101.h
+129
include/dt-bindings/clock/google,gs101.h
···
389
389
#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
390
390
#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
391
391
392
+
/* CMU_PERIC0 */
393
+
#define CLK_MOUT_PERIC0_BUS_USER 1
394
+
#define CLK_MOUT_PERIC0_I3C_USER 2
395
+
#define CLK_MOUT_PERIC0_USI0_UART_USER 3
396
+
#define CLK_MOUT_PERIC0_USI14_USI_USER 4
397
+
#define CLK_MOUT_PERIC0_USI1_USI_USER 5
398
+
#define CLK_MOUT_PERIC0_USI2_USI_USER 6
399
+
#define CLK_MOUT_PERIC0_USI3_USI_USER 7
400
+
#define CLK_MOUT_PERIC0_USI4_USI_USER 8
401
+
#define CLK_MOUT_PERIC0_USI5_USI_USER 9
402
+
#define CLK_MOUT_PERIC0_USI6_USI_USER 10
403
+
#define CLK_MOUT_PERIC0_USI7_USI_USER 11
404
+
#define CLK_MOUT_PERIC0_USI8_USI_USER 12
405
+
#define CLK_DOUT_PERIC0_I3C 13
406
+
#define CLK_DOUT_PERIC0_USI0_UART 14
407
+
#define CLK_DOUT_PERIC0_USI14_USI 15
408
+
#define CLK_DOUT_PERIC0_USI1_USI 16
409
+
#define CLK_DOUT_PERIC0_USI2_USI 17
410
+
#define CLK_DOUT_PERIC0_USI3_USI 18
411
+
#define CLK_DOUT_PERIC0_USI4_USI 19
412
+
#define CLK_DOUT_PERIC0_USI5_USI 20
413
+
#define CLK_DOUT_PERIC0_USI6_USI 21
414
+
#define CLK_DOUT_PERIC0_USI7_USI 22
415
+
#define CLK_DOUT_PERIC0_USI8_USI 23
416
+
#define CLK_GOUT_PERIC0_IP 24
417
+
#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25
418
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26
419
+
#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27
420
+
#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28
421
+
#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29
422
+
#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30
423
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31
424
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32
425
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33
426
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34
427
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35
428
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36
429
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37
430
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38
431
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39
432
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40
433
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41
434
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42
435
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43
436
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44
437
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45
438
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46
439
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47
440
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48
441
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49
442
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50
443
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51
444
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52
445
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53
446
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54
447
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55
448
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56
449
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57
450
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58
451
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59
452
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60
453
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61
454
+
#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62
455
+
#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63
456
+
#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64
457
+
#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65
458
+
#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66
459
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67
460
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68
461
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69
462
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70
463
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71
464
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72
465
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73
466
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74
467
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75
468
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76
469
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77
470
+
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
471
+
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
472
+
473
+
/* CMU_PERIC1 */
474
+
#define CLK_MOUT_PERIC1_BUS_USER 1
475
+
#define CLK_MOUT_PERIC1_I3C_USER 2
476
+
#define CLK_MOUT_PERIC1_USI0_USI_USER 3
477
+
#define CLK_MOUT_PERIC1_USI10_USI_USER 4
478
+
#define CLK_MOUT_PERIC1_USI11_USI_USER 5
479
+
#define CLK_MOUT_PERIC1_USI12_USI_USER 6
480
+
#define CLK_MOUT_PERIC1_USI13_USI_USER 7
481
+
#define CLK_MOUT_PERIC1_USI9_USI_USER 8
482
+
#define CLK_DOUT_PERIC1_I3C 9
483
+
#define CLK_DOUT_PERIC1_USI0_USI 10
484
+
#define CLK_DOUT_PERIC1_USI10_USI 11
485
+
#define CLK_DOUT_PERIC1_USI11_USI 12
486
+
#define CLK_DOUT_PERIC1_USI12_USI 13
487
+
#define CLK_DOUT_PERIC1_USI13_USI 14
488
+
#define CLK_DOUT_PERIC1_USI9_USI 15
489
+
#define CLK_GOUT_PERIC1_IP 16
490
+
#define CLK_GOUT_PERIC1_PCLK 17
491
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
492
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
493
+
#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
494
+
#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
495
+
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
496
+
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
497
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
498
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
499
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
500
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
501
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
502
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
503
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
504
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
505
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
506
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
507
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
508
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
509
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
510
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
511
+
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
512
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
513
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
514
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
515
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
516
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
517
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
518
+
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
519
+
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
520
+
392
521
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
+1
-2
include/dt-bindings/clock/rockchip,rk3588-cru.h
+1
-2
include/dt-bindings/clock/rockchip,rk3588-cru.h
+12
include/linux/clk.h
+12
include/linux/clk.h
···
202
202
int clk_rate_exclusive_get(struct clk *clk);
203
203
204
204
/**
205
+
* devm_clk_rate_exclusive_get - devm variant of clk_rate_exclusive_get
206
+
* @dev: device the exclusivity is bound to
207
+
* @clk: clock source
208
+
*
209
+
* Calls clk_rate_exclusive_get() on @clk and registers a devm cleanup handler
210
+
* on @dev to call clk_rate_exclusive_put().
211
+
*
212
+
* Must not be called from within atomic context.
213
+
*/
214
+
int devm_clk_rate_exclusive_get(struct device *dev, struct clk *clk);
215
+
216
+
/**
205
217
* clk_rate_exclusive_put - release exclusivity over the rate control of a
206
218
* producer
207
219
* @clk: clock source