Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: qcs404: specify per-sensor calibration cells
Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-19-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
306ccdf0
4d403f7a
+140
-5
+140
-5
arch/arm64/boot/dts/qcom/qcs404.dtsi
+140
-5
arch/arm64/boot/dts/qcom/qcs404.dtsi
···
368
368
reg = <0x000a4000 0x1000>;
369
369
#address-cells = <1>;
370
370
#size-cells = <1>;
371
-
tsens_caldata: caldata@d0 {
372
-
reg = <0x1f8 0x14>;
373
-
};
374
371
cpr_efuse_speedbin: speedbin@13c {
375
372
reg = <0x13c 0x4>;
376
373
bits = <2 3>;
377
374
};
375
+
376
+
tsens_s0_p1: s0-p1@1f8 {
377
+
reg = <0x1f8 0x1>;
378
+
bits = <0 6>;
379
+
};
380
+
381
+
tsens_s0_p2: s0-p2@1f8 {
382
+
reg = <0x1f8 0x2>;
383
+
bits = <6 6>;
384
+
};
385
+
386
+
tsens_s1_p1: s1-p1@1f9 {
387
+
reg = <0x1f9 0x2>;
388
+
bits = <4 6>;
389
+
};
390
+
391
+
tsens_s1_p2: s1-p2@1fa {
392
+
reg = <0x1fa 0x1>;
393
+
bits = <2 6>;
394
+
};
395
+
396
+
tsens_s2_p1: s2-p1@1fb {
397
+
reg = <0x1fb 0x1>;
398
+
bits = <0 6>;
399
+
};
400
+
401
+
tsens_s2_p2: s2-p2@1fb {
402
+
reg = <0x1fb 0x2>;
403
+
bits = <6 6>;
404
+
};
405
+
406
+
tsens_s3_p1: s3-p1@1fc {
407
+
reg = <0x1fc 0x2>;
408
+
bits = <4 6>;
409
+
};
410
+
411
+
tsens_s3_p2: s3-p2@1fd {
412
+
reg = <0x1fd 0x1>;
413
+
bits = <2 6>;
414
+
};
415
+
416
+
tsens_s4_p1: s4-p1@1fe {
417
+
reg = <0x1fe 0x1>;
418
+
bits = <0 6>;
419
+
};
420
+
421
+
tsens_s4_p2: s4-p2@1fe {
422
+
reg = <0x1fe 0x2>;
423
+
bits = <6 6>;
424
+
};
425
+
426
+
tsens_s5_p1: s5-p1@200 {
427
+
reg = <0x200 0x1>;
428
+
bits = <0 6>;
429
+
};
430
+
431
+
tsens_s5_p2: s5-p2@200 {
432
+
reg = <0x200 0x2>;
433
+
bits = <6 6>;
434
+
};
435
+
436
+
tsens_s6_p1: s6-p1@201 {
437
+
reg = <0x201 0x2>;
438
+
bits = <4 6>;
439
+
};
440
+
441
+
tsens_s6_p2: s6-p2@202 {
442
+
reg = <0x202 0x1>;
443
+
bits = <2 6>;
444
+
};
445
+
446
+
tsens_s7_p1: s7-p1@203 {
447
+
reg = <0x203 0x1>;
448
+
bits = <0 6>;
449
+
};
450
+
451
+
tsens_s7_p2: s7-p2@203 {
452
+
reg = <0x203 0x2>;
453
+
bits = <6 6>;
454
+
};
455
+
456
+
tsens_s8_p1: s8-p1@204 {
457
+
reg = <0x204 0x2>;
458
+
bits = <4 6>;
459
+
};
460
+
461
+
tsens_s8_p2: s8-p2@205 {
462
+
reg = <0x205 0x1>;
463
+
bits = <2 6>;
464
+
};
465
+
466
+
tsens_s9_p1: s9-p1@206 {
467
+
reg = <0x206 0x1>;
468
+
bits = <0 6>;
469
+
};
470
+
471
+
tsens_s9_p2: s9-p2@206 {
472
+
reg = <0x206 0x2>;
473
+
bits = <6 6>;
474
+
};
475
+
476
+
tsens_mode: mode@208 {
477
+
reg = <0x208 1>;
478
+
bits = <0 3>;
479
+
};
480
+
481
+
tsens_base1: base1@208 {
482
+
reg = <0x208 2>;
483
+
bits = <3 8>;
484
+
};
485
+
486
+
tsens_base2: base2@208 {
487
+
reg = <0x209 2>;
488
+
bits = <3 8>;
489
+
};
490
+
378
491
cpr_efuse_quot_offset1: qoffset1@231 {
379
492
reg = <0x231 0x4>;
380
493
bits = <4 7>;
···
562
449
compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
563
450
reg = <0x004a9000 0x1000>, /* TM */
564
451
<0x004a8000 0x1000>; /* SROT */
565
-
nvmem-cells = <&tsens_caldata>;
566
-
nvmem-cell-names = "calib";
452
+
nvmem-cells = <&tsens_mode>,
453
+
<&tsens_base1>, <&tsens_base2>,
454
+
<&tsens_s0_p1>, <&tsens_s0_p2>,
455
+
<&tsens_s1_p1>, <&tsens_s1_p2>,
456
+
<&tsens_s2_p1>, <&tsens_s2_p2>,
457
+
<&tsens_s3_p1>, <&tsens_s3_p2>,
458
+
<&tsens_s4_p1>, <&tsens_s4_p2>,
459
+
<&tsens_s5_p1>, <&tsens_s5_p2>,
460
+
<&tsens_s6_p1>, <&tsens_s6_p2>,
461
+
<&tsens_s7_p1>, <&tsens_s7_p2>,
462
+
<&tsens_s8_p1>, <&tsens_s8_p2>,
463
+
<&tsens_s9_p1>, <&tsens_s9_p2>;
464
+
nvmem-cell-names = "mode",
465
+
"base1", "base2",
466
+
"s0_p1", "s0_p2",
467
+
"s1_p1", "s1_p2",
468
+
"s2_p1", "s2_p2",
469
+
"s3_p1", "s3_p2",
470
+
"s4_p1", "s4_p2",
471
+
"s5_p1", "s5_p2",
472
+
"s6_p1", "s6_p2",
473
+
"s7_p1", "s7_p2",
474
+
"s8_p1", "s8_p2",
475
+
"s9_p1", "s9_p2";
567
476
#qcom,sensors = <10>;
568
477
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
569
478
interrupt-names = "uplow";