Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: msm8976: specify per-sensor calibration cells
Specify pre-parsed per-sensor calibration nvmem cells in the tsens
device node rather than parsing the whole data blob in the driver.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230101194034.831222-18-dmitry.baryshkov@linaro.org
authored by
Dmitry Baryshkov
and committed by
Bjorn Andersson
4d403f7a
24aafd04
+149
-4
+149
-4
arch/arm64/boot/dts/qcom/msm8976.dtsi
+149
-4
arch/arm64/boot/dts/qcom/msm8976.dtsi
···
481
481
#address-cells = <1>;
482
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#size-cells = <1>;
483
483
484
-
tsens_caldata: caldata@218 {
485
-
reg = <0x218 0x18>;
484
+
tsens_base1: base1@218 {
485
+
reg = <0x218 1>;
486
+
bits = <0 8>;
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+
};
488
+
489
+
tsens_s0_p1: s0-p1@219 {
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+
reg = <0x219 0x1>;
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+
bits = <0 6>;
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+
};
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+
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+
tsens_s0_p2: s0-p2@219 {
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+
reg = <0x219 0x2>;
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+
bits = <6 6>;
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+
};
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+
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+
tsens_s1_p1: s1-p1@21a {
500
+
reg = <0x21a 0x2>;
501
+
bits = <4 6>;
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+
};
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+
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+
tsens_s1_p2: s1-p2@21b {
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+
reg = <0x21b 0x1>;
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+
bits = <2 6>;
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+
};
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+
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+
tsens_s2_p1: s2-p1@21c {
510
+
reg = <0x21c 0x1>;
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+
bits = <0 6>;
512
+
};
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+
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+
tsens_s2_p2: s2-p2@21c {
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+
reg = <0x21c 0x2>;
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+
bits = <6 6>;
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+
};
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+
519
+
tsens_s3_p1: s3-p1@21d {
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+
reg = <0x21d 0x2>;
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+
bits = <4 6>;
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+
};
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+
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+
tsens_s3_p2: s3-p2@21e {
525
+
reg = <0x21e 0x1>;
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+
bits = <2 6>;
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+
};
528
+
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+
tsens_base2: base2@220 {
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+
reg = <0x220 1>;
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+
bits = <0 8>;
532
+
};
533
+
534
+
tsens_s4_p1: s4-p1@221 {
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+
reg = <0x221 0x1>;
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+
bits = <0 6>;
537
+
};
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+
539
+
tsens_s4_p2: s4-p2@221 {
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+
reg = <0x221 0x2>;
541
+
bits = <6 6>;
542
+
};
543
+
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+
tsens_s5_p1: s5-p1@222 {
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+
reg = <0x222 0x2>;
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+
bits = <4 6>;
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+
};
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+
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+
tsens_s5_p2: s5-p2@223 {
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+
reg = <0x224 0x1>;
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+
bits = <2 6>;
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+
};
553
+
554
+
tsens_s6_p1: s6-p1@224 {
555
+
reg = <0x224 0x1>;
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+
bits = <0 6>;
557
+
};
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+
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+
tsens_s6_p2: s6-p2@224 {
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+
reg = <0x224 0x2>;
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+
bits = <6 6>;
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+
};
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+
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+
tsens_s7_p1: s7-p1@225 {
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+
reg = <0x225 0x2>;
566
+
bits = <4 6>;
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+
};
568
+
569
+
tsens_s7_p2: s7-p2@226 {
570
+
reg = <0x226 0x2>;
571
+
bits = <2 6>;
572
+
};
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+
574
+
tsens_mode: mode@228 {
575
+
reg = <0x228 1>;
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+
bits = <0 3>;
577
+
};
578
+
579
+
tsens_s8_p1: s8-p1@228 {
580
+
reg = <0x228 0x2>;
581
+
bits = <3 6>;
582
+
};
583
+
584
+
tsens_s8_p2: s8-p2@229 {
585
+
reg = <0x229 0x1>;
586
+
bits = <1 6>;
587
+
};
588
+
589
+
tsens_s9_p1: s9-p1@229 {
590
+
reg = <0x229 0x2>;
591
+
bits = <7 6>;
592
+
};
593
+
594
+
tsens_s9_p2: s9-p2@22a {
595
+
reg = <0x22a 0x2>;
596
+
bits = <5 6>;
597
+
};
598
+
599
+
tsens_s10_p1: s10-p1@22b {
600
+
reg = <0x22b 0x2>;
601
+
bits = <3 6>;
602
+
};
603
+
604
+
tsens_s10_p2: s10-p2@22c {
605
+
reg = <0x22c 0x1>;
606
+
bits = <1 6>;
486
607
};
487
608
};
488
609
···
613
492
<0x004a8000 0x1000>; /* SROT */
614
493
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
615
494
interrupt-names = "uplow";
616
-
nvmem-cells = <&tsens_caldata>;
617
-
nvmem-cell-names = "calib";
495
+
nvmem-cells = <&tsens_mode>,
496
+
<&tsens_base1>, <&tsens_base2>,
497
+
<&tsens_s0_p1>, <&tsens_s0_p2>,
498
+
<&tsens_s1_p1>, <&tsens_s1_p2>,
499
+
<&tsens_s2_p1>, <&tsens_s2_p2>,
500
+
<&tsens_s3_p1>, <&tsens_s3_p2>,
501
+
<&tsens_s4_p1>, <&tsens_s4_p2>,
502
+
<&tsens_s5_p1>, <&tsens_s5_p2>,
503
+
<&tsens_s6_p1>, <&tsens_s6_p2>,
504
+
<&tsens_s7_p1>, <&tsens_s7_p2>,
505
+
<&tsens_s8_p1>, <&tsens_s8_p2>,
506
+
<&tsens_s9_p1>, <&tsens_s9_p2>,
507
+
<&tsens_s10_p1>, <&tsens_s10_p2>;
508
+
nvmem-cell-names = "mode",
509
+
"base1", "base2",
510
+
"s0_p1", "s0_p2",
511
+
"s1_p1", "s1_p2",
512
+
"s2_p1", "s2_p2",
513
+
"s3_p1", "s3_p2",
514
+
"s4_p1", "s4_p2",
515
+
"s5_p1", "s5_p2",
516
+
"s6_p1", "s6_p2",
517
+
"s7_p1", "s7_p2",
518
+
"s8_p1", "s8_p2",
519
+
"s9_p1", "s9_p2",
520
+
"s10_p1", "s10_p2";
618
521
#qcom,sensors = <11>;
619
522
#thermal-sensor-cells = <1>;
620
523
};