Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: octeontx2 - support setting ctx ilen for inline CPT LF
Provide an option in Inline IPsec configure mailbox to configure the
CPT_AF_LFX_CTL:CTX_ILEN for inline CPT LF attached to CPT RVU PF.
This is needed to set the ctx ilen to size of inbound SA for
HW errata IPBUCPT-38756. Not setting this would lead to new context's
not being fetched.
Also set FLR_FLUSH in CPT_LF_CTX_CTL for CPT LF's as workaround
for same errata.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Nithin Dabilpuram
and committed by
Herbert Xu
3139ebf7
434c1cb9
+61
-1
+2
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+2
drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+3
-1
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
+3
-1
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
···
102
102
#define OTX2_CPT_LF_Q_INST_PTR (0x110)
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#define OTX2_CPT_LF_Q_GRP_PTR (0x120)
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#define OTX2_CPT_LF_NQX(a) (0x400 | (a) << 3)
105
+
#define OTX2_CPT_LF_CTX_CTL (0x500)
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#define OTX2_CPT_LF_CTX_FLUSH (0x510)
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#define OTX2_CPT_LF_CTX_ERR (0x520)
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#define OTX2_CPT_RVU_FUNC_BLKADDR_SHIFT 20
···
473
472
u64 cont_err:1;
474
473
u64 reserved_11_15:5;
475
474
u64 nixtx_en:1;
476
-
u64 reserved_17_47:31;
475
+
u64 ctx_ilen:3;
476
+
u64 reserved_17_47:28;
477
477
u64 grp:8;
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u64 reserved_56_63:8;
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} s;
+32
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
+32
drivers/crypto/marvell/octeontx2/otx2_cptlf.c
···
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return ret;
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}
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109
+
static int cptlf_set_ctx_ilen(struct otx2_cptlfs_info *lfs, int ctx_ilen)
110
+
{
111
+
union otx2_cptx_af_lf_ctrl lf_ctrl;
112
+
struct otx2_cptlf_info *lf;
113
+
int slot, ret = 0;
114
+
115
+
for (slot = 0; slot < lfs->lfs_num; slot++) {
116
+
lf = &lfs->lf[slot];
117
+
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+
ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,
119
+
CPT_AF_LFX_CTL(lf->slot),
120
+
&lf_ctrl.u, lfs->blkaddr);
121
+
if (ret)
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+
return ret;
123
+
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+
lf_ctrl.s.ctx_ilen = ctx_ilen;
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+
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+
ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,
127
+
CPT_AF_LFX_CTL(lf->slot),
128
+
lf_ctrl.u, lfs->blkaddr);
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+
if (ret)
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+
return ret;
131
+
}
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+
return ret;
133
+
}
134
+
109
135
static void cptlf_hw_init(struct otx2_cptlfs_info *lfs)
110
136
{
111
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/* Disable instruction queues */
···
468
442
ret = cptlf_set_grp_and_pri(lfs, eng_grp_mask, pri);
469
443
if (ret)
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goto free_iq;
445
+
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+
if (lfs->ctx_ilen_ovrd) {
447
+
ret = cptlf_set_ctx_ilen(lfs, lfs->ctx_ilen);
448
+
if (ret)
449
+
goto free_iq;
450
+
}
471
451
472
452
return 0;
473
453
+19
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+19
drivers/crypto/marvell/octeontx2/otx2_cptlf.h
···
121
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atomic_t state; /* LF's state. started/reset */
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int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */
123
123
int global_slot; /* Global slot across the blocks */
124
+
u8 ctx_ilen;
125
+
u8 ctx_ilen_ovrd;
124
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};
125
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126
128
static inline void otx2_cpt_free_instruction_queues(
···
312
310
OTX2_CPT_LF_INPROG, lf_inprog.u);
313
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}
314
312
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+
static inline void otx2_cptlf_set_ctx_flr_flush(struct otx2_cptlf_info *lf)
314
+
{
315
+
u8 blkaddr = lf->lfs->blkaddr;
316
+
u64 val;
317
+
318
+
val = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,
319
+
OTX2_CPT_LF_CTX_CTL);
320
+
val |= BIT_ULL(0);
321
+
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+
otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,
323
+
OTX2_CPT_LF_CTX_CTL, val);
324
+
}
325
+
315
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static inline void otx2_cptlf_enable_iqueue_exec(struct otx2_cptlf_info *lf)
316
327
{
317
328
otx2_cptlf_set_iqueue_exec(lf, true);
···
340
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int slot;
341
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342
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for (slot = 0; slot < lfs->lfs_num; slot++) {
328
+
/* Enable flush on FLR for Errata */
329
+
if (is_dev_cn10kb(lfs->pdev))
330
+
otx2_cptlf_set_ctx_flr_flush(&lfs->lf[slot]);
331
+
343
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otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);
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otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);
345
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}
+5
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+5
drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
···
267
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otx2_cptlf_set_dev_info(&cptpf->lfs, cptpf->pdev, cptpf->reg_base,
268
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&cptpf->afpf_mbox, BLKADDR_CPT0);
269
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cptpf->lfs.global_slot = 0;
270
+
cptpf->lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid;
271
+
cptpf->lfs.ctx_ilen = cfg_req->ctx_ilen;
272
+
270
273
ret = otx2_inline_cptlf_setup(cptpf, &cptpf->lfs, egrp, num_lfs);
271
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if (ret) {
272
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dev_err(&cptpf->pdev->dev, "Inline-Ipsec CPT0 LF setup failed.\n");
···
282
279
cptpf->reg_base, &cptpf->afpf_mbox,
283
280
BLKADDR_CPT1);
284
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cptpf->cpt1_lfs.global_slot = num_lfs;
282
+
cptpf->cpt1_lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid;
283
+
cptpf->cpt1_lfs.ctx_ilen = cfg_req->ctx_ilen;
285
284
ret = otx2_inline_cptlf_setup(cptpf, &cptpf->cpt1_lfs, egrp,
286
285
num_lfs);
287
286
if (ret) {