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spi: cadence-qspi: Kill cqspi_jh7110_clk_init

This controller can be fed by either a main "ref" clock, or three clocks
("ref" again, "ahb", "apb"). In practice, it is likely that all
controllers have the same inputs, but a single clock feeds the three
interfaces (ref is used for controlling the external interface, ahb/apb
the internal ones). Handling these clocks is in no way SoC specific,
only the number of expected clocks may change. Plus, we will soon be
adding another controller requiring an AHB and an APB clock as well, so
it is time to align the whole clock handling.

Furthermore, the use of the cqspi_jh7110_clk_init() helper, which
specifically grabs and enables the "ahb" and "apb" clocks, is a bit
convoluted:
- only the JH7110 compatible provides the ->jh7110_clk_init() callback,
- in the probe, if the above callback is set in the driver data, the
driver does not call the callback (!) but instead calls the helper
directly (?),
- in the helper, the is_jh7110 boolean is set.

This logic does not make sense. Instead:
- in the probe, set the is_jh7110 boolean based on the compatible,
- collect all available clocks with the "bulk" helper,
- enable the extra clocks if they are available,
- kill the SoC specific cqspi_jh7110_clk_init() helper.

This also allows to group the clock handling instead of depending on the
driver data pointer, which further simplifies the error path and the
remove callback.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260205-schneider-6-19-rc1-qspi-v5-2-843632b3c674@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Miquel Raynal (Schneider Electric) and committed by
Mark Brown
324ecc77 2b97f5cd

+29 -83
+29 -83
drivers/spi/spi-cadence-quadspi.c
··· 57 57 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 58 58 59 59 enum { 60 - CLK_QSPI_APB = 0, 60 + CLK_QSPI_REF = 0, 61 + CLK_QSPI_APB, 61 62 CLK_QSPI_AHB, 62 63 CLK_QSPI_NUM, 63 64 }; ··· 79 78 struct cqspi_st { 80 79 struct platform_device *pdev; 81 80 struct spi_controller *host; 82 - struct clk *clk; 83 - struct clk *clks[CLK_QSPI_NUM]; 81 + struct clk_bulk_data clks[CLK_QSPI_NUM]; 84 82 unsigned int sclk; 85 83 86 84 void __iomem *iobase; ··· 123 123 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 124 124 u_char *rxbuf, loff_t from_addr, size_t n_rx); 125 125 u32 (*get_dma_status)(struct cqspi_st *cqspi); 126 - int (*jh7110_clk_init)(struct platform_device *pdev, 127 - struct cqspi_st *cqspi); 128 126 }; 129 127 130 128 /* Operation timeout value */ ··· 1769 1771 return 0; 1770 1772 } 1771 1773 1772 - static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi) 1773 - { 1774 - static struct clk_bulk_data qspiclk[] = { 1775 - { .id = "apb" }, 1776 - { .id = "ahb" }, 1777 - }; 1778 - 1779 - int ret = 0; 1780 - 1781 - ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); 1782 - if (ret) { 1783 - dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); 1784 - return ret; 1785 - } 1786 - 1787 - cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; 1788 - cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; 1789 - 1790 - ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); 1791 - if (ret) { 1792 - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); 1793 - return ret; 1794 - } 1795 - 1796 - ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); 1797 - if (ret) { 1798 - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); 1799 - goto disable_apb_clk; 1800 - } 1801 - 1802 - cqspi->is_jh7110 = true; 1803 - 1804 - return 0; 1805 - 1806 - disable_apb_clk: 1807 - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); 1808 - 1809 - return ret; 1810 - } 1811 - 1812 - static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi) 1813 - { 1814 - clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); 1815 - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); 1816 - } 1817 1774 static int cqspi_probe(struct platform_device *pdev) 1818 1775 { 1819 1776 const struct cqspi_driver_platdata *ddata; ··· 1777 1824 struct spi_controller *host; 1778 1825 struct resource *res_ahb; 1779 1826 struct cqspi_st *cqspi; 1780 - int ret; 1781 - int irq; 1827 + int ret, irq; 1782 1828 1783 1829 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); 1784 1830 if (!host) ··· 1788 1836 host->mem_caps = &cqspi_mem_caps; 1789 1837 1790 1838 cqspi = spi_controller_get_devdata(host); 1839 + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) 1840 + cqspi->is_jh7110 = true; 1791 1841 1792 1842 cqspi->pdev = pdev; 1793 1843 cqspi->host = host; 1794 - cqspi->is_jh7110 = false; 1795 1844 cqspi->ddata = ddata = of_device_get_match_data(dev); 1796 1845 platform_set_drvdata(pdev, cqspi); 1797 1846 ··· 1809 1856 return ret; 1810 1857 } 1811 1858 1812 - /* Obtain QSPI clock. */ 1813 - cqspi->clk = devm_clk_get(dev, NULL); 1814 - if (IS_ERR(cqspi->clk)) { 1815 - dev_err(dev, "Cannot claim QSPI clock.\n"); 1816 - ret = PTR_ERR(cqspi->clk); 1817 - return ret; 1859 + /* Obtain QSPI clocks. */ 1860 + ret = devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); 1861 + if (ret) 1862 + return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1863 + 1864 + if (!cqspi->clks[CLK_QSPI_REF].clk) { 1865 + dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); 1866 + return -ENODEV; 1818 1867 } 1819 1868 1820 1869 /* Obtain and remap controller address. */ ··· 1848 1893 if (ret) 1849 1894 return ret; 1850 1895 1851 - 1852 - ret = clk_prepare_enable(cqspi->clk); 1896 + ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 1853 1897 if (ret) { 1854 - dev_err(dev, "Cannot enable QSPI clock.\n"); 1898 + dev_err(dev, "Cannot enable QSPI clocks.\n"); 1855 1899 goto disable_rpm; 1856 1900 } 1857 1901 ··· 1859 1905 if (IS_ERR(rstc)) { 1860 1906 ret = PTR_ERR(rstc); 1861 1907 dev_err(dev, "Cannot get QSPI reset.\n"); 1862 - goto disable_clk; 1908 + goto disable_clks; 1863 1909 } 1864 1910 1865 1911 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1866 1912 if (IS_ERR(rstc_ocp)) { 1867 1913 ret = PTR_ERR(rstc_ocp); 1868 1914 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1869 - goto disable_clk; 1915 + goto disable_clks; 1870 1916 } 1871 1917 1872 - if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { 1918 + if (cqspi->is_jh7110) { 1873 1919 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1874 1920 if (IS_ERR(rstc_ref)) { 1875 1921 ret = PTR_ERR(rstc_ref); 1876 1922 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1877 - goto disable_clk; 1923 + goto disable_clks; 1878 1924 } 1879 1925 reset_control_assert(rstc_ref); 1880 1926 reset_control_deassert(rstc_ref); ··· 1886 1932 reset_control_assert(rstc_ocp); 1887 1933 reset_control_deassert(rstc_ocp); 1888 1934 1889 - cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1935 + cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); 1890 1936 host->max_speed_hz = cqspi->master_ref_clk_hz; 1891 1937 1892 1938 /* write completion is supported by default */ ··· 1912 1958 cqspi->slow_sram = true; 1913 1959 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) 1914 1960 cqspi->apb_ahb_hazard = true; 1915 - 1916 - if (ddata->jh7110_clk_init) { 1917 - ret = cqspi_jh7110_clk_init(pdev, cqspi); 1918 - if (ret) 1919 - goto disable_clk; 1920 - } 1921 1961 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) 1922 1962 cqspi->disable_stig_mode = true; 1923 1963 ··· 1977 2029 disable_controller: 1978 2030 cqspi_controller_enable(cqspi, 0); 1979 2031 disable_clks: 1980 - if (cqspi->is_jh7110) 1981 - cqspi_jh7110_disable_clk(pdev, cqspi); 1982 - disable_clk: 1983 2032 if (pm_runtime_get_sync(&pdev->dev) >= 0) 1984 - clk_disable_unprepare(cqspi->clk); 2033 + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 1985 2034 disable_rpm: 1986 2035 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 1987 2036 pm_runtime_disable(dev); ··· 2007 2062 2008 2063 cqspi_controller_enable(cqspi, 0); 2009 2064 2010 - if (cqspi->is_jh7110) 2011 - cqspi_jh7110_disable_clk(pdev, cqspi); 2012 2065 2013 2066 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2014 2067 ret = pm_runtime_get_sync(&pdev->dev); 2015 2068 2016 2069 if (ret >= 0) 2017 - clk_disable(cqspi->clk); 2070 + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2018 2071 2019 2072 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 2020 2073 pm_runtime_put_sync(&pdev->dev); ··· 2025 2082 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2026 2083 2027 2084 cqspi_controller_enable(cqspi, 0); 2028 - clk_disable_unprepare(cqspi->clk); 2085 + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2029 2086 return 0; 2030 2087 } 2031 2088 2032 2089 static int cqspi_runtime_resume(struct device *dev) 2033 2090 { 2034 2091 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2092 + int ret; 2035 2093 2036 - clk_prepare_enable(cqspi->clk); 2094 + ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 2095 + if (ret) 2096 + return ret; 2097 + 2037 2098 cqspi_wait_idle(cqspi); 2038 2099 cqspi_controller_enable(cqspi, 0); 2039 2100 cqspi_controller_init(cqspi); ··· 2120 2173 2121 2174 static const struct cqspi_driver_platdata jh7110_qspi = { 2122 2175 .quirks = CQSPI_DISABLE_DAC_MODE, 2123 - .jh7110_clk_init = cqspi_jh7110_clk_init, 2124 2176 }; 2125 2177 2126 2178 static const struct cqspi_driver_platdata pensando_cdns_qspi = {