Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
Program the rest of the LT Phy Non TBT PLL Enable sequence. This
can be done in a single patch since the rest of the prequistie
functions are already coded in.
Bspec: 74492, 69701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
+32
-2
+2
-2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+2
-2
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
408
408
__intel_cx0_write(encoder, lane, addr, val, committed);
409
409
}
410
410
411
-
static void intel_cx0_rmw(struct intel_encoder *encoder,
412
-
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
411
+
void intel_cx0_rmw(struct intel_encoder *encoder,
412
+
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
413
413
{
414
414
u8 lane;
415
415
+2
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+2
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
52
52
void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
53
53
bool intel_cx0_is_hdmi_frl(u32 clock);
54
54
u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);
55
+
void intel_cx0_rmw(struct intel_encoder *encoder,
56
+
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed);
55
57
void intel_cx0_write(struct intel_encoder *encoder,
56
58
u8 lane_mask, u16 addr, u8 data, bool committed);
57
59
int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
+28
drivers/gpu/drm/i915/display/intel_lt_phy.c
+28
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1509
1509
enum phy phy = intel_encoder_to_phy(encoder);
1510
1510
enum port port = encoder->port;
1511
1511
intel_wakeref_t wakeref = 0;
1512
+
u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES
1513
+
? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) |
1514
+
XE3PLPDP_LANE_PHY_PULSE_STATUS(1))
1515
+
: XE3PLPDP_LANE_PHY_PULSE_STATUS(0);
1516
+
u8 rate_update;
1512
1517
1513
1518
wakeref = intel_lt_phy_transaction_begin(encoder);
1514
1519
···
1568
1563
* Change. We handle this step in bxt_set_cdclk().
1569
1564
*/
1570
1565
/* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */
1566
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
1567
+
crtc_state->port_clock);
1568
+
1571
1569
/* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */
1572
1570
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
1573
1571
XELPDP_LANE_PCLK_PLL_REQUEST(0),
···
1593
1585
XELPDP_FORWARD_CLOCK_UNGATE);
1594
1586
1595
1587
/* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
1588
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
1589
+
lane_phy_pulse_status,
1590
+
lane_phy_pulse_status);
1596
1591
/*
1597
1592
* 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for
1598
1593
* Owned PHY Lanes.
1599
1594
*/
1595
+
rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);
1596
+
rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
1597
+
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE,
1598
+
rate_update, MB_WRITE_COMMITTED);
1599
+
1600
1600
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
1601
+
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
1602
+
lane_phy_pulse_status, lane_phy_pulse_status,
1603
+
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
1604
+
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
1605
+
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
1606
+
1601
1607
/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
1608
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
1609
+
lane_phy_pulse_status,
1610
+
lane_phy_pulse_status);
1611
+
1602
1612
/*
1603
1613
* 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.
1604
1614
* We handle this step in bxt_set_cdclk()
1605
1615
*/
1606
1616
/* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */
1617
+
intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask,
1618
+
XELPDP_P0_STATE_ACTIVE);
1607
1619
1608
1620
intel_lt_phy_transaction_end(encoder, wakeref);
1609
1621
}