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clk: qcom: gcc-msm8916: use parent_hws/_data instead of parent_names

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220704172453.838303-7-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson 342470f7 52a0a6cb

+349 -333
+349 -333
drivers/clk/qcom/gcc-msm8916.c
··· 52 52 .status_bit = 17, 53 53 .clkr.hw.init = &(struct clk_init_data){ 54 54 .name = "gpll0", 55 - .parent_names = (const char *[]){ "xo" }, 55 + .parent_data = &(const struct clk_parent_data){ 56 + .fw_name = "xo", .name = "xo_board", 57 + }, 56 58 .num_parents = 1, 57 59 .ops = &clk_pll_ops, 58 60 }, ··· 65 63 .enable_mask = BIT(0), 66 64 .hw.init = &(struct clk_init_data){ 67 65 .name = "gpll0_vote", 68 - .parent_names = (const char *[]){ "gpll0" }, 66 + .parent_hws = (const struct clk_hw*[]){ 67 + &gpll0.clkr.hw, 68 + }, 69 69 .num_parents = 1, 70 70 .ops = &clk_pll_vote_ops, 71 71 }, ··· 83 79 .status_bit = 17, 84 80 .clkr.hw.init = &(struct clk_init_data){ 85 81 .name = "gpll1", 86 - .parent_names = (const char *[]){ "xo" }, 82 + .parent_data = &(const struct clk_parent_data){ 83 + .fw_name = "xo", .name = "xo_board", 84 + }, 87 85 .num_parents = 1, 88 86 .ops = &clk_pll_ops, 89 87 }, ··· 96 90 .enable_mask = BIT(1), 97 91 .hw.init = &(struct clk_init_data){ 98 92 .name = "gpll1_vote", 99 - .parent_names = (const char *[]){ "gpll1" }, 93 + .parent_hws = (const struct clk_hw*[]){ 94 + &gpll1.clkr.hw, 95 + }, 100 96 .num_parents = 1, 101 97 .ops = &clk_pll_vote_ops, 102 98 }, ··· 114 106 .status_bit = 17, 115 107 .clkr.hw.init = &(struct clk_init_data){ 116 108 .name = "gpll2", 117 - .parent_names = (const char *[]){ "xo" }, 109 + .parent_data = &(const struct clk_parent_data){ 110 + .fw_name = "xo", .name = "xo_board", 111 + }, 118 112 .num_parents = 1, 119 113 .ops = &clk_pll_ops, 120 114 }, ··· 127 117 .enable_mask = BIT(2), 128 118 .hw.init = &(struct clk_init_data){ 129 119 .name = "gpll2_vote", 130 - .parent_names = (const char *[]){ "gpll2" }, 120 + .parent_hws = (const struct clk_hw*[]){ 121 + &gpll2.clkr.hw, 122 + }, 131 123 .num_parents = 1, 132 124 .ops = &clk_pll_vote_ops, 133 125 }, ··· 145 133 .status_bit = 17, 146 134 .clkr.hw.init = &(struct clk_init_data){ 147 135 .name = "bimc_pll", 148 - .parent_names = (const char *[]){ "xo" }, 136 + .parent_data = &(const struct clk_parent_data){ 137 + .fw_name = "xo", .name = "xo_board", 138 + }, 149 139 .num_parents = 1, 150 140 .ops = &clk_pll_ops, 151 141 }, ··· 158 144 .enable_mask = BIT(3), 159 145 .hw.init = &(struct clk_init_data){ 160 146 .name = "bimc_pll_vote", 161 - .parent_names = (const char *[]){ "bimc_pll" }, 147 + .parent_hws = (const struct clk_hw*[]){ 148 + &bimc_pll.clkr.hw, 149 + }, 162 150 .num_parents = 1, 163 151 .ops = &clk_pll_vote_ops, 164 152 }, ··· 171 155 { P_GPLL0, 1 }, 172 156 }; 173 157 174 - static const char * const gcc_xo_gpll0[] = { 175 - "xo", 176 - "gpll0_vote", 158 + static const struct clk_parent_data gcc_xo_gpll0[] = { 159 + { .fw_name = "xo", .name = "xo_board" }, 160 + { .hw = &gpll0_vote.hw }, 177 161 }; 178 162 179 163 static const struct parent_map gcc_xo_gpll0_bimc_map[] = { ··· 182 166 { P_BIMC, 2 }, 183 167 }; 184 168 185 - static const char * const gcc_xo_gpll0_bimc[] = { 186 - "xo", 187 - "gpll0_vote", 188 - "bimc_pll_vote", 169 + static const struct clk_parent_data gcc_xo_gpll0_bimc[] = { 170 + { .fw_name = "xo", .name = "xo_board" }, 171 + { .hw = &gpll0_vote.hw }, 172 + { .hw = &bimc_pll_vote.hw }, 189 173 }; 190 174 191 175 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { ··· 195 179 { P_GPLL2_AUX, 2 }, 196 180 }; 197 181 198 - static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { 199 - "xo", 200 - "gpll0_vote", 201 - "gpll1_vote", 202 - "gpll2_vote", 182 + static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2a[] = { 183 + { .fw_name = "xo", .name = "xo_board" }, 184 + { .hw = &gpll0_vote.hw }, 185 + { .hw = &gpll1_vote.hw }, 186 + { .hw = &gpll2_vote.hw }, 203 187 }; 204 188 205 189 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { ··· 208 192 { P_GPLL2, 2 }, 209 193 }; 210 194 211 - static const char * const gcc_xo_gpll0_gpll2[] = { 212 - "xo", 213 - "gpll0_vote", 214 - "gpll2_vote", 195 + static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { 196 + { .fw_name = "xo", .name = "xo_board" }, 197 + { .hw = &gpll0_vote.hw }, 198 + { .hw = &gpll2_vote.hw }, 215 199 }; 216 200 217 201 static const struct parent_map gcc_xo_gpll0a_map[] = { ··· 219 203 { P_GPLL0_AUX, 2 }, 220 204 }; 221 205 222 - static const char * const gcc_xo_gpll0a[] = { 223 - "xo", 224 - "gpll0_vote", 206 + static const struct clk_parent_data gcc_xo_gpll0a[] = { 207 + { .fw_name = "xo", .name = "xo_board" }, 208 + { .hw = &gpll0_vote.hw }, 225 209 }; 226 210 227 211 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { ··· 231 215 { P_SLEEP_CLK, 6 }, 232 216 }; 233 217 234 - static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { 235 - "xo", 236 - "gpll0_vote", 237 - "gpll1_vote", 238 - "sleep_clk", 218 + static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep[] = { 219 + { .fw_name = "xo", .name = "xo_board" }, 220 + { .hw = &gpll0_vote.hw }, 221 + { .hw = &gpll1_vote.hw }, 222 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 239 223 }; 240 224 241 225 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { ··· 244 228 { P_GPLL1_AUX, 2 }, 245 229 }; 246 230 247 - static const char * const gcc_xo_gpll0_gpll1a[] = { 248 - "xo", 249 - "gpll0_vote", 250 - "gpll1_vote", 231 + static const struct clk_parent_data gcc_xo_gpll0_gpll1a[] = { 232 + { .fw_name = "xo", .name = "xo_board" }, 233 + { .hw = &gpll0_vote.hw }, 234 + { .hw = &gpll1_vote.hw }, 251 235 }; 252 236 253 237 static const struct parent_map gcc_xo_dsibyte_map[] = { ··· 255 239 { P_DSI0_PHYPLL_BYTE, 2 }, 256 240 }; 257 241 258 - static const char * const gcc_xo_dsibyte[] = { 259 - "xo", 260 - "dsi0pllbyte", 242 + static const struct clk_parent_data gcc_xo_dsibyte[] = { 243 + { .fw_name = "xo", .name = "xo_board" }, 244 + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 261 245 }; 262 246 263 247 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { ··· 266 250 { P_DSI0_PHYPLL_BYTE, 1 }, 267 251 }; 268 252 269 - static const char * const gcc_xo_gpll0a_dsibyte[] = { 270 - "xo", 271 - "gpll0_vote", 272 - "dsi0pllbyte", 253 + static const struct clk_parent_data gcc_xo_gpll0a_dsibyte[] = { 254 + { .fw_name = "xo", .name = "xo_board" }, 255 + { .hw = &gpll0_vote.hw }, 256 + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, 273 257 }; 274 258 275 259 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { ··· 278 262 { P_DSI0_PHYPLL_DSI, 2 }, 279 263 }; 280 264 281 - static const char * const gcc_xo_gpll0_dsiphy[] = { 282 - "xo", 283 - "gpll0_vote", 284 - "dsi0pll", 265 + static const struct clk_parent_data gcc_xo_gpll0_dsiphy[] = { 266 + { .fw_name = "xo", .name = "xo_board" }, 267 + { .hw = &gpll0_vote.hw }, 268 + { .fw_name = "dsi0pll", .name = "dsi0pll" }, 285 269 }; 286 270 287 271 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { ··· 290 274 { P_DSI0_PHYPLL_DSI, 1 }, 291 275 }; 292 276 293 - static const char * const gcc_xo_gpll0a_dsiphy[] = { 294 - "xo", 295 - "gpll0_vote", 296 - "dsi0pll", 277 + static const struct clk_parent_data gcc_xo_gpll0a_dsiphy[] = { 278 + { .fw_name = "xo", .name = "xo_board" }, 279 + { .hw = &gpll0_vote.hw }, 280 + { .fw_name = "dsi0pll", .name = "dsi0pll" }, 297 281 }; 298 282 299 283 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { ··· 303 287 { P_GPLL2, 2 }, 304 288 }; 305 289 306 - static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { 307 - "xo", 308 - "gpll0_vote", 309 - "gpll1_vote", 310 - "gpll2_vote", 290 + static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2[] = { 291 + { .fw_name = "xo", .name = "xo_board" }, 292 + { .hw = &gpll0_vote.hw }, 293 + { .hw = &gpll1_vote.hw }, 294 + { .hw = &gpll2_vote.hw }, 311 295 }; 312 296 313 297 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { ··· 317 301 { P_SLEEP_CLK, 6 } 318 302 }; 319 303 320 - static const char * const gcc_xo_gpll0_gpll1_sleep[] = { 321 - "xo", 322 - "gpll0_vote", 323 - "gpll1_vote", 324 - "sleep_clk", 304 + static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = { 305 + { .fw_name = "xo", .name = "xo_board" }, 306 + { .hw = &gpll0_vote.hw }, 307 + { .hw = &gpll1_vote.hw }, 308 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 325 309 }; 326 310 327 311 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { ··· 332 316 { P_SLEEP_CLK, 6 } 333 317 }; 334 318 335 - static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { 336 - "xo", 337 - "gpll1_vote", 338 - "ext_pri_i2s", 339 - "ext_mclk", 340 - "sleep_clk", 319 + static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep[] = { 320 + { .fw_name = "xo", .name = "xo_board" }, 321 + { .hw = &gpll1_vote.hw }, 322 + { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" }, 323 + { .fw_name = "ext_mclk", .name = "ext_mclk" }, 324 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 341 325 }; 342 326 343 327 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { ··· 348 332 { P_SLEEP_CLK, 6 } 349 333 }; 350 334 351 - static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { 352 - "xo", 353 - "gpll1_vote", 354 - "ext_sec_i2s", 355 - "ext_mclk", 356 - "sleep_clk", 335 + static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep[] = { 336 + { .fw_name = "xo", .name = "xo_board" }, 337 + { .hw = &gpll1_vote.hw }, 338 + { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" }, 339 + { .fw_name = "ext_mclk", .name = "ext_mclk" }, 340 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 357 341 }; 358 342 359 343 static const struct parent_map gcc_xo_sleep_map[] = { ··· 361 345 { P_SLEEP_CLK, 6 } 362 346 }; 363 347 364 - static const char * const gcc_xo_sleep[] = { 365 - "xo", 366 - "sleep_clk", 348 + static const struct clk_parent_data gcc_xo_sleep[] = { 349 + { .fw_name = "xo", .name = "xo_board" }, 350 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 367 351 }; 368 352 369 353 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { ··· 373 357 { P_SLEEP_CLK, 6 } 374 358 }; 375 359 376 - static const char * const gcc_xo_gpll1_emclk_sleep[] = { 377 - "xo", 378 - "gpll1_vote", 379 - "ext_mclk", 380 - "sleep_clk", 360 + static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep[] = { 361 + { .fw_name = "xo", .name = "xo_board" }, 362 + { .hw = &gpll1_vote.hw }, 363 + { .fw_name = "ext_mclk", .name = "ext_mclk" }, 364 + { .fw_name = "sleep_clk", .name = "sleep_clk" }, 381 365 }; 382 366 383 367 static struct clk_rcg2 pcnoc_bfdcd_clk_src = { ··· 386 370 .parent_map = gcc_xo_gpll0_bimc_map, 387 371 .clkr.hw.init = &(struct clk_init_data){ 388 372 .name = "pcnoc_bfdcd_clk_src", 389 - .parent_names = gcc_xo_gpll0_bimc, 373 + .parent_data = gcc_xo_gpll0_bimc, 390 374 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 391 375 .ops = &clk_rcg2_ops, 392 376 }, ··· 398 382 .parent_map = gcc_xo_gpll0_bimc_map, 399 383 .clkr.hw.init = &(struct clk_init_data){ 400 384 .name = "system_noc_bfdcd_clk_src", 401 - .parent_names = gcc_xo_gpll0_bimc, 385 + .parent_data = gcc_xo_gpll0_bimc, 402 386 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 403 387 .ops = &clk_rcg2_ops, 404 388 }, ··· 418 402 .freq_tbl = ftbl_gcc_camss_ahb_clk, 419 403 .clkr.hw.init = &(struct clk_init_data){ 420 404 .name = "camss_ahb_clk_src", 421 - .parent_names = gcc_xo_gpll0, 405 + .parent_data = gcc_xo_gpll0, 422 406 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 423 407 .ops = &clk_rcg2_ops, 424 408 }, ··· 439 423 .freq_tbl = ftbl_apss_ahb_clk, 440 424 .clkr.hw.init = &(struct clk_init_data){ 441 425 .name = "apss_ahb_clk_src", 442 - .parent_names = gcc_xo_gpll0, 426 + .parent_data = gcc_xo_gpll0, 443 427 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 444 428 .ops = &clk_rcg2_ops, 445 429 }, ··· 458 442 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 459 443 .clkr.hw.init = &(struct clk_init_data){ 460 444 .name = "csi0_clk_src", 461 - .parent_names = gcc_xo_gpll0, 445 + .parent_data = gcc_xo_gpll0, 462 446 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 463 447 .ops = &clk_rcg2_ops, 464 448 }, ··· 471 455 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 472 456 .clkr.hw.init = &(struct clk_init_data){ 473 457 .name = "csi1_clk_src", 474 - .parent_names = gcc_xo_gpll0, 458 + .parent_data = gcc_xo_gpll0, 475 459 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 476 460 .ops = &clk_rcg2_ops, 477 461 }, ··· 499 483 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 500 484 .clkr.hw.init = &(struct clk_init_data){ 501 485 .name = "gfx3d_clk_src", 502 - .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 486 + .parent_data = gcc_xo_gpll0a_gpll1_gpll2a, 503 487 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a), 504 488 .ops = &clk_rcg2_ops, 505 489 }, ··· 526 510 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 527 511 .clkr.hw.init = &(struct clk_init_data){ 528 512 .name = "vfe0_clk_src", 529 - .parent_names = gcc_xo_gpll0_gpll2, 513 + .parent_data = gcc_xo_gpll0_gpll2, 530 514 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 531 515 .ops = &clk_rcg2_ops, 532 516 }, ··· 545 529 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 546 530 .clkr.hw.init = &(struct clk_init_data){ 547 531 .name = "blsp1_qup1_i2c_apps_clk_src", 548 - .parent_names = gcc_xo_gpll0, 532 + .parent_data = gcc_xo_gpll0, 549 533 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 550 534 .ops = &clk_rcg2_ops, 551 535 }, ··· 574 558 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 575 559 .clkr.hw.init = &(struct clk_init_data){ 576 560 .name = "blsp1_qup1_spi_apps_clk_src", 577 - .parent_names = gcc_xo_gpll0, 561 + .parent_data = gcc_xo_gpll0, 578 562 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 579 563 .ops = &clk_rcg2_ops, 580 564 }, ··· 587 571 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 588 572 .clkr.hw.init = &(struct clk_init_data){ 589 573 .name = "blsp1_qup2_i2c_apps_clk_src", 590 - .parent_names = gcc_xo_gpll0, 574 + .parent_data = gcc_xo_gpll0, 591 575 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 592 576 .ops = &clk_rcg2_ops, 593 577 }, ··· 601 585 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 602 586 .clkr.hw.init = &(struct clk_init_data){ 603 587 .name = "blsp1_qup2_spi_apps_clk_src", 604 - .parent_names = gcc_xo_gpll0, 588 + .parent_data = gcc_xo_gpll0, 605 589 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 606 590 .ops = &clk_rcg2_ops, 607 591 }, ··· 614 598 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 615 599 .clkr.hw.init = &(struct clk_init_data){ 616 600 .name = "blsp1_qup3_i2c_apps_clk_src", 617 - .parent_names = gcc_xo_gpll0, 601 + .parent_data = gcc_xo_gpll0, 618 602 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 619 603 .ops = &clk_rcg2_ops, 620 604 }, ··· 628 612 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 629 613 .clkr.hw.init = &(struct clk_init_data){ 630 614 .name = "blsp1_qup3_spi_apps_clk_src", 631 - .parent_names = gcc_xo_gpll0, 615 + .parent_data = gcc_xo_gpll0, 632 616 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 633 617 .ops = &clk_rcg2_ops, 634 618 }, ··· 641 625 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 642 626 .clkr.hw.init = &(struct clk_init_data){ 643 627 .name = "blsp1_qup4_i2c_apps_clk_src", 644 - .parent_names = gcc_xo_gpll0, 628 + .parent_data = gcc_xo_gpll0, 645 629 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 646 630 .ops = &clk_rcg2_ops, 647 631 }, ··· 655 639 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 656 640 .clkr.hw.init = &(struct clk_init_data){ 657 641 .name = "blsp1_qup4_spi_apps_clk_src", 658 - .parent_names = gcc_xo_gpll0, 642 + .parent_data = gcc_xo_gpll0, 659 643 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 660 644 .ops = &clk_rcg2_ops, 661 645 }, ··· 668 652 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 669 653 .clkr.hw.init = &(struct clk_init_data){ 670 654 .name = "blsp1_qup5_i2c_apps_clk_src", 671 - .parent_names = gcc_xo_gpll0, 655 + .parent_data = gcc_xo_gpll0, 672 656 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 673 657 .ops = &clk_rcg2_ops, 674 658 }, ··· 682 666 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 683 667 .clkr.hw.init = &(struct clk_init_data){ 684 668 .name = "blsp1_qup5_spi_apps_clk_src", 685 - .parent_names = gcc_xo_gpll0, 669 + .parent_data = gcc_xo_gpll0, 686 670 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 687 671 .ops = &clk_rcg2_ops, 688 672 }, ··· 695 679 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 696 680 .clkr.hw.init = &(struct clk_init_data){ 697 681 .name = "blsp1_qup6_i2c_apps_clk_src", 698 - .parent_names = gcc_xo_gpll0, 682 + .parent_data = gcc_xo_gpll0, 699 683 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 700 684 .ops = &clk_rcg2_ops, 701 685 }, ··· 709 693 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 710 694 .clkr.hw.init = &(struct clk_init_data){ 711 695 .name = "blsp1_qup6_spi_apps_clk_src", 712 - .parent_names = gcc_xo_gpll0, 696 + .parent_data = gcc_xo_gpll0, 713 697 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 714 698 .ops = &clk_rcg2_ops, 715 699 }, ··· 742 726 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 743 727 .clkr.hw.init = &(struct clk_init_data){ 744 728 .name = "blsp1_uart1_apps_clk_src", 745 - .parent_names = gcc_xo_gpll0, 729 + .parent_data = gcc_xo_gpll0, 746 730 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 747 731 .ops = &clk_rcg2_ops, 748 732 }, ··· 756 740 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 757 741 .clkr.hw.init = &(struct clk_init_data){ 758 742 .name = "blsp1_uart2_apps_clk_src", 759 - .parent_names = gcc_xo_gpll0, 743 + .parent_data = gcc_xo_gpll0, 760 744 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 761 745 .ops = &clk_rcg2_ops, 762 746 }, ··· 775 759 .freq_tbl = ftbl_gcc_camss_cci_clk, 776 760 .clkr.hw.init = &(struct clk_init_data){ 777 761 .name = "cci_clk_src", 778 - .parent_names = gcc_xo_gpll0a, 762 + .parent_data = gcc_xo_gpll0a, 779 763 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a), 780 764 .ops = &clk_rcg2_ops, 781 765 }, ··· 808 792 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 809 793 .clkr.hw.init = &(struct clk_init_data){ 810 794 .name = "camss_gp0_clk_src", 811 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 795 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 812 796 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 813 797 .ops = &clk_rcg2_ops, 814 798 }, ··· 822 806 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 823 807 .clkr.hw.init = &(struct clk_init_data){ 824 808 .name = "camss_gp1_clk_src", 825 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 809 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 826 810 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 827 811 .ops = &clk_rcg2_ops, 828 812 }, ··· 842 826 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 843 827 .clkr.hw.init = &(struct clk_init_data){ 844 828 .name = "jpeg0_clk_src", 845 - .parent_names = gcc_xo_gpll0, 829 + .parent_data = gcc_xo_gpll0, 846 830 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 847 831 .ops = &clk_rcg2_ops, 848 832 }, ··· 863 847 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 864 848 .clkr.hw.init = &(struct clk_init_data){ 865 849 .name = "mclk0_clk_src", 866 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 850 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 867 851 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 868 852 .ops = &clk_rcg2_ops, 869 853 }, ··· 877 861 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 878 862 .clkr.hw.init = &(struct clk_init_data){ 879 863 .name = "mclk1_clk_src", 880 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 864 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 881 865 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 882 866 .ops = &clk_rcg2_ops, 883 867 }, ··· 896 880 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 897 881 .clkr.hw.init = &(struct clk_init_data){ 898 882 .name = "csi0phytimer_clk_src", 899 - .parent_names = gcc_xo_gpll0_gpll1a, 883 + .parent_data = gcc_xo_gpll0_gpll1a, 900 884 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a), 901 885 .ops = &clk_rcg2_ops, 902 886 }, ··· 909 893 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 910 894 .clkr.hw.init = &(struct clk_init_data){ 911 895 .name = "csi1phytimer_clk_src", 912 - .parent_names = gcc_xo_gpll0_gpll1a, 896 + .parent_data = gcc_xo_gpll0_gpll1a, 913 897 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a), 914 898 .ops = &clk_rcg2_ops, 915 899 }, ··· 929 913 .freq_tbl = ftbl_gcc_camss_cpp_clk, 930 914 .clkr.hw.init = &(struct clk_init_data){ 931 915 .name = "cpp_clk_src", 932 - .parent_names = gcc_xo_gpll0_gpll2, 916 + .parent_data = gcc_xo_gpll0_gpll2, 933 917 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), 934 918 .ops = &clk_rcg2_ops, 935 919 }, ··· 950 934 .freq_tbl = ftbl_gcc_crypto_clk, 951 935 .clkr.hw.init = &(struct clk_init_data){ 952 936 .name = "crypto_clk_src", 953 - .parent_names = gcc_xo_gpll0, 937 + .parent_data = gcc_xo_gpll0, 954 938 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 955 939 .ops = &clk_rcg2_ops, 956 940 }, ··· 991 975 .freq_tbl = ftbl_gcc_gp1_3_clk, 992 976 .clkr.hw.init = &(struct clk_init_data){ 993 977 .name = "gp1_clk_src", 994 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 978 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 995 979 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 996 980 .ops = &clk_rcg2_ops, 997 981 }, ··· 1005 989 .freq_tbl = ftbl_gcc_gp1_3_clk, 1006 990 .clkr.hw.init = &(struct clk_init_data){ 1007 991 .name = "gp2_clk_src", 1008 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 992 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 1009 993 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 1010 994 .ops = &clk_rcg2_ops, 1011 995 }, ··· 1019 1003 .freq_tbl = ftbl_gcc_gp1_3_clk, 1020 1004 .clkr.hw.init = &(struct clk_init_data){ 1021 1005 .name = "gp3_clk_src", 1022 - .parent_names = gcc_xo_gpll0_gpll1a_sleep, 1006 + .parent_data = gcc_xo_gpll0_gpll1a_sleep, 1023 1007 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep), 1024 1008 .ops = &clk_rcg2_ops, 1025 1009 }, ··· 1031 1015 .parent_map = gcc_xo_gpll0a_dsibyte_map, 1032 1016 .clkr.hw.init = &(struct clk_init_data){ 1033 1017 .name = "byte0_clk_src", 1034 - .parent_names = gcc_xo_gpll0a_dsibyte, 1018 + .parent_data = gcc_xo_gpll0a_dsibyte, 1035 1019 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte), 1036 1020 .ops = &clk_byte2_ops, 1037 1021 .flags = CLK_SET_RATE_PARENT, ··· 1050 1034 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1051 1035 .clkr.hw.init = &(struct clk_init_data){ 1052 1036 .name = "esc0_clk_src", 1053 - .parent_names = gcc_xo_dsibyte, 1037 + .parent_data = gcc_xo_dsibyte, 1054 1038 .num_parents = ARRAY_SIZE(gcc_xo_dsibyte), 1055 1039 .ops = &clk_rcg2_ops, 1056 1040 }, ··· 1075 1059 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1076 1060 .clkr.hw.init = &(struct clk_init_data){ 1077 1061 .name = "mdp_clk_src", 1078 - .parent_names = gcc_xo_gpll0_dsiphy, 1062 + .parent_data = gcc_xo_gpll0_dsiphy, 1079 1063 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy), 1080 1064 .ops = &clk_rcg2_ops, 1081 1065 }, ··· 1088 1072 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1089 1073 .clkr.hw.init = &(struct clk_init_data){ 1090 1074 .name = "pclk0_clk_src", 1091 - .parent_names = gcc_xo_gpll0a_dsiphy, 1075 + .parent_data = gcc_xo_gpll0a_dsiphy, 1092 1076 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy), 1093 1077 .ops = &clk_pixel_ops, 1094 1078 .flags = CLK_SET_RATE_PARENT, ··· 1107 1091 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1108 1092 .clkr.hw.init = &(struct clk_init_data){ 1109 1093 .name = "vsync_clk_src", 1110 - .parent_names = gcc_xo_gpll0a, 1094 + .parent_data = gcc_xo_gpll0a, 1111 1095 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a), 1112 1096 .ops = &clk_rcg2_ops, 1113 1097 }, ··· 1125 1109 .freq_tbl = ftbl_gcc_pdm2_clk, 1126 1110 .clkr.hw.init = &(struct clk_init_data){ 1127 1111 .name = "pdm2_clk_src", 1128 - .parent_names = gcc_xo_gpll0, 1112 + .parent_data = gcc_xo_gpll0, 1129 1113 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1130 1114 .ops = &clk_rcg2_ops, 1131 1115 }, ··· 1150 1134 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1151 1135 .clkr.hw.init = &(struct clk_init_data){ 1152 1136 .name = "sdcc1_apps_clk_src", 1153 - .parent_names = gcc_xo_gpll0, 1137 + .parent_data = gcc_xo_gpll0, 1154 1138 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1155 1139 .ops = &clk_rcg2_floor_ops, 1156 1140 }, ··· 1175 1159 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1176 1160 .clkr.hw.init = &(struct clk_init_data){ 1177 1161 .name = "sdcc2_apps_clk_src", 1178 - .parent_names = gcc_xo_gpll0, 1162 + .parent_data = gcc_xo_gpll0, 1179 1163 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1180 1164 .ops = &clk_rcg2_floor_ops, 1181 1165 }, ··· 1195 1179 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1196 1180 .clkr.hw.init = &(struct clk_init_data){ 1197 1181 .name = "apss_tcu_clk_src", 1198 - .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1182 + .parent_data = gcc_xo_gpll0a_gpll1_gpll2, 1199 1183 .num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2), 1200 1184 .ops = &clk_rcg2_ops, 1201 1185 }, ··· 1218 1202 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1219 1203 .clkr.hw.init = &(struct clk_init_data){ 1220 1204 .name = "bimc_gpu_clk_src", 1221 - .parent_names = gcc_xo_gpll0_bimc, 1205 + .parent_data = gcc_xo_gpll0_bimc, 1222 1206 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 1223 1207 .flags = CLK_GET_RATE_NOCACHE, 1224 1208 .ops = &clk_rcg2_ops, ··· 1237 1221 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1238 1222 .clkr.hw.init = &(struct clk_init_data){ 1239 1223 .name = "usb_hs_system_clk_src", 1240 - .parent_names = gcc_xo_gpll0, 1224 + .parent_data = gcc_xo_gpll0, 1241 1225 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1242 1226 .ops = &clk_rcg2_ops, 1243 1227 }, ··· 1263 1247 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1264 1248 .clkr.hw.init = &(struct clk_init_data){ 1265 1249 .name = "ultaudio_ahbfabric_clk_src", 1266 - .parent_names = gcc_xo_gpll0_gpll1_sleep, 1250 + .parent_data = gcc_xo_gpll0_gpll1_sleep, 1267 1251 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep), 1268 1252 .ops = &clk_rcg2_ops, 1269 1253 }, ··· 1276 1260 .enable_mask = BIT(0), 1277 1261 .hw.init = &(struct clk_init_data){ 1278 1262 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1279 - .parent_names = (const char *[]){ 1280 - "ultaudio_ahbfabric_clk_src", 1263 + .parent_hws = (const struct clk_hw*[]){ 1264 + &ultaudio_ahbfabric_clk_src.clkr.hw, 1281 1265 }, 1282 1266 .num_parents = 1, 1283 1267 .flags = CLK_SET_RATE_PARENT, ··· 1293 1277 .enable_mask = BIT(0), 1294 1278 .hw.init = &(struct clk_init_data){ 1295 1279 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1296 - .parent_names = (const char *[]){ 1297 - "ultaudio_ahbfabric_clk_src", 1280 + .parent_hws = (const struct clk_hw*[]){ 1281 + &ultaudio_ahbfabric_clk_src.clkr.hw, 1298 1282 }, 1299 1283 .num_parents = 1, 1300 1284 .flags = CLK_SET_RATE_PARENT, ··· 1342 1326 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1343 1327 .clkr.hw.init = &(struct clk_init_data){ 1344 1328 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1345 - .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1329 + .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep, 1346 1330 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep), 1347 1331 .ops = &clk_rcg2_ops, 1348 1332 }, ··· 1355 1339 .enable_mask = BIT(0), 1356 1340 .hw.init = &(struct clk_init_data){ 1357 1341 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1358 - .parent_names = (const char *[]){ 1359 - "ultaudio_lpaif_pri_i2s_clk_src", 1342 + .parent_hws = (const struct clk_hw*[]){ 1343 + &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw, 1360 1344 }, 1361 1345 .num_parents = 1, 1362 1346 .flags = CLK_SET_RATE_PARENT, ··· 1373 1357 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1374 1358 .clkr.hw.init = &(struct clk_init_data){ 1375 1359 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1376 - .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1360 + .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep, 1377 1361 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep), 1378 1362 .ops = &clk_rcg2_ops, 1379 1363 }, ··· 1386 1370 .enable_mask = BIT(0), 1387 1371 .hw.init = &(struct clk_init_data){ 1388 1372 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1389 - .parent_names = (const char *[]){ 1390 - "ultaudio_lpaif_sec_i2s_clk_src", 1373 + .parent_hws = (const struct clk_hw*[]){ 1374 + &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw, 1391 1375 }, 1392 1376 .num_parents = 1, 1393 1377 .flags = CLK_SET_RATE_PARENT, ··· 1404 1388 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1405 1389 .clkr.hw.init = &(struct clk_init_data){ 1406 1390 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1407 - .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1391 + .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep, 1408 1392 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep), 1409 1393 .ops = &clk_rcg2_ops, 1410 1394 }, ··· 1417 1401 .enable_mask = BIT(0), 1418 1402 .hw.init = &(struct clk_init_data){ 1419 1403 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1420 - .parent_names = (const char *[]){ 1421 - "ultaudio_lpaif_aux_i2s_clk_src", 1404 + .parent_hws = (const struct clk_hw*[]){ 1405 + &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw, 1422 1406 }, 1423 1407 .num_parents = 1, 1424 1408 .flags = CLK_SET_RATE_PARENT, ··· 1439 1423 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1440 1424 .clkr.hw.init = &(struct clk_init_data){ 1441 1425 .name = "ultaudio_xo_clk_src", 1442 - .parent_names = gcc_xo_sleep, 1426 + .parent_data = gcc_xo_sleep, 1443 1427 .num_parents = ARRAY_SIZE(gcc_xo_sleep), 1444 1428 .ops = &clk_rcg2_ops, 1445 1429 }, ··· 1452 1436 .enable_mask = BIT(0), 1453 1437 .hw.init = &(struct clk_init_data){ 1454 1438 .name = "gcc_ultaudio_avsync_xo_clk", 1455 - .parent_names = (const char *[]){ 1456 - "ultaudio_xo_clk_src", 1439 + .parent_hws = (const struct clk_hw*[]){ 1440 + &ultaudio_xo_clk_src.clkr.hw, 1457 1441 }, 1458 1442 .num_parents = 1, 1459 1443 .flags = CLK_SET_RATE_PARENT, ··· 1469 1453 .enable_mask = BIT(0), 1470 1454 .hw.init = &(struct clk_init_data){ 1471 1455 .name = "gcc_ultaudio_stc_xo_clk", 1472 - .parent_names = (const char *[]){ 1473 - "ultaudio_xo_clk_src", 1456 + .parent_hws = (const struct clk_hw*[]){ 1457 + &ultaudio_xo_clk_src.clkr.hw, 1474 1458 }, 1475 1459 .num_parents = 1, 1476 1460 .flags = CLK_SET_RATE_PARENT, ··· 1495 1479 .freq_tbl = ftbl_codec_clk, 1496 1480 .clkr.hw.init = &(struct clk_init_data){ 1497 1481 .name = "codec_digcodec_clk_src", 1498 - .parent_names = gcc_xo_gpll1_emclk_sleep, 1482 + .parent_data = gcc_xo_gpll1_emclk_sleep, 1499 1483 .num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep), 1500 1484 .ops = &clk_rcg2_ops, 1501 1485 }, ··· 1508 1492 .enable_mask = BIT(0), 1509 1493 .hw.init = &(struct clk_init_data){ 1510 1494 .name = "gcc_ultaudio_codec_digcodec_clk", 1511 - .parent_names = (const char *[]){ 1512 - "codec_digcodec_clk_src", 1495 + .parent_hws = (const struct clk_hw*[]){ 1496 + &codec_digcodec_clk_src.clkr.hw, 1513 1497 }, 1514 1498 .num_parents = 1, 1515 1499 .flags = CLK_SET_RATE_PARENT, ··· 1525 1509 .enable_mask = BIT(0), 1526 1510 .hw.init = &(struct clk_init_data){ 1527 1511 .name = "gcc_ultaudio_pcnoc_mport_clk", 1528 - .parent_names = (const char *[]){ 1529 - "pcnoc_bfdcd_clk_src", 1512 + .parent_hws = (const struct clk_hw*[]){ 1513 + &pcnoc_bfdcd_clk_src.clkr.hw, 1530 1514 }, 1531 1515 .num_parents = 1, 1532 1516 .ops = &clk_branch2_ops, ··· 1541 1525 .enable_mask = BIT(0), 1542 1526 .hw.init = &(struct clk_init_data){ 1543 1527 .name = "gcc_ultaudio_pcnoc_sway_clk", 1544 - .parent_names = (const char *[]){ 1545 - "pcnoc_bfdcd_clk_src", 1528 + .parent_hws = (const struct clk_hw*[]){ 1529 + &pcnoc_bfdcd_clk_src.clkr.hw, 1546 1530 }, 1547 1531 .num_parents = 1, 1548 1532 .ops = &clk_branch2_ops, ··· 1565 1549 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1566 1550 .clkr.hw.init = &(struct clk_init_data){ 1567 1551 .name = "vcodec0_clk_src", 1568 - .parent_names = gcc_xo_gpll0, 1552 + .parent_data = gcc_xo_gpll0, 1569 1553 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1570 1554 .ops = &clk_rcg2_ops, 1571 1555 }, ··· 1579 1563 .enable_mask = BIT(10), 1580 1564 .hw.init = &(struct clk_init_data){ 1581 1565 .name = "gcc_blsp1_ahb_clk", 1582 - .parent_names = (const char *[]){ 1583 - "pcnoc_bfdcd_clk_src", 1566 + .parent_hws = (const struct clk_hw*[]){ 1567 + &pcnoc_bfdcd_clk_src.clkr.hw, 1584 1568 }, 1585 1569 .num_parents = 1, 1586 1570 .ops = &clk_branch2_ops, ··· 1595 1579 .enable_mask = BIT(0), 1596 1580 .hw.init = &(struct clk_init_data){ 1597 1581 .name = "gcc_blsp1_sleep_clk", 1598 - .parent_names = (const char *[]){ 1599 - "sleep_clk_src", 1582 + .parent_data = &(const struct clk_parent_data){ 1583 + .fw_name = "sleep_clk", .name = "sleep_clk_src", 1600 1584 }, 1601 1585 .num_parents = 1, 1602 1586 .flags = CLK_SET_RATE_PARENT, ··· 1612 1596 .enable_mask = BIT(0), 1613 1597 .hw.init = &(struct clk_init_data){ 1614 1598 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1615 - .parent_names = (const char *[]){ 1616 - "blsp1_qup1_i2c_apps_clk_src", 1599 + .parent_hws = (const struct clk_hw*[]){ 1600 + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1617 1601 }, 1618 1602 .num_parents = 1, 1619 1603 .flags = CLK_SET_RATE_PARENT, ··· 1629 1613 .enable_mask = BIT(0), 1630 1614 .hw.init = &(struct clk_init_data){ 1631 1615 .name = "gcc_blsp1_qup1_spi_apps_clk", 1632 - .parent_names = (const char *[]){ 1633 - "blsp1_qup1_spi_apps_clk_src", 1616 + .parent_hws = (const struct clk_hw*[]){ 1617 + &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1634 1618 }, 1635 1619 .num_parents = 1, 1636 1620 .flags = CLK_SET_RATE_PARENT, ··· 1646 1630 .enable_mask = BIT(0), 1647 1631 .hw.init = &(struct clk_init_data){ 1648 1632 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1649 - .parent_names = (const char *[]){ 1650 - "blsp1_qup2_i2c_apps_clk_src", 1633 + .parent_hws = (const struct clk_hw*[]){ 1634 + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1651 1635 }, 1652 1636 .num_parents = 1, 1653 1637 .flags = CLK_SET_RATE_PARENT, ··· 1663 1647 .enable_mask = BIT(0), 1664 1648 .hw.init = &(struct clk_init_data){ 1665 1649 .name = "gcc_blsp1_qup2_spi_apps_clk", 1666 - .parent_names = (const char *[]){ 1667 - "blsp1_qup2_spi_apps_clk_src", 1650 + .parent_hws = (const struct clk_hw*[]){ 1651 + &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1668 1652 }, 1669 1653 .num_parents = 1, 1670 1654 .flags = CLK_SET_RATE_PARENT, ··· 1680 1664 .enable_mask = BIT(0), 1681 1665 .hw.init = &(struct clk_init_data){ 1682 1666 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1683 - .parent_names = (const char *[]){ 1684 - "blsp1_qup3_i2c_apps_clk_src", 1667 + .parent_hws = (const struct clk_hw*[]){ 1668 + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1685 1669 }, 1686 1670 .num_parents = 1, 1687 1671 .flags = CLK_SET_RATE_PARENT, ··· 1697 1681 .enable_mask = BIT(0), 1698 1682 .hw.init = &(struct clk_init_data){ 1699 1683 .name = "gcc_blsp1_qup3_spi_apps_clk", 1700 - .parent_names = (const char *[]){ 1701 - "blsp1_qup3_spi_apps_clk_src", 1684 + .parent_hws = (const struct clk_hw*[]){ 1685 + &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1702 1686 }, 1703 1687 .num_parents = 1, 1704 1688 .flags = CLK_SET_RATE_PARENT, ··· 1714 1698 .enable_mask = BIT(0), 1715 1699 .hw.init = &(struct clk_init_data){ 1716 1700 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1717 - .parent_names = (const char *[]){ 1718 - "blsp1_qup4_i2c_apps_clk_src", 1701 + .parent_hws = (const struct clk_hw*[]){ 1702 + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1719 1703 }, 1720 1704 .num_parents = 1, 1721 1705 .flags = CLK_SET_RATE_PARENT, ··· 1731 1715 .enable_mask = BIT(0), 1732 1716 .hw.init = &(struct clk_init_data){ 1733 1717 .name = "gcc_blsp1_qup4_spi_apps_clk", 1734 - .parent_names = (const char *[]){ 1735 - "blsp1_qup4_spi_apps_clk_src", 1718 + .parent_hws = (const struct clk_hw*[]){ 1719 + &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1736 1720 }, 1737 1721 .num_parents = 1, 1738 1722 .flags = CLK_SET_RATE_PARENT, ··· 1748 1732 .enable_mask = BIT(0), 1749 1733 .hw.init = &(struct clk_init_data){ 1750 1734 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1751 - .parent_names = (const char *[]){ 1752 - "blsp1_qup5_i2c_apps_clk_src", 1735 + .parent_hws = (const struct clk_hw*[]){ 1736 + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1753 1737 }, 1754 1738 .num_parents = 1, 1755 1739 .flags = CLK_SET_RATE_PARENT, ··· 1765 1749 .enable_mask = BIT(0), 1766 1750 .hw.init = &(struct clk_init_data){ 1767 1751 .name = "gcc_blsp1_qup5_spi_apps_clk", 1768 - .parent_names = (const char *[]){ 1769 - "blsp1_qup5_spi_apps_clk_src", 1752 + .parent_hws = (const struct clk_hw*[]){ 1753 + &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1770 1754 }, 1771 1755 .num_parents = 1, 1772 1756 .flags = CLK_SET_RATE_PARENT, ··· 1782 1766 .enable_mask = BIT(0), 1783 1767 .hw.init = &(struct clk_init_data){ 1784 1768 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1785 - .parent_names = (const char *[]){ 1786 - "blsp1_qup6_i2c_apps_clk_src", 1769 + .parent_hws = (const struct clk_hw*[]){ 1770 + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1787 1771 }, 1788 1772 .num_parents = 1, 1789 1773 .flags = CLK_SET_RATE_PARENT, ··· 1799 1783 .enable_mask = BIT(0), 1800 1784 .hw.init = &(struct clk_init_data){ 1801 1785 .name = "gcc_blsp1_qup6_spi_apps_clk", 1802 - .parent_names = (const char *[]){ 1803 - "blsp1_qup6_spi_apps_clk_src", 1786 + .parent_hws = (const struct clk_hw*[]){ 1787 + &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1804 1788 }, 1805 1789 .num_parents = 1, 1806 1790 .flags = CLK_SET_RATE_PARENT, ··· 1816 1800 .enable_mask = BIT(0), 1817 1801 .hw.init = &(struct clk_init_data){ 1818 1802 .name = "gcc_blsp1_uart1_apps_clk", 1819 - .parent_names = (const char *[]){ 1820 - "blsp1_uart1_apps_clk_src", 1803 + .parent_hws = (const struct clk_hw*[]){ 1804 + &blsp1_uart1_apps_clk_src.clkr.hw, 1821 1805 }, 1822 1806 .num_parents = 1, 1823 1807 .flags = CLK_SET_RATE_PARENT, ··· 1833 1817 .enable_mask = BIT(0), 1834 1818 .hw.init = &(struct clk_init_data){ 1835 1819 .name = "gcc_blsp1_uart2_apps_clk", 1836 - .parent_names = (const char *[]){ 1837 - "blsp1_uart2_apps_clk_src", 1820 + .parent_hws = (const struct clk_hw*[]){ 1821 + &blsp1_uart2_apps_clk_src.clkr.hw, 1838 1822 }, 1839 1823 .num_parents = 1, 1840 1824 .flags = CLK_SET_RATE_PARENT, ··· 1851 1835 .enable_mask = BIT(7), 1852 1836 .hw.init = &(struct clk_init_data){ 1853 1837 .name = "gcc_boot_rom_ahb_clk", 1854 - .parent_names = (const char *[]){ 1855 - "pcnoc_bfdcd_clk_src", 1838 + .parent_hws = (const struct clk_hw*[]){ 1839 + &pcnoc_bfdcd_clk_src.clkr.hw, 1856 1840 }, 1857 1841 .num_parents = 1, 1858 1842 .ops = &clk_branch2_ops, ··· 1867 1851 .enable_mask = BIT(0), 1868 1852 .hw.init = &(struct clk_init_data){ 1869 1853 .name = "gcc_camss_cci_ahb_clk", 1870 - .parent_names = (const char *[]){ 1871 - "camss_ahb_clk_src", 1854 + .parent_hws = (const struct clk_hw*[]){ 1855 + &camss_ahb_clk_src.clkr.hw, 1872 1856 }, 1873 1857 .num_parents = 1, 1874 1858 .flags = CLK_SET_RATE_PARENT, ··· 1884 1868 .enable_mask = BIT(0), 1885 1869 .hw.init = &(struct clk_init_data){ 1886 1870 .name = "gcc_camss_cci_clk", 1887 - .parent_names = (const char *[]){ 1888 - "cci_clk_src", 1871 + .parent_hws = (const struct clk_hw*[]){ 1872 + &cci_clk_src.clkr.hw, 1889 1873 }, 1890 1874 .num_parents = 1, 1891 1875 .flags = CLK_SET_RATE_PARENT, ··· 1901 1885 .enable_mask = BIT(0), 1902 1886 .hw.init = &(struct clk_init_data){ 1903 1887 .name = "gcc_camss_csi0_ahb_clk", 1904 - .parent_names = (const char *[]){ 1905 - "camss_ahb_clk_src", 1888 + .parent_hws = (const struct clk_hw*[]){ 1889 + &camss_ahb_clk_src.clkr.hw, 1906 1890 }, 1907 1891 .num_parents = 1, 1908 1892 .flags = CLK_SET_RATE_PARENT, ··· 1918 1902 .enable_mask = BIT(0), 1919 1903 .hw.init = &(struct clk_init_data){ 1920 1904 .name = "gcc_camss_csi0_clk", 1921 - .parent_names = (const char *[]){ 1922 - "csi0_clk_src", 1905 + .parent_hws = (const struct clk_hw*[]){ 1906 + &csi0_clk_src.clkr.hw, 1923 1907 }, 1924 1908 .num_parents = 1, 1925 1909 .flags = CLK_SET_RATE_PARENT, ··· 1935 1919 .enable_mask = BIT(0), 1936 1920 .hw.init = &(struct clk_init_data){ 1937 1921 .name = "gcc_camss_csi0phy_clk", 1938 - .parent_names = (const char *[]){ 1939 - "csi0_clk_src", 1922 + .parent_hws = (const struct clk_hw*[]){ 1923 + &csi0_clk_src.clkr.hw, 1940 1924 }, 1941 1925 .num_parents = 1, 1942 1926 .flags = CLK_SET_RATE_PARENT, ··· 1952 1936 .enable_mask = BIT(0), 1953 1937 .hw.init = &(struct clk_init_data){ 1954 1938 .name = "gcc_camss_csi0pix_clk", 1955 - .parent_names = (const char *[]){ 1956 - "csi0_clk_src", 1939 + .parent_hws = (const struct clk_hw*[]){ 1940 + &csi0_clk_src.clkr.hw, 1957 1941 }, 1958 1942 .num_parents = 1, 1959 1943 .flags = CLK_SET_RATE_PARENT, ··· 1969 1953 .enable_mask = BIT(0), 1970 1954 .hw.init = &(struct clk_init_data){ 1971 1955 .name = "gcc_camss_csi0rdi_clk", 1972 - .parent_names = (const char *[]){ 1973 - "csi0_clk_src", 1956 + .parent_hws = (const struct clk_hw*[]){ 1957 + &csi0_clk_src.clkr.hw, 1974 1958 }, 1975 1959 .num_parents = 1, 1976 1960 .flags = CLK_SET_RATE_PARENT, ··· 1986 1970 .enable_mask = BIT(0), 1987 1971 .hw.init = &(struct clk_init_data){ 1988 1972 .name = "gcc_camss_csi1_ahb_clk", 1989 - .parent_names = (const char *[]){ 1990 - "camss_ahb_clk_src", 1973 + .parent_hws = (const struct clk_hw*[]){ 1974 + &camss_ahb_clk_src.clkr.hw, 1991 1975 }, 1992 1976 .num_parents = 1, 1993 1977 .flags = CLK_SET_RATE_PARENT, ··· 2003 1987 .enable_mask = BIT(0), 2004 1988 .hw.init = &(struct clk_init_data){ 2005 1989 .name = "gcc_camss_csi1_clk", 2006 - .parent_names = (const char *[]){ 2007 - "csi1_clk_src", 1990 + .parent_hws = (const struct clk_hw*[]){ 1991 + &csi1_clk_src.clkr.hw, 2008 1992 }, 2009 1993 .num_parents = 1, 2010 1994 .flags = CLK_SET_RATE_PARENT, ··· 2020 2004 .enable_mask = BIT(0), 2021 2005 .hw.init = &(struct clk_init_data){ 2022 2006 .name = "gcc_camss_csi1phy_clk", 2023 - .parent_names = (const char *[]){ 2024 - "csi1_clk_src", 2007 + .parent_hws = (const struct clk_hw*[]){ 2008 + &csi1_clk_src.clkr.hw, 2025 2009 }, 2026 2010 .num_parents = 1, 2027 2011 .flags = CLK_SET_RATE_PARENT, ··· 2037 2021 .enable_mask = BIT(0), 2038 2022 .hw.init = &(struct clk_init_data){ 2039 2023 .name = "gcc_camss_csi1pix_clk", 2040 - .parent_names = (const char *[]){ 2041 - "csi1_clk_src", 2024 + .parent_hws = (const struct clk_hw*[]){ 2025 + &csi1_clk_src.clkr.hw, 2042 2026 }, 2043 2027 .num_parents = 1, 2044 2028 .flags = CLK_SET_RATE_PARENT, ··· 2054 2038 .enable_mask = BIT(0), 2055 2039 .hw.init = &(struct clk_init_data){ 2056 2040 .name = "gcc_camss_csi1rdi_clk", 2057 - .parent_names = (const char *[]){ 2058 - "csi1_clk_src", 2041 + .parent_hws = (const struct clk_hw*[]){ 2042 + &csi1_clk_src.clkr.hw, 2059 2043 }, 2060 2044 .num_parents = 1, 2061 2045 .flags = CLK_SET_RATE_PARENT, ··· 2071 2055 .enable_mask = BIT(0), 2072 2056 .hw.init = &(struct clk_init_data){ 2073 2057 .name = "gcc_camss_csi_vfe0_clk", 2074 - .parent_names = (const char *[]){ 2075 - "vfe0_clk_src", 2058 + .parent_hws = (const struct clk_hw*[]){ 2059 + &vfe0_clk_src.clkr.hw, 2076 2060 }, 2077 2061 .num_parents = 1, 2078 2062 .flags = CLK_SET_RATE_PARENT, ··· 2088 2072 .enable_mask = BIT(0), 2089 2073 .hw.init = &(struct clk_init_data){ 2090 2074 .name = "gcc_camss_gp0_clk", 2091 - .parent_names = (const char *[]){ 2092 - "camss_gp0_clk_src", 2075 + .parent_hws = (const struct clk_hw*[]){ 2076 + &camss_gp0_clk_src.clkr.hw, 2093 2077 }, 2094 2078 .num_parents = 1, 2095 2079 .flags = CLK_SET_RATE_PARENT, ··· 2105 2089 .enable_mask = BIT(0), 2106 2090 .hw.init = &(struct clk_init_data){ 2107 2091 .name = "gcc_camss_gp1_clk", 2108 - .parent_names = (const char *[]){ 2109 - "camss_gp1_clk_src", 2092 + .parent_hws = (const struct clk_hw*[]){ 2093 + &camss_gp1_clk_src.clkr.hw, 2110 2094 }, 2111 2095 .num_parents = 1, 2112 2096 .flags = CLK_SET_RATE_PARENT, ··· 2122 2106 .enable_mask = BIT(0), 2123 2107 .hw.init = &(struct clk_init_data){ 2124 2108 .name = "gcc_camss_ispif_ahb_clk", 2125 - .parent_names = (const char *[]){ 2126 - "camss_ahb_clk_src", 2109 + .parent_hws = (const struct clk_hw*[]){ 2110 + &camss_ahb_clk_src.clkr.hw, 2127 2111 }, 2128 2112 .num_parents = 1, 2129 2113 .flags = CLK_SET_RATE_PARENT, ··· 2139 2123 .enable_mask = BIT(0), 2140 2124 .hw.init = &(struct clk_init_data){ 2141 2125 .name = "gcc_camss_jpeg0_clk", 2142 - .parent_names = (const char *[]){ 2143 - "jpeg0_clk_src", 2126 + .parent_hws = (const struct clk_hw*[]){ 2127 + &jpeg0_clk_src.clkr.hw, 2144 2128 }, 2145 2129 .num_parents = 1, 2146 2130 .flags = CLK_SET_RATE_PARENT, ··· 2156 2140 .enable_mask = BIT(0), 2157 2141 .hw.init = &(struct clk_init_data){ 2158 2142 .name = "gcc_camss_jpeg_ahb_clk", 2159 - .parent_names = (const char *[]){ 2160 - "camss_ahb_clk_src", 2143 + .parent_hws = (const struct clk_hw*[]){ 2144 + &camss_ahb_clk_src.clkr.hw, 2161 2145 }, 2162 2146 .num_parents = 1, 2163 2147 .flags = CLK_SET_RATE_PARENT, ··· 2173 2157 .enable_mask = BIT(0), 2174 2158 .hw.init = &(struct clk_init_data){ 2175 2159 .name = "gcc_camss_jpeg_axi_clk", 2176 - .parent_names = (const char *[]){ 2177 - "system_noc_bfdcd_clk_src", 2160 + .parent_hws = (const struct clk_hw*[]){ 2161 + &system_noc_bfdcd_clk_src.clkr.hw, 2178 2162 }, 2179 2163 .num_parents = 1, 2180 2164 .flags = CLK_SET_RATE_PARENT, ··· 2190 2174 .enable_mask = BIT(0), 2191 2175 .hw.init = &(struct clk_init_data){ 2192 2176 .name = "gcc_camss_mclk0_clk", 2193 - .parent_names = (const char *[]){ 2194 - "mclk0_clk_src", 2177 + .parent_hws = (const struct clk_hw*[]){ 2178 + &mclk0_clk_src.clkr.hw, 2195 2179 }, 2196 2180 .num_parents = 1, 2197 2181 .flags = CLK_SET_RATE_PARENT, ··· 2207 2191 .enable_mask = BIT(0), 2208 2192 .hw.init = &(struct clk_init_data){ 2209 2193 .name = "gcc_camss_mclk1_clk", 2210 - .parent_names = (const char *[]){ 2211 - "mclk1_clk_src", 2194 + .parent_hws = (const struct clk_hw*[]){ 2195 + &mclk1_clk_src.clkr.hw, 2212 2196 }, 2213 2197 .num_parents = 1, 2214 2198 .flags = CLK_SET_RATE_PARENT, ··· 2224 2208 .enable_mask = BIT(0), 2225 2209 .hw.init = &(struct clk_init_data){ 2226 2210 .name = "gcc_camss_micro_ahb_clk", 2227 - .parent_names = (const char *[]){ 2228 - "camss_ahb_clk_src", 2211 + .parent_hws = (const struct clk_hw*[]){ 2212 + &camss_ahb_clk_src.clkr.hw, 2229 2213 }, 2230 2214 .num_parents = 1, 2231 2215 .flags = CLK_SET_RATE_PARENT, ··· 2241 2225 .enable_mask = BIT(0), 2242 2226 .hw.init = &(struct clk_init_data){ 2243 2227 .name = "gcc_camss_csi0phytimer_clk", 2244 - .parent_names = (const char *[]){ 2245 - "csi0phytimer_clk_src", 2228 + .parent_hws = (const struct clk_hw*[]){ 2229 + &csi0phytimer_clk_src.clkr.hw, 2246 2230 }, 2247 2231 .num_parents = 1, 2248 2232 .flags = CLK_SET_RATE_PARENT, ··· 2258 2242 .enable_mask = BIT(0), 2259 2243 .hw.init = &(struct clk_init_data){ 2260 2244 .name = "gcc_camss_csi1phytimer_clk", 2261 - .parent_names = (const char *[]){ 2262 - "csi1phytimer_clk_src", 2245 + .parent_hws = (const struct clk_hw*[]){ 2246 + &csi1phytimer_clk_src.clkr.hw, 2263 2247 }, 2264 2248 .num_parents = 1, 2265 2249 .flags = CLK_SET_RATE_PARENT, ··· 2275 2259 .enable_mask = BIT(0), 2276 2260 .hw.init = &(struct clk_init_data){ 2277 2261 .name = "gcc_camss_ahb_clk", 2278 - .parent_names = (const char *[]){ 2279 - "camss_ahb_clk_src", 2262 + .parent_hws = (const struct clk_hw*[]){ 2263 + &camss_ahb_clk_src.clkr.hw, 2280 2264 }, 2281 2265 .num_parents = 1, 2282 2266 .flags = CLK_SET_RATE_PARENT, ··· 2292 2276 .enable_mask = BIT(0), 2293 2277 .hw.init = &(struct clk_init_data){ 2294 2278 .name = "gcc_camss_top_ahb_clk", 2295 - .parent_names = (const char *[]){ 2296 - "pcnoc_bfdcd_clk_src", 2279 + .parent_hws = (const struct clk_hw*[]){ 2280 + &pcnoc_bfdcd_clk_src.clkr.hw, 2297 2281 }, 2298 2282 .num_parents = 1, 2299 2283 .flags = CLK_SET_RATE_PARENT, ··· 2309 2293 .enable_mask = BIT(0), 2310 2294 .hw.init = &(struct clk_init_data){ 2311 2295 .name = "gcc_camss_cpp_ahb_clk", 2312 - .parent_names = (const char *[]){ 2313 - "camss_ahb_clk_src", 2296 + .parent_hws = (const struct clk_hw*[]){ 2297 + &camss_ahb_clk_src.clkr.hw, 2314 2298 }, 2315 2299 .num_parents = 1, 2316 2300 .flags = CLK_SET_RATE_PARENT, ··· 2326 2310 .enable_mask = BIT(0), 2327 2311 .hw.init = &(struct clk_init_data){ 2328 2312 .name = "gcc_camss_cpp_clk", 2329 - .parent_names = (const char *[]){ 2330 - "cpp_clk_src", 2313 + .parent_hws = (const struct clk_hw*[]){ 2314 + &cpp_clk_src.clkr.hw, 2331 2315 }, 2332 2316 .num_parents = 1, 2333 2317 .flags = CLK_SET_RATE_PARENT, ··· 2343 2327 .enable_mask = BIT(0), 2344 2328 .hw.init = &(struct clk_init_data){ 2345 2329 .name = "gcc_camss_vfe0_clk", 2346 - .parent_names = (const char *[]){ 2347 - "vfe0_clk_src", 2330 + .parent_hws = (const struct clk_hw*[]){ 2331 + &vfe0_clk_src.clkr.hw, 2348 2332 }, 2349 2333 .num_parents = 1, 2350 2334 .flags = CLK_SET_RATE_PARENT, ··· 2360 2344 .enable_mask = BIT(0), 2361 2345 .hw.init = &(struct clk_init_data){ 2362 2346 .name = "gcc_camss_vfe_ahb_clk", 2363 - .parent_names = (const char *[]){ 2364 - "camss_ahb_clk_src", 2347 + .parent_hws = (const struct clk_hw*[]){ 2348 + &camss_ahb_clk_src.clkr.hw, 2365 2349 }, 2366 2350 .num_parents = 1, 2367 2351 .flags = CLK_SET_RATE_PARENT, ··· 2377 2361 .enable_mask = BIT(0), 2378 2362 .hw.init = &(struct clk_init_data){ 2379 2363 .name = "gcc_camss_vfe_axi_clk", 2380 - .parent_names = (const char *[]){ 2381 - "system_noc_bfdcd_clk_src", 2364 + .parent_hws = (const struct clk_hw*[]){ 2365 + &system_noc_bfdcd_clk_src.clkr.hw, 2382 2366 }, 2383 2367 .num_parents = 1, 2384 2368 .flags = CLK_SET_RATE_PARENT, ··· 2395 2379 .enable_mask = BIT(0), 2396 2380 .hw.init = &(struct clk_init_data){ 2397 2381 .name = "gcc_crypto_ahb_clk", 2398 - .parent_names = (const char *[]){ 2399 - "pcnoc_bfdcd_clk_src", 2382 + .parent_hws = (const struct clk_hw*[]){ 2383 + &pcnoc_bfdcd_clk_src.clkr.hw, 2400 2384 }, 2401 2385 .num_parents = 1, 2402 2386 .flags = CLK_SET_RATE_PARENT, ··· 2413 2397 .enable_mask = BIT(1), 2414 2398 .hw.init = &(struct clk_init_data){ 2415 2399 .name = "gcc_crypto_axi_clk", 2416 - .parent_names = (const char *[]){ 2417 - "pcnoc_bfdcd_clk_src", 2400 + .parent_hws = (const struct clk_hw*[]){ 2401 + &pcnoc_bfdcd_clk_src.clkr.hw, 2418 2402 }, 2419 2403 .num_parents = 1, 2420 2404 .flags = CLK_SET_RATE_PARENT, ··· 2431 2415 .enable_mask = BIT(2), 2432 2416 .hw.init = &(struct clk_init_data){ 2433 2417 .name = "gcc_crypto_clk", 2434 - .parent_names = (const char *[]){ 2435 - "crypto_clk_src", 2418 + .parent_hws = (const struct clk_hw*[]){ 2419 + &crypto_clk_src.clkr.hw, 2436 2420 }, 2437 2421 .num_parents = 1, 2438 2422 .flags = CLK_SET_RATE_PARENT, ··· 2448 2432 .enable_mask = BIT(0), 2449 2433 .hw.init = &(struct clk_init_data){ 2450 2434 .name = "gcc_oxili_gmem_clk", 2451 - .parent_names = (const char *[]){ 2452 - "gfx3d_clk_src", 2435 + .parent_hws = (const struct clk_hw*[]){ 2436 + &gfx3d_clk_src.clkr.hw, 2453 2437 }, 2454 2438 .num_parents = 1, 2455 2439 .flags = CLK_SET_RATE_PARENT, ··· 2465 2449 .enable_mask = BIT(0), 2466 2450 .hw.init = &(struct clk_init_data){ 2467 2451 .name = "gcc_gp1_clk", 2468 - .parent_names = (const char *[]){ 2469 - "gp1_clk_src", 2452 + .parent_hws = (const struct clk_hw*[]){ 2453 + &gp1_clk_src.clkr.hw, 2470 2454 }, 2471 2455 .num_parents = 1, 2472 2456 .flags = CLK_SET_RATE_PARENT, ··· 2482 2466 .enable_mask = BIT(0), 2483 2467 .hw.init = &(struct clk_init_data){ 2484 2468 .name = "gcc_gp2_clk", 2485 - .parent_names = (const char *[]){ 2486 - "gp2_clk_src", 2469 + .parent_hws = (const struct clk_hw*[]){ 2470 + &gp2_clk_src.clkr.hw, 2487 2471 }, 2488 2472 .num_parents = 1, 2489 2473 .flags = CLK_SET_RATE_PARENT, ··· 2499 2483 .enable_mask = BIT(0), 2500 2484 .hw.init = &(struct clk_init_data){ 2501 2485 .name = "gcc_gp3_clk", 2502 - .parent_names = (const char *[]){ 2503 - "gp3_clk_src", 2486 + .parent_hws = (const struct clk_hw*[]){ 2487 + &gp3_clk_src.clkr.hw, 2504 2488 }, 2505 2489 .num_parents = 1, 2506 2490 .flags = CLK_SET_RATE_PARENT, ··· 2516 2500 .enable_mask = BIT(0), 2517 2501 .hw.init = &(struct clk_init_data){ 2518 2502 .name = "gcc_mdss_ahb_clk", 2519 - .parent_names = (const char *[]){ 2520 - "pcnoc_bfdcd_clk_src", 2503 + .parent_hws = (const struct clk_hw*[]){ 2504 + &pcnoc_bfdcd_clk_src.clkr.hw, 2521 2505 }, 2522 2506 .num_parents = 1, 2523 2507 .flags = CLK_SET_RATE_PARENT, ··· 2533 2517 .enable_mask = BIT(0), 2534 2518 .hw.init = &(struct clk_init_data){ 2535 2519 .name = "gcc_mdss_axi_clk", 2536 - .parent_names = (const char *[]){ 2537 - "system_noc_bfdcd_clk_src", 2520 + .parent_hws = (const struct clk_hw*[]){ 2521 + &system_noc_bfdcd_clk_src.clkr.hw, 2538 2522 }, 2539 2523 .num_parents = 1, 2540 2524 .flags = CLK_SET_RATE_PARENT, ··· 2550 2534 .enable_mask = BIT(0), 2551 2535 .hw.init = &(struct clk_init_data){ 2552 2536 .name = "gcc_mdss_byte0_clk", 2553 - .parent_names = (const char *[]){ 2554 - "byte0_clk_src", 2537 + .parent_hws = (const struct clk_hw*[]){ 2538 + &byte0_clk_src.clkr.hw, 2555 2539 }, 2556 2540 .num_parents = 1, 2557 2541 .flags = CLK_SET_RATE_PARENT, ··· 2567 2551 .enable_mask = BIT(0), 2568 2552 .hw.init = &(struct clk_init_data){ 2569 2553 .name = "gcc_mdss_esc0_clk", 2570 - .parent_names = (const char *[]){ 2571 - "esc0_clk_src", 2554 + .parent_hws = (const struct clk_hw*[]){ 2555 + &esc0_clk_src.clkr.hw, 2572 2556 }, 2573 2557 .num_parents = 1, 2574 2558 .flags = CLK_SET_RATE_PARENT, ··· 2584 2568 .enable_mask = BIT(0), 2585 2569 .hw.init = &(struct clk_init_data){ 2586 2570 .name = "gcc_mdss_mdp_clk", 2587 - .parent_names = (const char *[]){ 2588 - "mdp_clk_src", 2571 + .parent_hws = (const struct clk_hw*[]){ 2572 + &mdp_clk_src.clkr.hw, 2589 2573 }, 2590 2574 .num_parents = 1, 2591 2575 .flags = CLK_SET_RATE_PARENT, ··· 2601 2585 .enable_mask = BIT(0), 2602 2586 .hw.init = &(struct clk_init_data){ 2603 2587 .name = "gcc_mdss_pclk0_clk", 2604 - .parent_names = (const char *[]){ 2605 - "pclk0_clk_src", 2588 + .parent_hws = (const struct clk_hw*[]){ 2589 + &pclk0_clk_src.clkr.hw, 2606 2590 }, 2607 2591 .num_parents = 1, 2608 2592 .flags = CLK_SET_RATE_PARENT, ··· 2618 2602 .enable_mask = BIT(0), 2619 2603 .hw.init = &(struct clk_init_data){ 2620 2604 .name = "gcc_mdss_vsync_clk", 2621 - .parent_names = (const char *[]){ 2622 - "vsync_clk_src", 2605 + .parent_hws = (const struct clk_hw*[]){ 2606 + &vsync_clk_src.clkr.hw, 2623 2607 }, 2624 2608 .num_parents = 1, 2625 2609 .flags = CLK_SET_RATE_PARENT, ··· 2635 2619 .enable_mask = BIT(0), 2636 2620 .hw.init = &(struct clk_init_data){ 2637 2621 .name = "gcc_mss_cfg_ahb_clk", 2638 - .parent_names = (const char *[]){ 2639 - "pcnoc_bfdcd_clk_src", 2622 + .parent_hws = (const struct clk_hw*[]){ 2623 + &pcnoc_bfdcd_clk_src.clkr.hw, 2640 2624 }, 2641 2625 .num_parents = 1, 2642 2626 .flags = CLK_SET_RATE_PARENT, ··· 2652 2636 .enable_mask = BIT(0), 2653 2637 .hw.init = &(struct clk_init_data){ 2654 2638 .name = "gcc_oxili_ahb_clk", 2655 - .parent_names = (const char *[]){ 2656 - "pcnoc_bfdcd_clk_src", 2639 + .parent_hws = (const struct clk_hw*[]){ 2640 + &pcnoc_bfdcd_clk_src.clkr.hw, 2657 2641 }, 2658 2642 .num_parents = 1, 2659 2643 .flags = CLK_SET_RATE_PARENT, ··· 2669 2653 .enable_mask = BIT(0), 2670 2654 .hw.init = &(struct clk_init_data){ 2671 2655 .name = "gcc_oxili_gfx3d_clk", 2672 - .parent_names = (const char *[]){ 2673 - "gfx3d_clk_src", 2656 + .parent_hws = (const struct clk_hw*[]){ 2657 + &gfx3d_clk_src.clkr.hw, 2674 2658 }, 2675 2659 .num_parents = 1, 2676 2660 .flags = CLK_SET_RATE_PARENT, ··· 2686 2670 .enable_mask = BIT(0), 2687 2671 .hw.init = &(struct clk_init_data){ 2688 2672 .name = "gcc_pdm2_clk", 2689 - .parent_names = (const char *[]){ 2690 - "pdm2_clk_src", 2673 + .parent_hws = (const struct clk_hw*[]){ 2674 + &pdm2_clk_src.clkr.hw, 2691 2675 }, 2692 2676 .num_parents = 1, 2693 2677 .flags = CLK_SET_RATE_PARENT, ··· 2703 2687 .enable_mask = BIT(0), 2704 2688 .hw.init = &(struct clk_init_data){ 2705 2689 .name = "gcc_pdm_ahb_clk", 2706 - .parent_names = (const char *[]){ 2707 - "pcnoc_bfdcd_clk_src", 2690 + .parent_hws = (const struct clk_hw*[]){ 2691 + &pcnoc_bfdcd_clk_src.clkr.hw, 2708 2692 }, 2709 2693 .num_parents = 1, 2710 2694 .flags = CLK_SET_RATE_PARENT, ··· 2721 2705 .enable_mask = BIT(8), 2722 2706 .hw.init = &(struct clk_init_data){ 2723 2707 .name = "gcc_prng_ahb_clk", 2724 - .parent_names = (const char *[]){ 2725 - "pcnoc_bfdcd_clk_src", 2708 + .parent_hws = (const struct clk_hw*[]){ 2709 + &pcnoc_bfdcd_clk_src.clkr.hw, 2726 2710 }, 2727 2711 .num_parents = 1, 2728 2712 .ops = &clk_branch2_ops, ··· 2737 2721 .enable_mask = BIT(0), 2738 2722 .hw.init = &(struct clk_init_data){ 2739 2723 .name = "gcc_sdcc1_ahb_clk", 2740 - .parent_names = (const char *[]){ 2741 - "pcnoc_bfdcd_clk_src", 2724 + .parent_hws = (const struct clk_hw*[]){ 2725 + &pcnoc_bfdcd_clk_src.clkr.hw, 2742 2726 }, 2743 2727 .num_parents = 1, 2744 2728 .flags = CLK_SET_RATE_PARENT, ··· 2754 2738 .enable_mask = BIT(0), 2755 2739 .hw.init = &(struct clk_init_data){ 2756 2740 .name = "gcc_sdcc1_apps_clk", 2757 - .parent_names = (const char *[]){ 2758 - "sdcc1_apps_clk_src", 2741 + .parent_hws = (const struct clk_hw*[]){ 2742 + &sdcc1_apps_clk_src.clkr.hw, 2759 2743 }, 2760 2744 .num_parents = 1, 2761 2745 .flags = CLK_SET_RATE_PARENT, ··· 2771 2755 .enable_mask = BIT(0), 2772 2756 .hw.init = &(struct clk_init_data){ 2773 2757 .name = "gcc_sdcc2_ahb_clk", 2774 - .parent_names = (const char *[]){ 2775 - "pcnoc_bfdcd_clk_src", 2758 + .parent_hws = (const struct clk_hw*[]){ 2759 + &pcnoc_bfdcd_clk_src.clkr.hw, 2776 2760 }, 2777 2761 .num_parents = 1, 2778 2762 .flags = CLK_SET_RATE_PARENT, ··· 2788 2772 .enable_mask = BIT(0), 2789 2773 .hw.init = &(struct clk_init_data){ 2790 2774 .name = "gcc_sdcc2_apps_clk", 2791 - .parent_names = (const char *[]){ 2792 - "sdcc2_apps_clk_src", 2775 + .parent_hws = (const struct clk_hw*[]){ 2776 + &sdcc2_apps_clk_src.clkr.hw, 2793 2777 }, 2794 2778 .num_parents = 1, 2795 2779 .flags = CLK_SET_RATE_PARENT, ··· 2804 2788 .parent_map = gcc_xo_gpll0_bimc_map, 2805 2789 .clkr.hw.init = &(struct clk_init_data){ 2806 2790 .name = "bimc_ddr_clk_src", 2807 - .parent_names = gcc_xo_gpll0_bimc, 2791 + .parent_data = gcc_xo_gpll0_bimc, 2808 2792 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc), 2809 2793 .ops = &clk_rcg2_ops, 2810 2794 .flags = CLK_GET_RATE_NOCACHE, ··· 2818 2802 .enable_mask = BIT(0), 2819 2803 .hw.init = &(struct clk_init_data){ 2820 2804 .name = "gcc_mss_q6_bimc_axi_clk", 2821 - .parent_names = (const char *[]){ 2822 - "bimc_ddr_clk_src", 2805 + .parent_hws = (const struct clk_hw*[]){ 2806 + &bimc_ddr_clk_src.clkr.hw, 2823 2807 }, 2824 2808 .num_parents = 1, 2825 2809 .flags = CLK_SET_RATE_PARENT, ··· 2835 2819 .enable_mask = BIT(1), 2836 2820 .hw.init = &(struct clk_init_data){ 2837 2821 .name = "gcc_apss_tcu_clk", 2838 - .parent_names = (const char *[]){ 2839 - "bimc_ddr_clk_src", 2822 + .parent_hws = (const struct clk_hw*[]){ 2823 + &bimc_ddr_clk_src.clkr.hw, 2840 2824 }, 2841 2825 .num_parents = 1, 2842 2826 .ops = &clk_branch2_ops, ··· 2851 2835 .enable_mask = BIT(2), 2852 2836 .hw.init = &(struct clk_init_data){ 2853 2837 .name = "gcc_gfx_tcu_clk", 2854 - .parent_names = (const char *[]){ 2855 - "bimc_ddr_clk_src", 2838 + .parent_hws = (const struct clk_hw*[]){ 2839 + &bimc_ddr_clk_src.clkr.hw, 2856 2840 }, 2857 2841 .num_parents = 1, 2858 2842 .ops = &clk_branch2_ops, ··· 2867 2851 .enable_mask = BIT(13), 2868 2852 .hw.init = &(struct clk_init_data){ 2869 2853 .name = "gcc_gtcu_ahb_clk", 2870 - .parent_names = (const char *[]){ 2871 - "pcnoc_bfdcd_clk_src", 2854 + .parent_hws = (const struct clk_hw*[]){ 2855 + &pcnoc_bfdcd_clk_src.clkr.hw, 2872 2856 }, 2873 2857 .num_parents = 1, 2874 2858 .flags = CLK_SET_RATE_PARENT, ··· 2884 2868 .enable_mask = BIT(0), 2885 2869 .hw.init = &(struct clk_init_data){ 2886 2870 .name = "gcc_bimc_gfx_clk", 2887 - .parent_names = (const char *[]){ 2888 - "bimc_gpu_clk_src", 2871 + .parent_hws = (const struct clk_hw*[]){ 2872 + &bimc_gpu_clk_src.clkr.hw, 2889 2873 }, 2890 2874 .num_parents = 1, 2891 2875 .flags = CLK_SET_RATE_PARENT, ··· 2901 2885 .enable_mask = BIT(0), 2902 2886 .hw.init = &(struct clk_init_data){ 2903 2887 .name = "gcc_bimc_gpu_clk", 2904 - .parent_names = (const char *[]){ 2905 - "bimc_gpu_clk_src", 2888 + .parent_hws = (const struct clk_hw*[]){ 2889 + &bimc_gpu_clk_src.clkr.hw, 2906 2890 }, 2907 2891 .num_parents = 1, 2908 2892 .flags = CLK_SET_RATE_PARENT, ··· 2918 2902 .enable_mask = BIT(10), 2919 2903 .hw.init = &(struct clk_init_data){ 2920 2904 .name = "gcc_jpeg_tbu_clk", 2921 - .parent_names = (const char *[]){ 2922 - "system_noc_bfdcd_clk_src", 2905 + .parent_hws = (const struct clk_hw*[]){ 2906 + &system_noc_bfdcd_clk_src.clkr.hw, 2923 2907 }, 2924 2908 .num_parents = 1, 2925 2909 .flags = CLK_SET_RATE_PARENT, ··· 2935 2919 .enable_mask = BIT(4), 2936 2920 .hw.init = &(struct clk_init_data){ 2937 2921 .name = "gcc_mdp_tbu_clk", 2938 - .parent_names = (const char *[]){ 2939 - "system_noc_bfdcd_clk_src", 2922 + .parent_hws = (const struct clk_hw*[]){ 2923 + &system_noc_bfdcd_clk_src.clkr.hw, 2940 2924 }, 2941 2925 .num_parents = 1, 2942 2926 .flags = CLK_SET_RATE_PARENT, ··· 2952 2936 .enable_mask = BIT(12), 2953 2937 .hw.init = &(struct clk_init_data){ 2954 2938 .name = "gcc_smmu_cfg_clk", 2955 - .parent_names = (const char *[]){ 2956 - "pcnoc_bfdcd_clk_src", 2939 + .parent_hws = (const struct clk_hw*[]){ 2940 + &pcnoc_bfdcd_clk_src.clkr.hw, 2957 2941 }, 2958 2942 .num_parents = 1, 2959 2943 .flags = CLK_SET_RATE_PARENT, ··· 2969 2953 .enable_mask = BIT(5), 2970 2954 .hw.init = &(struct clk_init_data){ 2971 2955 .name = "gcc_venus_tbu_clk", 2972 - .parent_names = (const char *[]){ 2973 - "system_noc_bfdcd_clk_src", 2956 + .parent_hws = (const struct clk_hw*[]){ 2957 + &system_noc_bfdcd_clk_src.clkr.hw, 2974 2958 }, 2975 2959 .num_parents = 1, 2976 2960 .flags = CLK_SET_RATE_PARENT, ··· 2986 2970 .enable_mask = BIT(9), 2987 2971 .hw.init = &(struct clk_init_data){ 2988 2972 .name = "gcc_vfe_tbu_clk", 2989 - .parent_names = (const char *[]){ 2990 - "system_noc_bfdcd_clk_src", 2973 + .parent_hws = (const struct clk_hw*[]){ 2974 + &system_noc_bfdcd_clk_src.clkr.hw, 2991 2975 }, 2992 2976 .num_parents = 1, 2993 2977 .flags = CLK_SET_RATE_PARENT, ··· 3003 2987 .enable_mask = BIT(0), 3004 2988 .hw.init = &(struct clk_init_data){ 3005 2989 .name = "gcc_usb2a_phy_sleep_clk", 3006 - .parent_names = (const char *[]){ 3007 - "sleep_clk_src", 2990 + .parent_data = &(const struct clk_parent_data){ 2991 + .fw_name = "sleep_clk", .name = "sleep_clk_src", 3008 2992 }, 3009 2993 .num_parents = 1, 3010 2994 .flags = CLK_SET_RATE_PARENT, ··· 3020 3004 .enable_mask = BIT(0), 3021 3005 .hw.init = &(struct clk_init_data){ 3022 3006 .name = "gcc_usb_hs_ahb_clk", 3023 - .parent_names = (const char *[]){ 3024 - "pcnoc_bfdcd_clk_src", 3007 + .parent_hws = (const struct clk_hw*[]){ 3008 + &pcnoc_bfdcd_clk_src.clkr.hw, 3025 3009 }, 3026 3010 .num_parents = 1, 3027 3011 .flags = CLK_SET_RATE_PARENT, ··· 3037 3021 .enable_mask = BIT(0), 3038 3022 .hw.init = &(struct clk_init_data){ 3039 3023 .name = "gcc_usb_hs_system_clk", 3040 - .parent_names = (const char *[]){ 3041 - "usb_hs_system_clk_src", 3024 + .parent_hws = (const struct clk_hw*[]){ 3025 + &usb_hs_system_clk_src.clkr.hw, 3042 3026 }, 3043 3027 .num_parents = 1, 3044 3028 .flags = CLK_SET_RATE_PARENT, ··· 3054 3038 .enable_mask = BIT(0), 3055 3039 .hw.init = &(struct clk_init_data){ 3056 3040 .name = "gcc_venus0_ahb_clk", 3057 - .parent_names = (const char *[]){ 3058 - "pcnoc_bfdcd_clk_src", 3041 + .parent_hws = (const struct clk_hw*[]){ 3042 + &pcnoc_bfdcd_clk_src.clkr.hw, 3059 3043 }, 3060 3044 .num_parents = 1, 3061 3045 .flags = CLK_SET_RATE_PARENT, ··· 3071 3055 .enable_mask = BIT(0), 3072 3056 .hw.init = &(struct clk_init_data){ 3073 3057 .name = "gcc_venus0_axi_clk", 3074 - .parent_names = (const char *[]){ 3075 - "system_noc_bfdcd_clk_src", 3058 + .parent_hws = (const struct clk_hw*[]){ 3059 + &system_noc_bfdcd_clk_src.clkr.hw, 3076 3060 }, 3077 3061 .num_parents = 1, 3078 3062 .flags = CLK_SET_RATE_PARENT, ··· 3088 3072 .enable_mask = BIT(0), 3089 3073 .hw.init = &(struct clk_init_data){ 3090 3074 .name = "gcc_venus0_vcodec0_clk", 3091 - .parent_names = (const char *[]){ 3092 - "vcodec0_clk_src", 3075 + .parent_hws = (const struct clk_hw*[]){ 3076 + &vcodec0_clk_src.clkr.hw, 3093 3077 }, 3094 3078 .num_parents = 1, 3095 3079 .flags = CLK_SET_RATE_PARENT,