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drm/amd/display: Modify Vmin default value

Fine tune the Vmin clock value

Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Max Tseng <max.tseng@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Max Tseng and committed by
Alex Deucher
3557db42 776ecb46

+8 -2
+1 -1
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
··· 1914 1914 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1915 1915 dc->caps.color.mpc.ocsc = 1; 1916 1916 1917 - dc->caps.max_disp_clock_khz_at_vmin = 694000; 1917 + dc->caps.max_disp_clock_khz_at_vmin = 650000; 1918 1918 1919 1919 /* Use pipe context based otg sync logic */ 1920 1920 dc->config.use_pipe_ctx_sync_logic = true;
+7 -1
drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c
··· 1830 1830 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1831 1831 dc->caps.color.mpc.ocsc = 1; 1832 1832 1833 - dc->caps.max_disp_clock_khz_at_vmin = 669154; 1833 + /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order 1834 + * to provide some margin. 1835 + * It's expected for furture ASIC to have equal or higher value, in order to 1836 + * have determinstic power improvement from generate to genration. 1837 + * (i.e., we should not expect new ASIC generation with lower vmin rate) 1838 + */ 1839 + dc->caps.max_disp_clock_khz_at_vmin = 650000; 1834 1840 1835 1841 /* Use pipe context based otg sync logic */ 1836 1842 dc->config.use_pipe_ctx_sync_logic = true;