Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Update pmfw_driver_if new structure
[why]
pmfw header file updated, need align with data structure.
[How]
Update the data structure.
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Charlene Liu
and committed by
Alex Deucher
776ecb46
43693e85
+174
-76
+146
-68
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+146
-68
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
···
507
507
}
508
508
};
509
509
510
-
static DpmClocks_t dummy_clocks;
510
+
static DpmClocks_t_dcn35 dummy_clocks;
511
511
512
512
static struct dcn35_watermarks dummy_wms = { 0 };
513
513
···
597
597
static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
598
598
struct dcn35_smu_dpm_clks *smu_dpm_clks)
599
599
{
600
-
DpmClocks_t *table = smu_dpm_clks->dpm_clks;
600
+
DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
601
601
602
602
if (!clk_mgr->smu_ver)
603
603
return;
···
627
627
return max;
628
628
}
629
629
630
-
static unsigned int find_clk_for_voltage(
631
-
const DpmClocks_t *clock_table,
632
-
const uint32_t clocks[],
633
-
unsigned int voltage)
630
+
static inline bool is_valid_clock_value(uint32_t clock_value)
634
631
{
635
-
int i;
636
-
int max_voltage = 0;
637
-
int clock = 0;
632
+
return clock_value > 1 && clock_value < 100000;
633
+
}
638
634
639
-
for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
640
-
if (clock_table->SocVoltage[i] == voltage) {
641
-
return clocks[i];
642
-
} else if (clock_table->SocVoltage[i] >= max_voltage &&
643
-
clock_table->SocVoltage[i] < voltage) {
644
-
max_voltage = clock_table->SocVoltage[i];
645
-
clock = clocks[i];
646
-
}
635
+
static unsigned int convert_wck_ratio(uint8_t wck_ratio)
636
+
{
637
+
switch (wck_ratio) {
638
+
case WCK_RATIO_1_2:
639
+
return 2;
640
+
641
+
case WCK_RATIO_1_4:
642
+
return 4;
643
+
/* Find lowest DPM, FCLK is filled in reverse order*/
644
+
645
+
default:
646
+
break;
647
647
}
648
648
649
-
ASSERT(clock);
650
-
return clock;
649
+
return 1;
651
650
}
652
651
653
652
static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
654
653
struct integrated_info *bios_info,
655
-
const DpmClocks_t *clock_table)
654
+
DpmClocks_t_dcn35 *clock_table)
656
655
{
657
-
int i, j;
658
656
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
659
-
uint32_t max_dispclk = 0, max_dppclk = 0;
657
+
struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
658
+
uint32_t max_pstate = 0, max_uclk = 0, max_fclk = 0;
659
+
uint32_t min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
660
+
int i;
660
661
661
-
j = -1;
662
-
663
-
ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
664
-
665
-
/* Find lowest DPM, FCLK is filled in reverse order*/
666
-
667
-
for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
668
-
if (clock_table->DfPstateTable[i].FClk != 0) {
669
-
j = i;
670
-
break;
662
+
for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
663
+
if (is_valid_clock_value(clock_table->MemPstateTable[i].UClk) &&
664
+
clock_table->MemPstateTable[i].UClk > max_uclk) {
665
+
max_uclk = clock_table->MemPstateTable[i].UClk;
666
+
max_pstate = i;
671
667
}
672
668
}
673
669
674
-
if (j == -1) {
675
-
/* clock table is all 0s, just use our own hardcode */
676
-
ASSERT(0);
677
-
return;
678
-
}
670
+
/* We expect the table to contain at least one valid Uclk entry. */
671
+
ASSERT(is_valid_clock_value(max_uclk));
679
672
680
-
bw_params->clk_table.num_entries = j + 1;
681
673
682
674
/* dispclk and dppclk can be max at any voltage, same number of levels for both */
683
675
if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
684
676
clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
685
-
max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
686
-
max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
677
+
max_dispclk = find_max_clk_value(clock_table->DispClocks,
678
+
clock_table->NumDispClkLevelsEnabled);
679
+
max_dppclk = find_max_clk_value(clock_table->DppClocks,
680
+
clock_table->NumDispClkLevelsEnabled);
687
681
} else {
688
682
ASSERT(0);
689
683
}
684
+
if (clock_table->NumFclkLevelsEnabled <= NUM_FCLK_DPM_LEVELS)
685
+
max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq,
686
+
clock_table->NumFclkLevelsEnabled);
690
687
691
-
for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
692
-
bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
693
-
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
694
-
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
695
-
switch (clock_table->DfPstateTable[j].WckRatio) {
696
-
case WCK_RATIO_1_2:
697
-
bw_params->clk_table.entries[i].wck_ratio = 2;
698
-
break;
699
-
case WCK_RATIO_1_4:
700
-
bw_params->clk_table.entries[i].wck_ratio = 4;
701
-
break;
702
-
default:
703
-
bw_params->clk_table.entries[i].wck_ratio = 1;
688
+
for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
689
+
uint32_t min_uclk = clock_table->MemPstateTable[0].UClk;
690
+
int j;
691
+
692
+
for (j = 1; j < clock_table->NumMemPstatesEnabled; j++) {
693
+
if (is_valid_clock_value(clock_table->MemPstateTable[j].UClk) &&
694
+
clock_table->MemPstateTable[j].UClk < min_uclk &&
695
+
clock_table->MemPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
696
+
min_uclk = clock_table->MemPstateTable[j].UClk;
697
+
min_pstate = j;
698
+
}
704
699
}
705
-
bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
706
-
bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
700
+
701
+
for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
702
+
if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
703
+
break;
704
+
705
+
bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
706
+
bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
707
+
bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
708
+
bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
709
+
bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
710
+
bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
711
+
bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
712
+
bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
707
713
bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
708
714
bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
709
-
}
715
+
bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
716
+
clock_table->MemPstateTable[min_pstate].WckRatio);
717
+
}
710
718
719
+
/* Make sure to include at least one entry at highest pstate */
720
+
if (max_pstate != min_pstate || i == 0) {
721
+
if (i > MAX_NUM_DPM_LVL - 1)
722
+
i = MAX_NUM_DPM_LVL - 1;
723
+
bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
724
+
bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
725
+
bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
726
+
bw_params->clk_table.entries[i].dcfclk_mhz =
727
+
find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
728
+
bw_params->clk_table.entries[i].socclk_mhz =
729
+
find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
730
+
bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
731
+
bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
732
+
bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
733
+
clock_table->MemPstateTable[max_pstate].WckRatio);
734
+
i++;
735
+
}
736
+
bw_params->clk_table.num_entries = i--;
737
+
738
+
bw_params->clk_table.entries[i].socclk_mhz =
739
+
find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
740
+
bw_params->clk_table.entries[i].dispclk_mhz =
741
+
find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
742
+
bw_params->clk_table.entries[i].dppclk_mhz =
743
+
find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
744
+
bw_params->clk_table.entries[i].fclk_mhz =
745
+
find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
746
+
ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
747
+
bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
748
+
bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
749
+
bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
750
+
bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
751
+
bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
752
+
bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
753
+
bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
754
+
bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
755
+
bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
756
+
for (i = 0; i < bw_params->clk_table.num_entries; i++) {
757
+
if (!bw_params->clk_table.entries[i].fclk_mhz) {
758
+
bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
759
+
bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
760
+
bw_params->clk_table.entries[i].voltage = def_max.voltage;
761
+
}
762
+
if (!bw_params->clk_table.entries[i].dcfclk_mhz)
763
+
bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
764
+
if (!bw_params->clk_table.entries[i].socclk_mhz)
765
+
bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
766
+
if (!bw_params->clk_table.entries[i].dispclk_mhz)
767
+
bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
768
+
if (!bw_params->clk_table.entries[i].dppclk_mhz)
769
+
bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
770
+
if (!bw_params->clk_table.entries[i].fclk_mhz)
771
+
bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
772
+
if (!bw_params->clk_table.entries[i].phyclk_mhz)
773
+
bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
774
+
if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
775
+
bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
776
+
if (!bw_params->clk_table.entries[i].dtbclk_mhz)
777
+
bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
778
+
}
779
+
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
711
780
bw_params->vram_type = bios_info->memory_type;
781
+
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
712
782
bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
713
783
714
784
for (i = 0; i < WM_SET_COUNT; i++) {
···
1008
938
}
1009
939
ASSERT(clk_mgr->smu_wm_set.wm_set);
1010
940
1011
-
smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
941
+
smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1012
942
clk_mgr->base.base.ctx,
1013
943
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1014
-
sizeof(DpmClocks_t),
944
+
sizeof(DpmClocks_t_dcn35),
1015
945
&smu_dpm_clks.mc_address.quad_part);
1016
946
1017
947
if (smu_dpm_clks.dpm_clks == NULL) {
···
1058
988
"NumDispClkLevelsEnabled: %d\n"
1059
989
"NumSocClkLevelsEnabled: %d\n"
1060
990
"VcnClkLevelsEnabled: %d\n"
1061
-
"NumDfPst atesEnabled: %d\n"
991
+
"FClkLevelsEnabled: %d\n"
992
+
"NumMemPstatesEnabled: %d\n"
1062
993
"MinGfxClk: %d\n"
1063
994
"MaxGfxClk: %d\n",
1064
995
smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1065
996
smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1066
997
smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1067
998
smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1068
-
smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
999
+
smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1000
+
smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1069
1001
smu_dpm_clks.dpm_clks->MinGfxClk,
1070
1002
smu_dpm_clks.dpm_clks->MaxGfxClk);
1071
1003
for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
···
1083
1011
DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1084
1012
i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1085
1013
}
1086
-
for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
1014
+
for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1015
+
DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1016
+
i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1017
+
DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1018
+
i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1019
+
}
1020
+
for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1087
1021
DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1088
1022
i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1089
1023
1090
-
for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
1091
-
DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
1092
-
"smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
1093
-
"smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
1094
-
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
1095
-
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
1096
-
i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
1024
+
for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1025
+
DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1026
+
"smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1027
+
"smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1028
+
i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1029
+
i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1030
+
i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1097
1031
}
1098
1032
1099
1033
if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
+28
-8
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
+28
-8
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.h
···
79
79
#define NUM_SOCCLK_DPM_LEVELS 8
80
80
#define NUM_VCN_DPM_LEVELS 8
81
81
#define NUM_SOC_VOLTAGE_LEVELS 8
82
-
#define NUM_DF_PSTATE_LEVELS 4
82
+
#define NUM_VPE_DPM_LEVELS 8
83
+
#define NUM_FCLK_DPM_LEVELS 8
84
+
#define NUM_MEM_PSTATE_LEVELS 4
83
85
84
86
typedef enum{
85
87
WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
···
91
89
} WCK_RATIO_e;
92
90
93
91
typedef struct {
94
-
uint32_t FClk;
92
+
uint32_t UClk;
95
93
uint32_t MemClk;
96
94
uint32_t Voltage;
97
95
uint8_t WckRatio;
98
96
uint8_t Spare[3];
99
-
} DfPstateTable_t;
97
+
} MemPstateTable_t;
100
98
101
99
//Freq in MHz
102
100
//Voltage in milli volts with 2 fractional bits
···
107
105
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
108
106
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
109
107
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
108
+
uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
109
+
uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
110
+
uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
110
111
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
111
-
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
112
+
MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
112
113
113
114
uint8_t NumDcfClkLevelsEnabled;
114
115
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
115
116
uint8_t NumSocClkLevelsEnabled;
116
117
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
117
-
uint8_t NumDfPstatesEnabled;
118
-
uint8_t spare[3];
118
+
uint8_t VpeClkLevelsEnabled;
119
+
uint8_t NumMemPstatesEnabled;
120
+
uint8_t NumFclkLevelsEnabled;
121
+
uint8_t spare[2];
119
122
120
123
uint32_t MinGfxClk;
121
124
uint32_t MaxGfxClk;
122
-
} DpmClocks_t;
125
+
} DpmClocks_t_dcn35;
126
+
127
+
128
+
// Throttler Status Bitmask
129
+
130
+
131
+
132
+
133
+
134
+
135
+
136
+
137
+
138
+
123
139
124
140
#define TABLE_BIOS_IF 0 // Called by BIOS
125
141
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
···
159
139
};
160
140
161
141
struct dcn35_smu_dpm_clks {
162
-
DpmClocks_t *dpm_clks;
142
+
DpmClocks_t_dcn35 *dpm_clks;
163
143
union large_integer mc_address;
164
144
};
165
145