tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-etnaviv-next-2024-11-07' of https://git.pengutronix.de/git/lst/linux into drm-next

- improve handling of DMA address limited systems
- improve GPU hangcheck
- fix address space collision on >= 4K CPU pages
- flush all known writeback caches before memory release
- various code cleanups

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Lucas Stach <l.stach@pengutronix.de>
Link: https://patchwork.freedesktop.org/patch/msgid/c84075a0257e7bee222d008fa3118117422d664e.camel@pengutronix.de

Dave Airlie 35a6e15a 1f8bdc31

+107 -91
+2 -1
drivers/gpu/drm/etnaviv/etnaviv_buffer.c
··· 482 482 } else { 483 483 CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, 484 484 VIVS_GL_FLUSH_CACHE_DEPTH | 485 - VIVS_GL_FLUSH_CACHE_COLOR); 485 + VIVS_GL_FLUSH_CACHE_COLOR | 486 + VIVS_GL_FLUSH_CACHE_SHADER_L1); 486 487 if (has_blt) { 487 488 CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1); 488 489 CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
+2 -2
drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c
··· 5 5 6 6 #include <linux/dma-mapping.h> 7 7 8 - #include <drm/drm_mm.h> 9 - 10 8 #include "etnaviv_cmdbuf.h" 11 9 #include "etnaviv_gem.h" 12 10 #include "etnaviv_gpu.h" ··· 53 55 return suballoc; 54 56 55 57 free_suballoc: 58 + mutex_destroy(&suballoc->lock); 56 59 kfree(suballoc); 57 60 58 61 return ERR_PTR(ret); ··· 78 79 { 79 80 dma_free_wc(suballoc->dev, SUBALLOC_SIZE, suballoc->vaddr, 80 81 suballoc->paddr); 82 + mutex_destroy(&suballoc->lock); 81 83 kfree(suballoc); 82 84 } 83 85
+16 -5
drivers/gpu/drm/etnaviv/etnaviv_drv.c
··· 538 538 priv->num_gpus = 0; 539 539 priv->shm_gfp_mask = GFP_HIGHUSER | __GFP_RETRY_MAYFAIL | __GFP_NOWARN; 540 540 541 + /* 542 + * If the GPU is part of a system with DMA addressing limitations, 543 + * request pages for our SHM backend buffers from the DMA32 zone to 544 + * hopefully avoid performance killing SWIOTLB bounce buffering. 545 + */ 546 + if (dma_addressing_limited(dev)) { 547 + priv->shm_gfp_mask |= GFP_DMA32; 548 + priv->shm_gfp_mask &= ~__GFP_HIGHMEM; 549 + } 550 + 541 551 priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(drm->dev); 542 552 if (IS_ERR(priv->cmdbuf_suballoc)) { 543 553 dev_err(drm->dev, "Failed to create cmdbuf suballocator\n"); ··· 574 564 out_destroy_suballoc: 575 565 etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); 576 566 out_free_priv: 567 + mutex_destroy(&priv->gem_lock); 577 568 kfree(priv); 578 569 out_put: 579 570 drm_dev_put(drm); ··· 619 608 if (!of_device_is_available(core_node)) 620 609 continue; 621 610 622 - drm_of_component_match_add(&pdev->dev, &match, 611 + drm_of_component_match_add(dev, &match, 623 612 component_compare_of, core_node); 624 613 } 625 614 } else { ··· 642 631 * bit to make sure we are allocating the command buffers and 643 632 * TLBs in the lower 4 GiB address space. 644 633 */ 645 - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)) || 646 - dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { 647 - dev_dbg(&pdev->dev, "No suitable DMA available\n"); 634 + if (dma_set_mask(dev, DMA_BIT_MASK(40)) || 635 + dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) { 636 + dev_dbg(dev, "No suitable DMA available\n"); 648 637 return -ENODEV; 649 638 } 650 639 ··· 655 644 */ 656 645 first_node = etnaviv_of_first_available_node(); 657 646 if (first_node) { 658 - of_dma_configure(&pdev->dev, first_node, true); 647 + of_dma_configure(dev, first_node, true); 659 648 of_node_put(first_node); 660 649 } 661 650
+7 -7
drivers/gpu/drm/etnaviv/etnaviv_gem.c
··· 514 514 etnaviv_obj->ops->release(etnaviv_obj); 515 515 drm_gem_object_release(obj); 516 516 517 + mutex_destroy(&etnaviv_obj->lock); 517 518 kfree(etnaviv_obj); 518 519 } 519 520 ··· 544 543 .vm_ops = &vm_ops, 545 544 }; 546 545 547 - static int etnaviv_gem_new_impl(struct drm_device *dev, u32 flags, 546 + static int etnaviv_gem_new_impl(struct drm_device *dev, u32 size, u32 flags, 548 547 const struct etnaviv_gem_ops *ops, struct drm_gem_object **obj) 549 548 { 550 549 struct etnaviv_gem_object *etnaviv_obj; ··· 571 570 if (!etnaviv_obj) 572 571 return -ENOMEM; 573 572 573 + etnaviv_obj->size = ALIGN(size, SZ_4K); 574 574 etnaviv_obj->flags = flags; 575 575 etnaviv_obj->ops = ops; 576 576 ··· 592 590 struct drm_gem_object *obj = NULL; 593 591 int ret; 594 592 595 - size = PAGE_ALIGN(size); 596 - 597 - ret = etnaviv_gem_new_impl(dev, flags, &etnaviv_gem_shmem_ops, &obj); 593 + ret = etnaviv_gem_new_impl(dev, size, flags, &etnaviv_gem_shmem_ops, &obj); 598 594 if (ret) 599 595 goto fail; 600 596 601 597 lockdep_set_class(&to_etnaviv_bo(obj)->lock, &etnaviv_shm_lock_class); 602 598 603 - ret = drm_gem_object_init(dev, obj, size); 599 + ret = drm_gem_object_init(dev, obj, PAGE_ALIGN(size)); 604 600 if (ret) 605 601 goto fail; 606 602 ··· 627 627 struct drm_gem_object *obj; 628 628 int ret; 629 629 630 - ret = etnaviv_gem_new_impl(dev, flags, ops, &obj); 630 + ret = etnaviv_gem_new_impl(dev, size, flags, ops, &obj); 631 631 if (ret) 632 632 return ret; 633 633 ··· 686 686 kfree(etnaviv_obj->sgt); 687 687 } 688 688 if (etnaviv_obj->pages) { 689 - int npages = etnaviv_obj->base.size >> PAGE_SHIFT; 689 + unsigned int npages = etnaviv_obj->base.size >> PAGE_SHIFT; 690 690 691 691 unpin_user_pages(etnaviv_obj->pages, npages); 692 692 kvfree(etnaviv_obj->pages);
+5
drivers/gpu/drm/etnaviv/etnaviv_gem.h
··· 36 36 const struct etnaviv_gem_ops *ops; 37 37 struct mutex lock; 38 38 39 + /* 40 + * The actual size that is visible to the GPU, not necessarily 41 + * PAGE_SIZE aligned, but should be aligned to GPU page size. 42 + */ 43 + u32 size; 39 44 u32 flags; 40 45 41 46 struct list_head gem_node;
+1 -1
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
··· 17 17 struct sg_table *etnaviv_gem_prime_get_sg_table(struct drm_gem_object *obj) 18 18 { 19 19 struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); 20 - int npages = obj->size >> PAGE_SHIFT; 20 + unsigned int npages = obj->size >> PAGE_SHIFT; 21 21 22 22 if (WARN_ON(!etnaviv_obj->pages)) /* should have already pinned! */ 23 23 return ERR_PTR(-EINVAL);
-1
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
··· 6 6 #include <drm/drm_file.h> 7 7 #include <linux/dma-fence-array.h> 8 8 #include <linux/file.h> 9 - #include <linux/pm_runtime.h> 10 9 #include <linux/dma-resv.h> 11 10 #include <linux/sync_file.h> 12 11 #include <linux/uaccess.h>
+29 -35
drivers/gpu/drm/etnaviv/etnaviv_gpu.c
··· 574 574 continue; 575 575 } 576 576 577 - /* disable debug registers, as they are not normally needed */ 578 - control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 577 + /* enable debug register access */ 578 + control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 579 579 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 580 580 581 581 failed = false; ··· 839 839 if (ret) 840 840 goto fail; 841 841 842 - /* 843 - * If the GPU is part of a system with DMA addressing limitations, 844 - * request pages for our SHM backend buffers from the DMA32 zone to 845 - * hopefully avoid performance killing SWIOTLB bounce buffering. 846 - */ 847 - if (dma_addressing_limited(gpu->dev)) 848 - priv->shm_gfp_mask |= GFP_DMA32; 849 - 850 842 /* Create buffer: */ 851 - ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, 852 - PAGE_SIZE); 843 + ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K); 853 844 if (ret) { 854 845 dev_err(gpu->dev, "could not create command buffer\n"); 855 846 goto fail; ··· 1321 1330 { 1322 1331 u32 val; 1323 1332 1333 + mutex_lock(&gpu->lock); 1334 + 1324 1335 /* disable clock gating */ 1325 1336 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1326 1337 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1327 1338 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1328 1339 1329 - /* enable debug register */ 1330 - val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1331 - val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1332 - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1333 - 1334 1340 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1341 + 1342 + mutex_unlock(&gpu->lock); 1335 1343 } 1336 1344 1337 1345 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, ··· 1340 1350 unsigned int i; 1341 1351 u32 val; 1342 1352 1353 + mutex_lock(&gpu->lock); 1354 + 1343 1355 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1356 + 1357 + /* enable clock gating */ 1358 + val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1359 + val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1360 + gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1361 + 1362 + mutex_unlock(&gpu->lock); 1344 1363 1345 1364 for (i = 0; i < submit->nr_pmrs; i++) { 1346 1365 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1347 1366 1348 1367 *pmr->bo_vma = pmr->sequence; 1349 1368 } 1350 - 1351 - /* disable debug register */ 1352 - val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1353 - val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1354 - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1355 - 1356 - /* enable clock gating */ 1357 - val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); 1358 - val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1359 - gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); 1360 1369 } 1361 1370 1362 1371 ··· 1851 1862 if (!gpu) 1852 1863 return -ENOMEM; 1853 1864 1854 - gpu->dev = &pdev->dev; 1865 + gpu->dev = dev; 1855 1866 mutex_init(&gpu->lock); 1856 1867 mutex_init(&gpu->sched_lock); 1857 1868 ··· 1865 1876 if (gpu->irq < 0) 1866 1877 return gpu->irq; 1867 1878 1868 - err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1869 - dev_name(gpu->dev), gpu); 1879 + err = devm_request_irq(dev, gpu->irq, irq_handler, 0, 1880 + dev_name(dev), gpu); 1870 1881 if (err) { 1871 1882 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1872 1883 return err; ··· 1903 1914 * autosuspend delay is rather arbitary: no measurements have 1904 1915 * yet been performed to determine an appropriate value. 1905 1916 */ 1906 - pm_runtime_use_autosuspend(gpu->dev); 1907 - pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1908 - pm_runtime_enable(gpu->dev); 1917 + pm_runtime_use_autosuspend(dev); 1918 + pm_runtime_set_autosuspend_delay(dev, 200); 1919 + pm_runtime_enable(dev); 1909 1920 1910 - err = component_add(&pdev->dev, &gpu_ops); 1921 + err = component_add(dev, &gpu_ops); 1911 1922 if (err < 0) { 1912 - dev_err(&pdev->dev, "failed to register component: %d\n", err); 1923 + dev_err(dev, "failed to register component: %d\n", err); 1913 1924 return err; 1914 1925 } 1915 1926 ··· 1918 1929 1919 1930 static void etnaviv_gpu_platform_remove(struct platform_device *pdev) 1920 1931 { 1932 + struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev); 1933 + 1921 1934 component_del(&pdev->dev, &gpu_ops); 1922 1935 pm_runtime_disable(&pdev->dev); 1936 + 1937 + mutex_destroy(&gpu->lock); 1938 + mutex_destroy(&gpu->sched_lock); 1923 1939 } 1924 1940 1925 1941 static int etnaviv_gpu_rpm_suspend(struct device *dev)
+1
drivers/gpu/drm/etnaviv/etnaviv_gpu.h
··· 144 144 145 145 /* hang detection */ 146 146 u32 hangcheck_dma_addr; 147 + u32 hangcheck_primid; 147 148 u32 hangcheck_fence; 148 149 149 150 void __iomem *mmio;
+14 -26
drivers/gpu/drm/etnaviv/etnaviv_mmu.c
··· 69 69 return ret; 70 70 } 71 71 72 - static int etnaviv_iommu_map(struct etnaviv_iommu_context *context, u32 iova, 72 + static int etnaviv_iommu_map(struct etnaviv_iommu_context *context, 73 + u32 iova, unsigned int va_len, 73 74 struct sg_table *sgt, int prot) 74 - { struct scatterlist *sg; 75 + { 76 + struct scatterlist *sg; 75 77 unsigned int da = iova; 76 78 unsigned int i; 77 79 int ret; ··· 83 81 84 82 for_each_sgtable_dma_sg(sgt, sg, i) { 85 83 phys_addr_t pa = sg_dma_address(sg) - sg->offset; 86 - size_t bytes = sg_dma_len(sg) + sg->offset; 84 + unsigned int da_len = sg_dma_len(sg) + sg->offset; 85 + unsigned int bytes = min_t(unsigned int, da_len, va_len); 87 86 88 - VERB("map[%d]: %08x %pap(%zx)", i, iova, &pa, bytes); 87 + VERB("map[%d]: %08x %pap(%x)", i, iova, &pa, bytes); 89 88 90 89 ret = etnaviv_context_map(context, da, pa, bytes, prot); 91 90 if (ret) 92 91 goto fail; 93 92 93 + va_len -= bytes; 94 94 da += bytes; 95 95 } 96 96 ··· 108 104 static void etnaviv_iommu_unmap(struct etnaviv_iommu_context *context, u32 iova, 109 105 struct sg_table *sgt, unsigned len) 110 106 { 111 - struct scatterlist *sg; 112 - unsigned int da = iova; 113 - int i; 114 - 115 - for_each_sgtable_dma_sg(sgt, sg, i) { 116 - size_t bytes = sg_dma_len(sg) + sg->offset; 117 - 118 - etnaviv_context_unmap(context, da, bytes); 119 - 120 - VERB("unmap[%d]: %08x(%zx)", i, iova, bytes); 121 - 122 - BUG_ON(!PAGE_ALIGNED(bytes)); 123 - 124 - da += bytes; 125 - } 107 + etnaviv_context_unmap(context, iova, len); 126 108 127 109 context->flush_seq++; 128 110 } ··· 121 131 lockdep_assert_held(&context->lock); 122 132 123 133 etnaviv_iommu_unmap(context, mapping->vram_node.start, 124 - etnaviv_obj->sgt, etnaviv_obj->base.size); 134 + etnaviv_obj->sgt, etnaviv_obj->size); 125 135 drm_mm_remove_node(&mapping->vram_node); 126 136 } 127 137 ··· 295 305 node = &mapping->vram_node; 296 306 297 307 if (va) 298 - ret = etnaviv_iommu_insert_exact(context, node, 299 - etnaviv_obj->base.size, va); 308 + ret = etnaviv_iommu_insert_exact(context, node, etnaviv_obj->size, va); 300 309 else 301 - ret = etnaviv_iommu_find_iova(context, node, 302 - etnaviv_obj->base.size); 310 + ret = etnaviv_iommu_find_iova(context, node, etnaviv_obj->size); 303 311 if (ret < 0) 304 312 goto unlock; 305 313 306 314 mapping->iova = node->start; 307 - ret = etnaviv_iommu_map(context, node->start, sgt, 315 + ret = etnaviv_iommu_map(context, node->start, etnaviv_obj->size, sgt, 308 316 ETNAVIV_PROT_READ | ETNAVIV_PROT_WRITE); 309 317 310 318 if (ret < 0) { ··· 346 358 container_of(kref, struct etnaviv_iommu_context, refcount); 347 359 348 360 etnaviv_cmdbuf_suballoc_unmap(context, &context->cmdbuf_mapping); 349 - 361 + mutex_destroy(&context->lock); 350 362 context->global->ops->free(context); 351 363 } 352 364 void etnaviv_iommu_context_put(struct etnaviv_iommu_context *context)
-1
drivers/gpu/drm/etnaviv/etnaviv_mmu.h
··· 61 61 /* P(age) T(able) A(rray) */ 62 62 u64 *pta_cpu; 63 63 dma_addr_t pta_dma; 64 - struct spinlock pta_lock; 65 64 DECLARE_BITMAP(pta_alloc, ETNAVIV_PTA_ENTRIES); 66 65 } v2; 67 66 };
+4
drivers/gpu/drm/etnaviv/etnaviv_perfmon.c
··· 62 62 u32 value = 0; 63 63 unsigned i; 64 64 65 + lockdep_assert_held(&gpu->lock); 66 + 65 67 for (i = 0; i < gpu->identity.pixel_pipes; i++) { 66 68 pipe_select(gpu, clock, i); 67 69 value += perf_reg_read(gpu, domain, signal); ··· 82 80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 83 81 u32 value = 0; 84 82 unsigned i; 83 + 84 + lockdep_assert_held(&gpu->lock); 85 85 86 86 for (i = 0; i < gpu->identity.pixel_pipes; i++) { 87 87 pipe_select(gpu, clock, i);
+15 -2
drivers/gpu/drm/etnaviv/etnaviv_sched.c
··· 11 11 #include "etnaviv_gpu.h" 12 12 #include "etnaviv_sched.h" 13 13 #include "state.xml.h" 14 + #include "state_hi.xml.h" 14 15 15 16 static int etnaviv_job_hang_limit = 0; 16 17 module_param_named(job_hang_limit, etnaviv_job_hang_limit, int , 0444); ··· 36 35 { 37 36 struct etnaviv_gem_submit *submit = to_etnaviv_submit(sched_job); 38 37 struct etnaviv_gpu *gpu = submit->gpu; 39 - u32 dma_addr; 38 + u32 dma_addr, primid = 0; 40 39 int change; 41 40 42 41 /* ··· 53 52 */ 54 53 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 55 54 change = dma_addr - gpu->hangcheck_dma_addr; 55 + if (submit->exec_state == ETNA_PIPE_3D) { 56 + /* guard against concurrent usage from perfmon_sample */ 57 + mutex_lock(&gpu->lock); 58 + gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, 59 + VIVS_MC_PROFILE_CONFIG0_FE_CURRENT_PRIM << 60 + VIVS_MC_PROFILE_CONFIG0_FE__SHIFT); 61 + primid = gpu_read(gpu, VIVS_MC_PROFILE_FE_READ); 62 + mutex_unlock(&gpu->lock); 63 + } 56 64 if (gpu->state == ETNA_GPU_STATE_RUNNING && 57 65 (gpu->completed_fence != gpu->hangcheck_fence || 58 - change < 0 || change > 16)) { 66 + change < 0 || change > 16 || 67 + (submit->exec_state == ETNA_PIPE_3D && 68 + gpu->hangcheck_primid != primid))) { 59 69 gpu->hangcheck_dma_addr = dma_addr; 70 + gpu->hangcheck_primid = primid; 60 71 gpu->hangcheck_fence = gpu->completed_fence; 61 72 goto out_no_timeout; 62 73 }
+11 -10
drivers/gpu/drm/etnaviv/state_hi.xml.h
··· 8 8 git clone git://0x04.net/rules-ng-ng 9 9 10 10 The rules-ng-ng source files this header was generated from are: 11 - - state.xml ( 29355 bytes, from 2024-01-19 10:18:54) 12 - - common.xml ( 35664 bytes, from 2023-12-06 10:55:32) 13 - - common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) 14 - - state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17) 15 - - copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) 16 - - state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03) 17 - - state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54) 18 - - state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09) 19 - - state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) 11 + - state.xml ( 30729 bytes, from 2024-06-21 11:31:54) 12 + - common.xml ( 35664 bytes, from 2023-12-13 09:33:18) 13 + - common_3d.xml ( 15069 bytes, from 2023-12-13 09:33:18) 14 + - state_hi.xml ( 35909 bytes, from 2024-06-21 11:31:54) 15 + - copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) 16 + - state_2d.xml ( 52271 bytes, from 2023-05-30 20:50:02) 17 + - state_3d.xml ( 89626 bytes, from 2024-06-21 11:32:57) 18 + - state_blt.xml ( 14592 bytes, from 2023-12-13 09:33:18) 19 + - state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) 20 20 21 - Copyright (C) 2012-2023 by the following authors: 21 + Copyright (C) 2012-2024 by the following authors: 22 22 - Wladimir J. van der Laan <laanwj@gmail.com> 23 23 - Christian Gmeiner <christian.gmeiner@gmail.com> 24 24 - Lucas Stach <l.stach@pengutronix.de> ··· 467 467 #define VIVS_MC_PROFILE_CONFIG0 0x00000470 468 468 #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff 469 469 #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 470 + #define VIVS_MC_PROFILE_CONFIG0_FE_CURRENT_PRIM 0x00000009 470 471 #define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT 0x0000000a 471 472 #define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT 0x0000000b 472 473 #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT 0x0000000c