Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"The two large chunks is the header clean-up from Andy and the Qualcomm
DT bindings clean-up from Krzysztof. Each which could give rise to
conflicts, but I haven't seen any.
The YAML conversions happening around the device tree is the biggest
item in the series and is the result of Rob Herrings ambition to
autovalidate these trees against strict schemas and it is paying off
in lots of bugs found and ever prettier device trees. Sooner or later
the transition will be complete, Krzysztof is fixing up all of the
Qualcomm stuff, which is pretty voluminous.
Core changes:
- minor but nice and important documentation clean-ups
New drivers:
- subdriver for the Qualcomm SDM670 SoC
- subdriver for the Intel Moorefield SoC
- trivial support for the NXP Freescale i.MXRT1170 SoC
Other changes and improvements
- major clean-up of the Qualcomm pin control device tree bindings by
Krzysztof
- major header clean-up by Andy
- some immutable irqchip clean-up for the Actions Semiconductor and
Nuvoton drivers
- GPIO helpers for The Cypress cy8c95x0 driver
- bias handling in the Mediatek MT7986 driver
- remove the unused pins-are-numbered concept that never flew"
* tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits)
pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()
dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered
dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered
pinctrl: stm32: Remove check for pins-are-numbered
pinctrl: mediatek: common: Remove check for pins-are-numbered
pinctrl: qcom: remove duplicate included header files
pinctrl: sunxi: d1: Add CAN bus pinmuxes
pinctrl: loongson2: Fix some const correctness
pinctrl: pinconf-generic: add missing of_node_put()
pinctrl: intel: Enumerate PWM device when community has a capability
pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
pwm: lpss: Allow other drivers to enable PWM LPSS
pwm: lpss: Include headers we are the direct user of
pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
pwm: Add a stub for devm_pwmchip_add()
pinctrl: k210: call of_node_put()
pinctrl: starfive: Use existing variable gpio
dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching
pinconf-generic: fix style issues in pin_config_param doc
pinctrl: pinctrl-loongson2: fix Kconfig dependency
...
+7902
-4773
+12
Documentation/devicetree/bindings/arm/fsl.yaml
+12
Documentation/devicetree/bindings/arm/fsl.yaml
···
1070
1070
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
1071
1071
- const: fsl,imx93
1072
1072
1073
+
- description: i.MXRT1050 based Boards
1074
+
items:
1075
+
- enum:
1076
+
- fsl,imxrt1050-evk # i.MXRT1050 EVK Board
1077
+
- const: fsl,imxrt1050
1078
+
1079
+
- description: i.MXRT1170 based Boards
1080
+
items:
1081
+
- enum:
1082
+
- fsl,imxrt1170-evk # i.MXRT1170 EVK Board
1083
+
- const: fsl,imxrt1170
1084
+
1073
1085
- description:
1074
1086
Freescale Vybrid Platform Device Tree Bindings
1075
1087
+4
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+4
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
···
35
35
each entry consists of 6 integers and represents the mux and config
36
36
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
37
37
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
38
-
be found in <include/dt-bindings/pinctrl/pins-imxrt1050.h>. The last
38
+
be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last
39
39
integer CONFIG is the pad setting value like pull-up on this pin. Please
40
40
refer to i.MXRT1050 Reference Manual for detailed CONFIG settings.
41
41
$ref: /schemas/types.yaml#/definitions/uint32-matrix
+123
Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml
+123
Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Loongson-2 SoC Pinctrl Controller
8
+
9
+
maintainers:
10
+
- zhanghongchen <zhanghongchen@loongson.cn>
11
+
- Yinbo Zhu <zhuyinbo@loongson.cn>
12
+
13
+
allOf:
14
+
- $ref: pinctrl.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: loongson,ls2k-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
patternProperties:
24
+
'-pins$':
25
+
type: object
26
+
27
+
additionalProperties: false
28
+
29
+
patternProperties:
30
+
'pinmux$':
31
+
type: object
32
+
description: node for pinctrl.
33
+
$ref: pinmux-node.yaml#
34
+
35
+
unevaluatedProperties: false
36
+
37
+
properties:
38
+
groups:
39
+
description:
40
+
One or more groups of pins to mux to a certain function
41
+
items:
42
+
enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
43
+
nand, sata_led, i2s, hda]
44
+
function:
45
+
description:
46
+
The function that a group of pins is muxed to
47
+
enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
48
+
nand, sata_led, i2s, hda]
49
+
50
+
required:
51
+
- groups
52
+
- function
53
+
54
+
required:
55
+
- compatible
56
+
- reg
57
+
58
+
additionalProperties: false
59
+
60
+
examples:
61
+
- |
62
+
pctrl: pinctrl@1fe00420 {
63
+
compatible = "loongson,ls2k-pinctrl";
64
+
reg = <0x1fe00420 0x18>;
65
+
sdio_pins_default: sdio-pins {
66
+
sdio-pinmux {
67
+
groups = "sdio";
68
+
function = "sdio";
69
+
};
70
+
71
+
sdio-det-pinmux {
72
+
groups = "pwm2";
73
+
function = "gpio";
74
+
};
75
+
};
76
+
77
+
pwm1_pins_default: pwm1-pins {
78
+
pinmux {
79
+
groups = "pwm1";
80
+
function = "pwm1";
81
+
};
82
+
};
83
+
84
+
pwm0_pins_default: pwm0-pins {
85
+
pinmux {
86
+
groups = "pwm0";
87
+
function = "pwm0";
88
+
};
89
+
};
90
+
91
+
i2c1_pins_default: i2c1-pins {
92
+
pinmux {
93
+
groups = "i2c1";
94
+
function = "i2c1";
95
+
};
96
+
};
97
+
98
+
i2c0_pins_default: i2c0-pins {
99
+
pinmux {
100
+
groups = "i2c0";
101
+
function = "i2c0";
102
+
};
103
+
};
104
+
105
+
nand_pins_default: nand-pins {
106
+
pinmux {
107
+
groups = "nand";
108
+
function = "nand";
109
+
};
110
+
};
111
+
112
+
hda_pins_default: hda-pins {
113
+
grp0-pinmux {
114
+
groups = "hda";
115
+
function = "hda";
116
+
};
117
+
118
+
grp1-pinmux {
119
+
groups = "i2s";
120
+
function = "gpio";
121
+
};
122
+
};
123
+
};
+2
-3
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
+2
-3
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
···
31
31
pins-are-numbered:
32
32
$ref: /schemas/types.yaml#/definitions/flag
33
33
description: |
34
-
Specify the subnodes are using numbered pinmux to specify pins.
34
+
Specify the subnodes are using numbered pinmux to specify pins. (UNUSED)
35
+
deprecated: true
35
36
36
37
gpio-controller: true
37
38
···
63
62
64
63
required:
65
64
- compatible
66
-
- pins-are-numbered
67
65
- gpio-controller
68
66
- "#gpio-cells"
69
67
···
150
150
compatible = "mediatek,mt8135-pinctrl";
151
151
reg = <0 0x1000B000 0 0x1000>;
152
152
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
153
-
pins-are-numbered;
154
153
gpio-controller;
155
154
#gpio-cells = <2>;
156
155
interrupt-controller;
+68
-25
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
+68
-25
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
···
8
8
9
9
maintainers:
10
10
- Andy Teng <andy.teng@mediatek.com>
11
+
- Sean Wang <sean.wang@kernel.org>
11
12
12
-
description: |+
13
-
The pin controller node should be the child of a syscon node with the
14
-
required property:
15
-
- compatible: "syscon"
13
+
description:
14
+
The MediaTek pin controller on MT6779 is used to control pin
15
+
functions, pull up/down resistance and drive strength options.
16
16
17
17
properties:
18
18
compatible:
19
-
const: mediatek,mt6779-pinctrl
19
+
enum:
20
+
- mediatek,mt6779-pinctrl
21
+
- mediatek,mt6797-pinctrl
20
22
21
23
reg:
22
-
minItems: 9
23
-
maxItems: 9
24
+
description: Physical addresses for GPIO base(s) and EINT registers.
24
25
25
-
reg-names:
26
-
items:
27
-
- const: "gpio"
28
-
- const: "iocfg_rm"
29
-
- const: "iocfg_br"
30
-
- const: "iocfg_lm"
31
-
- const: "iocfg_lb"
32
-
- const: "iocfg_rt"
33
-
- const: "iocfg_lt"
34
-
- const: "iocfg_tl"
35
-
- const: "eint"
26
+
reg-names: true
36
27
37
28
gpio-controller: true
38
29
···
50
59
"#interrupt-cells":
51
60
const: 2
52
61
53
-
allOf:
54
-
- $ref: "pinctrl.yaml#"
55
-
56
62
required:
57
63
- compatible
58
64
- reg
59
65
- reg-names
60
66
- gpio-controller
61
67
- "#gpio-cells"
62
-
- gpio-ranges
63
-
- interrupt-controller
64
-
- interrupts
65
-
- "#interrupt-cells"
68
+
69
+
allOf:
70
+
- $ref: "pinctrl.yaml#"
71
+
- if:
72
+
properties:
73
+
compatible:
74
+
contains:
75
+
const: mediatek,mt6779-pinctrl
76
+
then:
77
+
properties:
78
+
reg:
79
+
minItems: 9
80
+
maxItems: 9
81
+
82
+
reg-names:
83
+
items:
84
+
- const: gpio
85
+
- const: iocfg_rm
86
+
- const: iocfg_br
87
+
- const: iocfg_lm
88
+
- const: iocfg_lb
89
+
- const: iocfg_rt
90
+
- const: iocfg_lt
91
+
- const: iocfg_tl
92
+
- const: eint
93
+
- if:
94
+
properties:
95
+
compatible:
96
+
contains:
97
+
const: mediatek,mt6797-pinctrl
98
+
then:
99
+
properties:
100
+
reg:
101
+
minItems: 5
102
+
maxItems: 5
103
+
104
+
reg-names:
105
+
items:
106
+
- const: gpio
107
+
- const: iocfgl
108
+
- const: iocfgb
109
+
- const: iocfgr
110
+
- const: iocfgt
111
+
- if:
112
+
properties:
113
+
reg-names:
114
+
contains:
115
+
const: eint
116
+
then:
117
+
required:
118
+
- interrupts
119
+
- interrupt-controller
120
+
- "#interrupt-cells"
66
121
67
122
patternProperties:
68
123
'-[0-9]*$':
···
149
112
input-schmitt-enable: true
150
113
151
114
input-schmitt-disable: true
115
+
116
+
drive-strength:
117
+
enum: [2, 4, 8, 12, 16]
118
+
119
+
slew-rate:
120
+
enum: [0, 1]
152
121
153
122
mediatek,pull-up-adv:
154
123
description: |
-176
Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml
-176
Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Mediatek MT6797 Pin Controller
8
-
9
-
maintainers:
10
-
- Sean Wang <sean.wang@kernel.org>
11
-
12
-
description: |+
13
-
The MediaTek's MT6797 Pin controller is used to control SoC pins.
14
-
15
-
properties:
16
-
compatible:
17
-
const: mediatek,mt6797-pinctrl
18
-
19
-
reg:
20
-
minItems: 5
21
-
maxItems: 5
22
-
23
-
reg-names:
24
-
items:
25
-
- const: gpio
26
-
- const: iocfgl
27
-
- const: iocfgb
28
-
- const: iocfgr
29
-
- const: iocfgt
30
-
31
-
gpio-controller: true
32
-
33
-
"#gpio-cells":
34
-
const: 2
35
-
description: |
36
-
Number of cells in GPIO specifier. Since the generic GPIO
37
-
binding is used, the amount of cells must be specified as 2. See the below
38
-
mentioned gpio binding representation for description of particular cells.
39
-
40
-
interrupt-controller: true
41
-
42
-
interrupts:
43
-
maxItems: 1
44
-
45
-
"#interrupt-cells":
46
-
const: 2
47
-
48
-
allOf:
49
-
- $ref: "pinctrl.yaml#"
50
-
51
-
required:
52
-
- compatible
53
-
- reg
54
-
- reg-names
55
-
- gpio-controller
56
-
- "#gpio-cells"
57
-
58
-
patternProperties:
59
-
'-[0-9]+$':
60
-
type: object
61
-
additionalProperties: false
62
-
patternProperties:
63
-
'pins':
64
-
type: object
65
-
additionalProperties: false
66
-
description: |
67
-
A pinctrl node should contain at least one subnodes representing the
68
-
pinctrl groups available on the machine. Each subnode will list the
69
-
pins it needs, and how they should be configured, with regard to muxer
70
-
configuration, pullups, drive strength, input enable/disable and input
71
-
schmitt.
72
-
$ref: "/schemas/pinctrl/pincfg-node.yaml"
73
-
74
-
properties:
75
-
pinmux:
76
-
description:
77
-
integer array, represents gpio pin number and mux setting.
78
-
Supported pin number and mux varies for different SoCs, and are
79
-
defined as macros in <soc>-pinfunc.h directly.
80
-
81
-
bias-disable: true
82
-
83
-
bias-pull-up: true
84
-
85
-
bias-pull-down: true
86
-
87
-
input-enable: true
88
-
89
-
input-disable: true
90
-
91
-
output-enable: true
92
-
93
-
output-low: true
94
-
95
-
output-high: true
96
-
97
-
input-schmitt-enable: true
98
-
99
-
input-schmitt-disable: true
100
-
101
-
drive-strength:
102
-
enum: [2, 4, 8, 12, 16]
103
-
104
-
slew-rate:
105
-
enum: [0, 1]
106
-
107
-
mediatek,pull-up-adv:
108
-
description: |
109
-
Pull up setings for 2 pull resistors, R0 and R1. User can
110
-
configure those special pins. Valid arguments are described as below:
111
-
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
112
-
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
113
-
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
114
-
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
115
-
$ref: /schemas/types.yaml#/definitions/uint32
116
-
enum: [0, 1, 2, 3]
117
-
118
-
mediatek,pull-down-adv:
119
-
description: |
120
-
Pull down settings for 2 pull resistors, R0 and R1. User can
121
-
configure those special pins. Valid arguments are described as below:
122
-
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
123
-
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
124
-
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
125
-
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
126
-
$ref: /schemas/types.yaml#/definitions/uint32
127
-
enum: [0, 1, 2, 3]
128
-
129
-
mediatek,tdsel:
130
-
description: |
131
-
An integer describing the steps for output level shifter duty
132
-
cycle when asserted (high pulse width adjustment). Valid arguments
133
-
are from 0 to 15.
134
-
$ref: /schemas/types.yaml#/definitions/uint32
135
-
136
-
mediatek,rdsel:
137
-
description: |
138
-
An integer describing the steps for input level shifter duty cycle
139
-
when asserted (high pulse width adjustment). Valid arguments are
140
-
from 0 to 63.
141
-
$ref: /schemas/types.yaml#/definitions/uint32
142
-
143
-
required:
144
-
- pinmux
145
-
146
-
additionalProperties: false
147
-
148
-
examples:
149
-
- |
150
-
#include <dt-bindings/interrupt-controller/irq.h>
151
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
152
-
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
153
-
154
-
soc {
155
-
#address-cells = <2>;
156
-
#size-cells = <2>;
157
-
158
-
pio: pinctrl@10005000 {
159
-
compatible = "mediatek,mt6797-pinctrl";
160
-
reg = <0 0x10005000 0 0x1000>,
161
-
<0 0x10002000 0 0x400>,
162
-
<0 0x10002400 0 0x400>,
163
-
<0 0x10002800 0 0x400>,
164
-
<0 0x10002C00 0 0x400>;
165
-
reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt";
166
-
gpio-controller;
167
-
#gpio-cells = <2>;
168
-
169
-
uart_pins_a: uart-0 {
170
-
pins1 {
171
-
pinmux = <MT6797_GPIO232__FUNC_URXD1>,
172
-
<MT6797_GPIO233__FUNC_UTXD1>;
173
-
};
174
-
};
175
-
};
176
-
};
+96
-10
Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml
+96
-10
Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml
···
87
87
"wifi_led" "led" 1, 2
88
88
"i2c" "i2c" 3, 4
89
89
"uart1_0" "uart" 7, 8, 9, 10
90
+
"uart1_rx_tx" "uart" 42, 43
91
+
"uart1_cts_rts" "uart" 44, 45
90
92
"pcie_clk" "pcie" 9
91
93
"pcie_wake" "pcie" 10
92
94
"spi1_0" "spi" 11, 12, 13, 14
···
100
98
"emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30,
101
99
31, 32
102
100
"spi1_1" "spi" 23, 24, 25, 26
103
-
"uart1_2" "uart" 29, 30, 31, 32
101
+
"uart1_2_rx_tx" "uart" 29, 30
102
+
"uart1_2_cts_rts" "uart" 31, 32
104
103
"uart1_1" "uart" 23, 24, 25, 26
105
-
"uart2_0" "uart" 29, 30, 31, 32
104
+
"uart2_0_rx_tx" "uart" 29, 30
105
+
"uart2_0_cts_rts" "uart" 31, 32
106
106
"spi0" "spi" 33, 34, 35, 36
107
107
"spi0_wp_hold" "spi" 37, 38
108
108
"uart1_3_rx_tx" "uart" 35, 36
···
161
157
then:
162
158
properties:
163
159
groups:
164
-
enum: [emmc, emmc_rst]
160
+
enum: [emmc_45, emmc_51]
165
161
- if:
166
162
properties:
167
163
function:
···
201
197
then:
202
198
properties:
203
199
groups:
204
-
enum: [pcie_clk, pcie_wake, pcie_pereset]
200
+
items:
201
+
enum: [pcie_clk, pcie_wake, pcie_pereset]
202
+
maxItems: 3
205
203
- if:
206
204
properties:
207
205
function:
···
211
205
then:
212
206
properties:
213
207
groups:
214
-
enum: [pwm0, pwm1_0, pwm1_1]
208
+
items:
209
+
enum: [pwm0, pwm1_0, pwm1_1]
210
+
maxItems: 2
215
211
- if:
216
212
properties:
217
213
function:
···
221
213
then:
222
214
properties:
223
215
groups:
224
-
enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
216
+
items:
217
+
enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
218
+
maxItems: 2
225
219
- if:
226
220
properties:
227
221
function:
···
231
221
then:
232
222
properties:
233
223
groups:
234
-
enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx,
235
-
uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, uart2]
224
+
items:
225
+
enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
226
+
uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
227
+
uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
228
+
uart2_1, uart0, uart1, uart2]
229
+
maxItems: 2
236
230
- if:
237
231
properties:
238
232
function:
···
292
278
293
279
bias-disable: true
294
280
295
-
bias-pull-up: true
281
+
bias-pull-up:
282
+
oneOf:
283
+
- type: boolean
284
+
description: normal pull up.
285
+
- enum: [100, 101, 102, 103]
286
+
description: |
287
+
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
288
+
dt-bindings/pinctrl/mt65xx.h.
296
289
297
-
bias-pull-down: true
290
+
bias-pull-down:
291
+
oneOf:
292
+
- type: boolean
293
+
description: normal pull down.
294
+
- enum: [100, 101, 102, 103]
295
+
description: |
296
+
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
297
+
dt-bindings/pinctrl/mt65xx.h.
298
298
299
299
input-enable: true
300
300
···
360
332
- |
361
333
#include <dt-bindings/interrupt-controller/irq.h>
362
334
#include <dt-bindings/interrupt-controller/arm-gic.h>
335
+
#include <dt-bindings/pinctrl/mt65xx.h>
363
336
364
337
soc {
365
338
#address-cells = <2>;
···
385
356
interrupt-parent = <&gic>;
386
357
#interrupt-cells = <2>;
387
358
359
+
pcie_pins: pcie-pins {
360
+
mux {
361
+
function = "pcie";
362
+
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
363
+
};
364
+
};
365
+
366
+
pwm_pins: pwm-pins {
367
+
mux {
368
+
function = "pwm";
369
+
groups = "pwm0", "pwm1_0";
370
+
};
371
+
};
372
+
373
+
spi0_pins: spi0-pins {
374
+
mux {
375
+
function = "spi";
376
+
groups = "spi0", "spi0_wp_hold";
377
+
};
378
+
};
379
+
388
380
uart1_pins: uart1-pins {
389
381
mux {
390
382
function = "uart";
···
413
363
};
414
364
};
415
365
366
+
uart1_3_pins: uart1-3-pins {
367
+
mux {
368
+
function = "uart";
369
+
groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
370
+
};
371
+
};
372
+
416
373
uart2_pins: uart2-pins {
417
374
mux {
418
375
function = "uart";
419
376
groups = "uart2";
377
+
};
378
+
};
379
+
380
+
mmc0_pins_default: mmc0-pins {
381
+
mux {
382
+
function = "emmc";
383
+
groups = "emmc_51";
384
+
};
385
+
conf-cmd-dat {
386
+
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
387
+
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
388
+
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
389
+
input-enable;
390
+
drive-strength = <4>;
391
+
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
392
+
};
393
+
conf-clk {
394
+
pins = "EMMC_CK";
395
+
drive-strength = <6>;
396
+
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
397
+
};
398
+
conf-ds {
399
+
pins = "EMMC_DSL";
400
+
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
401
+
};
402
+
conf-rst {
403
+
pins = "EMMC_RSTB";
404
+
drive-strength = <4>;
405
+
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
420
406
};
421
407
};
422
408
+5
-2
Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml
+5
-2
Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml
···
46
46
const: 2
47
47
48
48
interrupts:
49
-
description: The interrupt outputs to sysirq.
50
-
maxItems: 1
49
+
description: Interrupt outputs to the system interrupt controller (sysirq).
50
+
minItems: 1
51
+
items:
52
+
- description: EINT interrupt
53
+
- description: EINT event_b interrupt
51
54
52
55
# PIN CONFIGURATION NODES
53
56
patternProperties:
-72
Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
-72
Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt
···
1
-
SEMTECH SX150x GPIO expander bindings
2
-
3
-
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4
-
../interrupt-controller/interrupts.txt for generic information regarding
5
-
pin controller, GPIO, and interrupt bindings.
6
-
7
-
Required properties:
8
-
- compatible: should be one of :
9
-
"semtech,sx1501q",
10
-
"semtech,sx1502q",
11
-
"semtech,sx1503q",
12
-
"semtech,sx1504q",
13
-
"semtech,sx1505q",
14
-
"semtech,sx1506q",
15
-
"semtech,sx1507q",
16
-
"semtech,sx1508q",
17
-
"semtech,sx1509q".
18
-
19
-
- reg: The I2C slave address for this device.
20
-
21
-
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
22
-
second cell is used to specify optional parameters:
23
-
bit 0: polarity (0: normal, 1: inverted)
24
-
25
-
- gpio-controller: Marks the device as a GPIO controller.
26
-
27
-
Optional properties :
28
-
- interrupts: Interrupt specifier for the controllers interrupt.
29
-
30
-
- interrupt-controller: Marks the device as a interrupt controller.
31
-
32
-
- semtech,probe-reset: Will trigger a reset of the GPIO expander on probe,
33
-
only for sx1507q, sx1508q and sx1509q
34
-
35
-
The GPIO expander can optionally be used as an interrupt controller, in
36
-
which case it uses the default two cell specifier.
37
-
38
-
Required properties for pin configuration sub-nodes:
39
-
- pins: List of pins to which the configuration applies.
40
-
41
-
Optional properties for pin configuration sub-nodes:
42
-
----------------------------------------------------
43
-
- bias-disable: disable any pin bias, except the OSCIO pin
44
-
- bias-pull-up: pull up the pin, except the OSCIO pin
45
-
- bias-pull-down: pull down the pin, except the OSCIO pin
46
-
- bias-pull-pin-default: use pin-default pull state, except the OSCIO pin
47
-
- drive-push-pull: drive actively high and low
48
-
- drive-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin
49
-
- output-low: set the pin to output mode with low level
50
-
- output-high: set the pin to output mode with high level
51
-
52
-
Example:
53
-
54
-
i2c0gpio-expander@20{
55
-
#gpio-cells = <2>;
56
-
#interrupt-cells = <2>;
57
-
compatible = "semtech,sx1506q";
58
-
reg = <0x20>;
59
-
interrupt-parent = <&gpio_1>;
60
-
interrupts = <16 0>;
61
-
62
-
gpio-controller;
63
-
interrupt-controller;
64
-
65
-
pinctrl-names = "default";
66
-
pinctrl-0 = <&gpio1_cfg_pins>;
67
-
68
-
gpio1_cfg_pins: gpio1-cfg {
69
-
pins = "gpio1";
70
-
bias-pull-up;
71
-
};
72
-
};
+43
-68
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+43
-68
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
···
7
7
title: Qualcomm Technologies, Inc. IPQ6018 TLMM block
8
8
9
9
maintainers:
10
-
- Sricharan R <sricharan@codeaurora.org>
10
+
- Bjorn Andersson <andersson@kernel.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
IPQ6018 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm IPQ6018 SoC.
15
14
16
15
properties:
17
16
compatible:
···
19
20
reg:
20
21
maxItems: 1
21
22
22
-
interrupts:
23
-
description: Specifies the TLMM summary IRQ
24
-
maxItems: 1
25
-
23
+
interrupts: true
26
24
interrupt-controller: true
27
-
28
-
'#interrupt-cells':
29
-
description:
30
-
Specifies the PIN numbers and Flags, as defined in defined in
31
-
include/dt-bindings/interrupt-controller/irq.h
32
-
const: 2
33
-
25
+
"#interrupt-cells": true
34
26
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
35
29
36
-
'#gpio-cells':
37
-
description: Specifying the pin number and flags, as defined in
38
-
include/dt-bindings/gpio/gpio.h
39
-
const: 2
40
-
41
-
gpio-ranges:
42
-
maxItems: 1
43
-
44
-
#PIN CONFIGURATION NODES
45
30
patternProperties:
46
-
'-pinmux$':
47
-
type: object
31
+
"-state$":
32
+
oneOf:
33
+
- $ref: "#/$defs/qcom-ipq6018-tlmm-state"
34
+
- patternProperties:
35
+
"-pins$":
36
+
$ref: "#/$defs/qcom-ipq6018-tlmm-state"
37
+
additionalProperties: false
38
+
39
+
$defs:
40
+
qcom-ipq6018-tlmm-state:
48
41
description:
49
42
Pinctrl node's client devices use subnodes for desired pin configuration.
50
43
Client device subnodes use below standard properties.
51
-
$ref: "/schemas/pinctrl/pincfg-node.yaml"
44
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
52
45
53
46
properties:
54
47
pins:
···
54
63
sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
55
64
qdsd_data3 ]
56
65
minItems: 1
57
-
maxItems: 4
66
+
maxItems: 16
58
67
59
68
function:
60
69
description:
···
63
72
enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
64
73
atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac,
65
74
atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0,
66
-
atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp1_i2c,
67
-
blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp6_i2c, blsp1_spi,
75
+
atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp0_i2c, blsp1_i2c,
76
+
blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp0_spi, blsp1_spi,
68
77
blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi,
69
78
blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi,
70
79
blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi,
71
-
blsp6_spi, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
80
+
blsp0_uart, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
72
81
cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
73
82
cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v,
74
83
dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass,
···
83
92
qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
84
93
qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
85
94
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
86
-
qdss_tracedata_a, qdss_tracedata_b, reset_n, sd_card, sd_write,
87
-
sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3,
88
-
uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
89
-
90
-
drive-strength:
91
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
92
-
default: 2
93
-
description:
94
-
Selects the drive strength for the specified pins, in mA.
95
+
qdss_tracedata_a, qdss_tracedata_b, qpic_pad, reset_n, sd_card,
96
+
sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2,
97
+
uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]
95
98
96
99
bias-pull-down: true
97
-
98
100
bias-pull-up: true
99
-
100
101
bias-disable: true
101
-
102
+
drive-strength: true
102
103
output-high: true
103
-
104
104
output-low: true
105
105
106
106
required:
107
107
- pins
108
-
- function
109
108
110
109
additionalProperties: false
111
110
112
111
allOf:
113
-
- $ref: "pinctrl.yaml#"
112
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
114
113
115
114
required:
116
115
- compatible
117
116
- reg
118
-
- interrupts
119
-
- interrupt-controller
120
-
- '#interrupt-cells'
121
-
- gpio-controller
122
-
- '#gpio-cells'
123
-
- gpio-ranges
124
117
125
118
additionalProperties: false
126
119
127
120
examples:
128
121
- |
129
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
130
-
tlmm: pinctrl@1000000 {
131
-
compatible = "qcom,ipq6018-pinctrl";
132
-
reg = <0x01000000 0x300000>;
133
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
134
-
interrupt-controller;
135
-
#interrupt-cells = <2>;
136
-
gpio-controller;
137
-
#gpio-cells = <2>;
138
-
gpio-ranges = <&tlmm 0 0 80>;
122
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
123
+
tlmm: pinctrl@1000000 {
124
+
compatible = "qcom,ipq6018-pinctrl";
125
+
reg = <0x01000000 0x300000>;
126
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127
+
interrupt-controller;
128
+
#interrupt-cells = <2>;
129
+
gpio-controller;
130
+
#gpio-cells = <2>;
131
+
gpio-ranges = <&tlmm 0 0 80>;
139
132
140
-
serial3-pinmux {
141
-
pins = "gpio44", "gpio45";
142
-
function = "blsp2_uart";
143
-
drive-strength = <8>;
144
-
bias-pull-down;
145
-
};
133
+
serial3-state {
134
+
pins = "gpio44", "gpio45";
135
+
function = "blsp2_uart";
136
+
drive-strength = <8>;
137
+
bias-pull-down;
146
138
};
139
+
};
-181
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
-181
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
···
1
-
Qualcomm Technologies, Inc. IPQ8074 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
IPQ8074 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,ipq8074-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode. Valid pins are:
85
-
gpio0-gpio69
86
-
87
-
- function:
88
-
Usage: required
89
-
Value type: <string>
90
-
Definition: Specify the alternative function to be configured for the
91
-
specified pins. Functions are only valid for gpio pins.
92
-
Valid values are:
93
-
atest_char, atest_char0, atest_char1, atest_char2,
94
-
atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
95
-
audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
96
-
audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
97
-
blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
98
-
blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
99
-
blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
100
-
blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
101
-
blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,
102
-
cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,
103
-
ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,
104
-
mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,
105
-
mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,
106
-
pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,
107
-
pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,
108
-
pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
109
-
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
110
-
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
111
-
qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
112
-
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
113
-
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
114
-
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,
115
-
qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,
116
-
wci2b, wci2c, wci2d
117
-
118
-
- bias-disable:
119
-
Usage: optional
120
-
Value type: <none>
121
-
Definition: The specified pins should be configured as no pull.
122
-
123
-
- bias-pull-down:
124
-
Usage: optional
125
-
Value type: <none>
126
-
Definition: The specified pins should be configured as pull down.
127
-
128
-
- bias-pull-up:
129
-
Usage: optional
130
-
Value type: <none>
131
-
Definition: The specified pins should be configured as pull up.
132
-
133
-
- output-high:
134
-
Usage: optional
135
-
Value type: <none>
136
-
Definition: The specified pins are configured in output mode, driven
137
-
high.
138
-
139
-
- output-low:
140
-
Usage: optional
141
-
Value type: <none>
142
-
Definition: The specified pins are configured in output mode, driven
143
-
low.
144
-
145
-
- drive-strength:
146
-
Usage: optional
147
-
Value type: <u32>
148
-
Definition: Selects the drive strength for the specified pins, in mA.
149
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
150
-
151
-
Example:
152
-
153
-
tlmm: pinctrl@1000000 {
154
-
compatible = "qcom,ipq8074-pinctrl";
155
-
reg = <0x1000000 0x300000>;
156
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
157
-
gpio-controller;
158
-
#gpio-cells = <2>;
159
-
gpio-ranges = <&tlmm 0 0 70>;
160
-
interrupt-controller;
161
-
#interrupt-cells = <2>;
162
-
163
-
uart2: uart2-default {
164
-
mux {
165
-
pins = "gpio23", "gpio24";
166
-
function = "blsp4_uart1";
167
-
};
168
-
169
-
rx {
170
-
pins = "gpio23";
171
-
drive-strength = <4>;
172
-
bias-disable;
173
-
};
174
-
175
-
tx {
176
-
pins = "gpio24";
177
-
drive-strength = <2>;
178
-
bias-pull-up;
179
-
};
180
-
};
181
-
};
+135
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
+135
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ8074 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,ipq8074-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 35
34
+
35
+
gpio-line-names:
36
+
maxItems: 70
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-ipq8074-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-ipq8074-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-ipq8074-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
70
+
enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
71
+
atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
72
+
audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
73
+
audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
74
+
blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
75
+
blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
76
+
blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
77
+
blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
78
+
blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,
79
+
cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,
80
+
led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,
81
+
mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
82
+
pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,
83
+
pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,
84
+
pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
85
+
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
86
+
qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
87
+
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
88
+
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
89
+
qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
90
+
qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
91
+
tsens_max, wci2a, wci2b, wci2c, wci2d ]
92
+
93
+
bias-pull-down: true
94
+
bias-pull-up: true
95
+
bias-disable: true
96
+
drive-strength: true
97
+
input-enable: true
98
+
output-high: true
99
+
output-low: true
100
+
101
+
required:
102
+
- pins
103
+
104
+
additionalProperties: false
105
+
106
+
allOf:
107
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
108
+
109
+
required:
110
+
- compatible
111
+
- reg
112
+
113
+
additionalProperties: false
114
+
115
+
examples:
116
+
- |
117
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
118
+
119
+
tlmm: pinctrl@1000000 {
120
+
compatible = "qcom,ipq8074-pinctrl";
121
+
reg = <0x01000000 0x300000>;
122
+
gpio-controller;
123
+
#gpio-cells = <0x2>;
124
+
gpio-ranges = <&tlmm 0 0 70>;
125
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
126
+
interrupt-controller;
127
+
#interrupt-cells = <0x2>;
128
+
129
+
serial4-state {
130
+
pins = "gpio23", "gpio24";
131
+
function = "blsp4_uart1";
132
+
drive-strength = <8>;
133
+
bias-disable;
134
+
};
135
+
};
+19
-22
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
+19
-22
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. MDM9607 TLMM block
···
9
9
maintainers:
10
10
- Konrad Dybcio <konrad.dybcio@somainline.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
MDM9607 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
15
14
16
15
allOf:
17
-
- $ref: "pinctrl.yaml#"
18
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19
17
20
18
properties:
···
24
26
25
27
interrupts: true
26
28
interrupt-controller: true
27
-
'#interrupt-cells': true
29
+
"#interrupt-cells": true
28
30
gpio-controller: true
29
31
gpio-reserved-ranges: true
30
-
'#gpio-cells': true
32
+
"#gpio-cells": true
31
33
gpio-ranges: true
32
34
wakeup-parent: true
33
35
···
38
40
additionalProperties: false
39
41
40
42
patternProperties:
41
-
'-state$':
43
+
"-state$":
42
44
oneOf:
43
45
- $ref: "#/$defs/qcom-mdm9607-tlmm-state"
44
46
- patternProperties:
45
47
".*":
46
48
$ref: "#/$defs/qcom-mdm9607-tlmm-state"
47
49
48
-
'$defs':
50
+
$defs:
49
51
qcom-mdm9607-tlmm-state:
50
52
type: object
51
53
description:
52
54
Pinctrl node's client devices use subnodes for desired pin configuration.
53
55
Client device subnodes use below standard properties.
54
-
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
56
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
57
56
58
properties:
57
59
pins:
···
113
115
114
116
required:
115
117
- pins
116
-
- function
117
118
118
119
additionalProperties: false
119
120
120
121
examples:
121
122
- |
122
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
123
-
tlmm: pinctrl@1000000 {
124
-
compatible = "qcom,mdm9607-tlmm";
125
-
reg = <0x01000000 0x300000>;
126
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127
-
gpio-controller;
128
-
gpio-ranges = <&msmgpio 0 0 80>;
129
-
#gpio-cells = <2>;
130
-
interrupt-controller;
131
-
#interrupt-cells = <2>;
132
-
};
123
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
124
+
tlmm: pinctrl@1000000 {
125
+
compatible = "qcom,mdm9607-tlmm";
126
+
reg = <0x01000000 0x300000>;
127
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
128
+
gpio-controller;
129
+
gpio-ranges = <&msmgpio 0 0 80>;
130
+
#gpio-cells = <2>;
131
+
interrupt-controller;
132
+
#interrupt-cells = <2>;
133
+
};
-161
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt
-161
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt
···
1
-
Qualcomm MDM9615 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MDM9615 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,mdm9615-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode. Valid pins are:
85
-
gpio0-gpio87
86
-
87
-
- function:
88
-
Usage: required
89
-
Value type: <string>
90
-
Definition: Specify the alternative function to be configured for the
91
-
specified pins.
92
-
Valid values are:
93
-
gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
94
-
sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio,
95
-
cdc_mclk
96
-
97
-
- bias-disable:
98
-
Usage: optional
99
-
Value type: <none>
100
-
Definition: The specified pins should be configured as no pull.
101
-
102
-
- bias-pull-down:
103
-
Usage: optional
104
-
Value type: <none>
105
-
Definition: The specified pins should be configured as pull down.
106
-
107
-
- bias-pull-up:
108
-
Usage: optional
109
-
Value type: <none>
110
-
Definition: The specified pins should be configured as pull up.
111
-
112
-
- output-high:
113
-
Usage: optional
114
-
Value type: <none>
115
-
Definition: The specified pins are configured in output mode, driven
116
-
high.
117
-
118
-
- output-low:
119
-
Usage: optional
120
-
Value type: <none>
121
-
Definition: The specified pins are configured in output mode, driven
122
-
low.
123
-
124
-
- drive-strength:
125
-
Usage: optional
126
-
Value type: <u32>
127
-
Definition: Selects the drive strength for the specified pins, in mA.
128
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
129
-
130
-
Example:
131
-
132
-
msmgpio: pinctrl@800000 {
133
-
compatible = "qcom,mdm9615-pinctrl";
134
-
reg = <0x800000 0x4000>;
135
-
136
-
gpio-controller;
137
-
#gpio-cells = <2>;
138
-
gpio-ranges = <&msmgpio 0 0 88>;
139
-
interrupt-controller;
140
-
#interrupt-cells = <2>;
141
-
interrupts = <0 16 0x4>;
142
-
143
-
gsbi8_uart: gsbi8-uart {
144
-
mux {
145
-
pins = "gpio34", "gpio35";
146
-
function = "gsbi8";
147
-
};
148
-
149
-
tx {
150
-
pins = "gpio34";
151
-
drive-strength = <4>;
152
-
bias-disable;
153
-
};
154
-
155
-
rx {
156
-
pins = "gpio35";
157
-
drive-strength = <2>;
158
-
bias-pull-up;
159
-
};
160
-
};
161
-
};
+119
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
+119
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. MDM9615 TLMM block
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
12
+
description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
13
+
14
+
$ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,mdm9615-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
'#interrupt-cells': true
26
+
gpio-controller: true
27
+
'#gpio-cells': true
28
+
gpio-ranges: true
29
+
30
+
required:
31
+
- compatible
32
+
- reg
33
+
34
+
additionalProperties: false
35
+
36
+
patternProperties:
37
+
"-state$":
38
+
oneOf:
39
+
- $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
40
+
- patternProperties:
41
+
"-pins$":
42
+
$ref: "#/$defs/qcom-mdm9615-pinctrl-state"
43
+
additionalProperties: false
44
+
45
+
$defs:
46
+
qcom-mdm9615-pinctrl-state:
47
+
type: object
48
+
description:
49
+
Pinctrl node's client devices use subnodes for desired pin configuration.
50
+
Client device subnodes use below standard properties.
51
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
60
+
minItems: 1
61
+
maxItems: 16
62
+
63
+
function:
64
+
description:
65
+
Specify the alternative function to be configured for the specified
66
+
pins.
67
+
68
+
enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
69
+
sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]
70
+
71
+
bias-disable: true
72
+
bias-pull-down: true
73
+
bias-pull-up: true
74
+
drive-strength: true
75
+
output-high: true
76
+
output-low: true
77
+
input-enable: true
78
+
79
+
required:
80
+
- pins
81
+
82
+
additionalProperties: false
83
+
84
+
examples:
85
+
- |
86
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87
+
tlmm: pinctrl@1000000 {
88
+
compatible = "qcom,mdm9615-pinctrl";
89
+
reg = <0x01000000 0x300000>;
90
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
91
+
gpio-controller;
92
+
gpio-ranges = <&msmgpio 0 0 88>;
93
+
#gpio-cells = <2>;
94
+
interrupt-controller;
95
+
#interrupt-cells = <2>;
96
+
97
+
gsbi3-state {
98
+
pins = "gpio8", "gpio9", "gpio10", "gpio11";
99
+
function = "gsbi3";
100
+
drive-strength = <8>;
101
+
bias-disable;
102
+
};
103
+
104
+
gsbi5-i2c-state {
105
+
sda-pins {
106
+
pins = "gpio16";
107
+
function = "gsbi5_i2c";
108
+
drive-strength = <8>;
109
+
bias-disable;
110
+
};
111
+
112
+
scl-pins {
113
+
pins = "gpio17";
114
+
function = "gsbi5_i2c";
115
+
drive-strength = <2>;
116
+
bias-disable;
117
+
};
118
+
};
119
+
};
+39
-60
Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+39
-60
Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
···
9
9
maintainers:
10
10
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
MSM8226 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.
15
14
16
15
properties:
17
16
compatible:
···
20
21
description: Specifies the base address and size of the TLMM register space
21
22
maxItems: 1
22
23
23
-
interrupts:
24
-
description: Specifies the TLMM summary IRQ
25
-
maxItems: 1
26
-
24
+
interrupts: true
27
25
interrupt-controller: true
28
-
29
-
'#interrupt-cells':
30
-
description: Specifies the PIN numbers and Flags, as defined in
31
-
include/dt-bindings/interrupt-controller/irq.h
32
-
const: 2
33
-
26
+
"#interrupt-cells": true
34
27
gpio-controller: true
35
-
36
-
'#gpio-cells':
37
-
description: Specifying the pin number and flags, as defined in
38
-
include/dt-bindings/gpio/gpio.h
39
-
const: 2
40
-
41
-
gpio-ranges:
42
-
maxItems: 1
28
+
"#gpio-cells": true
29
+
gpio-ranges: true
43
30
44
31
gpio-reserved-ranges:
45
32
maxItems: 1
46
33
47
-
#PIN CONFIGURATION NODES
48
34
patternProperties:
49
-
'-pins$':
35
+
"-state$":
36
+
oneOf:
37
+
- $ref: "#/$defs/qcom-msm8226-tlmm-state"
38
+
- patternProperties:
39
+
"-pins$":
40
+
$ref: "#/$defs/qcom-msm8226-tlmm-state"
41
+
additionalProperties: false
42
+
43
+
$defs:
44
+
qcom-msm8226-tlmm-state:
50
45
type: object
51
46
description:
52
47
Pinctrl node's client devices use subnodes for desired pin configuration.
53
48
Client device subnodes use below standard properties.
54
-
$ref: "/schemas/pinctrl/pincfg-node.yaml"
49
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
50
56
51
properties:
57
52
pins:
···
64
71
Specify the alternative function to be configured for the specified
65
72
pins. Functions are only valid for gpio pins.
66
73
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
67
-
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
74
+
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
68
75
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
69
-
blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
70
-
71
-
drive-strength:
72
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
73
-
default: 2
74
-
description:
75
-
Selects the drive strength for the specified pins, in mA.
76
+
blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
77
+
wlan ]
76
78
77
79
bias-pull-down: true
78
-
79
80
bias-pull-up: true
80
-
81
81
bias-disable: true
82
-
82
+
drive-strength: true
83
+
input-enable: true
83
84
output-high: true
84
-
85
85
output-low: true
86
86
87
87
required:
88
88
- pins
89
-
- function
90
89
91
90
additionalProperties: false
92
91
93
92
allOf:
94
-
- $ref: "pinctrl.yaml#"
93
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
95
94
96
95
required:
97
96
- compatible
98
97
- reg
99
-
- interrupts
100
-
- interrupt-controller
101
-
- '#interrupt-cells'
102
-
- gpio-controller
103
-
- '#gpio-cells'
104
-
- gpio-ranges
105
98
106
99
additionalProperties: false
107
100
108
101
examples:
109
102
- |
110
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
111
-
msmgpio: pinctrl@fd510000 {
112
-
compatible = "qcom,msm8226-pinctrl";
113
-
reg = <0xfd510000 0x4000>;
103
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
104
+
msmgpio: pinctrl@fd510000 {
105
+
compatible = "qcom,msm8226-pinctrl";
106
+
reg = <0xfd510000 0x4000>;
114
107
115
-
gpio-controller;
116
-
#gpio-cells = <2>;
117
-
gpio-ranges = <&msmgpio 0 0 117>;
118
-
interrupt-controller;
119
-
#interrupt-cells = <2>;
120
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
108
+
gpio-controller;
109
+
#gpio-cells = <2>;
110
+
gpio-ranges = <&msmgpio 0 0 117>;
111
+
interrupt-controller;
112
+
#interrupt-cells = <2>;
113
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
121
114
122
-
serial-pins {
123
-
pins = "gpio8", "gpio9";
124
-
function = "blsp_uart3";
125
-
drive-strength = <8>;
126
-
bias-disable;
127
-
};
115
+
serial-state {
116
+
pins = "gpio8", "gpio9";
117
+
function = "blsp_uart3";
118
+
drive-strength = <8>;
119
+
bias-disable;
128
120
};
121
+
};
-96
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt
-96
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt
···
1
-
Qualcomm MSM8660 TLMM block
2
-
3
-
Required properties:
4
-
- compatible: "qcom,msm8660-pinctrl"
5
-
- reg: Should be the base address and length of the TLMM block.
6
-
- interrupts: Should be the parent IRQ of the TLMM block.
7
-
- interrupt-controller: Marks the device node as an interrupt controller.
8
-
- #interrupt-cells: Should be two.
9
-
- gpio-controller: Marks the device node as a GPIO controller.
10
-
- #gpio-cells : Should be two.
11
-
The first cell is the gpio pin number and the
12
-
second cell is used for optional parameters.
13
-
- gpio-ranges: see ../gpio/gpio.txt
14
-
15
-
Optional properties:
16
-
17
-
- gpio-reserved-ranges: see ../gpio/gpio.txt
18
-
19
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
20
-
a general description of GPIO and interrupt bindings.
21
-
22
-
Please refer to pinctrl-bindings.txt in this directory for details of the
23
-
common pinctrl bindings used by client devices, including the meaning of the
24
-
phrase "pin configuration node".
25
-
26
-
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
27
-
subnodes. Each of these subnodes represents some desired configuration for a
28
-
pin, a group, or a list of pins or groups. This configuration can include the
29
-
mux function to select on those pin(s)/group(s), and various pin configuration
30
-
parameters, such as pull-up, drive strength, etc.
31
-
32
-
The name of each subnode is not important; all subnodes should be enumerated
33
-
and processed purely based on their content.
34
-
35
-
Each subnode only affects those parameters that are explicitly listed. In
36
-
other words, a subnode that lists a mux function but no pin configuration
37
-
parameters implies no information about any pin configuration parameters.
38
-
Similarly, a pin subnode that describes a pullup parameter implies no
39
-
information about e.g. the mux function.
40
-
41
-
42
-
The following generic properties as defined in pinctrl-bindings.txt are valid
43
-
to specify in a pin configuration subnode:
44
-
45
-
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
46
-
output-low, output-high.
47
-
48
-
Non-empty subnodes must specify the 'pins' property.
49
-
50
-
Valid values for pins are:
51
-
gpio0-gpio172, sdc3_clk, sdc3_cmd, sdc3_data sdc4_clk, sdc4_cmd, sdc4_data
52
-
53
-
Valid values for function are:
54
-
gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, gp_clk_1b,
55
-
gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n,
56
-
gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
57
-
gsbi2_spi_cs3_n, gsbi3, gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n,
58
-
gsbi4, gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, hdmi, i2s,
59
-
lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, sdc5, tsif1, tsif2, usb_fs1,
60
-
usb_fs1_oe_n, usb_fs2, usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs
61
-
62
-
Example:
63
-
64
-
msmgpio: pinctrl@800000 {
65
-
compatible = "qcom,msm8660-pinctrl";
66
-
reg = <0x800000 0x4000>;
67
-
68
-
gpio-controller;
69
-
#gpio-cells = <2>;
70
-
gpio-ranges = <&msmgpio 0 0 173>;
71
-
interrupt-controller;
72
-
#interrupt-cells = <2>;
73
-
interrupts = <0 16 0x4>;
74
-
75
-
pinctrl-names = "default";
76
-
pinctrl-0 = <&gsbi12_uart>;
77
-
78
-
gsbi12_uart: gsbi12-uart {
79
-
mux {
80
-
pins = "gpio117", "gpio118";
81
-
function = "gsbi12";
82
-
};
83
-
84
-
tx {
85
-
pins = "gpio118";
86
-
drive-strength = <8>;
87
-
bias-disable;
88
-
};
89
-
90
-
rx {
91
-
pins = "gpio117";
92
-
drive-strength = <2>;
93
-
bias-pull-up;
94
-
};
95
-
};
96
-
};
+125
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml
+125
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8660 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8660-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 86
34
+
35
+
gpio-line-names:
36
+
maxItems: 173
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8660-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8660-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8660-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
oneOf:
62
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$"
63
+
- enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ]
64
+
minItems: 1
65
+
maxItems: 36
66
+
67
+
function:
68
+
description:
69
+
Specify the alternative function to be configured for the specified
70
+
pins.
71
+
72
+
enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a,
73
+
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n,
74
+
gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2,
75
+
gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3,
76
+
gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4,
77
+
gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12,
78
+
hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2,
79
+
sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2,
80
+
usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ]
81
+
82
+
83
+
bias-pull-down: true
84
+
bias-pull-up: true
85
+
bias-disable: true
86
+
drive-strength: true
87
+
input-enable: true
88
+
output-high: true
89
+
output-low: true
90
+
91
+
required:
92
+
- pins
93
+
94
+
additionalProperties: false
95
+
96
+
allOf:
97
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
98
+
99
+
required:
100
+
- compatible
101
+
- reg
102
+
103
+
additionalProperties: false
104
+
105
+
examples:
106
+
- |
107
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
108
+
tlmm: pinctrl@800000 {
109
+
compatible = "qcom,msm8660-pinctrl";
110
+
reg = <0x800000 0x4000>;
111
+
112
+
gpio-controller;
113
+
gpio-ranges = <&tlmm 0 0 173>;
114
+
#gpio-cells = <2>;
115
+
interrupts = <0 16 0x4>;
116
+
interrupt-controller;
117
+
#interrupt-cells = <2>;
118
+
119
+
gsbi3-i2c-state {
120
+
pins = "gpio43", "gpio44";
121
+
function = "gsbi3";
122
+
drive-strength = <8>;
123
+
bias-disable;
124
+
};
125
+
};
+35
-36
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
+35
-36
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
···
10
10
- Stephan Gerhold <stephan@gerhold.net>
11
11
12
12
description: |
13
-
This binding describes the Top Level Mode Multiplexer (TLMM) block found
14
-
in the MSM8909 platform.
13
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC.
15
14
16
15
allOf:
17
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
···
24
25
25
26
interrupts: true
26
27
interrupt-controller: true
27
-
'#interrupt-cells': true
28
+
"#interrupt-cells": true
28
29
gpio-controller: true
29
30
gpio-reserved-ranges: true
30
-
'#gpio-cells': true
31
+
"#gpio-cells": true
31
32
gpio-ranges: true
32
33
wakeup-parent: true
33
34
···
38
39
additionalProperties: false
39
40
40
41
patternProperties:
41
-
'-state$':
42
+
"-state$":
42
43
oneOf:
43
44
- $ref: "#/$defs/qcom-msm8909-tlmm-state"
44
45
- patternProperties:
45
-
".*":
46
+
"-pins$":
46
47
$ref: "#/$defs/qcom-msm8909-tlmm-state"
48
+
additionalProperties: false
47
49
48
50
$defs:
49
51
qcom-msm8909-tlmm-state:
···
52
52
description:
53
53
Pinctrl node's client devices use subnodes for desired pin configuration.
54
54
Client device subnodes use below standard properties.
55
-
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
55
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56
56
57
57
properties:
58
58
pins:
···
112
112
113
113
required:
114
114
- pins
115
-
- function
116
115
117
116
additionalProperties: false
118
117
119
118
examples:
120
119
- |
121
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
120
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
122
121
123
-
pinctrl@1000000 {
124
-
compatible = "qcom,msm8909-tlmm";
125
-
reg = <0x1000000 0x300000>;
126
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127
-
gpio-controller;
128
-
#gpio-cells = <2>;
129
-
gpio-ranges = <&tlmm 0 0 117>;
130
-
interrupt-controller;
131
-
#interrupt-cells = <2>;
122
+
pinctrl@1000000 {
123
+
compatible = "qcom,msm8909-tlmm";
124
+
reg = <0x1000000 0x300000>;
125
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
126
+
gpio-controller;
127
+
#gpio-cells = <2>;
128
+
gpio-ranges = <&tlmm 0 0 117>;
129
+
interrupt-controller;
130
+
#interrupt-cells = <2>;
132
131
133
-
gpio-wo-subnode-state {
134
-
pins = "gpio1";
135
-
function = "gpio";
136
-
};
137
-
138
-
uart-w-subnodes-state {
139
-
rx {
140
-
pins = "gpio4";
141
-
function = "blsp_uart1";
142
-
bias-pull-up;
143
-
};
144
-
145
-
tx {
146
-
pins = "gpio5";
147
-
function = "blsp_uart1";
148
-
bias-disable;
149
-
};
150
-
};
132
+
gpio-wo-subnode-state {
133
+
pins = "gpio1";
134
+
function = "gpio";
151
135
};
136
+
137
+
uart-w-subnodes-state {
138
+
rx-pins {
139
+
pins = "gpio4";
140
+
function = "blsp_uart1";
141
+
bias-pull-up;
142
+
};
143
+
144
+
tx-pins {
145
+
pins = "gpio5";
146
+
function = "blsp_uart1";
147
+
bias-disable;
148
+
};
149
+
};
150
+
};
152
151
...
-195
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt
-195
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt
···
1
-
Qualcomm MSM8916 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8916 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,msm8916-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode. Valid pins are:
85
-
gpio0-gpio121,
86
-
sdc1_clk,
87
-
sdc1_cmd,
88
-
sdc1_data
89
-
sdc2_clk,
90
-
sdc2_cmd,
91
-
sdc2_data,
92
-
qdsd_cmd,
93
-
qdsd_data0,
94
-
qdsd_data1,
95
-
qdsd_data2,
96
-
qdsd_data3
97
-
98
-
- function:
99
-
Usage: required
100
-
Value type: <string>
101
-
Definition: Specify the alternative function to be configured for the
102
-
specified pins. Functions are only valid for gpio pins.
103
-
Valid values are:
104
-
adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
105
-
atest_char1, atest_char2, atest_char3, atest_combodac, atest_gpsadc0,
106
-
atest_gpsadc1, atest_tsens, atest_wlan0, atest_wlan1, backlight_en,
107
-
bimc_dte0,bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
108
-
blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,
109
-
blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3,
110
-
blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4,
111
-
blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2,
112
-
cam1_rst, cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c,
113
-
cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,
114
-
display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us,
115
-
ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
116
-
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, gsm0_tx1,
117
-
gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, ldo_en,
118
-
ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, nav_pps, nav_tsync,
119
-
pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,
120
-
pwr_crypto_enabled_a, pwr_crypto_enabled_b, pwr_modem_enabled_a,
121
-
pwr_modem_enabled_b, pwr_nav_enabled_a, pwr_nav_enabled_b,
122
-
qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, qdss_ctitrig_in_b0,
123
-
qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, qdss_ctitrig_out_a1,
124
-
qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, qdss_traceclk_a,
125
-
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
126
-
qdss_tracedata_b, reset_n, sd_card, sd_write, sec_mi2s, smb_int,
127
-
ssbi_wtr0, ssbi_wtr1, uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm,
128
-
wcss_wlan, webcam1_rst
129
-
130
-
- bias-disable:
131
-
Usage: optional
132
-
Value type: <none>
133
-
Definition: The specified pins should be configured as no pull.
134
-
135
-
- bias-pull-down:
136
-
Usage: optional
137
-
Value type: <none>
138
-
Definition: The specified pins should be configured as pull down.
139
-
140
-
- bias-pull-up:
141
-
Usage: optional
142
-
Value type: <none>
143
-
Definition: The specified pins should be configured as pull up.
144
-
145
-
- output-high:
146
-
Usage: optional
147
-
Value type: <none>
148
-
Definition: The specified pins are configured in output mode, driven
149
-
high.
150
-
Not valid for sdc pins.
151
-
152
-
- output-low:
153
-
Usage: optional
154
-
Value type: <none>
155
-
Definition: The specified pins are configured in output mode, driven
156
-
low.
157
-
Not valid for sdc pins.
158
-
159
-
- drive-strength:
160
-
Usage: optional
161
-
Value type: <u32>
162
-
Definition: Selects the drive strength for the specified pins, in mA.
163
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
164
-
165
-
Example:
166
-
167
-
tlmm: pinctrl@1000000 {
168
-
compatible = "qcom,msm8916-pinctrl";
169
-
reg = <0x1000000 0x300000>;
170
-
interrupts = <0 208 0>;
171
-
gpio-controller;
172
-
#gpio-cells = <2>;
173
-
gpio-ranges = <&tlmm 0 0 122>;
174
-
interrupt-controller;
175
-
#interrupt-cells = <2>;
176
-
177
-
uart2: uart2-default {
178
-
mux {
179
-
pins = "gpio4", "gpio5";
180
-
function = "blsp_uart2";
181
-
};
182
-
183
-
tx {
184
-
pins = "gpio4";
185
-
drive-strength = <4>;
186
-
bias-disable;
187
-
};
188
-
189
-
rx {
190
-
pins = "gpio5";
191
-
drive-strength = <2>;
192
-
bias-pull-up;
193
-
};
194
-
};
195
-
};
+166
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml
+166
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8916-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8916 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8916 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8916-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 61
34
+
35
+
gpio-line-names:
36
+
maxItems: 122
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8916-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8916-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8916-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
oneOf:
62
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[01])$"
63
+
- enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
64
+
qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
65
+
sdc2_cmd, sdc2_data ]
66
+
minItems: 1
67
+
maxItems: 36
68
+
69
+
function:
70
+
description:
71
+
Specify the alternative function to be configured for the specified
72
+
pins.
73
+
74
+
enum: [ gpio, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
75
+
atest_char0, atest_char1, atest_char2, atest_char3,
76
+
atest_combodac, atest_gpsadc0, atest_gpsadc1, atest_tsens,
77
+
atest_wlan0, atest_wlan1, backlight_en, bimc_dte0, bimc_dte1,
78
+
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
79
+
blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,
80
+
blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2,
81
+
blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
82
+
blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_uart1,
83
+
blsp_uart2, blsp_uim1, blsp_uim2, cam1_rst, cam1_standby,
84
+
cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
85
+
cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,
86
+
display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc,
87
+
euro_us, ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b,
88
+
gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b,
89
+
gsm0_tx0, gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0,
90
+
kpsns1, kpsns2, ldo_en, ldo_update, mag_int, mdp_vsync,
91
+
modem_tsync, m_voc, nav_pps, nav_tsync, pa_indicator, pbs0,
92
+
pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,
93
+
pwr_crypto_enabled_a, pwr_crypto_enabled_b,
94
+
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
95
+
pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1,
96
+
qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
97
+
qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
98
+
qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
99
+
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, reset_n,
100
+
sd_card, sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1,
101
+
uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan,
102
+
webcam1_rst ]
103
+
104
+
bias-pull-down: true
105
+
bias-pull-up: true
106
+
bias-disable: true
107
+
drive-strength: true
108
+
input-enable: true
109
+
output-high: true
110
+
output-low: true
111
+
112
+
required:
113
+
- pins
114
+
115
+
additionalProperties: false
116
+
117
+
allOf:
118
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
119
+
120
+
required:
121
+
- compatible
122
+
- reg
123
+
124
+
additionalProperties: false
125
+
126
+
examples:
127
+
- |
128
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
129
+
130
+
msmgpio: pinctrl@1000000 {
131
+
compatible = "qcom,msm8916-pinctrl";
132
+
reg = <0x01000000 0x300000>;
133
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
134
+
gpio-controller;
135
+
gpio-ranges = <&msmgpio 0 0 122>;
136
+
#gpio-cells = <2>;
137
+
interrupt-controller;
138
+
#interrupt-cells = <2>;
139
+
140
+
blsp1-uart2-sleep-state {
141
+
pins = "gpio4", "gpio5";
142
+
function = "gpio";
143
+
144
+
drive-strength = <2>;
145
+
bias-pull-down;
146
+
};
147
+
148
+
spi1-default-state {
149
+
spi-pins {
150
+
pins = "gpio0", "gpio1", "gpio3";
151
+
function = "blsp_spi1";
152
+
153
+
drive-strength = <12>;
154
+
bias-disable;
155
+
};
156
+
157
+
cs-pins {
158
+
pins = "gpio2";
159
+
function = "gpio";
160
+
161
+
drive-strength = <16>;
162
+
bias-disable;
163
+
output-high;
164
+
};
165
+
};
166
+
};
+35
-60
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+35
-60
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
···
9
9
maintainers:
10
10
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
MSM8953 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8953 SoC.
15
14
16
15
properties:
17
16
compatible:
···
19
20
reg:
20
21
maxItems: 1
21
22
22
-
interrupts:
23
-
description: Specifies the TLMM summary IRQ
24
-
maxItems: 1
25
-
23
+
interrupts: true
26
24
interrupt-controller: true
27
-
28
-
'#interrupt-cells':
29
-
description:
30
-
Specifies the PIN numbers and Flags, as defined in defined in
31
-
include/dt-bindings/interrupt-controller/irq.h
32
-
const: 2
33
-
25
+
"#interrupt-cells": true
34
26
gpio-controller: true
35
-
36
27
gpio-reserved-ranges: true
28
+
"#gpio-cells": true
29
+
gpio-ranges: true
37
30
38
-
'#gpio-cells':
39
-
description: Specifying the pin number and flags, as defined in
40
-
include/dt-bindings/gpio/gpio.h
41
-
const: 2
42
-
43
-
gpio-ranges:
44
-
maxItems: 1
45
-
46
-
#PIN CONFIGURATION NODES
47
31
patternProperties:
48
-
'-pins$':
32
+
"-state$":
33
+
oneOf:
34
+
- $ref: "#/$defs/qcom-msm8953-tlmm-state"
35
+
- patternProperties:
36
+
"-pins$":
37
+
$ref: "#/$defs/qcom-msm8953-tlmm-state"
38
+
additionalProperties: false
39
+
40
+
$defs:
41
+
qcom-msm8953-tlmm-state:
49
42
type: object
50
43
description:
51
44
Pinctrl node's client devices use subnodes for desired pin configuration.
52
45
Client device subnodes use below standard properties.
53
-
$ref: "/schemas/pinctrl/pincfg-node.yaml"
46
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
47
55
48
properties:
56
49
pins:
···
104
113
uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan,
105
114
wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ]
106
115
107
-
drive-strength:
108
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
109
-
default: 2
110
-
description:
111
-
Selects the drive strength for the specified pins, in mA.
112
-
113
116
bias-pull-down: true
114
-
115
117
bias-pull-up: true
116
-
117
118
bias-disable: true
118
-
119
+
drive-strength: true
119
120
output-high: true
120
-
121
121
output-low: true
122
122
123
123
required:
124
124
- pins
125
-
- function
126
125
127
126
additionalProperties: false
128
127
129
128
allOf:
130
-
- $ref: "pinctrl.yaml#"
129
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
131
130
132
131
required:
133
132
- compatible
134
133
- reg
135
-
- interrupts
136
-
- interrupt-controller
137
-
- '#interrupt-cells'
138
-
- gpio-controller
139
-
- '#gpio-cells'
140
-
- gpio-ranges
141
134
142
135
additionalProperties: false
143
136
144
137
examples:
145
138
- |
146
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
147
-
tlmm: pinctrl@1000000 {
148
-
compatible = "qcom,msm8953-pinctrl";
149
-
reg = <0x01000000 0x300000>;
150
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
151
-
interrupt-controller;
152
-
#interrupt-cells = <2>;
153
-
gpio-controller;
154
-
#gpio-cells = <2>;
155
-
gpio-ranges = <&tlmm 0 0 142>;
139
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
140
+
tlmm: pinctrl@1000000 {
141
+
compatible = "qcom,msm8953-pinctrl";
142
+
reg = <0x01000000 0x300000>;
143
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
144
+
interrupt-controller;
145
+
#interrupt-cells = <2>;
146
+
gpio-controller;
147
+
#gpio-cells = <2>;
148
+
gpio-ranges = <&tlmm 0 0 142>;
156
149
157
-
serial_default: serial-pins {
158
-
pins = "gpio4", "gpio5";
159
-
function = "blsp_uart2";
160
-
drive-strength = <2>;
161
-
bias-disable;
162
-
};
150
+
serial_default: serial-state {
151
+
pins = "gpio4", "gpio5";
152
+
function = "blsp_uart2";
153
+
drive-strength = <2>;
154
+
bias-disable;
163
155
};
156
+
};
-190
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt
-190
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt
···
1
-
Qualcomm MSM8960 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8960 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,msm8960-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode. Valid pins are:
85
-
gpio0-gpio151,
86
-
sdc1_clk,
87
-
sdc1_cmd,
88
-
sdc1_data
89
-
sdc3_clk,
90
-
sdc3_cmd,
91
-
sdc3_data
92
-
93
-
- function:
94
-
Usage: required
95
-
Value type: <string>
96
-
Definition: Specify the alternative function to be configured for the
97
-
specified pins. Functions are only valid for gpio pins.
98
-
Valid values are:
99
-
audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2,
100
-
codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking,
101
-
gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a,
102
-
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a,
103
-
gp_pdm_0b, gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gpio,
104
-
gsbi1, gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n,
105
-
gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
106
-
gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l,
107
-
gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l,
108
-
gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10,
109
-
gsbi11, gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n,
110
-
gsbi11_spi_cs2a_n, gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n,
111
-
gsbi12, hdmi_cec, hdmi_ddc_clock, hdmi_ddc_data,
112
-
hdmi_hot_plug_detect, hsic, mdp_vsync, mi2s, mic_i2s,
113
-
pmb_clk, pmb_ext_ctrl, ps_hold, rpm_wdog, sdc2, sdc4, sdc5,
114
-
slimbus1, slimbus2, spkr_i2s, ssbi1, ssbi2, ssbi_ext_gps,
115
-
ssbi_pmic2, ssbi_qpa1, ssbi_ts, tsif1, tsif2, ts_eoc,
116
-
usb_fs1, usb_fs1_oe, usb_fs1_oe_n, usb_fs2, usb_fs2_oe,
117
-
usb_fs2_oe_n, vfe_camif_timer1_a, vfe_camif_timer1_b,
118
-
vfe_camif_timer2, vfe_camif_timer3_a, vfe_camif_timer3_b,
119
-
vfe_camif_timer4_a, vfe_camif_timer4_b, vfe_camif_timer4_c,
120
-
vfe_camif_timer5_a, vfe_camif_timer5_b, vfe_camif_timer6_a,
121
-
vfe_camif_timer6_b, vfe_camif_timer6_c, vfe_camif_timer7_a,
122
-
vfe_camif_timer7_b, vfe_camif_timer7_c, wlan
123
-
124
-
- bias-disable:
125
-
Usage: optional
126
-
Value type: <none>
127
-
Definition: The specified pins should be configured as no pull.
128
-
129
-
- bias-pull-down:
130
-
Usage: optional
131
-
Value type: <none>
132
-
Definition: The specified pins should be configured as pull down.
133
-
134
-
- bias-pull-up:
135
-
Usage: optional
136
-
Value type: <none>
137
-
Definition: The specified pins should be configured as pull up.
138
-
139
-
- output-high:
140
-
Usage: optional
141
-
Value type: <none>
142
-
Definition: The specified pins are configured in output mode, driven
143
-
high.
144
-
Not valid for sdc pins.
145
-
146
-
- output-low:
147
-
Usage: optional
148
-
Value type: <none>
149
-
Definition: The specified pins are configured in output mode, driven
150
-
low.
151
-
Not valid for sdc pins.
152
-
153
-
- drive-strength:
154
-
Usage: optional
155
-
Value type: <u32>
156
-
Definition: Selects the drive strength for the specified pins, in mA.
157
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
158
-
159
-
Example:
160
-
161
-
msmgpio: pinctrl@800000 {
162
-
compatible = "qcom,msm8960-pinctrl";
163
-
reg = <0x800000 0x4000>;
164
-
165
-
gpio-controller;
166
-
#gpio-cells = <2>;
167
-
gpio-ranges = <&msmgpio 0 0 152>;
168
-
interrupt-controller;
169
-
#interrupt-cells = <2>;
170
-
interrupts = <0 16 0x4>;
171
-
172
-
gsbi8_uart: gsbi8-uart {
173
-
mux {
174
-
pins = "gpio34", "gpio35";
175
-
function = "gsbi8";
176
-
};
177
-
178
-
tx {
179
-
pins = "gpio34";
180
-
drive-strength = <4>;
181
-
bias-disable;
182
-
};
183
-
184
-
rx {
185
-
pins = "gpio35";
186
-
drive-strength = <2>;
187
-
bias-pull-up;
188
-
};
189
-
};
190
-
};
+164
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml
+164
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8960 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8960 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8960-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 76
34
+
35
+
gpio-line-names:
36
+
maxItems: 152
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8960-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8960-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8960-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
oneOf:
62
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-1])$"
63
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd,
64
+
sdc3_data ]
65
+
minItems: 1
66
+
maxItems: 36
67
+
68
+
function:
69
+
description:
70
+
Specify the alternative function to be configured for the specified
71
+
pins.
72
+
73
+
enum: [ gpio, audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2,
74
+
codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking,
75
+
gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a,
76
+
gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a, gp_pdm_0b,
77
+
gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gsbi1,
78
+
gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n,
79
+
gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
80
+
gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l,
81
+
gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l,
82
+
gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11,
83
+
gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n, gsbi11_spi_cs2a_n,
84
+
gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n, gsbi12, hdmi_cec,
85
+
hdmi_ddc_clock, hdmi_ddc_data, hdmi_hot_plug_detect, hsic,
86
+
mdp_vsync, mi2s, mic_i2s, pmb_clk, pmb_ext_ctrl, ps_hold,
87
+
rpm_wdog, sdc2, sdc4, sdc5, slimbus1, slimbus2, spkr_i2s,
88
+
ssbi1, ssbi2, ssbi_ext_gps, ssbi_pmic2, ssbi_qpa1, ssbi_ts,
89
+
tsif1, tsif2, ts_eoc, usb_fs1, usb_fs1_oe, usb_fs1_oe_n,
90
+
usb_fs2, usb_fs2_oe, usb_fs2_oe_n, vfe_camif_timer1_a,
91
+
vfe_camif_timer1_b, vfe_camif_timer2, vfe_camif_timer3_a,
92
+
vfe_camif_timer3_b, vfe_camif_timer4_a, vfe_camif_timer4_b,
93
+
vfe_camif_timer4_c, vfe_camif_timer5_a, vfe_camif_timer5_b,
94
+
vfe_camif_timer6_a, vfe_camif_timer6_b, vfe_camif_timer6_c,
95
+
vfe_camif_timer7_a, vfe_camif_timer7_b, vfe_camif_timer7_c,
96
+
wlan ]
97
+
98
+
bias-pull-down: true
99
+
bias-pull-up: true
100
+
bias-disable: true
101
+
drive-strength: true
102
+
input-enable: true
103
+
output-high: true
104
+
output-low: true
105
+
106
+
required:
107
+
- pins
108
+
109
+
additionalProperties: false
110
+
111
+
allOf:
112
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
113
+
114
+
required:
115
+
- compatible
116
+
- reg
117
+
118
+
additionalProperties: false
119
+
120
+
examples:
121
+
- |
122
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
123
+
124
+
msmgpio: pinctrl@800000 {
125
+
compatible = "qcom,msm8960-pinctrl";
126
+
reg = <0x800000 0x4000>;
127
+
#gpio-cells = <2>;
128
+
gpio-controller;
129
+
gpio-ranges = <&msmgpio 0 0 152>;
130
+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
131
+
interrupt-controller;
132
+
#interrupt-cells = <2>;
133
+
134
+
spi1-default-state {
135
+
mosi-pins {
136
+
pins = "gpio6";
137
+
function = "gsbi1";
138
+
drive-strength = <12>;
139
+
bias-disable;
140
+
};
141
+
142
+
miso-pins {
143
+
pins = "gpio7";
144
+
function = "gsbi1";
145
+
drive-strength = <12>;
146
+
bias-disable;
147
+
};
148
+
149
+
cs-pins {
150
+
pins = "gpio8";
151
+
function = "gpio";
152
+
drive-strength = <12>;
153
+
bias-disable;
154
+
output-low;
155
+
};
156
+
157
+
clk-pins {
158
+
pins = "gpio9";
159
+
function = "gsbi1";
160
+
drive-strength = <12>;
161
+
bias-disable;
162
+
};
163
+
};
164
+
};
-121
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
-121
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
···
1
-
Qualcomm MSM8974 TLMM block
2
-
3
-
Required properties:
4
-
- compatible: "qcom,msm8974-pinctrl"
5
-
- reg: Should be the base address and length of the TLMM block.
6
-
- interrupts: Should be the parent IRQ of the TLMM block.
7
-
- interrupt-controller: Marks the device node as an interrupt controller.
8
-
- #interrupt-cells: Should be two.
9
-
- gpio-controller: Marks the device node as a GPIO controller.
10
-
- #gpio-cells : Should be two.
11
-
The first cell is the gpio pin number and the
12
-
second cell is used for optional parameters.
13
-
- gpio-ranges: see ../gpio/gpio.txt
14
-
15
-
Optional properties:
16
-
17
-
- gpio-reserved-ranges: see ../gpio/gpio.txt
18
-
19
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
20
-
a general description of GPIO and interrupt bindings.
21
-
22
-
Please refer to pinctrl-bindings.txt in this directory for details of the
23
-
common pinctrl bindings used by client devices, including the meaning of the
24
-
phrase "pin configuration node".
25
-
26
-
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
27
-
subnodes. Each of these subnodes represents some desired configuration for a
28
-
pin, a group, or a list of pins or groups. This configuration can include the
29
-
mux function to select on those pin(s)/group(s), and various pin configuration
30
-
parameters, such as pull-up, drive strength, etc.
31
-
32
-
The name of each subnode is not important; all subnodes should be enumerated
33
-
and processed purely based on their content.
34
-
35
-
Each subnode only affects those parameters that are explicitly listed. In
36
-
other words, a subnode that lists a mux function but no pin configuration
37
-
parameters implies no information about any pin configuration parameters.
38
-
Similarly, a pin subnode that describes a pullup parameter implies no
39
-
information about e.g. the mux function.
40
-
41
-
42
-
The following generic properties as defined in pinctrl-bindings.txt are valid
43
-
to specify in a pin configuration subnode:
44
-
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength.
45
-
46
-
Non-empty subnodes must specify the 'pins' property.
47
-
Note that not all properties are valid for all pins.
48
-
49
-
50
-
Valid values for pins are:
51
-
gpio0-gpio145
52
-
Supports mux, bias and drive-strength
53
-
54
-
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
55
-
Supports bias and drive-strength
56
-
57
-
hsic_data, hsic_strobe
58
-
Supports only mux
59
-
60
-
Valid values for function are:
61
-
cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
62
-
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1,
63
-
blsp_uim2, blsp_uart2, blsp_i2c2, blsp_spi2,
64
-
blsp_uim3, blsp_uart3, blsp_i2c3, blsp_spi3,
65
-
blsp_uim4, blsp_uart4, blsp_i2c4, blsp_spi4,
66
-
blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
67
-
blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6,
68
-
blsp_uim7, blsp_uart7, blsp_i2c7, blsp_spi7,
69
-
blsp_uim8, blsp_uart8, blsp_i2c8, blsp_spi8,
70
-
blsp_uim9, blsp_uart9, blsp_i2c9, blsp_spi9,
71
-
blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
72
-
blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11,
73
-
blsp_uim12, blsp_uart12, blsp_i2c12, blsp_spi12,
74
-
blsp_spi1_cs1, blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
75
-
blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
76
-
sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, cci_timer1,
77
-
cci_timer2, cci_timer3, cci_async_in0, cci_async_in1, cci_async_in2,
78
-
cam_mckl0, cam_mclk1, cam_mclk2, cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc,
79
-
hdmi_hpd, edp_hpd, gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk,
80
-
gp_mn, tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, spkr_mi2s,
81
-
ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl, gpio
82
-
83
-
(Note that this is not yet the complete list of functions)
84
-
85
-
86
-
87
-
Example:
88
-
89
-
msmgpio: pinctrl@fd510000 {
90
-
compatible = "qcom,msm8974-pinctrl";
91
-
reg = <0xfd510000 0x4000>;
92
-
93
-
gpio-controller;
94
-
#gpio-cells = <2>;
95
-
gpio-ranges = <&msmgpio 0 0 146>;
96
-
interrupt-controller;
97
-
#interrupt-cells = <2>;
98
-
interrupts = <0 208 0>;
99
-
100
-
pinctrl-names = "default";
101
-
pinctrl-0 = <&uart2_default>;
102
-
103
-
uart2_default: uart2_default {
104
-
mux {
105
-
pins = "gpio4", "gpio5";
106
-
function = "blsp_uart2";
107
-
};
108
-
109
-
tx {
110
-
pins = "gpio4";
111
-
drive-strength = <4>;
112
-
bias-disable;
113
-
};
114
-
115
-
rx {
116
-
pins = "gpio5";
117
-
drive-strength = <2>;
118
-
bias-pull-up;
119
-
};
120
-
};
121
-
};
+179
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
+179
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8974 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8974-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 73
34
+
35
+
gpio-line-names:
36
+
maxItems: 146
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8974-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8974-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8974-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
oneOf:
62
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
63
+
- enum: [ hsic_data, hsic_strobe, sdc1_clk, sdc1_cmd, sdc1_data,
64
+
sdc2_clk, sdc2_cmd, sdc2_data ]
65
+
minItems: 1
66
+
maxItems: 36
67
+
68
+
function:
69
+
description:
70
+
Specify the alternative function to be configured for the specified
71
+
pins.
72
+
73
+
enum: [ gpio, cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
74
+
blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, blsp_uim2,
75
+
blsp_uart2, blsp_i2c2, blsp_spi2, blsp_uim3, blsp_uart3,
76
+
blsp_i2c3, blsp_spi3, blsp_uim4, blsp_uart4, blsp_i2c4,
77
+
blsp_spi4, blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
78
+
blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, blsp_uim7,
79
+
blsp_uart7, blsp_i2c7, blsp_spi7, blsp_uim8, blsp_uart8,
80
+
blsp_i2c8, blsp_spi8, blsp_uim9, blsp_uart9, blsp_i2c9,
81
+
blsp_spi9, blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
82
+
blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, blsp_uim12,
83
+
blsp_uart12, blsp_i2c12, blsp_spi12, blsp_spi1_cs1,
84
+
blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
85
+
blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
86
+
sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0,
87
+
cci_timer1, cci_timer2, cci_timer3, cci_async_in0,
88
+
cci_async_in1, cci_async_in2, cam_mckl0, cam_mclk1, cam_mclk2,
89
+
cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd,
90
+
gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn,
91
+
tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s,
92
+
spkr_mi2s, ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl ]
93
+
94
+
bias-pull-down: true
95
+
bias-pull-up: true
96
+
bias-disable: true
97
+
drive-strength: true
98
+
input-enable: true
99
+
output-high: true
100
+
output-low: true
101
+
102
+
required:
103
+
- pins
104
+
105
+
allOf:
106
+
- if:
107
+
properties:
108
+
pins:
109
+
contains:
110
+
enum:
111
+
- hsic_data
112
+
- hsic_strobe
113
+
required:
114
+
- pins
115
+
then:
116
+
properties:
117
+
bias-pull-down: false
118
+
bias-pull-up: false
119
+
bias-disable: false
120
+
drive-strength: false
121
+
input-enable: false
122
+
output-high: false
123
+
output-low: false
124
+
125
+
additionalProperties: false
126
+
127
+
allOf:
128
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
129
+
130
+
required:
131
+
- compatible
132
+
- reg
133
+
134
+
additionalProperties: false
135
+
136
+
examples:
137
+
- |
138
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
139
+
tlmm: pinctrl@fd510000 {
140
+
compatible = "qcom,msm8974-pinctrl";
141
+
reg = <0xfd510000 0x4000>;
142
+
gpio-controller;
143
+
gpio-ranges = <&tlmm 0 0 146>;
144
+
#gpio-cells = <2>;
145
+
interrupt-controller;
146
+
#interrupt-cells = <2>;
147
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
148
+
149
+
sdc1-off-state {
150
+
clk-pins {
151
+
pins = "sdc1_clk";
152
+
bias-disable;
153
+
drive-strength = <2>;
154
+
};
155
+
156
+
cmd-pins {
157
+
pins = "sdc1_cmd";
158
+
bias-pull-up;
159
+
drive-strength = <2>;
160
+
};
161
+
162
+
data-pins {
163
+
pins = "sdc1_data";
164
+
bias-pull-up;
165
+
drive-strength = <2>;
166
+
};
167
+
};
168
+
169
+
blsp2-uart1-sleep-state {
170
+
pins = "gpio41", "gpio42", "gpio43", "gpio44";
171
+
function = "gpio";
172
+
drive-strength = <2>;
173
+
bias-pull-down;
174
+
};
175
+
176
+
hsic-state {
177
+
pins = "hsic_data", "hsic_strobe";
178
+
};
179
+
};
-183
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.txt
-183
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.txt
···
1
-
Qualcomm MSM8976 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8956 and MSM8976 platforms.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,msm8976-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode.
85
-
86
-
Valid pins are:
87
-
gpio0-gpio145
88
-
Supports mux, bias and drive-strength
89
-
90
-
sdc1_clk, sdc1_cmd, sdc1_data,
91
-
sdc2_clk, sdc2_cmd, sdc2_data,
92
-
sdc3_clk, sdc3_cmd, sdc3_data
93
-
Supports bias and drive-strength
94
-
95
-
- function:
96
-
Usage: required
97
-
Value type: <string>
98
-
Definition: Specify the alternative function to be configured for the
99
-
specified pins. Functions are only valid for gpio pins.
100
-
Valid values are:
101
-
102
-
gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
103
-
blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
104
-
qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
105
-
blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
106
-
qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
107
-
qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
108
-
blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
109
-
sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
110
-
blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
111
-
uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
112
-
uim1_present, uim2_data, uim2_clk, uim2_reset,
113
-
uim2_present, ts_xvdd, mipi_dsi0, us_euro, ts_resout,
114
-
ts_sample, sec_mi2s_mclk_b, pri_mi2s, codec_reset,
115
-
cdc_pdm0, us_emitter, pri_mi2s_mclk_b, pri_mi2s_mclk_c,
116
-
lpass_slimbus, lpass_slimbus0, lpass_slimbus1, codec_int1,
117
-
codec_int2, wcss_bt, sdc3, wcss_wlan2, wcss_wlan1,
118
-
wcss_wlan0, wcss_wlan, wcss_fm, key_volp, key_snapshot,
119
-
key_focus, key_home, pwr_down, dmic0_clk, hdmi_int,
120
-
dmic0_data, wsa_vi, wsa_en, blsp_spi8, wsa_irq, blsp_i2c8,
121
-
pa_indicator, modem_tsync, ssbi_wtr1, gsm1_tx, gsm0_tx,
122
-
sdcard_det, sec_mi2s, ss_switch,
123
-
124
-
- bias-disable:
125
-
Usage: optional
126
-
Value type: <none>
127
-
Definition: The specified pins should be configured as no pull.
128
-
129
-
- bias-pull-down:
130
-
Usage: optional
131
-
Value type: <none>
132
-
Definition: The specified pins should be configured as pull down.
133
-
134
-
- bias-pull-up:
135
-
Usage: optional
136
-
Value type: <none>
137
-
Definition: The specified pins should be configured as pull up.
138
-
139
-
- output-high:
140
-
Usage: optional
141
-
Value type: <none>
142
-
Definition: The specified pins are configured in output mode, driven
143
-
high.
144
-
Not valid for sdc pins.
145
-
146
-
- output-low:
147
-
Usage: optional
148
-
Value type: <none>
149
-
Definition: The specified pins are configured in output mode, driven
150
-
low.
151
-
Not valid for sdc pins.
152
-
153
-
- drive-strength:
154
-
Usage: optional
155
-
Value type: <u32>
156
-
Definition: Selects the drive strength for the specified pins, in mA.
157
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
158
-
159
-
Example:
160
-
161
-
tlmm: pinctrl@1000000 {
162
-
compatible = "qcom,msm8976-pinctrl";
163
-
reg = <0x1000000 0x300000>;
164
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
165
-
gpio-controller;
166
-
#gpio-cells = <2>;
167
-
gpio-ranges = <&tlmm 0 0 145>;
168
-
interrupt-controller;
169
-
#interrupt-cells = <2>;
170
-
171
-
blsp1_uart2_active: blsp1_uart2_active {
172
-
mux {
173
-
pins = "gpio4", "gpio5", "gpio6", "gpio7";
174
-
function = "blsp_uart2";
175
-
};
176
-
177
-
config {
178
-
pins = "gpio4", "gpio5", "gpio6", "gpio7";
179
-
drive-strength = <2>;
180
-
bias-disable;
181
-
};
182
-
};
183
-
};
+136
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml
+136
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8976-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8976 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8976 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8976-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 73
34
+
35
+
gpio-line-names:
36
+
maxItems: 145
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8976-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8976-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8976-tlmm-state:
49
+
type: object
50
+
description:
51
+
Desired pin configuration for a device or its specific state (like sleep
52
+
or active).
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this state.
59
+
items:
60
+
oneOf:
61
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-4])$"
62
+
- enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
63
+
qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
64
+
sdc2_clk, sdc2_cmd, sdc2_data ]
65
+
minItems: 1
66
+
maxItems: 36
67
+
68
+
function:
69
+
description:
70
+
Specify the alternative function to be configured for the specified
71
+
pins.
72
+
73
+
enum: [ gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
74
+
blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
75
+
qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
76
+
blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
77
+
qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
78
+
qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
79
+
blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
80
+
sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
81
+
blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
82
+
uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
83
+
uim1_present, uim2_data, uim2_clk, uim2_reset, uim2_present,
84
+
ts_xvdd, mipi_dsi0, us_euro, ts_resout, ts_sample,
85
+
sec_mi2s_mclk_b, pri_mi2s, codec_reset, cdc_pdm0, us_emitter,
86
+
pri_mi2s_mclk_b, pri_mi2s_mclk_c, lpass_slimbus,
87
+
lpass_slimbus0, lpass_slimbus1, codec_int1, codec_int2,
88
+
wcss_bt, sdc3, wcss_wlan2, wcss_wlan1, wcss_wlan0, wcss_wlan,
89
+
wcss_fm, key_volp, key_snapshot, key_focus, key_home, pwr_down,
90
+
dmic0_clk, hdmi_int, dmic0_data, wsa_vi, wsa_en, blsp_spi8,
91
+
wsa_irq, blsp_i2c8, pa_indicator, modem_tsync, ssbi_wtr1,
92
+
gsm1_tx, gsm0_tx, sdcard_det, sec_mi2s, ss_switch ]
93
+
94
+
bias-pull-down: true
95
+
bias-pull-up: true
96
+
bias-disable: true
97
+
drive-strength: true
98
+
input-enable: true
99
+
output-high: true
100
+
output-low: true
101
+
102
+
required:
103
+
- pins
104
+
105
+
additionalProperties: false
106
+
107
+
allOf:
108
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
109
+
110
+
required:
111
+
- compatible
112
+
- reg
113
+
114
+
additionalProperties: false
115
+
116
+
examples:
117
+
- |
118
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
119
+
120
+
tlmm: pinctrl@1000000 {
121
+
compatible = "qcom,msm8976-pinctrl";
122
+
reg = <0x1000000 0x300000>;
123
+
#gpio-cells = <2>;
124
+
gpio-controller;
125
+
gpio-ranges = <&tlmm 0 0 145>;
126
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127
+
interrupt-controller;
128
+
#interrupt-cells = <2>;
129
+
130
+
blsp1-uart2-active-state {
131
+
pins = "gpio4", "gpio5", "gpio6", "gpio7";
132
+
function = "blsp_uart2";
133
+
drive-strength = <2>;
134
+
bias-disable;
135
+
};
136
+
};
-186
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt
-186
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt
···
1
-
Qualcomm MSM8994 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8994 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: Should contain one of:
10
-
"qcom,msm8992-pinctrl",
11
-
"qcom,msm8994-pinctrl".
12
-
13
-
- reg:
14
-
Usage: required
15
-
Value type: <prop-encoded-array>
16
-
Definition: the base address and size of the TLMM register space.
17
-
18
-
- interrupts:
19
-
Usage: required
20
-
Value type: <prop-encoded-array>
21
-
Definition: should specify the TLMM summary IRQ.
22
-
23
-
- interrupt-controller:
24
-
Usage: required
25
-
Value type: <none>
26
-
Definition: identifies this node as an interrupt controller
27
-
28
-
- #interrupt-cells:
29
-
Usage: required
30
-
Value type: <u32>
31
-
Definition: must be 2. Specifying the pin number and flags, as defined
32
-
in <dt-bindings/interrupt-controller/irq.h>
33
-
34
-
- gpio-controller:
35
-
Usage: required
36
-
Value type: <none>
37
-
Definition: identifies this node as a gpio controller
38
-
39
-
- #gpio-cells:
40
-
Usage: required
41
-
Value type: <u32>
42
-
Definition: must be 2. Specifying the pin number and flags, as defined
43
-
in <dt-bindings/gpio/gpio.h>
44
-
45
-
- gpio-ranges:
46
-
Usage: required
47
-
Definition: see ../gpio/gpio.txt
48
-
49
-
- gpio-reserved-ranges:
50
-
Usage: optional
51
-
Definition: see ../gpio/gpio.txt
52
-
53
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
54
-
a general description of GPIO and interrupt bindings.
55
-
56
-
Please refer to pinctrl-bindings.txt in this directory for details of the
57
-
common pinctrl bindings used by client devices, including the meaning of the
58
-
phrase "pin configuration node".
59
-
60
-
The pin configuration nodes act as a container for an arbitrary number of
61
-
subnodes. Each of these subnodes represents some desired configuration for a
62
-
pin, a group, or a list of pins or groups. This configuration can include the
63
-
mux function to select on those pin(s)/group(s), and various pin configuration
64
-
parameters, such as pull-up, drive strength, etc.
65
-
66
-
67
-
PIN CONFIGURATION NODES:
68
-
69
-
The name of each subnode is not important; all subnodes should be enumerated
70
-
and processed purely based on their content.
71
-
72
-
Each subnode only affects those parameters that are explicitly listed. In
73
-
other words, a subnode that lists a mux function but no pin configuration
74
-
parameters implies no information about any pin configuration parameters.
75
-
Similarly, a pin subnode that describes a pullup parameter implies no
76
-
information about e.g. the mux function.
77
-
78
-
79
-
The following generic properties as defined in pinctrl-bindings.txt are valid
80
-
to specify in a pin configuration subnode:
81
-
82
-
- pins:
83
-
Usage: required
84
-
Value type: <string-array>
85
-
Definition: List of gpio pins affected by the properties specified in
86
-
this subnode.
87
-
88
-
Valid pins are:
89
-
gpio0-gpio145
90
-
Supports mux, bias and drive-strength
91
-
92
-
sdc1_clk, sdc1_cmd, sdc1_data sdc1_rclk, sdc2_clk,
93
-
sdc2_cmd, sdc2_data
94
-
Supports bias and drive-strength
95
-
96
-
- function:
97
-
Usage: required
98
-
Value type: <string>
99
-
Definition: Specify the alternative function to be configured for the
100
-
specified pins. Functions are only valid for gpio pins.
101
-
Valid values are:
102
-
103
-
audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
104
-
blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11,
105
-
blsp_i2c12, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
106
-
blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
107
-
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9,
108
-
blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, blsp_spi11,
109
-
blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, blsp_uart5,
110
-
blsp_uart6, blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11,
111
-
blsp_uart12, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
112
-
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
113
-
blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, blsp11_uart_rx_b,
114
-
blsp11_uart_tx_b, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
115
-
cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c0, cci_i2c1,
116
-
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
117
-
gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
118
-
gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
119
-
gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, hdmi_rcv,
120
-
mdp_vsync, mss_lte, nav_pps, nav_tsync, qdss_cti_trig_in_a,
121
-
qdss_cti_trig_in_b, qdss_cti_trig_in_c, qdss_cti_trig_in_d,
122
-
qdss_cti_trig_out_a, qdss_cti_trig_out_b, qdss_cti_trig_out_c,
123
-
qdss_cti_trig_out_d, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
124
-
qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0,
125
-
pci_e1, pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
126
-
tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4, gpio
127
-
128
-
- bias-disable:
129
-
Usage: optional
130
-
Value type: <none>
131
-
Definition: The specified pins should be configured as no pull.
132
-
133
-
- bias-pull-down:
134
-
Usage: optional
135
-
Value type: <none>
136
-
Definition: The specified pins should be configured as pull down.
137
-
138
-
- bias-pull-up:
139
-
Usage: optional
140
-
Value type: <none>
141
-
Definition: The specified pins should be configured as pull up.
142
-
143
-
- output-high:
144
-
Usage: optional
145
-
Value type: <none>
146
-
Definition: The specified pins are configured in output mode, driven
147
-
high.
148
-
Not valid for sdc pins.
149
-
150
-
- output-low:
151
-
Usage: optional
152
-
Value type: <none>
153
-
Definition: The specified pins are configured in output mode, driven
154
-
low.
155
-
Not valid for sdc pins.
156
-
157
-
- drive-strength:
158
-
Usage: optional
159
-
Value type: <u32>
160
-
Definition: Selects the drive strength for the specified pins, in mA.
161
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
162
-
163
-
Example:
164
-
165
-
msmgpio: pinctrl@fd510000 {
166
-
compatible = "qcom,msm8994-pinctrl";
167
-
reg = <0xfd510000 0x4000>;
168
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
169
-
gpio-controller;
170
-
#gpio-cells = <2>;
171
-
gpio-ranges = <&msmgpio 0 0 146>;
172
-
interrupt-controller;
173
-
#interrupt-cells = <2>;
174
-
175
-
blsp1_uart2_default: blsp1_uart2_default {
176
-
pinmux {
177
-
pins = "gpio4", "gpio5";
178
-
function = "blsp_uart2";
179
-
};
180
-
pinconf {
181
-
pins = "gpio4", "gpio5";
182
-
drive-strength = <16>;
183
-
bias-disable;
184
-
};
185
-
};
186
-
};
+162
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml
+162
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8994 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- qcom,msm8992-pinctrl
20
+
- qcom,msm8994-pinctrl
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts: true
26
+
interrupt-controller: true
27
+
"#interrupt-cells": true
28
+
gpio-controller: true
29
+
"#gpio-cells": true
30
+
gpio-ranges: true
31
+
wakeup-parent: true
32
+
33
+
gpio-reserved-ranges:
34
+
minItems: 1
35
+
maxItems: 75
36
+
37
+
gpio-line-names:
38
+
maxItems: 150
39
+
40
+
patternProperties:
41
+
"-state$":
42
+
oneOf:
43
+
- $ref: "#/$defs/qcom-msm8994-tlmm-state"
44
+
- patternProperties:
45
+
"-pins$":
46
+
$ref: "#/$defs/qcom-msm8994-tlmm-state"
47
+
additionalProperties: false
48
+
49
+
$defs:
50
+
qcom-msm8994-tlmm-state:
51
+
type: object
52
+
description:
53
+
Pinctrl node's client devices use subnodes for desired pin configuration.
54
+
Client device subnodes use below standard properties.
55
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56
+
57
+
properties:
58
+
pins:
59
+
description:
60
+
List of gpio pins affected by the properties specified in this
61
+
subnode.
62
+
items:
63
+
oneOf:
64
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
65
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
66
+
sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
67
+
minItems: 1
68
+
maxItems: 36
69
+
70
+
function:
71
+
description:
72
+
Specify the alternative function to be configured for the specified
73
+
pins.
74
+
75
+
enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
76
+
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
77
+
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
78
+
blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
79
+
blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
80
+
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
81
+
blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
82
+
blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
83
+
blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
84
+
blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
85
+
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
86
+
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
87
+
blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
88
+
blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
89
+
cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
90
+
cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
91
+
cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
92
+
gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
93
+
gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
94
+
gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
95
+
hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
96
+
qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
97
+
qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
98
+
qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
99
+
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
100
+
qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
101
+
pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
102
+
tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]
103
+
104
+
bias-pull-down: true
105
+
bias-pull-up: true
106
+
bias-disable: true
107
+
drive-strength: true
108
+
input-enable: true
109
+
output-high: true
110
+
output-low: true
111
+
112
+
required:
113
+
- pins
114
+
115
+
additionalProperties: false
116
+
117
+
allOf:
118
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
119
+
120
+
required:
121
+
- compatible
122
+
- reg
123
+
124
+
additionalProperties: false
125
+
126
+
examples:
127
+
- |
128
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
129
+
130
+
tlmm: pinctrl@fd510000 {
131
+
compatible = "qcom,msm8994-pinctrl";
132
+
reg = <0xfd510000 0x4000>;
133
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
134
+
gpio-controller;
135
+
gpio-ranges = <&tlmm 0 0 146>;
136
+
#gpio-cells = <2>;
137
+
interrupt-controller;
138
+
#interrupt-cells = <2>;
139
+
140
+
blsp1-uart2-default-state {
141
+
function = "blsp_uart2";
142
+
pins = "gpio4", "gpio5";
143
+
drive-strength = <16>;
144
+
bias-disable;
145
+
};
146
+
147
+
blsp1-spi1-default-state {
148
+
default-pins {
149
+
pins = "gpio0", "gpio1", "gpio3";
150
+
function = "blsp_spi1";
151
+
drive-strength = <10>;
152
+
bias-pull-down;
153
+
};
154
+
155
+
cs-pins {
156
+
pins = "gpio8";
157
+
function = "gpio";
158
+
drive-strength = <2>;
159
+
bias-disable;
160
+
};
161
+
};
162
+
};
-208
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt
-208
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt
···
1
-
Qualcomm MSM8996 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8996 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,msm8996-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode.
85
-
86
-
Valid pins are:
87
-
gpio0-gpio149
88
-
Supports mux, bias and drive-strength
89
-
90
-
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
91
-
sdc2_data sdc1_rclk
92
-
Supports bias and drive-strength
93
-
94
-
- function:
95
-
Usage: required
96
-
Value type: <string>
97
-
Definition: Specify the alternative function to be configured for the
98
-
specified pins. Functions are only valid for gpio pins.
99
-
Valid values are:
100
-
101
-
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
102
-
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
103
-
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
104
-
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
105
-
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
106
-
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
107
-
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
108
-
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
109
-
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
110
-
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
111
-
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
112
-
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
113
-
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
114
-
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
115
-
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
116
-
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
117
-
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
118
-
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
119
-
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
120
-
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
121
-
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
122
-
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
123
-
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
124
-
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
125
-
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
126
-
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
127
-
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
128
-
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
129
-
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
130
-
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
131
-
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
132
-
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
133
-
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
134
-
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
135
-
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
136
-
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
137
-
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
138
-
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
139
-
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
140
-
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
141
-
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
142
-
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
143
-
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
144
-
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
145
-
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
146
-
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
147
-
gpio
148
-
149
-
- bias-disable:
150
-
Usage: optional
151
-
Value type: <none>
152
-
Definition: The specified pins should be configured as no pull.
153
-
154
-
- bias-pull-down:
155
-
Usage: optional
156
-
Value type: <none>
157
-
Definition: The specified pins should be configured as pull down.
158
-
159
-
- bias-pull-up:
160
-
Usage: optional
161
-
Value type: <none>
162
-
Definition: The specified pins should be configured as pull up.
163
-
164
-
- output-high:
165
-
Usage: optional
166
-
Value type: <none>
167
-
Definition: The specified pins are configured in output mode, driven
168
-
high.
169
-
Not valid for sdc pins.
170
-
171
-
- output-low:
172
-
Usage: optional
173
-
Value type: <none>
174
-
Definition: The specified pins are configured in output mode, driven
175
-
low.
176
-
Not valid for sdc pins.
177
-
178
-
- drive-strength:
179
-
Usage: optional
180
-
Value type: <u32>
181
-
Definition: Selects the drive strength for the specified pins, in mA.
182
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
183
-
184
-
Example:
185
-
186
-
tlmm: pinctrl@1010000 {
187
-
compatible = "qcom,msm8996-pinctrl";
188
-
reg = <0x01010000 0x300000>;
189
-
interrupts = <0 208 0>;
190
-
gpio-controller;
191
-
gpio-ranges = <&tlmm 0 0 150>;
192
-
#gpio-cells = <2>;
193
-
interrupt-controller;
194
-
#interrupt-cells = <2>;
195
-
196
-
uart_console_active: uart_console_active {
197
-
mux {
198
-
pins = "gpio4", "gpio5";
199
-
function = "blsp_uart8";
200
-
};
201
-
202
-
config {
203
-
pins = "gpio4", "gpio5";
204
-
drive-strength = <2>;
205
-
bias-disable;
206
-
};
207
-
};
208
-
};
+182
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml
+182
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8996-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8996 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8996 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8996-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 75
34
+
35
+
gpio-line-names:
36
+
maxItems: 150
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8996-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8996-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8996-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
oneOf:
62
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
63
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
64
+
sdc2_cmd, sdc2_data ]
65
+
minItems: 1
66
+
maxItems: 36
67
+
68
+
function:
69
+
description:
70
+
Specify the alternative function to be configured for the specified
71
+
pins.
72
+
73
+
enum: [ gpio, blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
74
+
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
75
+
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
76
+
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
77
+
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
78
+
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
79
+
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio,
80
+
atest_char, cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8,
81
+
qdss_tracedata_b, pll_reset, qdss_stm6, qdss_stm5, qdss_stm4,
82
+
atest_usb2, cci_i2c, qdss_stm3, dac_calib3, atest_usb23,
83
+
atest_char3, dac_calib4, qdss_stm2, atest_usb22, atest_char2,
84
+
qdss_stm1, dac_calib5, atest_usb21, atest_char1, dbg_out,
85
+
qdss_stm0, dac_calib6, atest_usb20, atest_char0, dac_calib10,
86
+
qdss_stm10, qdss_cti_trig_in_a, cci_timer4, blsp_spi6,
87
+
blsp_uart6, blsp_uim6, blsp2_spi, qdss_stm9,
88
+
qdss_cti_trig_out_a, dac_calib11, qdss_stm8, cci_timer0,
89
+
qdss_stm13, dac_calib7, cci_timer1, qdss_stm12, dac_calib8,
90
+
cci_timer2, blsp1_spi, qdss_stm11, dac_calib9, cci_timer3,
91
+
cci_async, dac_calib12, blsp_i2c6, qdss_tracectl_a,
92
+
dac_calib13, qdss_traceclk_a, dac_calib14, dac_calib15,
93
+
hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, dac_calib17,
94
+
hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, dac_calib19,
95
+
hdmi_hot, dac_calib20, dac_calib21, pci_e0, dac_calib22,
96
+
dac_calib23, dac_calib24, tsif1_sync, dac_calib25, sd_write,
97
+
tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti,
98
+
blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, uim3,
99
+
blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
100
+
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
101
+
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11,
102
+
blsp_uart11, blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a,
103
+
blsp_i2c11, cri_trng0, cri_trng1, cri_trng, qdss_stm18,
104
+
pri_mi2s, qdss_stm17, blsp_spi4, blsp_uart4, blsp_uim4,
105
+
qdss_stm16, qdss_stm15, blsp_i2c4, qdss_stm14, dac_calib26,
106
+
spkr_i2s, audio_ref, lpass_slimbus, isense_dbg, tsense_pwm1,
107
+
tsense_pwm2, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_stm21,
108
+
qdss_stm20, qdss_stm19, gcc_gp1_clk_b, sec_mi2s, blsp_spi5,
109
+
blsp_uart5, blsp_uim5, gcc_gp2_clk_b, gcc_gp3_clk_b, blsp_i2c5,
110
+
blsp_spi12, blsp_uart12, blsp_uim12, qdss_stm25, qdss_stm31,
111
+
blsp_i2c12, qdss_stm30, qdss_stm29, tsif1_clk, qdss_stm28,
112
+
tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b,
113
+
tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, sdc4_clk,
114
+
qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
115
+
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
116
+
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b,
117
+
blsp11_uart_rx_b, blsp11_i2c_sda_b, prng_rosc,
118
+
blsp11_i2c_scl_b, uim2, uim1, uim_batt, pci_e2, pa_indicator,
119
+
adsp_ext, ddr_bist, qdss_tracedata_11, qdss_tracedata_12,
120
+
modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, qspi_cs, ssbi2,
121
+
ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3 ]
122
+
123
+
bias-pull-down: true
124
+
bias-pull-up: true
125
+
bias-disable: true
126
+
drive-strength: true
127
+
input-enable: true
128
+
output-high: true
129
+
output-low: true
130
+
131
+
required:
132
+
- pins
133
+
134
+
additionalProperties: false
135
+
136
+
allOf:
137
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
138
+
139
+
required:
140
+
- compatible
141
+
- reg
142
+
143
+
additionalProperties: false
144
+
145
+
examples:
146
+
- |
147
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
148
+
149
+
tlmm: pinctrl@1010000 {
150
+
compatible = "qcom,msm8996-pinctrl";
151
+
reg = <0x01010000 0x300000>;
152
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
153
+
gpio-controller;
154
+
gpio-ranges = <&tlmm 0 0 150>;
155
+
#gpio-cells = <2>;
156
+
interrupt-controller;
157
+
#interrupt-cells = <2>;
158
+
159
+
blsp1-spi1-default-state {
160
+
spi-pins {
161
+
pins = "gpio0", "gpio1", "gpio3";
162
+
function = "blsp_spi1";
163
+
drive-strength = <12>;
164
+
bias-disable;
165
+
};
166
+
167
+
cs-pins {
168
+
pins = "gpio2";
169
+
function = "gpio";
170
+
drive-strength = <16>;
171
+
bias-disable;
172
+
output-high;
173
+
};
174
+
};
175
+
176
+
blsp1-spi1-sleep-state {
177
+
pins = "gpio0", "gpio1", "gpio2", "gpio3";
178
+
function = "gpio";
179
+
drive-strength = <2>;
180
+
bias-pull-down;
181
+
};
182
+
};
-202
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
-202
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
···
1
-
Qualcomm MSM8998 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
MSM8998 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,msm8998-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
- gpio-ranges:
44
-
Usage: required
45
-
Definition: see ../gpio/gpio.txt
46
-
47
-
- gpio-reserved-ranges:
48
-
Usage: optional
49
-
Definition: see ../gpio/gpio.txt
50
-
51
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52
-
a general description of GPIO and interrupt bindings.
53
-
54
-
Please refer to pinctrl-bindings.txt in this directory for details of the
55
-
common pinctrl bindings used by client devices, including the meaning of the
56
-
phrase "pin configuration node".
57
-
58
-
The pin configuration nodes act as a container for an arbitrary number of
59
-
subnodes. Each of these subnodes represents some desired configuration for a
60
-
pin, a group, or a list of pins or groups. This configuration can include the
61
-
mux function to select on those pin(s)/group(s), and various pin configuration
62
-
parameters, such as pull-up, drive strength, etc.
63
-
64
-
65
-
PIN CONFIGURATION NODES:
66
-
67
-
The name of each subnode is not important; all subnodes should be enumerated
68
-
and processed purely based on their content.
69
-
70
-
Each subnode only affects those parameters that are explicitly listed. In
71
-
other words, a subnode that lists a mux function but no pin configuration
72
-
parameters implies no information about any pin configuration parameters.
73
-
Similarly, a pin subnode that describes a pullup parameter implies no
74
-
information about e.g. the mux function.
75
-
76
-
77
-
The following generic properties as defined in pinctrl-bindings.txt are valid
78
-
to specify in a pin configuration subnode:
79
-
80
-
- pins:
81
-
Usage: required
82
-
Value type: <string-array>
83
-
Definition: List of gpio pins affected by the properties specified in
84
-
this subnode.
85
-
86
-
Valid pins are:
87
-
gpio0-gpio149
88
-
Supports mux, bias and drive-strength
89
-
90
-
sdc2_clk, sdc2_cmd, sdc2_data
91
-
Supports bias and drive-strength
92
-
93
-
ufs_reset
94
-
Supports bias and drive-strength
95
-
96
-
- function:
97
-
Usage: required
98
-
Value type: <string>
99
-
Definition: Specify the alternative function to be configured for the
100
-
specified pins. Functions are only valid for gpio pins.
101
-
Valid values are:
102
-
103
-
gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
104
-
atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
105
-
atest_usb10, atest_usb11, atest_usb12, atest_usb13,
106
-
audio_ref, bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a,
107
-
blsp10_spi_b, blsp11_i2c, blsp1_spi, blsp1_spi_a,
108
-
blsp1_spi_b, blsp2_spi, blsp9_spi, blsp_i2c1, blsp_i2c2,
109
-
blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
110
-
blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
111
-
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
112
-
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
113
-
blsp_spi11, blsp_spi12, blsp_uart1_a, blsp_uart1_b,
114
-
blsp_uart2_a, blsp_uart2_b, blsp_uart3_a, blsp_uart3_b,
115
-
blsp_uart7_a, blsp_uart7_b, blsp_uart8, blsp_uart8_a,
116
-
blsp_uart8_b, blsp_uart9_a, blsp_uart9_b, blsp_uim1_a,
117
-
blsp_uim1_b, blsp_uim2_a, blsp_uim2_b, blsp_uim3_a,
118
-
blsp_uim3_b, blsp_uim7_a, blsp_uim7_b, blsp_uim8_a,
119
-
blsp_uim8_b, blsp_uim9_a, blsp_uim9_b, bt_reset,
120
-
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
121
-
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
122
-
cri_trng0, cri_trng1, dbg_out, ddr_bist, edp_hot, edp_lcd,
123
-
gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, gcc_gp3_a,
124
-
gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
125
-
isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
126
-
m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
127
-
mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
128
-
nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
129
-
pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
130
-
pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
131
-
qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable,
132
-
qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
133
-
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
134
-
spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
135
-
tsense_pwm1, tsense_pwm2, tsif0, tsif1,
136
-
uim1_clk, uim1_data, uim1_present,
137
-
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
138
-
uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
139
-
vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
140
-
wlan2_adc0, wlan2_adc1,
141
-
142
-
- bias-disable:
143
-
Usage: optional
144
-
Value type: <none>
145
-
Definition: The specified pins should be configured as no pull.
146
-
147
-
- bias-pull-down:
148
-
Usage: optional
149
-
Value type: <none>
150
-
Definition: The specified pins should be configured as pull down.
151
-
152
-
- bias-pull-up:
153
-
Usage: optional
154
-
Value type: <none>
155
-
Definition: The specified pins should be configured as pull up.
156
-
157
-
- output-high:
158
-
Usage: optional
159
-
Value type: <none>
160
-
Definition: The specified pins are configured in output mode, driven
161
-
high.
162
-
Not valid for sdc pins.
163
-
164
-
- output-low:
165
-
Usage: optional
166
-
Value type: <none>
167
-
Definition: The specified pins are configured in output mode, driven
168
-
low.
169
-
Not valid for sdc pins.
170
-
171
-
- drive-strength:
172
-
Usage: optional
173
-
Value type: <u32>
174
-
Definition: Selects the drive strength for the specified pins, in mA.
175
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
176
-
177
-
Example:
178
-
179
-
tlmm: pinctrl@03400000 {
180
-
compatible = "qcom,msm8998-pinctrl";
181
-
reg = <0x03400000 0xc00000>;
182
-
interrupts = <0 208 0>;
183
-
gpio-controller;
184
-
#gpio-cells = <2>;
185
-
gpio-ranges = <&tlmm 0 0 175>;
186
-
gpio-reserved-ranges = <0 4>, <81 4>;
187
-
interrupt-controller;
188
-
#interrupt-cells = <2>;
189
-
190
-
uart_console_active: uart_console_active {
191
-
mux {
192
-
pins = "gpio4", "gpio5";
193
-
function = "blsp_uart8_a";
194
-
};
195
-
196
-
config {
197
-
pins = "gpio4", "gpio5";
198
-
drive-strength = <2>;
199
-
bias-disable;
200
-
};
201
-
};
202
-
};
+171
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml
+171
Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8998-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8998 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm MSM8998 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,msm8998-pinctrl
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts: true
24
+
interrupt-controller: true
25
+
"#interrupt-cells": true
26
+
gpio-controller: true
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
29
+
wakeup-parent: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 75
34
+
35
+
gpio-line-names:
36
+
maxItems: 150
37
+
38
+
patternProperties:
39
+
"-state$":
40
+
oneOf:
41
+
- $ref: "#/$defs/qcom-msm8998-tlmm-state"
42
+
- patternProperties:
43
+
"-pins$":
44
+
$ref: "#/$defs/qcom-msm8998-tlmm-state"
45
+
additionalProperties: false
46
+
47
+
$defs:
48
+
qcom-msm8998-tlmm-state:
49
+
type: object
50
+
description:
51
+
Pinctrl node's client devices use subnodes for desired pin configuration.
52
+
Client device subnodes use below standard properties.
53
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
54
+
55
+
properties:
56
+
pins:
57
+
description:
58
+
List of gpio pins affected by the properties specified in this
59
+
subnode.
60
+
items:
61
+
oneOf:
62
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
63
+
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
64
+
minItems: 1
65
+
maxItems: 36
66
+
67
+
function:
68
+
description:
69
+
Specify the alternative function to be configured for the specified
70
+
pins.
71
+
72
+
enum: [ gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
73
+
atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
74
+
atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref,
75
+
bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b,
76
+
blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi,
77
+
blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
78
+
blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9,
79
+
blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2,
80
+
blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
81
+
blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12,
82
+
blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b,
83
+
blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b,
84
+
blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a,
85
+
blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a,
86
+
blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a,
87
+
blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a,
88
+
blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async,
89
+
cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
90
+
cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
91
+
edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b,
92
+
gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
93
+
isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
94
+
m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
95
+
mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
96
+
nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
97
+
pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
98
+
pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
99
+
qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request,
100
+
qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43,
101
+
sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq,
102
+
ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0,
103
+
tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
104
+
uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
105
+
vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
106
+
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
107
+
108
+
bias-pull-down: true
109
+
bias-pull-up: true
110
+
bias-disable: true
111
+
drive-strength: true
112
+
input-enable: true
113
+
output-high: true
114
+
output-low: true
115
+
116
+
required:
117
+
- pins
118
+
119
+
additionalProperties: false
120
+
121
+
allOf:
122
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
123
+
124
+
required:
125
+
- compatible
126
+
- reg
127
+
128
+
additionalProperties: false
129
+
130
+
examples:
131
+
- |
132
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
133
+
134
+
tlmm: pinctrl@3400000 {
135
+
compatible = "qcom,msm8998-pinctrl";
136
+
reg = <0x03400000 0xc00000>;
137
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
138
+
gpio-ranges = <&tlmm 0 0 150>;
139
+
gpio-controller;
140
+
#gpio-cells = <2>;
141
+
interrupt-controller;
142
+
#interrupt-cells = <2>;
143
+
gpio-reserved-ranges = <0 4>, <81 4>;
144
+
145
+
sdc2-off-state {
146
+
clk-pins {
147
+
pins = "sdc2_clk";
148
+
drive-strength = <2>;
149
+
bias-disable;
150
+
};
151
+
152
+
cmd-pins {
153
+
pins = "sdc2_cmd";
154
+
drive-strength = <2>;
155
+
bias-pull-up;
156
+
};
157
+
158
+
data-pins {
159
+
pins = "sdc2_data";
160
+
drive-strength = <2>;
161
+
bias-pull-up;
162
+
};
163
+
};
164
+
165
+
sdc2-cd-state {
166
+
pins = "gpio95";
167
+
function = "gpio";
168
+
bias-pull-up;
169
+
drive-strength = <2>;
170
+
};
171
+
};
+23
-22
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
+23
-22
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml
···
15
15
16
16
properties:
17
17
compatible:
18
-
items:
19
-
- enum:
20
-
- qcom,pm8018-mpp
21
-
- qcom,pm8019-mpp
22
-
- qcom,pm8038-mpp
23
-
- qcom,pm8058-mpp
24
-
- qcom,pm8226-mpp
25
-
- qcom,pm8821-mpp
26
-
- qcom,pm8841-mpp
27
-
- qcom,pm8916-mpp
28
-
- qcom,pm8917-mpp
29
-
- qcom,pm8921-mpp
30
-
- qcom,pm8941-mpp
31
-
- qcom,pm8950-mpp
32
-
- qcom,pmi8950-mpp
33
-
- qcom,pm8994-mpp
34
-
- qcom,pma8084-mpp
35
-
- qcom,pmi8994-mpp
36
-
37
-
- enum:
38
-
- qcom,spmi-mpp
39
-
- qcom,ssbi-mpp
18
+
oneOf:
19
+
- items:
20
+
- enum:
21
+
- qcom,pm8019-mpp
22
+
- qcom,pm8226-mpp
23
+
- qcom,pm8841-mpp
24
+
- qcom,pm8916-mpp
25
+
- qcom,pm8941-mpp
26
+
- qcom,pm8950-mpp
27
+
- qcom,pmi8950-mpp
28
+
- qcom,pm8994-mpp
29
+
- qcom,pma8084-mpp
30
+
- qcom,pmi8994-mpp
31
+
- const: qcom,spmi-mpp
32
+
- items:
33
+
- enum:
34
+
- qcom,pm8018-mpp
35
+
- qcom,pm8038-mpp
36
+
- qcom,pm8058-mpp
37
+
- qcom,pm8821-mpp
38
+
- qcom,pm8917-mpp
39
+
- qcom,pm8921-mpp
40
+
- const: qcom,ssbi-mpp
40
41
41
42
reg:
42
43
maxItems: 1
+16
-48
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml
+16
-48
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. QCM2290 TLMM block
···
10
10
- Shawn Guo <shawn.guo@linaro.org>
11
11
12
12
description:
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
QCM2290 platform.
13
+
Top Level Mode Multiplexer pin controller in Qualcomm QCM2290 SoC.
15
14
16
15
properties:
17
16
compatible:
···
19
20
reg:
20
21
maxItems: 1
21
22
22
-
interrupts:
23
-
description: Specifies the TLMM summary IRQ
24
-
maxItems: 1
25
-
23
+
interrupts: true
26
24
interrupt-controller: true
27
-
28
-
'#interrupt-cells':
29
-
description:
30
-
Specifies the PIN numbers and Flags, as defined in defined in
31
-
include/dt-bindings/interrupt-controller/irq.h
32
-
const: 2
33
-
25
+
"#interrupt-cells": true
34
26
gpio-controller: true
35
-
36
-
'#gpio-cells':
37
-
description: Specifying the pin number and flags, as defined in
38
-
include/dt-bindings/gpio/gpio.h
39
-
const: 2
40
-
41
-
gpio-ranges:
42
-
maxItems: 1
43
-
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
44
29
wakeup-parent: true
45
30
46
-
#PIN CONFIGURATION NODES
47
31
patternProperties:
48
-
'-state$':
32
+
"-state$":
49
33
oneOf:
50
34
- $ref: "#/$defs/qcom-qcm2290-tlmm-state"
51
35
- patternProperties:
52
-
".*":
36
+
"-pins$":
53
37
$ref: "#/$defs/qcom-qcm2290-tlmm-state"
38
+
additionalProperties: false
54
39
55
-
'$defs':
40
+
$defs:
56
41
qcom-qcm2290-tlmm-state:
57
42
type: object
58
43
description:
59
44
Pinctrl node's client devices use subnodes for desired pin configuration.
60
45
Client device subnodes use below standard properties.
61
-
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
46
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
62
47
63
48
properties:
64
49
pins:
···
79
96
uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1,
80
97
vsense_trigger, wlan1_adc0, wlan1_adc1 ]
81
98
82
-
drive-strength:
83
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
84
-
default: 2
85
-
description:
86
-
Selects the drive strength for the specified pins, in mA.
87
-
88
99
bias-pull-down: true
89
-
90
100
bias-pull-up: true
91
-
92
101
bias-disable: true
93
-
102
+
drive-strength: true
94
103
output-high: true
95
-
96
104
output-low: true
97
105
98
106
required:
···
92
118
additionalProperties: false
93
119
94
120
allOf:
95
-
- $ref: "pinctrl.yaml#"
121
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
96
122
97
123
required:
98
124
- compatible
99
125
- reg
100
-
- interrupts
101
-
- interrupt-controller
102
-
- '#interrupt-cells'
103
-
- gpio-controller
104
-
- '#gpio-cells'
105
-
- gpio-ranges
106
126
107
127
additionalProperties: false
108
128
···
114
146
gpio-ranges = <&tlmm 0 0 127>;
115
147
116
148
sdc2_on_state: sdc2-on-state {
117
-
clk {
149
+
clk-pins {
118
150
pins = "sdc2_clk";
119
151
bias-disable;
120
152
drive-strength = <16>;
121
153
};
122
154
123
-
cmd {
155
+
cmd-pins {
124
156
pins = "sdc2_cmd";
125
157
bias-pull-up;
126
158
drive-strength = <10>;
127
159
};
128
160
129
-
data {
161
+
data-pins {
130
162
pins = "sdc2_data";
131
163
bias-pull-up;
132
164
drive-strength = <10>;
-199
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt
-199
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt
···
1
-
Qualcomm QCS404 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
QCS404 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,qcs404-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the north, south and east TLMM
15
-
tiles.
16
-
17
-
- reg-names:
18
-
Usage: required
19
-
Value type: <stringlist>
20
-
Defintiion: names for the cells of reg, must contain "north", "south"
21
-
and "east".
22
-
23
-
- interrupts:
24
-
Usage: required
25
-
Value type: <prop-encoded-array>
26
-
Definition: should specify the TLMM summary IRQ.
27
-
28
-
- interrupt-controller:
29
-
Usage: required
30
-
Value type: <none>
31
-
Definition: identifies this node as an interrupt controller
32
-
33
-
- #interrupt-cells:
34
-
Usage: required
35
-
Value type: <u32>
36
-
Definition: must be 2. Specifying the pin number and flags, as defined
37
-
in <dt-bindings/interrupt-controller/irq.h>
38
-
39
-
- gpio-controller:
40
-
Usage: required
41
-
Value type: <none>
42
-
Definition: identifies this node as a gpio controller
43
-
44
-
- #gpio-cells:
45
-
Usage: required
46
-
Value type: <u32>
47
-
Definition: must be 2. Specifying the pin number and flags, as defined
48
-
in <dt-bindings/gpio/gpio.h>
49
-
50
-
- gpio-ranges:
51
-
Usage: required
52
-
Definition: see ../gpio/gpio.txt
53
-
54
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
55
-
a general description of GPIO and interrupt bindings.
56
-
57
-
Please refer to pinctrl-bindings.txt in this directory for details of the
58
-
common pinctrl bindings used by client devices, including the meaning of the
59
-
phrase "pin configuration node".
60
-
61
-
The pin configuration nodes act as a container for an arbitrary number of
62
-
subnodes. Each of these subnodes represents some desired configuration for a
63
-
pin, a group, or a list of pins or groups. This configuration can include the
64
-
mux function to select on those pin(s)/group(s), and various pin configuration
65
-
parameters, such as pull-up, drive strength, etc.
66
-
67
-
68
-
PIN CONFIGURATION NODES:
69
-
70
-
The name of each subnode is not important; all subnodes should be enumerated
71
-
and processed purely based on their content.
72
-
73
-
Each subnode only affects those parameters that are explicitly listed. In
74
-
other words, a subnode that lists a mux function but no pin configuration
75
-
parameters implies no information about any pin configuration parameters.
76
-
Similarly, a pin subnode that describes a pullup parameter implies no
77
-
information about e.g. the mux function.
78
-
79
-
80
-
The following generic properties as defined in pinctrl-bindings.txt are valid
81
-
to specify in a pin configuration subnode:
82
-
83
-
- pins:
84
-
Usage: required
85
-
Value type: <string-array>
86
-
Definition: List of gpio pins affected by the properties specified in
87
-
this subnode.
88
-
89
-
Valid pins are:
90
-
gpio0-gpio119
91
-
Supports mux, bias and drive-strength
92
-
93
-
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
94
-
sdc2_data
95
-
Supports bias and drive-strength
96
-
97
-
ufs_reset
98
-
Supports bias and drive-strength
99
-
100
-
- function:
101
-
Usage: required
102
-
Value type: <string>
103
-
Definition: Specify the alternative function to be configured for the
104
-
specified pins. Functions are only valid for gpio pins.
105
-
Valid values are:
106
-
107
-
gpio, hdmi_tx, hdmi_ddc, blsp_uart_tx_a2, blsp_spi2, m_voc,
108
-
qdss_cti_trig_in_a0, blsp_uart_rx_a2, qdss_tracectl_a,
109
-
blsp_uart2, aud_cdc, blsp_i2c_sda_a2, qdss_tracedata_a,
110
-
blsp_i2c_scl_a2, qdss_tracectl_b, qdss_cti_trig_in_b0,
111
-
blsp_uart1, blsp_spi_mosi_a1, blsp_spi_miso_a1,
112
-
qdss_tracedata_b, blsp_i2c1, blsp_spi_cs_n_a1, gcc_plltest,
113
-
blsp_spi_clk_a1, rgb_data0, blsp_uart5, blsp_spi5,
114
-
adsp_ext, rgb_data1, prng_rosc, rgb_data2, blsp_i2c5,
115
-
gcc_gp1_clk_b, rgb_data3, gcc_gp2_clk_b, blsp_spi0,
116
-
blsp_uart0, gcc_gp3_clk_b, blsp_i2c0, qdss_traceclk_b,
117
-
pcie_clk, nfc_irq, blsp_spi4, nfc_dwl, audio_ts, rgb_data4,
118
-
spi_lcd, blsp_uart_tx_b2, gcc_gp3_clk_a, rgb_data5,
119
-
blsp_uart_rx_b2, blsp_i2c_sda_b2, blsp_i2c_scl_b2,
120
-
pwm_led11, i2s_3_data0_a, ebi2_lcd, i2s_3_data1_a,
121
-
i2s_3_data2_a, atest_char, pwm_led3, i2s_3_data3_a,
122
-
pwm_led4, i2s_4, ebi2_a, dsd_clk_b, pwm_led5, pwm_led6,
123
-
pwm_led7, pwm_led8, pwm_led24, spkr_dac0, blsp_i2c4,
124
-
pwm_led9, pwm_led10, spdifrx_opt, pwm_led12, pwm_led13,
125
-
pwm_led14, wlan1_adc1, rgb_data_b0, pwm_led15,
126
-
blsp_spi_mosi_b1, wlan1_adc0, rgb_data_b1, pwm_led16,
127
-
blsp_spi_miso_b1, qdss_cti_trig_out_b0, wlan2_adc1,
128
-
rgb_data_b2, pwm_led17, blsp_spi_cs_n_b1, wlan2_adc0,
129
-
rgb_data_b3, pwm_led18, blsp_spi_clk_b1, rgb_data_b4,
130
-
pwm_led19, ext_mclk1_b, qdss_traceclk_a, rgb_data_b5,
131
-
pwm_led20, atest_char3, i2s_3_sck_b, ldo_update, bimc_dte0,
132
-
rgb_hsync, pwm_led21, i2s_3_ws_b, dbg_out, rgb_vsync,
133
-
i2s_3_data0_b, ldo_en, hdmi_dtest, rgb_de, i2s_3_data1_b,
134
-
hdmi_lbk9, rgb_clk, atest_char1, i2s_3_data2_b, ebi_cdc,
135
-
hdmi_lbk8, rgb_mdp, atest_char0, i2s_3_data3_b, hdmi_lbk7,
136
-
rgb_data_b6, rgb_data_b7, hdmi_lbk6, rgmii_int, cri_trng1,
137
-
rgmii_wol, cri_trng0, gcc_tlmm, rgmii_ck, rgmii_tx,
138
-
hdmi_lbk5, hdmi_pixel, hdmi_rcv, hdmi_lbk4, rgmii_ctl,
139
-
ext_lpass, rgmii_rx, cri_trng, hdmi_lbk3, hdmi_lbk2,
140
-
qdss_cti_trig_out_b1, rgmii_mdio, hdmi_lbk1, rgmii_mdc,
141
-
hdmi_lbk0, ir_in, wsa_en, rgb_data6, rgb_data7,
142
-
atest_char2, ebi_ch0, blsp_uart3, blsp_spi3, sd_write,
143
-
blsp_i2c3, gcc_gp1_clk_a, qdss_cti_trig_in_b1,
144
-
gcc_gp2_clk_a, ext_mclk0, mclk_in1, i2s_1, dsd_clk_a,
145
-
qdss_cti_trig_in_a1, rgmi_dll1, pwm_led22, pwm_led23,
146
-
qdss_cti_trig_out_a0, rgmi_dll2, pwm_led1,
147
-
qdss_cti_trig_out_a1, pwm_led2, i2s_2, pll_bist,
148
-
ext_mclk1_a, mclk_in2, bimc_dte1, i2s_3_sck_a, i2s_3_ws_a
149
-
150
-
- bias-disable:
151
-
Usage: optional
152
-
Value type: <none>
153
-
Definition: The specified pins should be configured as no pull.
154
-
155
-
- bias-pull-down:
156
-
Usage: optional
157
-
Value type: <none>
158
-
Definition: The specified pins should be configured as pull down.
159
-
160
-
- bias-pull-up:
161
-
Usage: optional
162
-
Value type: <none>
163
-
Definition: The specified pins should be configured as pull up.
164
-
165
-
- output-high:
166
-
Usage: optional
167
-
Value type: <none>
168
-
Definition: The specified pins are configured in output mode, driven
169
-
high.
170
-
Not valid for sdc pins.
171
-
172
-
- output-low:
173
-
Usage: optional
174
-
Value type: <none>
175
-
Definition: The specified pins are configured in output mode, driven
176
-
low.
177
-
Not valid for sdc pins.
178
-
179
-
- drive-strength:
180
-
Usage: optional
181
-
Value type: <u32>
182
-
Definition: Selects the drive strength for the specified pins, in mA.
183
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
184
-
185
-
Example:
186
-
187
-
tlmm: pinctrl@1000000 {
188
-
compatible = "qcom,qcs404-pinctrl";
189
-
reg = <0x01000000 0x200000>,
190
-
<0x01300000 0x200000>,
191
-
<0x07b00000 0x200000>;
192
-
reg-names = "south", "north", "east";
193
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
194
-
gpio-controller;
195
-
#gpio-cells = <2>;
196
-
gpio-ranges = <&tlmm 0 0 120>;
197
-
interrupt-controller;
198
-
#interrupt-cells = <2>;
199
-
};
+176
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml
+176
Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm QCS404 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,qcs404-pinctrl
19
+
20
+
reg:
21
+
maxItems: 3
22
+
23
+
reg-names:
24
+
items:
25
+
- const: south
26
+
- const: north
27
+
- const: east
28
+
29
+
interrupts: true
30
+
interrupt-controller: true
31
+
"#interrupt-cells": true
32
+
gpio-controller: true
33
+
"#gpio-cells": true
34
+
gpio-ranges: true
35
+
wakeup-parent: true
36
+
37
+
gpio-reserved-ranges:
38
+
minItems: 1
39
+
maxItems: 60
40
+
41
+
gpio-line-names:
42
+
maxItems: 120
43
+
44
+
patternProperties:
45
+
"-state$":
46
+
oneOf:
47
+
- $ref: "#/$defs/qcom-qcs404-tlmm-state"
48
+
- patternProperties:
49
+
"-pins$":
50
+
$ref: "#/$defs/qcom-qcs404-tlmm-state"
51
+
additionalProperties: false
52
+
53
+
$defs:
54
+
qcom-qcs404-tlmm-state:
55
+
type: object
56
+
description:
57
+
Pinctrl node's client devices use subnodes for desired pin configuration.
58
+
Client device subnodes use below standard properties.
59
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
60
+
61
+
properties:
62
+
pins:
63
+
description:
64
+
List of gpio pins affected by the properties specified in this
65
+
subnode.
66
+
items:
67
+
oneOf:
68
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$"
69
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
70
+
sdc2_cmd, sdc2_data, ufs_reset ]
71
+
minItems: 1
72
+
maxItems: 36
73
+
74
+
function:
75
+
description:
76
+
Specify the alternative function to be configured for the specified
77
+
pins.
78
+
79
+
enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1,
80
+
atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0,
81
+
bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4,
82
+
blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2,
83
+
blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4,
84
+
blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1,
85
+
blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1,
86
+
blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1,
87
+
blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2,
88
+
blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng,
89
+
cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a,
90
+
ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a,
91
+
ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
92
+
gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest,
93
+
gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1,
94
+
hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6,
95
+
hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx,
96
+
i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a,
97
+
i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a,
98
+
i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a,
99
+
i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1,
100
+
mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist,
101
+
prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12,
102
+
pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17,
103
+
pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21,
104
+
pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5,
105
+
pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0,
106
+
qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
107
+
qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
108
+
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
109
+
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
110
+
qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0,
111
+
rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5,
112
+
rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2,
113
+
rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6,
114
+
rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1,
115
+
rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc,
116
+
rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write,
117
+
spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1,
118
+
wlan2_adc0, wlan2_adc1, wsa_en ]
119
+
120
+
bias-pull-down: true
121
+
bias-pull-up: true
122
+
bias-disable: true
123
+
drive-strength: true
124
+
input-enable: true
125
+
output-high: true
126
+
output-low: true
127
+
128
+
required:
129
+
- pins
130
+
131
+
additionalProperties: false
132
+
133
+
allOf:
134
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
135
+
136
+
required:
137
+
- compatible
138
+
- reg
139
+
140
+
additionalProperties: false
141
+
142
+
examples:
143
+
- |
144
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
145
+
146
+
tlmm: pinctrl@1000000 {
147
+
compatible = "qcom,qcs404-pinctrl";
148
+
reg = <0x01000000 0x200000>,
149
+
<0x01300000 0x200000>,
150
+
<0x07b00000 0x200000>;
151
+
reg-names = "south", "north", "east";
152
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
153
+
gpio-ranges = <&tlmm 0 0 120>;
154
+
gpio-controller;
155
+
#gpio-cells = <2>;
156
+
interrupt-controller;
157
+
#interrupt-cells = <2>;
158
+
159
+
160
+
blsp1-i2c1-default-state {
161
+
pins = "gpio24", "gpio25";
162
+
function = "blsp_i2c1";
163
+
};
164
+
165
+
blsp1-i2c2-default-state {
166
+
sda-pins {
167
+
pins = "gpio19";
168
+
function = "blsp_i2c_sda_a2";
169
+
};
170
+
171
+
scl-pins {
172
+
pins = "gpio20";
173
+
function = "blsp_i2c_scl_a2";
174
+
};
175
+
};
176
+
};
-187
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
-187
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
···
1
-
Qualcomm Technologies, Inc. SC7180 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
SC7180 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,sc7180-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the north, south and west
15
-
TLMM tiles
16
-
17
-
- reg-names:
18
-
Usage: required
19
-
Value type: <prop-encoded-array>
20
-
Definition: names for the cells of reg, must contain "north", "south"
21
-
and "west".
22
-
23
-
- interrupts:
24
-
Usage: required
25
-
Value type: <prop-encoded-array>
26
-
Definition: should specify the TLMM summary IRQ.
27
-
28
-
- interrupt-controller:
29
-
Usage: required
30
-
Value type: <none>
31
-
Definition: identifies this node as an interrupt controller
32
-
33
-
- #interrupt-cells:
34
-
Usage: required
35
-
Value type: <u32>
36
-
Definition: must be 2. Specifying the pin number and flags, as defined
37
-
in <dt-bindings/interrupt-controller/irq.h>
38
-
39
-
- gpio-controller:
40
-
Usage: required
41
-
Value type: <none>
42
-
Definition: identifies this node as a gpio controller
43
-
44
-
- #gpio-cells:
45
-
Usage: required
46
-
Value type: <u32>
47
-
Definition: must be 2. Specifying the pin number and flags, as defined
48
-
in <dt-bindings/gpio/gpio.h>
49
-
50
-
- gpio-ranges:
51
-
Usage: required
52
-
Value type: <prop-encoded-array>
53
-
Definition: see ../gpio/gpio.txt
54
-
55
-
- gpio-reserved-ranges:
56
-
Usage: optional
57
-
Value type: <prop-encoded-array>
58
-
Definition: see ../gpio/gpio.txt
59
-
60
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
61
-
a general description of GPIO and interrupt bindings.
62
-
63
-
Please refer to pinctrl-bindings.txt in this directory for details of the
64
-
common pinctrl bindings used by client devices, including the meaning of the
65
-
phrase "pin configuration node".
66
-
67
-
The pin configuration nodes act as a container for an arbitrary number of
68
-
subnodes. Each of these subnodes represents some desired configuration for a
69
-
pin, a group, or a list of pins or groups. This configuration can include the
70
-
mux function to select on those pin(s)/group(s), and various pin configuration
71
-
parameters, such as pull-up, drive strength, etc.
72
-
73
-
74
-
PIN CONFIGURATION NODES:
75
-
76
-
The name of each subnode is not important; all subnodes should be enumerated
77
-
and processed purely based on their content.
78
-
79
-
Each subnode only affects those parameters that are explicitly listed. In
80
-
other words, a subnode that lists a mux function but no pin configuration
81
-
parameters implies no information about any pin configuration parameters.
82
-
Similarly, a pin subnode that describes a pullup parameter implies no
83
-
information about e.g. the mux function.
84
-
85
-
86
-
The following generic properties as defined in pinctrl-bindings.txt are valid
87
-
to specify in a pin configuration subnode:
88
-
89
-
- pins:
90
-
Usage: required
91
-
Value type: <string-array>
92
-
Definition: List of gpio pins affected by the properties specified in
93
-
this subnode.
94
-
95
-
Valid pins are:
96
-
gpio0-gpio118
97
-
Supports mux, bias and drive-strength
98
-
99
-
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
100
-
sdc2_data sdc1_rclk
101
-
Supports bias and drive-strength
102
-
103
-
ufs_reset
104
-
Supports bias and drive-strength
105
-
106
-
- function:
107
-
Usage: required
108
-
Value type: <string>
109
-
Definition: Specify the alternative function to be configured for the
110
-
specified pins. Functions are only valid for gpio pins.
111
-
Valid values are:
112
-
113
-
adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
114
-
atest_char1, atest_char2, atest_char3, atest_tsens,
115
-
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
116
-
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
117
-
atest_usb21, atest_usb22, atest_usb23, audio_ref,
118
-
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
119
-
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
120
-
cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
121
-
ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2,
122
-
gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
123
-
jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
124
-
mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0,
125
-
mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
126
-
PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
127
-
qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
128
-
qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,
129
-
qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,
130
-
qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,
131
-
sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
132
-
tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
133
-
usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
134
-
vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
135
-
wlan2_adc1,
136
-
137
-
- bias-disable:
138
-
Usage: optional
139
-
Value type: <none>
140
-
Definition: The specified pins should be configured as no pull.
141
-
142
-
- bias-pull-down:
143
-
Usage: optional
144
-
Value type: <none>
145
-
Definition: The specified pins should be configured as pull down.
146
-
147
-
- bias-pull-up:
148
-
Usage: optional
149
-
Value type: <none>
150
-
Definition: The specified pins should be configured as pull up.
151
-
152
-
- output-high:
153
-
Usage: optional
154
-
Value type: <none>
155
-
Definition: The specified pins are configured in output mode, driven
156
-
high.
157
-
Not valid for sdc pins.
158
-
159
-
- output-low:
160
-
Usage: optional
161
-
Value type: <none>
162
-
Definition: The specified pins are configured in output mode, driven
163
-
low.
164
-
Not valid for sdc pins.
165
-
166
-
- drive-strength:
167
-
Usage: optional
168
-
Value type: <u32>
169
-
Definition: Selects the drive strength for the specified pins, in mA.
170
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
171
-
172
-
Example:
173
-
174
-
tlmm: pinctrl@3500000 {
175
-
compatible = "qcom,sc7180-pinctrl";
176
-
reg = <0x3500000 0x300000>,
177
-
<0x3900000 0x300000>,
178
-
<0x3D00000 0x300000>;
179
-
reg-names = "west", "north", "south";
180
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
181
-
gpio-controller;
182
-
#gpio-cells = <2>;
183
-
gpio-ranges = <&tlmm 0 0 119>;
184
-
gpio-reserved-ranges = <0 4>, <106 4>;
185
-
interrupt-controller;
186
-
#interrupt-cells = <2>;
187
-
};
+158
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
+158
Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SC7180 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,sc7180-pinctrl
19
+
20
+
reg:
21
+
maxItems: 3
22
+
23
+
reg-names:
24
+
items:
25
+
- const: west
26
+
- const: north
27
+
- const: south
28
+
29
+
interrupts: true
30
+
interrupt-controller: true
31
+
"#interrupt-cells": true
32
+
gpio-controller: true
33
+
"#gpio-cells": true
34
+
gpio-ranges: true
35
+
wakeup-parent: true
36
+
37
+
gpio-reserved-ranges:
38
+
minItems: 1
39
+
maxItems: 60
40
+
41
+
gpio-line-names:
42
+
maxItems: 119
43
+
44
+
patternProperties:
45
+
"-state$":
46
+
oneOf:
47
+
- $ref: "#/$defs/qcom-sc7180-tlmm-state"
48
+
- patternProperties:
49
+
"-pins$":
50
+
$ref: "#/$defs/qcom-sc7180-tlmm-state"
51
+
additionalProperties: false
52
+
53
+
$defs:
54
+
qcom-sc7180-tlmm-state:
55
+
type: object
56
+
description:
57
+
Pinctrl node's client devices use subnodes for desired pin configuration.
58
+
Client device subnodes use below standard properties.
59
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
60
+
61
+
properties:
62
+
pins:
63
+
description:
64
+
List of gpio pins affected by the properties specified in this
65
+
subnode.
66
+
items:
67
+
oneOf:
68
+
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
69
+
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
70
+
sdc2_cmd, sdc2_data, ufs_reset ]
71
+
minItems: 1
72
+
maxItems: 36
73
+
74
+
function:
75
+
description:
76
+
Specify the alternative function to be configured for the specified
77
+
pins.
78
+
79
+
enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
80
+
atest_char1, atest_char2, atest_char3, atest_tsens,
81
+
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
82
+
atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
83
+
atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
84
+
cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
85
+
cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
86
+
ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
87
+
gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
88
+
jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
89
+
mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
90
+
mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
91
+
pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
92
+
qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
93
+
qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
94
+
qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
95
+
qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
96
+
sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
97
+
tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
98
+
_V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
99
+
wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
100
+
101
+
bias-pull-down: true
102
+
bias-pull-up: true
103
+
bias-disable: true
104
+
drive-strength: true
105
+
input-enable: true
106
+
output-high: true
107
+
output-low: true
108
+
109
+
required:
110
+
- pins
111
+
112
+
additionalProperties: false
113
+
114
+
allOf:
115
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
116
+
117
+
required:
118
+
- compatible
119
+
- reg
120
+
- reg-names
121
+
122
+
additionalProperties: false
123
+
124
+
examples:
125
+
- |
126
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
127
+
128
+
tlmm: pinctrl@3500000 {
129
+
compatible = "qcom,sc7180-pinctrl";
130
+
reg = <0x03500000 0x300000>,
131
+
<0x03900000 0x300000>,
132
+
<0x03d00000 0x300000>;
133
+
reg-names = "west", "north", "south";
134
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
135
+
gpio-controller;
136
+
#gpio-cells = <2>;
137
+
interrupt-controller;
138
+
#interrupt-cells = <2>;
139
+
gpio-ranges = <&tlmm 0 0 120>;
140
+
wakeup-parent = <&pdc>;
141
+
142
+
dp_hot_plug_det: dp-hot-plug-det-state {
143
+
pins = "gpio117";
144
+
function = "dp_hot";
145
+
};
146
+
147
+
qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
148
+
spi-pins {
149
+
pins = "gpio53", "gpio54", "gpio55";
150
+
function = "qup15";
151
+
};
152
+
153
+
cs-pins {
154
+
pins = "gpio56";
155
+
function = "gpio";
156
+
};
157
+
};
158
+
};
+34
-14
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+34
-14
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
···
4
4
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8
-
Low Power Island (LPI) TLMM block
7
+
title: Qualcomm SC7280 SoC LPASS LPI TLMM
9
8
10
9
maintainers:
11
10
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
11
13
-
description: |
14
-
This binding describes the Top Level Mode Multiplexer block found in the
15
-
LPASS LPI IP on most Qualcomm SoCs
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
16
15
17
16
properties:
18
17
compatible:
···
23
24
type: boolean
24
25
25
26
reg:
26
-
minItems: 2
27
27
maxItems: 2
28
28
29
29
gpio-controller: true
30
30
31
-
'#gpio-cells':
31
+
"#gpio-cells":
32
32
description: Specifying the pin number and flags, as defined in
33
33
include/dt-bindings/gpio/gpio.h
34
34
const: 2
···
35
37
gpio-ranges:
36
38
maxItems: 1
37
39
38
-
#PIN CONFIGURATION NODES
39
40
patternProperties:
40
-
'-pins$':
41
+
"-state$":
42
+
oneOf:
43
+
- $ref: "#/$defs/qcom-sc7280-lpass-state"
44
+
- patternProperties:
45
+
"-pins$":
46
+
$ref: "#/$defs/qcom-sc7280-lpass-state"
47
+
additionalProperties: false
48
+
49
+
$defs:
50
+
qcom-sc7280-lpass-state:
41
51
type: object
42
52
description:
43
53
Pinctrl node's client devices use subnodes for desired pin configuration.
···
89
83
3: Reserved (No adjustments)
90
84
91
85
bias-pull-down: true
92
-
93
86
bias-pull-up: true
94
-
87
+
bias-bus-hold: true
95
88
bias-disable: true
96
-
97
89
output-high: true
98
-
99
90
output-low: true
100
91
101
92
required:
···
105
102
- compatible
106
103
- reg
107
104
- gpio-controller
108
-
- '#gpio-cells'
105
+
- "#gpio-cells"
109
106
- gpio-ranges
110
107
111
108
additionalProperties: false
···
119
116
gpio-controller;
120
117
#gpio-cells = <2>;
121
118
gpio-ranges = <&lpass_tlmm 0 0 15>;
119
+
120
+
dmic01-state {
121
+
dmic01-clk-pins {
122
+
pins = "gpio6";
123
+
function = "dmic1_clk";
124
+
};
125
+
126
+
dmic01-clk-sleep-pins {
127
+
pins = "gpio6";
128
+
function = "dmic1_clk";
129
+
};
130
+
};
131
+
132
+
tx-swr-data-sleep-state {
133
+
pins = "gpio1", "gpio2", "gpio14";
134
+
function = "swr_tx_data";
135
+
};
122
136
};
+19
-28
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
+19
-28
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
···
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SC7280 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.
15
14
16
15
properties:
17
16
compatible:
···
42
43
maxItems: 1
43
44
44
45
gpio-line-names:
45
-
maxItems: 174
46
+
maxItems: 175
46
47
47
48
wakeup-parent: true
48
49
49
-
#PIN CONFIGURATION NODES
50
50
patternProperties:
51
-
'-pins$':
51
+
"-state$":
52
+
oneOf:
53
+
- $ref: "#/$defs/qcom-sc7280-tlmm-state"
54
+
- patternProperties:
55
+
"-pins$":
56
+
$ref: "#/$defs/qcom-sc7280-tlmm-state"
57
+
additionalProperties: false
58
+
59
+
$defs:
60
+
qcom-sc7280-tlmm-state:
52
61
type: object
53
62
description:
54
63
Pinctrl node's client devices use subnodes for desired pin configuration.
55
64
Client device subnodes use below standard properties.
65
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56
66
57
67
properties:
58
68
pins:
···
70
62
subnode.
71
63
items:
72
64
oneOf:
73
-
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
65
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
74
66
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
75
67
sdc2_cmd, sdc2_data, ufs_reset ]
76
68
minItems: 1
···
110
102
uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
111
103
usb_phy, vfr_0, vfr_1, vsense_trigger ]
112
104
113
-
drive-strength:
114
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
115
-
default: 2
116
-
description:
117
-
Selects the drive strength for the specified pins, in mA.
118
-
119
105
bias-pull-down: true
120
-
121
106
bias-pull-up: true
122
-
107
+
bias-bus-hold: true
123
108
bias-disable: true
124
-
109
+
drive-strength: true
110
+
input-enable: true
125
111
output-high: true
126
-
127
112
output-low: true
128
113
129
114
required:
130
115
- pins
131
-
132
-
allOf:
133
-
- $ref: /schemas/pinctrl/pincfg-node.yaml
134
-
- if:
135
-
properties:
136
-
pins:
137
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
138
-
then:
139
-
required:
140
-
- function
141
116
142
117
additionalProperties: false
143
118
···
153
162
gpio-ranges = <&tlmm 0 0 175>;
154
163
wakeup-parent = <&pdc>;
155
164
156
-
qup_uart5_default: qup-uart5-pins {
165
+
qup_uart5_default: qup-uart5-state {
157
166
pins = "gpio46", "gpio47";
158
167
function = "qup13";
159
168
drive-strength = <2>;
+9
-20
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml
+9
-20
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SC8180X TLMM block
···
9
9
maintainers:
10
10
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SC8180X platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.
15
14
16
15
allOf:
17
-
- $ref: "pinctrl.yaml#"
18
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19
17
20
18
properties:
···
24
26
25
27
reg-names:
26
28
items:
27
-
- const: "west"
28
-
- const: "east"
29
-
- const: "south"
29
+
- const: west
30
+
- const: east
31
+
- const: south
30
32
31
33
interrupts: true
32
34
interrupt-controller: true
···
45
47
additionalProperties: false
46
48
47
49
patternProperties:
48
-
'-state$':
50
+
"-state$":
49
51
oneOf:
50
52
- $ref: "#/$defs/qcom-sc8180x-tlmm-state"
51
53
- patternProperties:
···
53
55
$ref: "#/$defs/qcom-sc8180x-tlmm-state"
54
56
additionalProperties: false
55
57
56
-
'$defs':
58
+
$defs:
57
59
qcom-sc8180x-tlmm-state:
58
60
type: object
59
61
description:
60
62
Pinctrl node's client devices use subnodes for desired pin configuration.
61
63
Client device subnodes use below standard properties.
64
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
62
65
63
66
properties:
64
67
pins:
···
110
111
111
112
required:
112
113
- pins
113
-
114
-
allOf:
115
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
116
-
- if:
117
-
properties:
118
-
pins:
119
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
120
-
then:
121
-
required:
122
-
- function
123
114
124
115
additionalProperties: false
125
116
+34
-10
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
+34
-10
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
···
4
4
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8
-
Low Power Island (LPI) TLMM block
7
+
title: Qualcomm SC8280XP SoC LPASS LPI TLMM
9
8
10
9
maintainers:
11
10
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
11
13
-
description: |
14
-
This binding describes the Top Level Mode Multiplexer block found in the
15
-
LPASS LPI IP on most Qualcomm SoCs
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
16
15
17
16
properties:
18
17
compatible:
···
34
35
35
36
gpio-controller: true
36
37
37
-
'#gpio-cells':
38
+
"#gpio-cells":
38
39
description: Specifying the pin number and flags, as defined in
39
40
include/dt-bindings/gpio/gpio.h
40
41
const: 2
···
42
43
gpio-ranges:
43
44
maxItems: 1
44
45
45
-
#PIN CONFIGURATION NODES
46
46
patternProperties:
47
-
'-pins$':
47
+
"-state$":
48
+
oneOf:
49
+
- $ref: "#/$defs/qcom-sc8280xp-lpass-state"
50
+
- patternProperties:
51
+
"-pins$":
52
+
$ref: "#/$defs/qcom-sc8280xp-lpass-state"
53
+
additionalProperties: false
54
+
55
+
$defs:
56
+
qcom-sc8280xp-lpass-state:
48
57
type: object
49
58
description:
50
59
Pinctrl node's client devices use subnodes for desired pin configuration.
···
65
58
List of gpio pins affected by the properties specified in this
66
59
subnode.
67
60
items:
68
-
pattern: "^gpio([0-1]|1[0-8]])$"
61
+
pattern: "^gpio([0-1]|1[0-8])$"
69
62
70
63
function:
71
64
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
···
119
112
- clocks
120
113
- clock-names
121
114
- gpio-controller
122
-
- '#gpio-cells'
115
+
- "#gpio-cells"
123
116
- gpio-ranges
124
117
125
118
additionalProperties: false
···
137
130
gpio-controller;
138
131
#gpio-cells = <2>;
139
132
gpio-ranges = <&lpi_tlmm 0 0 18>;
133
+
134
+
dmic01-state {
135
+
dmic01-clk-pins {
136
+
pins = "gpio16";
137
+
function = "dmic1_clk";
138
+
};
139
+
140
+
dmic01-clk-sleep-pins {
141
+
pins = "gpio16";
142
+
function = "dmic1_clk";
143
+
};
144
+
};
145
+
146
+
tx-swr-data-sleep-state {
147
+
pins = "gpio0", "gpio1";
148
+
function = "swr_tx_data";
149
+
};
140
150
};
+9
-19
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
+9
-19
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SC8280XP TLMM block
···
10
10
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
11
12
12
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SC8280XP platform.
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC.
15
14
16
15
allOf:
17
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
···
24
25
25
26
interrupts: true
26
27
interrupt-controller: true
27
-
'#interrupt-cells': true
28
+
"#interrupt-cells": true
28
29
gpio-controller: true
29
30
gpio-reserved-ranges: true
30
-
'#gpio-cells': true
31
+
"#gpio-cells": true
31
32
gpio-ranges: true
32
33
wakeup-parent: true
33
34
···
38
39
additionalProperties: false
39
40
40
41
patternProperties:
41
-
'-state$':
42
+
"-state$":
42
43
oneOf:
43
44
- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
44
45
- patternProperties:
···
46
47
$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
47
48
additionalProperties: false
48
49
49
-
'$defs':
50
+
$defs:
50
51
qcom-sc8280xp-tlmm-state:
51
52
type: object
52
53
description:
53
54
Pinctrl node's client devices use subnodes for desired pin configuration.
54
55
Client device subnodes use below standard properties.
56
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
57
56
58
properties:
57
59
pins:
···
113
113
required:
114
114
- pins
115
115
116
-
allOf:
117
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
118
-
- if:
119
-
properties:
120
-
pins:
121
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
122
-
then:
123
-
required:
124
-
- function
125
-
126
116
additionalProperties: false
127
117
128
118
examples:
···
129
139
gpio-ranges = <&tlmm 0 0 230>;
130
140
131
141
gpio-wo-subnode-state {
132
-
pins = "gpio1";
133
-
function = "gpio";
142
+
pins = "gpio1";
143
+
function = "gpio";
134
144
};
135
145
136
146
uart-w-subnodes-state {
+188
Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml
+188
Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDM630 and SDM660 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.
15
+
16
+
allOf:
17
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,sdm630-pinctrl
23
+
- qcom,sdm660-pinctrl
24
+
25
+
reg:
26
+
maxItems: 3
27
+
28
+
reg-names:
29
+
items:
30
+
- const: south
31
+
- const: center
32
+
- const: north
33
+
34
+
interrupts: true
35
+
interrupt-controller: true
36
+
"#interrupt-cells": true
37
+
gpio-controller: true
38
+
39
+
gpio-reserved-ranges:
40
+
minItems: 1
41
+
maxItems: 57
42
+
43
+
gpio-line-names:
44
+
maxItems: 114
45
+
46
+
"#gpio-cells": true
47
+
gpio-ranges: true
48
+
wakeup-parent: true
49
+
50
+
patternProperties:
51
+
"-state$":
52
+
oneOf:
53
+
- $ref: "#/$defs/qcom-sdm630-tlmm-state"
54
+
- patternProperties:
55
+
"-pins$":
56
+
$ref: "#/$defs/qcom-sdm630-tlmm-state"
57
+
additionalProperties: false
58
+
59
+
$defs:
60
+
qcom-sdm630-tlmm-state:
61
+
type: object
62
+
description:
63
+
Pinctrl node's client devices use subnodes for desired pin configuration.
64
+
Client device subnodes use below standard properties.
65
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
66
+
67
+
properties:
68
+
pins:
69
+
description:
70
+
List of gpio pins affected by the properties specified in this
71
+
subnode.
72
+
items:
73
+
oneOf:
74
+
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
75
+
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
76
+
sdc2_cmd, sdc2_data ]
77
+
minItems: 1
78
+
maxItems: 36
79
+
80
+
function:
81
+
description:
82
+
Specify the alternative function to be configured for the specified
83
+
pins.
84
+
enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
85
+
atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
86
+
atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
87
+
atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20,
88
+
atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0,
89
+
bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
90
+
blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b,
91
+
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
92
+
blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a,
93
+
blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1,
94
+
blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
95
+
blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c,
96
+
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1,
97
+
gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
98
+
isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
99
+
mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
100
+
nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
101
+
phase_flag1, phase_flag10, phase_flag11, phase_flag12,
102
+
phase_flag13, phase_flag14, phase_flag15, phase_flag16,
103
+
phase_flag17, phase_flag18, phase_flag19, phase_flag2,
104
+
phase_flag20, phase_flag21, phase_flag22, phase_flag23,
105
+
phase_flag24, phase_flag25, phase_flag26, phase_flag27,
106
+
phase_flag28, phase_flag29, phase_flag3, phase_flag30,
107
+
phase_flag31, phase_flag4, phase_flag5, phase_flag6,
108
+
phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,
109
+
pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem,
110
+
pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b,
111
+
qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
112
+
qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2,
113
+
qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
114
+
qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk,
115
+
qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3,
116
+
qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu,
117
+
ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk,
118
+
uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
119
+
uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout,
120
+
vsense_data0, vsense_data1, vsense_mode, wlan1_adc0,
121
+
wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
122
+
123
+
bias-disable: true
124
+
bias-pull-down: true
125
+
bias-pull-up: true
126
+
drive-strength: true
127
+
input-enable: true
128
+
output-high: true
129
+
output-low: true
130
+
131
+
required:
132
+
- pins
133
+
134
+
additionalProperties: false
135
+
136
+
required:
137
+
- compatible
138
+
- reg
139
+
140
+
additionalProperties: false
141
+
142
+
examples:
143
+
- |
144
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
145
+
146
+
tlmm: pinctrl@3100000 {
147
+
compatible = "qcom,sdm630-pinctrl";
148
+
reg = <0x03100000 0x400000>,
149
+
<0x03500000 0x400000>,
150
+
<0x03900000 0x400000>;
151
+
reg-names = "south", "center", "north";
152
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
153
+
gpio-controller;
154
+
gpio-ranges = <&tlmm 0 0 114>;
155
+
#gpio-cells = <2>;
156
+
interrupt-controller;
157
+
#interrupt-cells = <2>;
158
+
159
+
blsp1-uart1-default-state {
160
+
pins = "gpio0", "gpio1", "gpio2", "gpio3";
161
+
function = "gpio";
162
+
drive-strength = <2>;
163
+
bias-disable;
164
+
};
165
+
166
+
blsp2_uart1_default: blsp2-uart1-active-state {
167
+
tx-rts-pins {
168
+
pins = "gpio16", "gpio19";
169
+
function = "blsp_uart5";
170
+
drive-strength = <2>;
171
+
bias-disable;
172
+
};
173
+
174
+
rx-pins {
175
+
pins = "gpio17";
176
+
function = "blsp_uart5";
177
+
drive-strength = <2>;
178
+
bias-pull-up;
179
+
};
180
+
181
+
cts-pins {
182
+
pins = "gpio18";
183
+
function = "blsp_uart5";
184
+
drive-strength = <2>;
185
+
bias-pull-down;
186
+
};
187
+
};
188
+
};
-191
Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt
-191
Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt
···
1
-
Qualcomm Technologies, Inc. SDM660 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
SDM660 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,sdm660-pinctrl" or
10
-
"qcom,sdm630-pinctrl".
11
-
12
-
- reg:
13
-
Usage: required
14
-
Value type: <prop-encoded-array>
15
-
Definition: the base address and size of the north, center and south
16
-
TLMM tiles.
17
-
18
-
- reg-names:
19
-
Usage: required
20
-
Value type: <stringlist>
21
-
Definition: names for the cells of reg, must contain "north", "center"
22
-
and "south".
23
-
24
-
- interrupts:
25
-
Usage: required
26
-
Value type: <prop-encoded-array>
27
-
Definition: should specify the TLMM summary IRQ.
28
-
29
-
- interrupt-controller:
30
-
Usage: required
31
-
Value type: <none>
32
-
Definition: identifies this node as an interrupt controller
33
-
34
-
- #interrupt-cells:
35
-
Usage: required
36
-
Value type: <u32>
37
-
Definition: must be 2. Specifying the pin number and flags, as defined
38
-
in <dt-bindings/interrupt-controller/irq.h>
39
-
40
-
- gpio-controller:
41
-
Usage: required
42
-
Value type: <none>
43
-
Definition: identifies this node as a gpio controller
44
-
45
-
- gpio-ranges:
46
-
Usage: required
47
-
Value type: <prop-encoded-array>
48
-
Definition: Specifies the mapping between gpio controller and
49
-
pin-controller pins.
50
-
51
-
- #gpio-cells:
52
-
Usage: required
53
-
Value type: <u32>
54
-
Definition: must be 2. Specifying the pin number and flags, as defined
55
-
in <dt-bindings/gpio/gpio.h>
56
-
57
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
58
-
a general description of GPIO and interrupt bindings.
59
-
60
-
Please refer to pinctrl-bindings.txt in this directory for details of the
61
-
common pinctrl bindings used by client devices, including the meaning of the
62
-
phrase "pin configuration node".
63
-
64
-
The pin configuration nodes act as a container for an arbitrary number of
65
-
subnodes. Each of these subnodes represents some desired configuration for a
66
-
pin, a group, or a list of pins or groups. This configuration can include the
67
-
mux function to select on those pin(s)/group(s), and various pin configuration
68
-
parameters, such as pull-up, drive strength, etc.
69
-
70
-
71
-
PIN CONFIGURATION NODES:
72
-
73
-
The name of each subnode is not important; all subnodes should be enumerated
74
-
and processed purely based on their content.
75
-
76
-
Each subnode only affects those parameters that are explicitly listed. In
77
-
other words, a subnode that lists a mux function but no pin configuration
78
-
parameters implies no information about any pin configuration parameters.
79
-
Similarly, a pin subnode that describes a pullup parameter implies no
80
-
information about e.g. the mux function.
81
-
82
-
83
-
The following generic properties as defined in pinctrl-bindings.txt are valid
84
-
to specify in a pin configuration subnode:
85
-
86
-
- pins:
87
-
Usage: required
88
-
Value type: <string-array>
89
-
Definition: List of gpio pins affected by the properties specified in
90
-
this subnode. Valid pins are:
91
-
gpio0-gpio113,
92
-
Supports mux, bias and drive-strength
93
-
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk,
94
-
Supports bias and drive-strength
95
-
96
-
- function:
97
-
Usage: required
98
-
Value type: <string>
99
-
Definition: Specify the alternative function to be configured for the
100
-
specified pins. Functions are only valid for gpio pins.
101
-
Valid values are:
102
-
adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
103
-
atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
104
-
atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
105
-
atest_usb11, atest_usb12, atest_usb13, atest_usb2,
106
-
atest_usb20, atest_usb21, atest_usb22, atest_usb23,
107
-
audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2,
108
-
blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7,
109
-
blsp_i2c8_a, blsp_i2c8_b, blsp_spi1, blsp_spi2, blsp_spi3,
110
-
blsp_spi3_cs1, blsp_spi3_cs2, blsp_spi4, blsp_spi5,
111
-
blsp_spi6, blsp_spi7, blsp_spi8_a, blsp_spi8_b,
112
-
blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, blsp_uart2,
113
-
blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
114
-
blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async,
115
-
cci_i2c, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
116
-
gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
117
-
isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
118
-
mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
119
-
nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
120
-
phase_flag1, phase_flag10, phase_flag11, phase_flag12,
121
-
phase_flag13, phase_flag14, phase_flag15, phase_flag16,
122
-
phase_flag17, phase_flag18, phase_flag19, phase_flag2,
123
-
phase_flag20, phase_flag21, phase_flag22, phase_flag23,
124
-
phase_flag24, phase_flag25, phase_flag26, phase_flag27,
125
-
phase_flag28, phase_flag29, phase_flag3, phase_flag30,
126
-
phase_flag31, phase_flag4, phase_flag5, phase_flag6,
127
-
phase_flag7, phase_flag8, phase_flag9, pll_bypassnl,
128
-
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto,
129
-
pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a,
130
-
qdss_cti1_b, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10,
131
-
qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
132
-
qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
133
-
qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request,
134
-
qspi_clk, qspi_cs, qspi_data0, qspi_data1, qspi_data2,
135
-
qspi_data3, qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data,
136
-
sp_cmu, ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2,
137
-
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
138
-
uim2_data, uim2_present, uim2_reset, uim_batt, vfr_1,
139
-
vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
140
-
wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1
141
-
142
-
- bias-disable:
143
-
Usage: optional
144
-
Value type: <none>
145
-
Definition: The specified pins should be configured as no pull.
146
-
147
-
- bias-pull-down:
148
-
Usage: optional
149
-
Value type: <none>
150
-
Definition: The specified pins should be configured as pull down.
151
-
152
-
- bias-pull-up:
153
-
Usage: optional
154
-
Value type: <none>
155
-
Definition: The specified pins should be configured as pull up.
156
-
157
-
- output-high:
158
-
Usage: optional
159
-
Value type: <none>
160
-
Definition: The specified pins are configured in output mode, driven
161
-
high.
162
-
Not valid for sdc pins.
163
-
164
-
- output-low:
165
-
Usage: optional
166
-
Value type: <none>
167
-
Definition: The specified pins are configured in output mode, driven
168
-
low.
169
-
Not valid for sdc pins.
170
-
171
-
- drive-strength:
172
-
Usage: optional
173
-
Value type: <u32>
174
-
Definition: Selects the drive strength for the specified pins, in mA.
175
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
176
-
177
-
Example:
178
-
179
-
tlmm: pinctrl@3100000 {
180
-
compatible = "qcom,sdm660-pinctrl";
181
-
reg = <0x3100000 0x200000>,
182
-
<0x3500000 0x200000>,
183
-
<0x3900000 0x200000>;
184
-
reg-names = "south", "center", "north";
185
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
186
-
gpio-controller;
187
-
gpio-ranges = <&tlmm 0 0 114>;
188
-
#gpio-cells = <2>;
189
-
interrupt-controller;
190
-
#interrupt-cells = <2>;
191
-
};
+127
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml
+127
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. SDM670 TLMM block
8
+
9
+
maintainers:
10
+
- Richard Acayan <mailingradian@gmail.com>
11
+
12
+
description: |
13
+
The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,sdm670-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts: true
26
+
interrupt-controller: true
27
+
"#interrupt-cells": true
28
+
gpio-controller: true
29
+
gpio-reserved-ranges:
30
+
minItems: 1
31
+
maxItems: 75
32
+
33
+
"#gpio-cells": true
34
+
gpio-ranges: true
35
+
wakeup-parent: true
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
41
+
additionalProperties: false
42
+
43
+
patternProperties:
44
+
"-state$":
45
+
oneOf:
46
+
- $ref: "#/$defs/qcom-sdm670-tlmm-state"
47
+
- patternProperties:
48
+
"-pins$":
49
+
$ref: "#/$defs/qcom-sdm670-tlmm-state"
50
+
additionalProperties: false
51
+
52
+
$defs:
53
+
qcom-sdm670-tlmm-state:
54
+
type: object
55
+
description:
56
+
Pinctrl node's client devices use subnodes for desired pin configuration.
57
+
Client device subnodes use below standard properties.
58
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
59
+
60
+
properties:
61
+
pins:
62
+
description:
63
+
List of gpio pins affected by the properties specified in this
64
+
subnode.
65
+
items:
66
+
oneOf:
67
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
68
+
- enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
69
+
sdc2_clk, sdc2_cmd, sdc2_data ]
70
+
minItems: 1
71
+
maxItems: 36
72
+
73
+
function:
74
+
description:
75
+
Specify the alternative function to be configured for the specified
76
+
pins.
77
+
78
+
enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
79
+
atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
80
+
atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
81
+
cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,
82
+
ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
83
+
gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,
84
+
lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
85
+
mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
86
+
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
87
+
qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,
88
+
qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,
89
+
sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,
90
+
tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,
91
+
tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
92
+
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
93
+
vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]
94
+
95
+
96
+
bias-disable: true
97
+
bias-pull-down: true
98
+
bias-pull-up: true
99
+
drive-strength: true
100
+
input-enable: true
101
+
output-high: true
102
+
output-low: true
103
+
104
+
required:
105
+
- pins
106
+
107
+
additionalProperties: false
108
+
109
+
examples:
110
+
- |
111
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
112
+
pinctrl@3400000 {
113
+
compatible = "qcom,sdm670-tlmm";
114
+
reg = <0x03400000 0x300000>;
115
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
116
+
gpio-controller;
117
+
#gpio-cells = <2>;
118
+
interrupt-controller;
119
+
#interrupt-cells = <2>;
120
+
gpio-ranges = <&tlmm 0 0 151>;
121
+
122
+
qup-i2c9-state {
123
+
pins = "gpio6", "gpio7";
124
+
function = "qup9";
125
+
};
126
+
};
127
+
...
-176
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
-176
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
···
1
-
Qualcomm SDM845 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
SDM845 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,sdm845-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the TLMM register space.
15
-
16
-
- interrupts:
17
-
Usage: required
18
-
Value type: <prop-encoded-array>
19
-
Definition: should specify the TLMM summary IRQ.
20
-
21
-
- interrupt-controller:
22
-
Usage: required
23
-
Value type: <none>
24
-
Definition: identifies this node as an interrupt controller
25
-
26
-
- #interrupt-cells:
27
-
Usage: required
28
-
Value type: <u32>
29
-
Definition: must be 2. Specifying the pin number and flags, as defined
30
-
in <dt-bindings/interrupt-controller/irq.h>
31
-
32
-
- gpio-controller:
33
-
Usage: required
34
-
Value type: <none>
35
-
Definition: identifies this node as a gpio controller
36
-
37
-
- #gpio-cells:
38
-
Usage: required
39
-
Value type: <u32>
40
-
Definition: must be 2. Specifying the pin number and flags, as defined
41
-
in <dt-bindings/gpio/gpio.h>
42
-
43
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
44
-
a general description of GPIO and interrupt bindings.
45
-
46
-
Please refer to pinctrl-bindings.txt in this directory for details of the
47
-
common pinctrl bindings used by client devices, including the meaning of the
48
-
phrase "pin configuration node".
49
-
50
-
The pin configuration nodes act as a container for an arbitrary number of
51
-
subnodes. Each of these subnodes represents some desired configuration for a
52
-
pin, a group, or a list of pins or groups. This configuration can include the
53
-
mux function to select on those pin(s)/group(s), and various pin configuration
54
-
parameters, such as pull-up, drive strength, etc.
55
-
56
-
57
-
PIN CONFIGURATION NODES:
58
-
59
-
The name of each subnode is not important; all subnodes should be enumerated
60
-
and processed purely based on their content.
61
-
62
-
Each subnode only affects those parameters that are explicitly listed. In
63
-
other words, a subnode that lists a mux function but no pin configuration
64
-
parameters implies no information about any pin configuration parameters.
65
-
Similarly, a pin subnode that describes a pullup parameter implies no
66
-
information about e.g. the mux function.
67
-
68
-
69
-
The following generic properties as defined in pinctrl-bindings.txt are valid
70
-
to specify in a pin configuration subnode:
71
-
72
-
- pins:
73
-
Usage: required
74
-
Value type: <string-array>
75
-
Definition: List of gpio pins affected by the properties specified in
76
-
this subnode.
77
-
78
-
Valid pins are:
79
-
gpio0-gpio149
80
-
Supports mux, bias and drive-strength
81
-
82
-
sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
83
-
Supports bias and drive-strength
84
-
85
-
- function:
86
-
Usage: required
87
-
Value type: <string>
88
-
Definition: Specify the alternative function to be configured for the
89
-
specified pins. Functions are only valid for gpio pins.
90
-
Valid values are:
91
-
92
-
gpio, adsp_ext, agera_pll, atest_char, atest_tsens,
93
-
atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
94
-
atest_usb12, atest_usb13, atest_usb2, atest_usb20,
95
-
atest_usb21, atest_usb22, atest_usb23, audio_ref,
96
-
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
97
-
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
98
-
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
99
-
ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
100
-
gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update,
101
-
lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1,
102
-
mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator,
103
-
pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
104
-
pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti,
105
-
qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1,
106
-
qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4,
107
-
qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
108
-
qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd,
109
-
sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0,
110
-
tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2,
111
-
tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync,
112
-
tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync,
113
-
uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
114
-
uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy,
115
-
vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
116
-
wlan2_adc1,
117
-
118
-
- bias-disable:
119
-
Usage: optional
120
-
Value type: <none>
121
-
Definition: The specified pins should be configured as no pull.
122
-
123
-
- bias-pull-down:
124
-
Usage: optional
125
-
Value type: <none>
126
-
Definition: The specified pins should be configured as pull down.
127
-
128
-
- bias-pull-up:
129
-
Usage: optional
130
-
Value type: <none>
131
-
Definition: The specified pins should be configured as pull up.
132
-
133
-
- output-high:
134
-
Usage: optional
135
-
Value type: <none>
136
-
Definition: The specified pins are configured in output mode, driven
137
-
high.
138
-
Not valid for sdc pins.
139
-
140
-
- output-low:
141
-
Usage: optional
142
-
Value type: <none>
143
-
Definition: The specified pins are configured in output mode, driven
144
-
low.
145
-
Not valid for sdc pins.
146
-
147
-
- drive-strength:
148
-
Usage: optional
149
-
Value type: <u32>
150
-
Definition: Selects the drive strength for the specified pins, in mA.
151
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
152
-
153
-
Example:
154
-
155
-
tlmm: pinctrl@3400000 {
156
-
compatible = "qcom,sdm845-pinctrl";
157
-
reg = <0x03400000 0xc00000>;
158
-
interrupts = <GIC_SPI 208 0>;
159
-
gpio-controller;
160
-
#gpio-cells = <2>;
161
-
interrupt-controller;
162
-
#interrupt-cells = <2>;
163
-
164
-
qup9_active: qup9-active {
165
-
mux {
166
-
pins = "gpio4", "gpio5";
167
-
function = "qup9";
168
-
};
169
-
170
-
config {
171
-
pins = "gpio4", "gpio5";
172
-
drive-strength = <2>;
173
-
bias-disable;
174
-
};
175
-
};
176
-
};
+158
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
+158
Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDM845 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
15
+
16
+
allOf:
17
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
const: qcom,sdm845-pinctrl
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts: true
27
+
interrupt-controller: true
28
+
"#interrupt-cells": true
29
+
gpio-controller: true
30
+
31
+
gpio-reserved-ranges:
32
+
minItems: 1
33
+
maxItems: 75
34
+
35
+
gpio-line-names:
36
+
maxItems: 150
37
+
38
+
"#gpio-cells": true
39
+
gpio-ranges: true
40
+
wakeup-parent: true
41
+
42
+
patternProperties:
43
+
"-state$":
44
+
oneOf:
45
+
- $ref: "#/$defs/qcom-sdm845-tlmm-state"
46
+
- patternProperties:
47
+
"-pins$":
48
+
$ref: "#/$defs/qcom-sdm845-tlmm-state"
49
+
additionalProperties: false
50
+
51
+
$defs:
52
+
qcom-sdm845-tlmm-state:
53
+
type: object
54
+
description:
55
+
Pinctrl node's client devices use subnodes for desired pin configuration.
56
+
Client device subnodes use below standard properties.
57
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58
+
59
+
properties:
60
+
pins:
61
+
description:
62
+
List of gpio pins affected by the properties specified in this
63
+
subnode.
64
+
items:
65
+
oneOf:
66
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
67
+
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
68
+
minItems: 1
69
+
maxItems: 36
70
+
71
+
function:
72
+
description:
73
+
Specify the alternative function to be configured for the specified
74
+
pins.
75
+
enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
76
+
atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
77
+
atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
78
+
audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
79
+
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
80
+
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
81
+
ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
82
+
gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
83
+
lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
84
+
mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
85
+
pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
86
+
pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
87
+
qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
88
+
qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
89
+
qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
90
+
sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
91
+
spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
92
+
tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
93
+
tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
94
+
tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
95
+
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
96
+
uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
97
+
wlan1_adc1, wlan2_adc0, wlan2_adc1]
98
+
99
+
bias-disable: true
100
+
bias-pull-down: true
101
+
bias-pull-up: true
102
+
drive-strength: true
103
+
input-enable: true
104
+
output-high: true
105
+
output-low: true
106
+
107
+
required:
108
+
- pins
109
+
110
+
additionalProperties: false
111
+
112
+
required:
113
+
- compatible
114
+
- reg
115
+
116
+
additionalProperties: false
117
+
118
+
examples:
119
+
- |
120
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
121
+
122
+
pinctrl@3400000 {
123
+
compatible = "qcom,sdm845-pinctrl";
124
+
reg = <0x03400000 0xc00000>;
125
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
126
+
gpio-controller;
127
+
#gpio-cells = <2>;
128
+
interrupt-controller;
129
+
#interrupt-cells = <2>;
130
+
gpio-ranges = <&tlmm 0 0 151>;
131
+
wakeup-parent = <&pdc_intc>;
132
+
133
+
cci0-default-state {
134
+
pins = "gpio17", "gpio18";
135
+
function = "cci_i2c";
136
+
137
+
bias-pull-up;
138
+
drive-strength = <2>;
139
+
};
140
+
141
+
cam0-default-state {
142
+
rst-pins {
143
+
pins = "gpio9";
144
+
function = "gpio";
145
+
146
+
drive-strength = <16>;
147
+
bias-disable;
148
+
};
149
+
150
+
mclk0-pins {
151
+
pins = "gpio13";
152
+
function = "cam_mclk";
153
+
154
+
drive-strength = <16>;
155
+
bias-disable;
156
+
};
157
+
};
158
+
};
+35
-58
Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
+35
-58
Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
···
9
9
maintainers:
10
10
- Vinod Koul <vkoul@kernel.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SDX55 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
15
14
16
15
properties:
17
16
compatible:
···
20
21
description: Specifies the base address and size of the TLMM register space
21
22
maxItems: 1
22
23
23
-
interrupts:
24
-
description: Specifies the TLMM summary IRQ
25
-
maxItems: 1
26
-
24
+
interrupts: true
27
25
interrupt-controller: true
28
-
29
-
'#interrupt-cells':
30
-
description: Specifies the PIN numbers and Flags, as defined in
31
-
include/dt-bindings/interrupt-controller/irq.h
32
-
const: 2
33
-
26
+
"#interrupt-cells": true
34
27
gpio-controller: true
35
-
36
-
'#gpio-cells':
37
-
description: Specifying the pin number and flags, as defined in
38
-
include/dt-bindings/gpio/gpio.h
39
-
const: 2
40
-
41
-
gpio-ranges:
42
-
maxItems: 1
28
+
"#gpio-cells": true
29
+
gpio-ranges: true
43
30
44
31
gpio-reserved-ranges:
45
32
maxItems: 1
46
33
47
-
#PIN CONFIGURATION NODES
48
34
patternProperties:
49
-
'-pins$':
35
+
"-state$":
36
+
oneOf:
37
+
- $ref: "#/$defs/qcom-sdx55-tlmm-state"
38
+
- patternProperties:
39
+
"-pins$":
40
+
$ref: "#/$defs/qcom-sdx55-tlmm-state"
41
+
additionalProperties: false
42
+
43
+
$defs:
44
+
qcom-sdx55-tlmm-state:
50
45
type: object
51
46
description:
52
47
Pinctrl node's client devices use subnodes for desired pin configuration.
53
48
Client device subnodes use below standard properties.
54
-
$ref: "/schemas/pinctrl/pincfg-node.yaml"
49
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
50
56
51
properties:
57
52
pins:
···
89
96
uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
90
97
uim2_reset, usb2phy_ac, vsense_trigger ]
91
98
92
-
drive-strength:
93
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
94
-
default: 2
95
-
description:
96
-
Selects the drive strength for the specified pins, in mA.
97
-
98
99
bias-pull-down: true
99
-
100
100
bias-pull-up: true
101
-
102
101
bias-disable: true
103
-
102
+
drive-strength: true
104
103
output-high: true
105
-
106
104
output-low: true
107
105
108
106
required:
109
107
- pins
110
-
- function
111
108
112
109
additionalProperties: false
113
110
114
111
allOf:
115
-
- $ref: "pinctrl.yaml#"
112
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
116
113
117
114
required:
118
115
- compatible
119
116
- reg
120
-
- interrupts
121
-
- interrupt-controller
122
-
- '#interrupt-cells'
123
-
- gpio-controller
124
-
- '#gpio-cells'
125
-
- gpio-ranges
126
117
127
118
additionalProperties: false
128
119
129
120
examples:
130
121
- |
131
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
132
-
tlmm: pinctrl@1f00000 {
133
-
compatible = "qcom,sdx55-pinctrl";
134
-
reg = <0x0f100000 0x300000>;
135
-
gpio-controller;
136
-
#gpio-cells = <2>;
137
-
gpio-ranges = <&tlmm 0 0 108>;
138
-
interrupt-controller;
139
-
#interrupt-cells = <2>;
140
-
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
122
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
123
+
tlmm: pinctrl@1f00000 {
124
+
compatible = "qcom,sdx55-pinctrl";
125
+
reg = <0x0f100000 0x300000>;
126
+
gpio-controller;
127
+
#gpio-cells = <2>;
128
+
gpio-ranges = <&tlmm 0 0 108>;
129
+
interrupt-controller;
130
+
#interrupt-cells = <2>;
131
+
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
141
132
142
-
serial-pins {
143
-
pins = "gpio8", "gpio9";
144
-
function = "blsp_uart3";
145
-
drive-strength = <8>;
146
-
bias-disable;
147
-
};
133
+
serial-state {
134
+
pins = "gpio8", "gpio9";
135
+
function = "blsp_uart3";
136
+
drive-strength = <8>;
137
+
bias-disable;
148
138
};
139
+
};
149
140
150
141
...
+18
-44
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml
+18
-44
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SDX65 TLMM block
···
10
10
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
11
11
12
12
description:
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SDX65 platform.
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC.
15
14
16
15
properties:
17
16
compatible:
···
19
20
reg:
20
21
maxItems: 1
21
22
22
-
interrupts:
23
-
maxItems: 1
24
-
23
+
interrupts: true
25
24
interrupt-controller: true
26
-
27
-
'#interrupt-cells':
28
-
description: Specifies the PIN numbers and Flags, as defined in
29
-
include/dt-bindings/interrupt-controller/irq.h
30
-
const: 2
31
-
25
+
"#interrupt-cells": true
32
26
gpio-controller: true
33
-
34
-
'#gpio-cells':
35
-
description: Specifying the pin number and flags, as defined in
36
-
include/dt-bindings/gpio/gpio.h
37
-
const: 2
38
-
39
-
gpio-ranges:
40
-
maxItems: 1
27
+
"#gpio-cells": true
28
+
gpio-ranges: true
41
29
42
30
gpio-reserved-ranges:
43
31
maxItems: 1
44
32
45
-
#PIN CONFIGURATION NODES
46
33
patternProperties:
47
-
'-state$':
34
+
"-state$":
48
35
oneOf:
49
36
- $ref: "#/$defs/qcom-sdx65-tlmm-state"
50
37
- patternProperties:
51
-
".*":
38
+
"-pins$":
52
39
$ref: "#/$defs/qcom-sdx65-tlmm-state"
53
-
'$defs':
40
+
additionalProperties: false
41
+
42
+
$defs:
54
43
qcom-sdx65-tlmm-state:
55
44
type: object
56
45
description:
57
46
Pinctrl node's client devices use subnodes for desired pin configuration.
58
47
Client device subnodes use below standard properties.
59
-
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
48
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
60
49
61
50
properties:
62
51
pins:
···
109
122
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
110
123
gpio ]
111
124
112
-
drive-strength:
113
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
114
-
default: 2
115
-
description:
116
-
Selects the drive strength for the specified pins, in mA.
117
-
118
125
bias-pull-down: true
119
-
120
126
bias-pull-up: true
121
-
122
127
bias-disable: true
123
-
128
+
drive-strength: true
124
129
output-high: true
125
-
126
130
output-low: true
127
131
128
132
required:
129
133
- pins
130
-
- function
131
134
132
135
additionalProperties: false
136
+
137
+
allOf:
138
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
133
139
134
140
required:
135
141
- compatible
136
142
- reg
137
-
- interrupts
138
-
- interrupt-controller
139
-
- '#interrupt-cells'
140
-
- gpio-controller
141
-
- '#gpio-cells'
142
-
- gpio-ranges
143
143
144
144
additionalProperties: false
145
145
···
149
175
};
150
176
151
177
uart-w-subnodes-state {
152
-
rx {
178
+
rx-pins {
153
179
pins = "gpio4";
154
180
function = "blsp_uart1";
155
181
bias-pull-up;
156
182
};
157
183
158
-
tx {
184
+
tx-pins {
159
185
pins = "gpio5";
160
186
function = "blsp_uart1";
161
187
bias-disable;
+12
-55
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml
+12
-55
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
···
10
10
- Iskren Chernev <iskren.chernev@gmail.com>
11
11
12
12
description:
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SM4250/6115 platforms.
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
14
+
SoCs.
15
15
16
16
properties:
17
17
compatible:
18
18
const: qcom,sm6115-tlmm
19
19
20
20
reg:
21
-
minItems: 3
22
21
maxItems: 3
23
22
24
23
reg-names:
···
26
27
- const: south
27
28
- const: east
28
29
29
-
interrupts:
30
-
description: Specifies the TLMM summary IRQ
31
-
maxItems: 1
32
-
30
+
interrupts: true
33
31
interrupt-controller: true
34
-
35
-
'#interrupt-cells':
36
-
description:
37
-
Specifies the PIN numbers and Flags, as defined in defined in
38
-
include/dt-bindings/interrupt-controller/irq.h
39
-
const: 2
40
-
32
+
"#interrupt-cells": true
41
33
gpio-controller: true
42
-
43
-
'#gpio-cells':
44
-
description: Specifying the pin number and flags, as defined in
45
-
include/dt-bindings/gpio/gpio.h
46
-
const: 2
47
-
48
-
gpio-ranges:
49
-
maxItems: 1
50
-
34
+
"#gpio-cells": true
35
+
gpio-ranges: true
51
36
gpio-reserved-ranges: true
52
-
53
37
wakeup-parent: true
54
38
55
-
#PIN CONFIGURATION NODES
56
39
patternProperties:
57
-
'-state$':
40
+
"-state$":
58
41
oneOf:
59
42
- $ref: "#/$defs/qcom-sm6115-tlmm-state"
60
43
- patternProperties:
···
44
63
$ref: "#/$defs/qcom-sm6115-tlmm-state"
45
64
additionalProperties: false
46
65
47
-
'$defs':
66
+
$defs:
48
67
qcom-sm6115-tlmm-state:
49
68
type: object
50
69
description:
51
70
Pinctrl node's client devices use subnodes for desired pin configuration.
52
71
Client device subnodes use below standard properties.
72
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
53
73
54
74
properties:
55
75
pins:
···
83
101
uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
84
102
wlan1_adc0, elan1_adc1 ]
85
103
86
-
drive-strength:
87
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
88
-
default: 2
89
-
description:
90
-
Selects the drive strength for the specified pins, in mA.
91
-
92
104
bias-pull-down: true
93
-
94
105
bias-pull-up: true
95
-
96
106
bias-disable: true
97
-
107
+
drive-strength: true
98
108
output-high: true
99
-
100
109
output-low: true
101
110
102
111
required:
103
112
- pins
104
113
105
-
allOf:
106
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
107
-
- if:
108
-
properties:
109
-
pins:
110
-
pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
111
-
then:
112
-
required:
113
-
- function
114
-
115
114
additionalProperties: false
116
115
117
116
allOf:
118
-
- $ref: "pinctrl.yaml#"
117
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
119
118
120
119
required:
121
120
- compatible
122
121
- reg
123
122
- reg-names
124
-
- interrupts
125
-
- interrupt-controller
126
-
- '#interrupt-cells'
127
-
- gpio-controller
128
-
- '#gpio-cells'
129
-
- gpio-ranges
130
123
131
124
additionalProperties: false
132
125
+10
-22
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml
+10
-22
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
title: Qualcomm Technologies, Inc. SM6125 TLMM block
7
7
8
8
maintainers:
9
9
- Martin Botka <martin.botka@somainline.org>
10
10
11
-
description: |
12
-
This binding describes the Top Level Mode Multiplexer (TLMM) block found
13
-
in the SM6125 platform.
11
+
description:
12
+
Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.
14
13
15
14
allOf:
16
-
- $ref: "pinctrl.yaml#"
17
15
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
16
19
17
properties:
···
19
21
const: qcom,sm6125-tlmm
20
22
21
23
reg:
22
-
minItems: 3
23
24
maxItems: 3
24
25
25
26
reg-names:
26
27
items:
27
-
- const: "west"
28
-
- const: "south"
29
-
- const: "east"
28
+
- const: west
29
+
- const: south
30
+
- const: east
30
31
31
32
interrupts: true
32
33
interrupt-controller: true
33
-
'#interrupt-cells': true
34
+
"#interrupt-cells": true
34
35
gpio-controller: true
35
36
gpio-reserved-ranges: true
36
-
'#gpio-cells': true
37
+
"#gpio-cells": true
37
38
gpio-ranges: true
38
39
wakeup-parent: true
39
40
···
44
47
additionalProperties: false
45
48
46
49
patternProperties:
47
-
'-state$':
50
+
"-state$":
48
51
oneOf:
49
52
- $ref: "#/$defs/qcom-sm6125-tlmm-state"
50
53
- patternProperties:
···
58
61
description:
59
62
Pinctrl node's client devices use subnodes for desired pin configuration.
60
63
Client device subnodes use below standard properties.
64
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
61
65
62
66
properties:
63
67
pins:
···
109
111
110
112
required:
111
113
- pins
112
-
113
-
allOf:
114
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
115
-
- if:
116
-
properties:
117
-
pins:
118
-
pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
119
-
then:
120
-
required:
121
-
- function
122
114
123
115
additionalProperties: false
124
116
+7
-18
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml
+7
-18
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SM6350 TLMM block
···
9
9
maintainers:
10
10
- Konrad Dybcio <konrad.dybcio@somainline.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer (TLMM) block found
14
-
in the SM6350 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.
15
14
16
15
allOf:
17
-
- $ref: "pinctrl.yaml#"
18
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19
17
20
18
properties:
···
24
26
25
27
interrupts: true
26
28
interrupt-controller: true
27
-
'#interrupt-cells': true
29
+
"#interrupt-cells": true
28
30
gpio-controller: true
29
31
gpio-reserved-ranges: true
30
-
'#gpio-cells': true
32
+
"#gpio-cells": true
31
33
gpio-ranges: true
32
34
wakeup-parent: true
33
35
···
38
40
additionalProperties: false
39
41
40
42
patternProperties:
41
-
'-state$':
43
+
"-state$":
42
44
oneOf:
43
45
- $ref: "#/$defs/qcom-sm6350-tlmm-state"
44
46
- patternProperties:
···
52
54
description:
53
55
Pinctrl node's client devices use subnodes for desired pin configuration.
54
56
Client device subnodes use below standard properties.
57
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
58
56
59
properties:
57
60
pins:
···
109
110
110
111
required:
111
112
- pins
112
-
113
-
allOf:
114
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
115
-
- if:
116
-
properties:
117
-
pins:
118
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
119
-
then:
120
-
required:
121
-
- function
122
113
123
114
additionalProperties: false
124
115
+6
-17
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
+6
-17
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
···
9
9
maintainers:
10
10
- Konrad Dybcio <konrad.dybcio@somainline.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer (TLMM) block found
14
-
in the SM6375 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
15
14
16
15
allOf:
17
-
- $ref: "pinctrl.yaml#"
18
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19
17
20
18
properties:
···
24
26
25
27
interrupts: true
26
28
interrupt-controller: true
27
-
'#interrupt-cells': true
29
+
"#interrupt-cells": true
28
30
gpio-controller: true
29
31
gpio-reserved-ranges: true
30
-
'#gpio-cells': true
32
+
"#gpio-cells": true
31
33
gpio-ranges: true
32
34
wakeup-parent: true
33
35
···
38
40
additionalProperties: false
39
41
40
42
patternProperties:
41
-
'-state$':
43
+
"-state$":
42
44
oneOf:
43
45
- $ref: "#/$defs/qcom-sm6375-tlmm-state"
44
46
- patternProperties:
···
52
54
description:
53
55
Pinctrl node's client devices use subnodes for desired pin configuration.
54
56
Client device subnodes use below standard properties.
57
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
58
56
59
properties:
57
60
pins:
···
118
119
119
120
required:
120
121
- pins
121
-
122
-
allOf:
123
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
124
-
- if:
125
-
properties:
126
-
pins:
127
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
128
-
then:
129
-
required:
130
-
- function
131
122
132
123
additionalProperties: false
133
124
-190
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
-190
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
···
1
-
Qualcomm SM8150 TLMM block
2
-
3
-
This binding describes the Top Level Mode Multiplexer block found in the
4
-
QCS404 platform.
5
-
6
-
- compatible:
7
-
Usage: required
8
-
Value type: <string>
9
-
Definition: must be "qcom,sm8150-pinctrl"
10
-
11
-
- reg:
12
-
Usage: required
13
-
Value type: <prop-encoded-array>
14
-
Definition: the base address and size of the north, south, west
15
-
and east TLMM tiles.
16
-
17
-
- reg-names:
18
-
Usage: required
19
-
Value type: <prop-encoded-array>
20
-
Defintiion: names for the cells of reg, must contain "north", "south"
21
-
"west" and "east".
22
-
23
-
- interrupts:
24
-
Usage: required
25
-
Value type: <prop-encoded-array>
26
-
Definition: should specify the TLMM summary IRQ.
27
-
28
-
- interrupt-controller:
29
-
Usage: required
30
-
Value type: <none>
31
-
Definition: identifies this node as an interrupt controller
32
-
33
-
- #interrupt-cells:
34
-
Usage: required
35
-
Value type: <u32>
36
-
Definition: must be 2. Specifying the pin number and flags, as defined
37
-
in <dt-bindings/interrupt-controller/irq.h>
38
-
39
-
- gpio-controller:
40
-
Usage: required
41
-
Value type: <none>
42
-
Definition: identifies this node as a gpio controller
43
-
44
-
- #gpio-cells:
45
-
Usage: required
46
-
Value type: <u32>
47
-
Definition: must be 2. Specifying the pin number and flags, as defined
48
-
in <dt-bindings/gpio/gpio.h>
49
-
50
-
- gpio-ranges:
51
-
Usage: required
52
-
Value type: <prop-encoded-array>
53
-
Definition: see ../gpio/gpio.txt
54
-
55
-
- gpio-reserved-ranges:
56
-
Usage: optional
57
-
Value type: <prop-encoded-array>
58
-
Definition: see ../gpio/gpio.txt
59
-
60
-
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
61
-
a general description of GPIO and interrupt bindings.
62
-
63
-
Please refer to pinctrl-bindings.txt in this directory for details of the
64
-
common pinctrl bindings used by client devices, including the meaning of the
65
-
phrase "pin configuration node".
66
-
67
-
The pin configuration nodes act as a container for an arbitrary number of
68
-
subnodes. Each of these subnodes represents some desired configuration for a
69
-
pin, a group, or a list of pins or groups. This configuration can include the
70
-
mux function to select on those pin(s)/group(s), and various pin configuration
71
-
parameters, such as pull-up, drive strength, etc.
72
-
73
-
74
-
PIN CONFIGURATION NODES:
75
-
76
-
The name of each subnode is not important; all subnodes should be enumerated
77
-
and processed purely based on their content.
78
-
79
-
Each subnode only affects those parameters that are explicitly listed. In
80
-
other words, a subnode that lists a mux function but no pin configuration
81
-
parameters implies no information about any pin configuration parameters.
82
-
Similarly, a pin subnode that describes a pullup parameter implies no
83
-
information about e.g. the mux function.
84
-
85
-
86
-
The following generic properties as defined in pinctrl-bindings.txt are valid
87
-
to specify in a pin configuration subnode:
88
-
89
-
- pins:
90
-
Usage: required
91
-
Value type: <string-array>
92
-
Definition: List of gpio pins affected by the properties specified in
93
-
this subnode.
94
-
95
-
Valid pins are:
96
-
gpio0-gpio149
97
-
Supports mux, bias and drive-strength
98
-
99
-
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
100
-
sdc2_data sdc1_rclk
101
-
Supports bias and drive-strength
102
-
103
-
ufs_reset
104
-
Supports bias and drive-strength
105
-
106
-
- function:
107
-
Usage: required
108
-
Value type: <string>
109
-
Definition: Specify the alternative function to be configured for the
110
-
specified pins. Functions are only valid for gpio pins.
111
-
Valid values are:
112
-
113
-
adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
114
-
atest_char0, atest_char1, atest_char2, atest_char3,
115
-
audio_ref, atest_usb1, atest_usb2, atest_usb10,
116
-
atest_usb11, atest_usb12, atest_usb13, atest_usb20,
117
-
atest_usb21, atest_usb22, atest_usb2, atest_usb23,
118
-
btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
119
-
cci_timer1, cci_timer2, cci_timer3, cci_timer4,
120
-
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
121
-
ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
122
-
emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
123
-
hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
124
-
lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
125
-
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
126
-
pa_indicator, pci_e0, phase_flag, pll_bypassnl,
127
-
pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
128
-
prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
129
-
qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
130
-
qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
131
-
qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
132
-
qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
133
-
sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
134
-
tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
135
-
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
136
-
usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
137
-
wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
138
-
139
-
- bias-disable:
140
-
Usage: optional
141
-
Value type: <none>
142
-
Definition: The specified pins should be configued as no pull.
143
-
144
-
- bias-pull-down:
145
-
Usage: optional
146
-
Value type: <none>
147
-
Definition: The specified pins should be configued as pull down.
148
-
149
-
- bias-pull-up:
150
-
Usage: optional
151
-
Value type: <none>
152
-
Definition: The specified pins should be configued as pull up.
153
-
154
-
- output-high:
155
-
Usage: optional
156
-
Value type: <none>
157
-
Definition: The specified pins are configured in output mode, driven
158
-
high.
159
-
Not valid for sdc pins.
160
-
161
-
- output-low:
162
-
Usage: optional
163
-
Value type: <none>
164
-
Definition: The specified pins are configured in output mode, driven
165
-
low.
166
-
Not valid for sdc pins.
167
-
168
-
- drive-strength:
169
-
Usage: optional
170
-
Value type: <u32>
171
-
Definition: Selects the drive strength for the specified pins, in mA.
172
-
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
173
-
174
-
Example:
175
-
176
-
tlmm: pinctrl@3000000 {
177
-
compatible = "qcom,sm8150-pinctrl";
178
-
reg = <0x03100000 0x300000>,
179
-
<0x03500000 0x300000>,
180
-
<0x03900000 0x300000>,
181
-
<0x03D00000 0x300000>;
182
-
reg-names = "west", "east", "north", "south";
183
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
184
-
gpio-controller;
185
-
#gpio-cells = <2>;
186
-
gpio-ranges = <&tlmm 0 0 175>;
187
-
gpio-reserved-ranges = <0 4>, <126 4>;
188
-
interrupt-controller;
189
-
#interrupt-cells = <2>;
190
-
};
+173
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
+173
Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SM8150 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,sm8150-pinctrl
19
+
20
+
reg:
21
+
maxItems: 4
22
+
23
+
reg-names:
24
+
items:
25
+
- const: west
26
+
- const: east
27
+
- const: north
28
+
- const: south
29
+
30
+
interrupts: true
31
+
interrupt-controller: true
32
+
"#interrupt-cells": true
33
+
gpio-controller: true
34
+
"#gpio-cells": true
35
+
gpio-ranges: true
36
+
wakeup-parent: true
37
+
38
+
gpio-reserved-ranges:
39
+
minItems: 1
40
+
maxItems: 88
41
+
42
+
gpio-line-names:
43
+
maxItems: 175
44
+
45
+
patternProperties:
46
+
"-state$":
47
+
oneOf:
48
+
- $ref: "#/$defs/qcom-sm8150-tlmm-state"
49
+
- patternProperties:
50
+
"-pins$":
51
+
$ref: "#/$defs/qcom-sm8150-tlmm-state"
52
+
additionalProperties: false
53
+
54
+
$defs:
55
+
qcom-sm8150-tlmm-state:
56
+
type: object
57
+
description:
58
+
Pinctrl node's client devices use subnodes for desired pin configuration.
59
+
Client device subnodes use below standard properties.
60
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
61
+
62
+
properties:
63
+
pins:
64
+
description:
65
+
List of gpio pins affected by the properties specified in this
66
+
subnode.
67
+
items:
68
+
oneOf:
69
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
70
+
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
71
+
minItems: 1
72
+
maxItems: 36
73
+
74
+
function:
75
+
description:
76
+
Specify the alternative function to be configured for the specified
77
+
pins.
78
+
79
+
enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
80
+
atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
81
+
atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
82
+
atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
83
+
atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
84
+
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
85
+
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
86
+
ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
87
+
gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
88
+
jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
89
+
mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
90
+
pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
91
+
pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
92
+
qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
93
+
qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
94
+
qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
95
+
qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
96
+
qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
97
+
ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
98
+
tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
99
+
usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
100
+
wlan2_adc0, wlan2_adc1, wmss_reset ]
101
+
102
+
bias-pull-down: true
103
+
bias-pull-up: true
104
+
bias-disable: true
105
+
drive-strength: true
106
+
input-enable: true
107
+
output-high: true
108
+
output-low: true
109
+
110
+
required:
111
+
- pins
112
+
113
+
additionalProperties: false
114
+
115
+
allOf:
116
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
117
+
118
+
required:
119
+
- compatible
120
+
- reg
121
+
- reg-names
122
+
123
+
additionalProperties: false
124
+
125
+
examples:
126
+
- |
127
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
128
+
129
+
tlmm: pinctrl@3100000 {
130
+
compatible = "qcom,sm8150-pinctrl";
131
+
reg = <0x03100000 0x300000>,
132
+
<0x03500000 0x300000>,
133
+
<0x03900000 0x300000>,
134
+
<0x03d00000 0x300000>;
135
+
reg-names = "west", "east", "north", "south";
136
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
137
+
gpio-ranges = <&tlmm 0 0 176>;
138
+
gpio-controller;
139
+
#gpio-cells = <2>;
140
+
interrupt-controller;
141
+
#interrupt-cells = <2>;
142
+
wakeup-parent = <&pdc>;
143
+
144
+
qup-spi0-default-state {
145
+
pins = "gpio0", "gpio1", "gpio2", "gpio3";
146
+
function = "qup0";
147
+
drive-strength = <6>;
148
+
bias-disable;
149
+
};
150
+
151
+
pcie1-default-state {
152
+
perst-pins {
153
+
pins = "gpio102";
154
+
function = "gpio";
155
+
drive-strength = <2>;
156
+
bias-pull-down;
157
+
};
158
+
159
+
clkreq-pins {
160
+
pins = "gpio103";
161
+
function = "pci_e1";
162
+
drive-strength = <2>;
163
+
bias-pull-up;
164
+
};
165
+
166
+
wake-pins {
167
+
pins = "gpio104";
168
+
function = "gpio";
169
+
drive-strength = <2>;
170
+
bias-pull-up;
171
+
};
172
+
};
173
+
};
+43
-15
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
+43
-15
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
···
4
4
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8
-
Low Power Island (LPI) TLMM block
7
+
title: Qualcomm SM8250 SoC LPASS LPI TLMM
9
8
10
9
maintainers:
11
10
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
11
13
-
description: |
14
-
This binding describes the Top Level Mode Multiplexer block found in the
15
-
LPASS LPI IP on most Qualcomm SoCs
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
16
15
17
16
properties:
18
17
compatible:
19
18
const: qcom,sm8250-lpass-lpi-pinctrl
20
19
21
20
reg:
22
-
minItems: 2
23
21
maxItems: 2
24
22
25
23
clocks:
···
32
34
33
35
gpio-controller: true
34
36
35
-
'#gpio-cells':
37
+
"#gpio-cells":
36
38
description: Specifying the pin number and flags, as defined in
37
39
include/dt-bindings/gpio/gpio.h
38
40
const: 2
···
40
42
gpio-ranges:
41
43
maxItems: 1
42
44
43
-
#PIN CONFIGURATION NODES
44
45
patternProperties:
45
-
'-pins$':
46
+
"-state$":
47
+
oneOf:
48
+
- $ref: "#/$defs/qcom-sm8250-lpass-state"
49
+
- patternProperties:
50
+
"-pins$":
51
+
$ref: "#/$defs/qcom-sm8250-lpass-state"
52
+
additionalProperties: false
53
+
54
+
$defs:
55
+
qcom-sm8250-lpass-state:
46
56
type: object
47
57
description:
48
58
Pinctrl node's client devices use subnodes for desired pin configuration.
···
94
88
3: Reserved (No adjustments)
95
89
96
90
bias-pull-down: true
97
-
98
91
bias-pull-up: true
99
-
92
+
bias-bus-hold: true
100
93
bias-disable: true
101
-
94
+
input-enable: true
102
95
output-high: true
103
-
104
96
output-low: true
105
97
106
98
required:
···
108
104
additionalProperties: false
109
105
110
106
allOf:
111
-
- $ref: "pinctrl.yaml#"
107
+
- $ref: pinctrl.yaml#
112
108
113
109
required:
114
110
- compatible
···
116
112
- clocks
117
113
- clock-names
118
114
- gpio-controller
119
-
- '#gpio-cells'
115
+
- "#gpio-cells"
120
116
- gpio-ranges
121
117
122
118
additionalProperties: false
···
134
130
gpio-controller;
135
131
#gpio-cells = <2>;
136
132
gpio-ranges = <&lpi_tlmm 0 0 14>;
133
+
134
+
wsa-swr-active-state {
135
+
clk-pins {
136
+
pins = "gpio10";
137
+
function = "wsa_swr_clk";
138
+
drive-strength = <2>;
139
+
slew-rate = <1>;
140
+
bias-disable;
141
+
};
142
+
143
+
data-pins {
144
+
pins = "gpio11";
145
+
function = "wsa_swr_data";
146
+
drive-strength = <2>;
147
+
slew-rate = <1>;
148
+
};
149
+
};
150
+
151
+
tx-swr-sleep-clk-state {
152
+
pins = "gpio0";
153
+
function = "swr_tx_clk";
154
+
drive-strength = <2>;
155
+
bias-pull-down;
156
+
};
137
157
};
+85
-109
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
+85
-109
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
···
9
9
maintainers:
10
10
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer block found in the
14
-
SM8250 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
15
14
16
15
properties:
17
16
compatible:
18
17
const: qcom,sm8250-pinctrl
19
18
20
19
reg:
21
-
minItems: 3
22
20
maxItems: 3
23
21
24
22
reg-names:
25
23
items:
26
-
- const: "west"
27
-
- const: "south"
28
-
- const: "north"
24
+
- const: west
25
+
- const: south
26
+
- const: north
29
27
30
-
interrupts:
31
-
description: Specifies the TLMM summary IRQ
32
-
maxItems: 1
33
-
28
+
interrupts: true
34
29
interrupt-controller: true
35
-
36
-
'#interrupt-cells':
37
-
description:
38
-
Specifies the PIN numbers and Flags, as defined in defined in
39
-
include/dt-bindings/interrupt-controller/irq.h
40
-
const: 2
41
-
30
+
"#interrupt-cells": true
42
31
gpio-controller: true
43
-
44
-
'#gpio-cells':
45
-
description: Specifying the pin number and flags, as defined in
46
-
include/dt-bindings/gpio/gpio.h
47
-
const: 2
48
-
49
-
gpio-ranges:
50
-
maxItems: 1
51
-
32
+
"#gpio-cells": true
33
+
gpio-ranges: true
52
34
wakeup-parent: true
53
35
54
-
#PIN CONFIGURATION NODES
36
+
gpio-reserved-ranges:
37
+
minItems: 1
38
+
maxItems: 90
39
+
40
+
gpio-line-names:
41
+
maxItems: 180
42
+
55
43
patternProperties:
56
-
'^.*$':
57
-
if:
58
-
type: object
59
-
then:
60
-
properties:
61
-
pins:
62
-
description:
63
-
List of gpio pins affected by the properties specified in this
64
-
subnode.
65
-
items:
66
-
oneOf:
67
-
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
68
-
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
69
-
minItems: 1
70
-
maxItems: 36
44
+
"-state$":
45
+
oneOf:
46
+
- $ref: "#/$defs/qcom-sm8250-tlmm-state"
47
+
- patternProperties:
48
+
"-pins$":
49
+
$ref: "#/$defs/qcom-sm8250-tlmm-state"
50
+
additionalProperties: false
71
51
72
-
function:
73
-
description:
74
-
Specify the alternative function to be configured for the specified
75
-
pins.
52
+
$defs:
53
+
qcom-sm8250-tlmm-state:
54
+
type: object
55
+
description:
56
+
Pinctrl node's client devices use subnodes for desired pin configuration.
57
+
Client device subnodes use below standard properties.
58
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
76
59
77
-
enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
78
-
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
79
-
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
80
-
ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
81
-
ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
82
-
mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
83
-
mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
84
-
mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
85
-
pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
86
-
pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
87
-
qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
88
-
qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
89
-
qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
90
-
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
91
-
tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
92
-
tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
93
-
tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
60
+
properties:
61
+
pins:
62
+
description:
63
+
List of gpio pins affected by the properties specified in this
64
+
subnode.
65
+
items:
66
+
oneOf:
67
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
68
+
- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
69
+
minItems: 1
70
+
maxItems: 36
94
71
95
-
drive-strength:
96
-
enum: [2, 4, 6, 8, 10, 12, 14, 16]
97
-
default: 2
98
-
description:
99
-
Selects the drive strength for the specified pins, in mA.
72
+
function:
73
+
description:
74
+
Specify the alternative function to be configured for the specified
75
+
pins.
100
76
101
-
bias-pull-down: true
77
+
enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
78
+
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
79
+
cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
80
+
ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
81
+
ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
82
+
mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
83
+
mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
84
+
mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
85
+
pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
86
+
pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
87
+
qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
88
+
qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
89
+
qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
90
+
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
91
+
tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
92
+
tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
93
+
tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
102
94
103
-
bias-pull-up: true
95
+
bias-pull-down: true
96
+
bias-pull-up: true
97
+
bias-disable: true
98
+
drive-strength: true
99
+
input-enable: true
100
+
output-high: true
101
+
output-low: true
104
102
105
-
bias-disable: true
103
+
required:
104
+
- pins
106
105
107
-
output-high: true
108
-
109
-
output-low: true
110
-
111
-
required:
112
-
- pins
113
-
114
-
allOf:
115
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
116
-
- if:
117
-
properties:
118
-
pins:
119
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
120
-
then:
121
-
required:
122
-
- function
123
-
124
-
additionalProperties: false
106
+
additionalProperties: false
125
107
126
108
allOf:
127
-
- $ref: "pinctrl.yaml#"
109
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
128
110
129
111
required:
130
112
- compatible
131
113
- reg
132
114
- reg-names
133
-
- interrupts
134
-
- interrupt-controller
135
-
- '#interrupt-cells'
136
-
- gpio-controller
137
-
- '#gpio-cells'
138
-
- gpio-ranges
139
115
140
116
additionalProperties: false
141
117
···
119
143
- |
120
144
#include <dt-bindings/interrupt-controller/arm-gic.h>
121
145
pinctrl@1f00000 {
122
-
compatible = "qcom,sm8250-pinctrl";
123
-
reg = <0x0f100000 0x300000>,
124
-
<0x0f500000 0x300000>,
125
-
<0x0f900000 0x300000>;
126
-
reg-names = "west", "south", "north";
127
-
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
128
-
gpio-controller;
129
-
#gpio-cells = <2>;
130
-
interrupt-controller;
131
-
#interrupt-cells = <2>;
132
-
gpio-ranges = <&tlmm 0 0 180>;
133
-
wakeup-parent = <&pdc>;
146
+
compatible = "qcom,sm8250-pinctrl";
147
+
reg = <0x0f100000 0x300000>,
148
+
<0x0f500000 0x300000>,
149
+
<0x0f900000 0x300000>;
150
+
reg-names = "west", "south", "north";
151
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
152
+
gpio-controller;
153
+
#gpio-cells = <2>;
154
+
interrupt-controller;
155
+
#interrupt-cells = <2>;
156
+
gpio-ranges = <&tlmm 0 0 180>;
157
+
wakeup-parent = <&pdc>;
134
158
};
+7
-18
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml
+7
-18
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SM8350 TLMM block
···
9
9
maintainers:
10
10
- Vinod Koul <vkoul@kernel.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer (TLMM) block found
14
-
in the SM8350 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC.
15
14
16
15
allOf:
17
-
- $ref: "pinctrl.yaml#"
18
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19
17
20
18
properties:
···
24
26
25
27
interrupts: true
26
28
interrupt-controller: true
27
-
'#interrupt-cells': true
29
+
"#interrupt-cells": true
28
30
gpio-controller: true
29
31
gpio-reserved-ranges: true
30
-
'#gpio-cells': true
32
+
"#gpio-cells": true
31
33
gpio-ranges: true
32
34
wakeup-parent: true
33
35
···
38
40
additionalProperties: false
39
41
40
42
patternProperties:
41
-
'-state$':
43
+
"-state$":
42
44
oneOf:
43
45
- $ref: "#/$defs/qcom-sm8350-tlmm-state"
44
46
- patternProperties:
···
52
54
description:
53
55
Pinctrl node's client devices use subnodes for desired pin configuration.
54
56
Client device subnodes use below standard properties.
57
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
58
56
59
properties:
57
60
pins:
···
106
107
107
108
required:
108
109
- pins
109
-
110
-
allOf:
111
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
112
-
- if:
113
-
properties:
114
-
pins:
115
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
116
-
then:
117
-
required:
118
-
- function
119
110
120
111
additionalProperties: false
121
112
+41
-10
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+41
-10
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
···
4
4
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8
-
Low Power Island (LPI) TLMM block
7
+
title: Qualcomm SM8450 SoC LPASS LPI TLMM
9
8
10
9
maintainers:
11
10
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
12
11
13
-
description: |
14
-
This binding describes the Top Level Mode Multiplexer block found in the
15
-
LPASS LPI IP on most Qualcomm SoCs
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
16
15
17
16
properties:
18
17
compatible:
···
34
35
35
36
gpio-controller: true
36
37
37
-
'#gpio-cells':
38
+
"#gpio-cells":
38
39
description: Specifying the pin number and flags, as defined in
39
40
include/dt-bindings/gpio/gpio.h
40
41
const: 2
···
42
43
gpio-ranges:
43
44
maxItems: 1
44
45
45
-
#PIN CONFIGURATION NODES
46
46
patternProperties:
47
-
'-pins$':
47
+
"-state$":
48
+
oneOf:
49
+
- $ref: "#/$defs/qcom-sm8450-lpass-state"
50
+
- patternProperties:
51
+
"-pins$":
52
+
$ref: "#/$defs/qcom-sm8450-lpass-state"
53
+
additionalProperties: false
54
+
55
+
$defs:
56
+
qcom-sm8450-lpass-state:
48
57
type: object
49
58
description:
50
59
Pinctrl node's client devices use subnodes for desired pin configuration.
···
65
58
List of gpio pins affected by the properties specified in this
66
59
subnode.
67
60
items:
68
-
pattern: "^gpio([0-9]|[1-2][0-9]])$"
61
+
pattern: "^gpio([0-9]|[1-2][0-9])$"
69
62
70
63
function:
71
64
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
···
121
114
- clocks
122
115
- clock-names
123
116
- gpio-controller
124
-
- '#gpio-cells'
117
+
- "#gpio-cells"
125
118
- gpio-ranges
126
119
127
120
additionalProperties: false
···
139
132
gpio-controller;
140
133
#gpio-cells = <2>;
141
134
gpio-ranges = <&lpi_tlmm 0 0 23>;
135
+
136
+
wsa-swr-active-state {
137
+
clk-pins {
138
+
pins = "gpio10";
139
+
function = "wsa_swr_clk";
140
+
drive-strength = <2>;
141
+
slew-rate = <1>;
142
+
bias-disable;
143
+
};
144
+
145
+
data-pins {
146
+
pins = "gpio11";
147
+
function = "wsa_swr_data";
148
+
drive-strength = <2>;
149
+
slew-rate = <1>;
150
+
};
151
+
};
152
+
153
+
tx-swr-sleep-clk-state {
154
+
pins = "gpio0";
155
+
function = "swr_tx_clk";
156
+
drive-strength = <2>;
157
+
bias-pull-down;
158
+
};
142
159
};
+7
-17
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml
+7
-17
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml
···
1
1
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
2
%YAML 1.2
3
3
---
4
-
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
7
title: Qualcomm Technologies, Inc. SM8450 TLMM block
···
9
9
maintainers:
10
10
- Vinod Koul <vkoul@kernel.org>
11
11
12
-
description: |
13
-
This binding describes the Top Level Mode Multiplexer (TLMM) block found
14
-
in the SM8450 platform.
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
15
14
16
15
allOf:
17
16
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
···
24
25
25
26
interrupts: true
26
27
interrupt-controller: true
27
-
'#interrupt-cells': true
28
+
"#interrupt-cells": true
28
29
gpio-controller: true
29
30
30
31
gpio-reserved-ranges:
···
34
35
gpio-line-names:
35
36
maxItems: 209
36
37
37
-
'#gpio-cells': true
38
+
"#gpio-cells": true
38
39
gpio-ranges: true
39
40
wakeup-parent: true
40
41
···
45
46
additionalProperties: false
46
47
47
48
patternProperties:
48
-
'-state$':
49
+
"-state$":
49
50
oneOf:
50
51
- $ref: "#/$defs/qcom-sm8450-tlmm-state"
51
52
- patternProperties:
···
59
60
description:
60
61
Pinctrl node's client devices use subnodes for desired pin configuration.
61
62
Client device subnodes use below standard properties.
63
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
62
64
63
65
properties:
64
66
pins:
···
111
111
112
112
required:
113
113
- pins
114
-
115
-
allOf:
116
-
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
117
-
- if:
118
-
properties:
119
-
pins:
120
-
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
121
-
then:
122
-
required:
123
-
- function
124
114
125
115
additionalProperties: false
126
116
+16
-4
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
+16
-4
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml
···
65
65
66
66
$defs:
67
67
qcom-tlmm-state:
68
-
allOf:
69
-
- $ref: pincfg-node.yaml#
70
-
- $ref: pinmux-node.yaml#
71
-
72
68
properties:
73
69
drive-strength:
74
70
enum: [2, 4, 6, 8, 10, 12, 14, 16]
···
77
81
input-enable: true
78
82
output-high: true
79
83
output-low: true
84
+
85
+
allOf:
86
+
- $ref: pincfg-node.yaml#
87
+
- $ref: pinmux-node.yaml#
88
+
89
+
- if:
90
+
properties:
91
+
pins:
92
+
items:
93
+
pattern: "^gpio"
94
+
then:
95
+
required:
96
+
- function
97
+
else:
98
+
properties:
99
+
function: false
80
100
81
101
additionalProperties: true
82
102
...
+1
-1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+1
-1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+208
Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml
+208
Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright 2022 Linaro Ltd.
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Semtech SX150x GPIO expander
9
+
10
+
maintainers:
11
+
- Neil Armstrong <neil.armstrong@linaro.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- semtech,sx1501q
17
+
- semtech,sx1502q
18
+
- semtech,sx1503q
19
+
- semtech,sx1504q
20
+
- semtech,sx1505q
21
+
- semtech,sx1506q
22
+
- semtech,sx1507q
23
+
- semtech,sx1508q
24
+
- semtech,sx1509q
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
'#interrupt-cells':
33
+
const: 2
34
+
35
+
interrupt-controller: true
36
+
37
+
'#gpio-cells':
38
+
const: 2
39
+
40
+
gpio-controller: true
41
+
42
+
semtech,probe-reset:
43
+
description: Will trigger a reset of the GPIO expander on probe
44
+
type: boolean
45
+
46
+
patternProperties:
47
+
'-cfg$':
48
+
type: object
49
+
properties:
50
+
pins: true
51
+
52
+
bias-disable: true
53
+
bias-pull-up: true
54
+
bias-pull-down: true
55
+
bias-pull-pin-default: true
56
+
drive-push-pull: true
57
+
output-low: true
58
+
output-high: true
59
+
drive-open-drain: true
60
+
61
+
required:
62
+
- pins
63
+
64
+
allOf:
65
+
- $ref: "pincfg-node.yaml#"
66
+
- $ref: "pinmux-node.yaml#"
67
+
- if:
68
+
properties:
69
+
pins:
70
+
contains:
71
+
const: oscio
72
+
then:
73
+
properties:
74
+
bias-disable: false
75
+
bias-pull-up: false
76
+
bias-pull-down: false
77
+
bias-pull-pin-default: false
78
+
drive-open-drain: false
79
+
80
+
additionalProperties: false
81
+
82
+
required:
83
+
- compatible
84
+
- reg
85
+
- '#gpio-cells'
86
+
- gpio-controller
87
+
88
+
allOf:
89
+
- $ref: "pinctrl.yaml#"
90
+
- if:
91
+
not:
92
+
properties:
93
+
compatible:
94
+
contains:
95
+
enum:
96
+
- semtech,sx1507q
97
+
- semtech,sx1508q
98
+
- semtech,sx1509q
99
+
then:
100
+
properties:
101
+
semtech,probe-reset: false
102
+
- if:
103
+
properties:
104
+
compatible:
105
+
contains:
106
+
enum:
107
+
- semtech,sx1501q
108
+
- semtech,sx1504q
109
+
then:
110
+
patternProperties:
111
+
'-cfg$':
112
+
properties:
113
+
pins:
114
+
items:
115
+
pattern: '^gpio[0-3]$'
116
+
- if:
117
+
properties:
118
+
compatible:
119
+
contains:
120
+
enum:
121
+
- semtech,sx1502q
122
+
- semtech,sx1505q
123
+
then:
124
+
patternProperties:
125
+
'-cfg$':
126
+
properties:
127
+
pins:
128
+
items:
129
+
pattern: '^gpio[0-7]$'
130
+
- if:
131
+
properties:
132
+
compatible:
133
+
contains:
134
+
enum:
135
+
- semtech,sx1503q
136
+
- semtech,sx1506q
137
+
then:
138
+
patternProperties:
139
+
'-cfg$':
140
+
properties:
141
+
pins:
142
+
items:
143
+
pattern: '^(gpio[0-9]|gpio1[0-5])$'
144
+
- if:
145
+
properties:
146
+
compatible:
147
+
contains:
148
+
const: semtech,sx1507q
149
+
then:
150
+
patternProperties:
151
+
'-cfg$':
152
+
properties:
153
+
pins:
154
+
items:
155
+
pattern: '^(oscio|gpio[0-3])$'
156
+
- if:
157
+
properties:
158
+
compatible:
159
+
contains:
160
+
const: semtech,sx1508q
161
+
then:
162
+
patternProperties:
163
+
'-cfg$':
164
+
properties:
165
+
pins:
166
+
items:
167
+
pattern: '^(oscio|gpio[0-7])$'
168
+
- if:
169
+
properties:
170
+
compatible:
171
+
contains:
172
+
const: semtech,sx1509q
173
+
then:
174
+
patternProperties:
175
+
'-cfg$':
176
+
properties:
177
+
pins:
178
+
items:
179
+
pattern: '^(oscio|gpio[0-9]|gpio1[0-5])$'
180
+
181
+
additionalProperties: false
182
+
183
+
examples:
184
+
- |
185
+
#include <dt-bindings/interrupt-controller/irq.h>
186
+
i2c@1000 {
187
+
reg = <0x1000 0x80>;
188
+
#address-cells = <1>;
189
+
#size-cells = <0>;
190
+
191
+
pinctrl@20 {
192
+
compatible = "semtech,sx1501q";
193
+
reg = <0x20>;
194
+
195
+
#gpio-cells = <2>;
196
+
#interrupt-cells = <2>;
197
+
198
+
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
199
+
200
+
gpio-controller;
201
+
interrupt-controller;
202
+
203
+
gpio1-cfg {
204
+
pins = "gpio1";
205
+
bias-pull-up;
206
+
};
207
+
};
208
+
};
+3
-4
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+3
-4
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
···
34
34
const: 1
35
35
36
36
ranges: true
37
-
pins-are-numbered: true
37
+
pins-are-numbered:
38
+
$ref: /schemas/types.yaml#/definitions/flag
39
+
deprecated: true
38
40
hwlocks: true
39
41
40
42
interrupts:
···
208
206
- '#address-cells'
209
207
- '#size-cells'
210
208
- ranges
211
-
- pins-are-numbered
212
209
213
210
additionalProperties: false
214
211
···
221
220
#size-cells = <1>;
222
221
compatible = "st,stm32f429-pinctrl";
223
222
ranges = <0 0x40020000 0x3000>;
224
-
pins-are-numbered;
225
223
226
224
gpioa: gpio@0 {
227
225
gpio-controller;
···
238
238
#size-cells = <1>;
239
239
compatible = "st,stm32f429-pinctrl";
240
240
ranges = <0 0x50020000 0x3000>;
241
-
pins-are-numbered;
242
241
243
242
gpiob: gpio@1000 {
244
243
gpio-controller;
+3
Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+3
Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+2
Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
+2
Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
+5
-5
Documentation/driver-api/pin-control.rst
+5
-5
Documentation/driver-api/pin-control.rst
···
1238
1238
return PTR_ERR(foo->s);
1239
1239
}
1240
1240
1241
-
ret = pinctrl_select_state(foo->s);
1241
+
ret = pinctrl_select_state(foo->p, foo->s);
1242
1242
if (ret < 0) {
1243
1243
/* FIXME: clean up "foo" here */
1244
1244
return ret;
···
1399
1399
if (IS_ERR(p))
1400
1400
...
1401
1401
1402
-
s1 = pinctrl_lookup_state(foo->p, "pos-A");
1402
+
s1 = pinctrl_lookup_state(p, "pos-A");
1403
1403
if (IS_ERR(s1))
1404
1404
...
1405
1405
1406
-
s2 = pinctrl_lookup_state(foo->p, "pos-B");
1406
+
s2 = pinctrl_lookup_state(p, "pos-B");
1407
1407
if (IS_ERR(s2))
1408
1408
...
1409
1409
}
···
1411
1411
foo_switch()
1412
1412
{
1413
1413
/* Enable on position A */
1414
-
ret = pinctrl_select_state(s1);
1414
+
ret = pinctrl_select_state(p, s1);
1415
1415
if (ret < 0)
1416
1416
...
1417
1417
1418
1418
...
1419
1419
1420
1420
/* Enable on position B */
1421
-
ret = pinctrl_select_state(s2);
1421
+
ret = pinctrl_select_state(p, s2);
1422
1422
if (ret < 0)
1423
1423
...
1424
1424
+9
-1
MAINTAINERS
+9
-1
MAINTAINERS
···
12093
12093
F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml
12094
12094
F: drivers/soc/loongson/loongson2_guts.c
12095
12095
12096
+
LOONGSON-2 SOC SERIES PINCTRL DRIVER
12097
+
M: zhanghongchen <zhanghongchen@loongson.cn>
12098
+
M: Yinbo Zhu <zhuyinbo@loongson.cn>
12099
+
L: linux-gpio@vger.kernel.org
12100
+
S: Maintained
12101
+
F: Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml
12102
+
F: drivers/pinctrl/pinctrl-loongson2.c
12103
+
12096
12104
LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
12097
12105
M: Sathya Prakash <sathya.prakash@broadcom.com>
12098
12106
M: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
···
16411
16403
L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
16412
16404
S: Maintained
16413
16405
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
16414
-
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml
16406
+
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
16415
16407
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
16416
16408
F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
16417
16409
F: drivers/pinctrl/mediatek/
+3
-4
drivers/gpio/gpio-arizona.c
+3
-4
drivers/gpio/gpio-arizona.c
···
7
7
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8
8
*/
9
9
10
-
#include <linux/kernel.h>
11
-
#include <linux/slab.h>
12
-
#include <linux/module.h>
13
10
#include <linux/gpio/driver.h>
11
+
#include <linux/kernel.h>
12
+
#include <linux/module.h>
14
13
#include <linux/platform_device.h>
15
14
#include <linux/pm_runtime.h>
16
-
#include <linux/seq_file.h>
15
+
#include <linux/slab.h>
17
16
18
17
#include <linux/mfd/arizona/core.h>
19
18
#include <linux/mfd/arizona/pdata.h>
+3
-2
drivers/gpio/gpio-aspeed.c
+3
-2
drivers/gpio/gpio-aspeed.c
···
5
5
* Joel Stanley <joel@jms.id.au>
6
6
*/
7
7
8
-
#include <asm/div64.h>
9
8
#include <linux/clk.h>
10
-
#include <linux/gpio/driver.h>
11
9
#include <linux/gpio/aspeed.h>
10
+
#include <linux/gpio/driver.h>
12
11
#include <linux/hashtable.h>
13
12
#include <linux/init.h>
14
13
#include <linux/io.h>
···
17
18
#include <linux/platform_device.h>
18
19
#include <linux/spinlock.h>
19
20
#include <linux/string.h>
21
+
22
+
#include <asm/div64.h>
20
23
21
24
/*
22
25
* These two headers aren't meant to be used by GPIO drivers. We need
+4
-5
drivers/gpio/gpio-da9052.c
+4
-5
drivers/gpio/gpio-da9052.c
···
6
6
*
7
7
* Author: David Dajun Chen <dchen@diasemi.com>
8
8
*/
9
-
#include <linux/module.h>
10
9
#include <linux/fs.h>
11
-
#include <linux/uaccess.h>
12
-
#include <linux/platform_device.h>
13
10
#include <linux/gpio/driver.h>
11
+
#include <linux/module.h>
12
+
#include <linux/platform_device.h>
14
13
#include <linux/syscalls.h>
15
-
#include <linux/seq_file.h>
14
+
#include <linux/uaccess.h>
16
15
17
16
#include <linux/mfd/da9052/da9052.h>
18
-
#include <linux/mfd/da9052/reg.h>
19
17
#include <linux/mfd/da9052/pdata.h>
18
+
#include <linux/mfd/da9052/reg.h>
20
19
21
20
#define DA9052_INPUT 1
22
21
#define DA9052_OUTPUT_OPENDRAIN 2
+1
drivers/gpio/gpio-mockup.c
+1
drivers/gpio/gpio-mockup.c
+91
-1
drivers/gpio/gpio-mxc.c
+91
-1
drivers/gpio/gpio-mxc.c
···
24
24
#include <linux/of_device.h>
25
25
#include <linux/bug.h>
26
26
27
+
#define IMX_SCU_WAKEUP_OFF 0
28
+
#define IMX_SCU_WAKEUP_LOW_LVL 4
29
+
#define IMX_SCU_WAKEUP_FALL_EDGE 5
30
+
#define IMX_SCU_WAKEUP_RISE_EDGE 6
31
+
#define IMX_SCU_WAKEUP_HIGH_LVL 7
32
+
27
33
/* device type dependent stuff */
28
34
struct mxc_gpio_hwdata {
29
35
unsigned dr_reg;
···
67
61
u32 both_edges;
68
62
struct mxc_gpio_reg_saved gpio_saved_reg;
69
63
bool power_off;
64
+
u32 wakeup_pads;
65
+
bool is_pad_wakeup;
66
+
u32 pad_type[32];
70
67
const struct mxc_gpio_hwdata *hwdata;
71
68
};
72
69
···
139
130
{ .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
140
131
{ .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
141
132
{ .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
133
+
{ .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata },
134
+
{ .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata },
135
+
{ .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata },
142
136
{ /* sentinel */ }
143
137
};
144
138
MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
···
215
203
}
216
204
217
205
writel(1 << gpio_idx, port->base + GPIO_ISR);
206
+
port->pad_type[gpio_idx] = type;
218
207
219
208
return 0;
220
209
}
···
266
253
u32 irq_stat;
267
254
struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
268
255
struct irq_chip *chip = irq_desc_get_chip(desc);
256
+
257
+
if (port->is_pad_wakeup)
258
+
return;
269
259
270
260
chained_irq_enter(chip, desc);
271
261
···
322
306
ret = enable_irq_wake(port->irq_high);
323
307
else
324
308
ret = enable_irq_wake(port->irq);
309
+
port->wakeup_pads |= (1 << gpio_idx);
325
310
} else {
326
311
if (port->irq_high && (gpio_idx >= 16))
327
312
ret = disable_irq_wake(port->irq_high);
328
313
else
329
314
ret = disable_irq_wake(port->irq);
315
+
port->wakeup_pads &= ~(1 << gpio_idx);
330
316
}
331
317
332
318
return ret;
···
383
365
return -ENOMEM;
384
366
385
367
port->dev = &pdev->dev;
386
-
387
368
port->hwdata = device_get_match_data(&pdev->dev);
388
369
389
370
port->base = devm_platform_ioremap_resource(pdev, 0);
···
515
498
writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
516
499
}
517
500
501
+
static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
502
+
unsigned int offset, unsigned long conf)
503
+
{
504
+
struct device_node *np = port->dev->of_node;
505
+
506
+
if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
507
+
of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
508
+
of_device_is_compatible(np, "fsl,imx8qm-gpio"))
509
+
return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
510
+
511
+
return false;
512
+
}
513
+
514
+
static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
515
+
{
516
+
unsigned long config;
517
+
bool ret = false;
518
+
int i, type;
519
+
520
+
static const u32 pad_type_map[] = {
521
+
IMX_SCU_WAKEUP_OFF, /* 0 */
522
+
IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */
523
+
IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */
524
+
IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */
525
+
IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */
526
+
IMX_SCU_WAKEUP_OFF, /* 5 */
527
+
IMX_SCU_WAKEUP_OFF, /* 6 */
528
+
IMX_SCU_WAKEUP_OFF, /* 7 */
529
+
IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */
530
+
};
531
+
532
+
for (i = 0; i < 32; i++) {
533
+
if ((port->wakeup_pads & (1 << i))) {
534
+
type = port->pad_type[i];
535
+
if (enable)
536
+
config = pad_type_map[type];
537
+
else
538
+
config = IMX_SCU_WAKEUP_OFF;
539
+
ret |= mxc_gpio_generic_config(port, i, config);
540
+
}
541
+
}
542
+
543
+
return ret;
544
+
}
545
+
546
+
static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev)
547
+
{
548
+
struct platform_device *pdev = to_platform_device(dev);
549
+
struct mxc_gpio_port *port = platform_get_drvdata(pdev);
550
+
551
+
if (port->wakeup_pads > 0)
552
+
port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
553
+
554
+
return 0;
555
+
}
556
+
557
+
static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev)
558
+
{
559
+
struct platform_device *pdev = to_platform_device(dev);
560
+
struct mxc_gpio_port *port = platform_get_drvdata(pdev);
561
+
562
+
if (port->wakeup_pads > 0)
563
+
mxc_gpio_set_pad_wakeup(port, false);
564
+
port->is_pad_wakeup = false;
565
+
566
+
return 0;
567
+
}
568
+
569
+
static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
570
+
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
571
+
};
572
+
518
573
static int mxc_gpio_syscore_suspend(void)
519
574
{
520
575
struct mxc_gpio_port *port;
···
626
537
.name = "gpio-mxc",
627
538
.of_match_table = mxc_gpio_dt_ids,
628
539
.suppress_bind_attrs = true,
540
+
.pm = &mxc_gpio_dev_pm_ops,
629
541
},
630
542
.probe = mxc_gpio_probe,
631
543
};
+2
-1
drivers/gpio/gpio-pca953x.c
+2
-1
drivers/gpio/gpio-pca953x.c
···
10
10
11
11
#include <linux/acpi.h>
12
12
#include <linux/bitmap.h>
13
-
#include <linux/gpio/driver.h>
14
13
#include <linux/gpio/consumer.h>
14
+
#include <linux/gpio/driver.h>
15
15
#include <linux/i2c.h>
16
16
#include <linux/init.h>
17
17
#include <linux/interrupt.h>
···
20
20
#include <linux/platform_data/pca953x.h>
21
21
#include <linux/regmap.h>
22
22
#include <linux/regulator/consumer.h>
23
+
#include <linux/seq_file.h>
23
24
#include <linux/slab.h>
24
25
25
26
#include <asm/unaligned.h>
+8
-7
drivers/gpio/gpio-pl061.c
+8
-7
drivers/gpio/gpio-pl061.c
···
8
8
*
9
9
* Data sheet: ARM DDI 0190B, September 2000
10
10
*/
11
-
#include <linux/spinlock.h>
11
+
#include <linux/amba/bus.h>
12
+
#include <linux/bitops.h>
13
+
#include <linux/device.h>
12
14
#include <linux/errno.h>
15
+
#include <linux/gpio/driver.h>
13
16
#include <linux/init.h>
17
+
#include <linux/interrupt.h>
14
18
#include <linux/io.h>
15
19
#include <linux/ioport.h>
16
-
#include <linux/interrupt.h>
17
20
#include <linux/irq.h>
18
21
#include <linux/irqchip/chained_irq.h>
19
22
#include <linux/module.h>
20
-
#include <linux/bitops.h>
21
-
#include <linux/gpio/driver.h>
22
-
#include <linux/device.h>
23
-
#include <linux/amba/bus.h>
24
-
#include <linux/slab.h>
25
23
#include <linux/pinctrl/consumer.h>
26
24
#include <linux/pm.h>
25
+
#include <linux/seq_file.h>
26
+
#include <linux/slab.h>
27
+
#include <linux/spinlock.h>
27
28
28
29
#define GPIODIR 0x400
29
30
#define GPIOIS 0x404
+2
-1
drivers/gpio/gpio-tegra186.c
+2
-1
drivers/gpio/gpio-tegra186.c
···
7
7
*/
8
8
9
9
#include <linux/gpio/driver.h>
10
+
#include <linux/hte.h>
10
11
#include <linux/interrupt.h>
11
12
#include <linux/irq.h>
12
13
#include <linux/module.h>
13
14
#include <linux/of_device.h>
14
15
#include <linux/platform_device.h>
15
-
#include <linux/hte.h>
16
+
#include <linux/seq_file.h>
16
17
17
18
#include <dt-bindings/gpio/tegra186-gpio.h>
18
19
#include <dt-bindings/gpio/tegra194-gpio.h>
+3
-4
drivers/gpio/gpio-wm8350.c
+3
-4
drivers/gpio/gpio-wm8350.c
···
8
8
*
9
9
*/
10
10
11
-
#include <linux/kernel.h>
12
-
#include <linux/slab.h>
13
-
#include <linux/module.h>
14
11
#include <linux/gpio/driver.h>
12
+
#include <linux/kernel.h>
15
13
#include <linux/mfd/core.h>
14
+
#include <linux/module.h>
16
15
#include <linux/platform_device.h>
17
-
#include <linux/seq_file.h>
16
+
#include <linux/slab.h>
18
17
19
18
#include <linux/mfd/wm8350/core.h>
20
19
#include <linux/mfd/wm8350/gpio.h>
+12
drivers/gpio/gpiolib-acpi.h
+12
drivers/gpio/gpiolib-acpi.h
···
8
8
#ifndef GPIOLIB_ACPI_H
9
9
#define GPIOLIB_ACPI_H
10
10
11
+
#include <linux/err.h>
12
+
#include <linux/errno.h>
13
+
#include <linux/types.h>
14
+
15
+
#include <linux/gpio/consumer.h>
16
+
11
17
struct acpi_device;
18
+
struct device;
19
+
struct fwnode_handle;
20
+
21
+
struct gpio_chip;
22
+
struct gpio_desc;
23
+
struct gpio_device;
12
24
13
25
/**
14
26
* struct acpi_gpio_info - ACPI GPIO specific information
+3
-1
drivers/gpio/gpiolib-cdev.c
+3
-1
drivers/gpio/gpiolib-cdev.c
···
12
12
#include <linux/file.h>
13
13
#include <linux/gpio.h>
14
14
#include <linux/gpio/driver.h>
15
+
#include <linux/hte.h>
15
16
#include <linux/interrupt.h>
16
17
#include <linux/irqreturn.h>
17
18
#include <linux/kernel.h>
···
21
20
#include <linux/mutex.h>
22
21
#include <linux/pinctrl/consumer.h>
23
22
#include <linux/poll.h>
23
+
#include <linux/seq_file.h>
24
24
#include <linux/spinlock.h>
25
25
#include <linux/timekeeping.h>
26
26
#include <linux/uaccess.h>
27
27
#include <linux/workqueue.h>
28
-
#include <linux/hte.h>
28
+
29
29
#include <uapi/linux/gpio.h>
30
30
31
31
#include "gpiolib.h"
+10
-1
drivers/gpio/gpiolib-of.h
+10
-1
drivers/gpio/gpiolib-of.h
···
3
3
#ifndef GPIOLIB_OF_H
4
4
#define GPIOLIB_OF_H
5
5
6
+
#include <linux/err.h>
7
+
#include <linux/errno.h>
8
+
#include <linux/types.h>
9
+
10
+
#include <linux/notifier.h>
11
+
12
+
struct device;
13
+
6
14
struct gpio_chip;
7
-
enum of_gpio_flags;
15
+
struct gpio_desc;
16
+
struct gpio_device;
8
17
9
18
#ifdef CONFIG_OF_GPIO
10
19
struct gpio_desc *of_find_gpio(struct device *dev,
+2
drivers/gpio/gpiolib-sysfs.h
+2
drivers/gpio/gpiolib-sysfs.h
+11
drivers/pinctrl/Kconfig
+11
drivers/pinctrl/Kconfig
···
258
258
depends on SOC_FALCON
259
259
depends on PINCTRL_LANTIQ
260
260
261
+
config PINCTRL_LOONGSON2
262
+
tristate "Pinctrl driver for the Loongson-2 SoC"
263
+
depends on OF && (LOONGARCH || COMPILE_TEST)
264
+
select PINMUX
265
+
select GENERIC_PINCONF
266
+
help
267
+
This selects pin control driver for the Loongson-2 SoC. It
268
+
provides pin config functions multiplexing. GPIO pin pull-up,
269
+
pull-down functions are not supported. Say yes to enable
270
+
pinctrl for Loongson-2 SoC.
271
+
261
272
config PINCTRL_XWAY
262
273
bool
263
274
depends on SOC_TYPE_XWAY
+1
drivers/pinctrl/Makefile
+1
drivers/pinctrl/Makefile
···
28
28
obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o
29
29
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
30
30
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
31
+
obj-$(CONFIG_PINCTRL_LOONGSON2) += pinctrl-loongson2.o
31
32
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
32
33
obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
33
34
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
+31
-20
drivers/pinctrl/actions/pinctrl-owl.c
+31
-20
drivers/pinctrl/actions/pinctrl-owl.c
···
17
17
#include <linux/module.h>
18
18
#include <linux/of.h>
19
19
#include <linux/platform_device.h>
20
-
#include <linux/pinctrl/machine.h>
21
-
#include <linux/pinctrl/pinctrl.h>
22
-
#include <linux/pinctrl/pinmux.h>
23
-
#include <linux/pinctrl/pinconf.h>
24
-
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/seq_file.h>
25
21
#include <linux/slab.h>
26
22
#include <linux/spinlock.h>
23
+
24
+
#include <linux/pinctrl/machine.h>
25
+
#include <linux/pinctrl/pinconf-generic.h>
26
+
#include <linux/pinctrl/pinconf.h>
27
+
#include <linux/pinctrl/pinctrl.h>
28
+
#include <linux/pinctrl/pinmux.h>
27
29
28
30
#include "../core.h"
29
31
#include "../pinctrl-utils.h"
···
40
38
* @clk: clock control
41
39
* @soc: reference to soc_data
42
40
* @base: pinctrl register base address
43
-
* @irq_chip: IRQ chip information
44
41
* @num_irq: number of possible interrupts
45
42
* @irq: interrupt numbers
46
43
*/
···
51
50
struct clk *clk;
52
51
const struct owl_pinctrl_soc_data *soc;
53
52
void __iomem *base;
54
-
struct irq_chip irq_chip;
55
53
unsigned int num_irq;
56
54
unsigned int *irq;
57
55
};
···
722
722
{
723
723
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
724
724
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
725
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
725
726
const struct owl_gpio_port *port;
727
+
unsigned int gpio = hwirq;
726
728
void __iomem *gpio_base;
727
729
unsigned long flags;
728
-
unsigned int gpio = data->hwirq;
729
730
u32 val;
730
731
731
732
port = owl_gpio_get_port(pctrl, &gpio);
···
746
745
OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
747
746
748
747
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
748
+
749
+
gpiochip_disable_irq(gc, hwirq);
749
750
}
750
751
751
752
static void owl_gpio_irq_unmask(struct irq_data *data)
752
753
{
753
754
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
754
755
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
756
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
755
757
const struct owl_gpio_port *port;
758
+
unsigned int gpio = hwirq;
756
759
void __iomem *gpio_base;
757
760
unsigned long flags;
758
-
unsigned int gpio = data->hwirq;
759
761
u32 value;
760
762
761
763
port = owl_gpio_get_port(pctrl, &gpio);
762
764
if (WARN_ON(port == NULL))
763
765
return;
766
+
767
+
gpiochip_enable_irq(gc, hwirq);
764
768
765
769
gpio_base = pctrl->base + port->offset;
766
770
raw_spin_lock_irqsave(&pctrl->lock, flags);
···
786
780
{
787
781
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
788
782
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
783
+
irq_hw_number_t hwirq = irqd_to_hwirq(data);
789
784
const struct owl_gpio_port *port;
785
+
unsigned int gpio = hwirq;
790
786
void __iomem *gpio_base;
791
787
unsigned long flags;
792
-
unsigned int gpio = data->hwirq;
793
788
794
789
/*
795
790
* Switch the interrupt edge to the opposite edge of the interrupt
796
791
* which got triggered for the case of emulating both edges
797
792
*/
798
793
if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
799
-
if (owl_gpio_get(gc, gpio))
800
-
irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
794
+
if (owl_gpio_get(gc, hwirq))
795
+
irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING);
801
796
else
802
-
irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
797
+
irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING);
803
798
}
804
799
805
800
port = owl_gpio_get_port(pctrl, &gpio);
···
831
824
832
825
return 0;
833
826
}
827
+
828
+
static const struct irq_chip owl_gpio_irqchip = {
829
+
.name = "owl-irq",
830
+
.irq_ack = owl_gpio_irq_ack,
831
+
.irq_mask = owl_gpio_irq_mask,
832
+
.irq_unmask = owl_gpio_irq_unmask,
833
+
.irq_set_type = owl_gpio_irq_set_type,
834
+
.flags = IRQCHIP_IMMUTABLE,
835
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
836
+
};
834
837
835
838
static void owl_gpio_irq_handler(struct irq_desc *desc)
836
839
{
···
892
875
chip->parent = pctrl->dev;
893
876
chip->owner = THIS_MODULE;
894
877
895
-
pctrl->irq_chip.name = chip->of_node->name;
896
-
pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
897
-
pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
898
-
pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
899
-
pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
900
-
901
878
gpio_irq = &chip->irq;
902
-
gpio_irq->chip = &pctrl->irq_chip;
879
+
gpio_irq_chip_set_chip(gpio_irq, &owl_gpio_irqchip);
903
880
gpio_irq->handler = handle_simple_irq;
904
881
gpio_irq->default_type = IRQ_TYPE_NONE;
905
882
gpio_irq->parent_handler = owl_gpio_irq_handler;
+1
drivers/pinctrl/aspeed/pinctrl-aspeed.c
+1
drivers/pinctrl/aspeed/pinctrl-aspeed.c
+8
-5
drivers/pinctrl/bcm/pinctrl-bcm281xx.c
+8
-5
drivers/pinctrl/bcm/pinctrl-bcm281xx.c
···
2
2
// Copyright (C) 2013-2017 Broadcom
3
3
4
4
#include <linux/err.h>
5
-
#include <linux/io.h>
6
5
#include <linux/init.h>
6
+
#include <linux/io.h>
7
7
#include <linux/of.h>
8
8
#include <linux/platform_device.h>
9
+
#include <linux/regmap.h>
10
+
#include <linux/seq_file.h>
11
+
#include <linux/slab.h>
12
+
13
+
#include <linux/pinctrl/pinconf-generic.h>
14
+
#include <linux/pinctrl/pinconf.h>
9
15
#include <linux/pinctrl/pinctrl.h>
10
16
#include <linux/pinctrl/pinmux.h>
11
-
#include <linux/pinctrl/pinconf.h>
12
-
#include <linux/pinctrl/pinconf-generic.h>
13
-
#include <linux/regmap.h>
14
-
#include <linux/slab.h>
17
+
15
18
#include "../core.h"
16
19
#include "../pinctrl-utils.h"
17
20
+6
-3
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
+6
-3
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
···
13
13
#include <linux/err.h>
14
14
#include <linux/io.h>
15
15
#include <linux/of.h>
16
-
#include <linux/slab.h>
17
16
#include <linux/platform_device.h>
17
+
#include <linux/seq_file.h>
18
+
#include <linux/slab.h>
19
+
20
+
#include <linux/pinctrl/pinconf-generic.h>
21
+
#include <linux/pinctrl/pinconf.h>
18
22
#include <linux/pinctrl/pinctrl.h>
19
23
#include <linux/pinctrl/pinmux.h>
20
-
#include <linux/pinctrl/pinconf.h>
21
-
#include <linux/pinctrl/pinconf-generic.h>
24
+
22
25
#include "../core.h"
23
26
#include "../pinctrl-utils.h"
24
27
+7
-5
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+7
-5
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
···
16
16
* SoCs IOMUX controller.
17
17
*/
18
18
19
-
#include <linux/kernel.h>
20
-
#include <linux/slab.h>
19
+
#include <linux/gpio/driver.h>
21
20
#include <linux/interrupt.h>
22
21
#include <linux/io.h>
23
-
#include <linux/gpio/driver.h>
24
22
#include <linux/ioport.h>
23
+
#include <linux/kernel.h>
25
24
#include <linux/of_device.h>
26
25
#include <linux/of_irq.h>
27
-
#include <linux/pinctrl/pinctrl.h>
28
-
#include <linux/pinctrl/pinconf.h>
26
+
#include <linux/slab.h>
27
+
28
+
#include <linux/pinctrl/consumer.h>
29
29
#include <linux/pinctrl/pinconf-generic.h>
30
+
#include <linux/pinctrl/pinconf.h>
31
+
#include <linux/pinctrl/pinctrl.h>
30
32
31
33
#include "../pinctrl-utils.h"
32
34
+5
-3
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
+5
-3
drivers/pinctrl/bcm/pinctrl-ns2-mux.c
···
9
9
#include <linux/err.h>
10
10
#include <linux/io.h>
11
11
#include <linux/of.h>
12
-
#include <linux/pinctrl/pinconf.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/seq_file.h>
14
+
#include <linux/slab.h>
15
+
13
16
#include <linux/pinctrl/pinconf-generic.h>
17
+
#include <linux/pinctrl/pinconf.h>
14
18
#include <linux/pinctrl/pinctrl.h>
15
19
#include <linux/pinctrl/pinmux.h>
16
-
#include <linux/platform_device.h>
17
-
#include <linux/slab.h>
18
20
19
21
#include "../core.h"
20
22
#include "../pinctrl-utils.h"
+5
-3
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
+5
-3
drivers/pinctrl/bcm/pinctrl-nsp-mux.c
···
20
20
#include <linux/err.h>
21
21
#include <linux/io.h>
22
22
#include <linux/of.h>
23
-
#include <linux/pinctrl/pinconf.h>
23
+
#include <linux/platform_device.h>
24
+
#include <linux/seq_file.h>
25
+
#include <linux/slab.h>
26
+
24
27
#include <linux/pinctrl/pinconf-generic.h>
28
+
#include <linux/pinctrl/pinconf.h>
25
29
#include <linux/pinctrl/pinctrl.h>
26
30
#include <linux/pinctrl/pinmux.h>
27
-
#include <linux/platform_device.h>
28
-
#include <linux/slab.h>
29
31
30
32
#include "../core.h"
31
33
#include "../pinctrl-utils.h"
+4
-2
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
+4
-2
drivers/pinctrl/cirrus/pinctrl-lochnagar.c
···
15
15
#include <linux/of.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/regmap.h>
18
+
19
+
#include <linux/pinctrl/consumer.h>
20
+
#include <linux/pinctrl/pinconf-generic.h>
21
+
#include <linux/pinctrl/pinconf.h>
18
22
#include <linux/pinctrl/pinctrl.h>
19
23
#include <linux/pinctrl/pinmux.h>
20
-
#include <linux/pinctrl/pinconf.h>
21
-
#include <linux/pinctrl/pinconf-generic.h>
22
24
23
25
#include <linux/mfd/lochnagar.h>
24
26
#include <linux/mfd/lochnagar1_regs.h>
+3
-2
drivers/pinctrl/cirrus/pinctrl-madera-core.c
+3
-2
drivers/pinctrl/cirrus/pinctrl-madera-core.c
···
10
10
#include <linux/platform_device.h>
11
11
#include <linux/property.h>
12
12
#include <linux/regmap.h>
13
+
#include <linux/seq_file.h>
13
14
#include <linux/slab.h>
14
15
15
16
#include <linux/pinctrl/machine.h>
17
+
#include <linux/pinctrl/pinconf-generic.h>
18
+
#include <linux/pinctrl/pinconf.h>
16
19
#include <linux/pinctrl/pinctrl.h>
17
20
#include <linux/pinctrl/pinmux.h>
18
-
#include <linux/pinctrl/pinconf.h>
19
-
#include <linux/pinctrl/pinconf-generic.h>
20
21
21
22
#include <linux/mfd/madera/core.h>
22
23
#include <linux/mfd/madera/registers.h>
+12
-13
drivers/pinctrl/core.c
+12
-13
drivers/pinctrl/core.c
···
12
12
*/
13
13
#define pr_fmt(fmt) "pinctrl core: " fmt
14
14
15
-
#include <linux/kernel.h>
16
-
#include <linux/kref.h>
15
+
#include <linux/debugfs.h>
16
+
#include <linux/device.h>
17
+
#include <linux/err.h>
17
18
#include <linux/export.h>
18
19
#include <linux/init.h>
19
-
#include <linux/device.h>
20
-
#include <linux/slab.h>
21
-
#include <linux/err.h>
20
+
#include <linux/kernel.h>
21
+
#include <linux/kref.h>
22
22
#include <linux/list.h>
23
-
#include <linux/debugfs.h>
24
23
#include <linux/seq_file.h>
24
+
#include <linux/slab.h>
25
+
25
26
#include <linux/pinctrl/consumer.h>
26
-
#include <linux/pinctrl/pinctrl.h>
27
+
#include <linux/pinctrl/devinfo.h>
27
28
#include <linux/pinctrl/machine.h>
29
+
#include <linux/pinctrl/pinctrl.h>
28
30
29
31
#ifdef CONFIG_GPIOLIB
30
32
#include "../gpio/gpiolib.h"
···
35
33
36
34
#include "core.h"
37
35
#include "devicetree.h"
38
-
#include "pinmux.h"
39
36
#include "pinconf.h"
40
-
37
+
#include "pinmux.h"
41
38
42
39
static bool pinctrl_dummy_state;
43
40
···
1029
1028
struct pinctrl *p;
1030
1029
const char *devname;
1031
1030
struct pinctrl_maps *maps_node;
1032
-
int i;
1033
1031
const struct pinctrl_map *map;
1034
1032
int ret;
1035
1033
···
1054
1054
1055
1055
mutex_lock(&pinctrl_maps_mutex);
1056
1056
/* Iterate over the pin control maps to locate the right ones */
1057
-
for_each_maps(maps_node, i, map) {
1057
+
for_each_pin_map(maps_node, map) {
1058
1058
/* Map must be for this device */
1059
1059
if (strcmp(map->dev_name, devname))
1060
1060
continue;
···
1805
1805
static int pinctrl_maps_show(struct seq_file *s, void *what)
1806
1806
{
1807
1807
struct pinctrl_maps *maps_node;
1808
-
int i;
1809
1808
const struct pinctrl_map *map;
1810
1809
1811
1810
seq_puts(s, "Pinctrl maps:\n");
1812
1811
1813
1812
mutex_lock(&pinctrl_maps_mutex);
1814
-
for_each_maps(maps_node, i, map) {
1813
+
for_each_pin_map(maps_node, map) {
1815
1814
seq_printf(s, "device %s\nstate %s\ntype %s (%d)\n",
1816
1815
map->dev_name, map->name, map_type(map->type),
1817
1816
map->type);
+16
-6
drivers/pinctrl/core.h
+16
-6
drivers/pinctrl/core.h
···
9
9
*/
10
10
11
11
#include <linux/kref.h>
12
+
#include <linux/list.h>
12
13
#include <linux/mutex.h>
13
14
#include <linux/radix-tree.h>
14
-
#include <linux/pinctrl/pinconf.h>
15
+
#include <linux/types.h>
16
+
15
17
#include <linux/pinctrl/machine.h>
16
18
19
+
struct dentry;
20
+
struct device;
21
+
struct device_node;
22
+
struct module;
23
+
24
+
struct pinctrl;
25
+
struct pinctrl_desc;
17
26
struct pinctrl_gpio_range;
27
+
struct pinctrl_state;
18
28
19
29
/**
20
30
* struct pinctrl_dev - pin control class device
···
252
242
extern struct mutex pinctrl_maps_mutex;
253
243
extern struct list_head pinctrl_maps;
254
244
255
-
#define for_each_maps(_maps_node_, _i_, _map_) \
256
-
list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
257
-
for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
258
-
_i_ < _maps_node_->num_maps; \
259
-
_i_++, _map_ = &_maps_node_->maps[_i_])
245
+
#define for_each_pin_map(_maps_node_, _map_) \
246
+
list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
247
+
for (unsigned int __i = 0; \
248
+
__i < _maps_node_->num_maps && (_map_ = &_maps_node_->maps[__i]); \
249
+
__i++)
+6
drivers/pinctrl/devicetree.h
+6
drivers/pinctrl/devicetree.h
+5
-3
drivers/pinctrl/freescale/pinctrl-imx.c
+5
-3
drivers/pinctrl/freescale/pinctrl-imx.c
···
13
13
#include <linux/mfd/syscon.h>
14
14
#include <linux/module.h>
15
15
#include <linux/of.h>
16
-
#include <linux/of_device.h>
17
16
#include <linux/of_address.h>
17
+
#include <linux/of_device.h>
18
+
#include <linux/regmap.h>
19
+
#include <linux/seq_file.h>
20
+
#include <linux/slab.h>
21
+
18
22
#include <linux/pinctrl/machine.h>
19
23
#include <linux/pinctrl/pinconf.h>
20
24
#include <linux/pinctrl/pinctrl.h>
21
25
#include <linux/pinctrl/pinmux.h>
22
-
#include <linux/slab.h>
23
-
#include <linux/regmap.h>
24
26
25
27
#include "../core.h"
26
28
#include "../pinconf.h"
+3
-1
drivers/pinctrl/freescale/pinctrl-imx1-core.c
+3
-1
drivers/pinctrl/freescale/pinctrl-imx1-core.c
···
16
16
#include <linux/io.h>
17
17
#include <linux/of.h>
18
18
#include <linux/of_device.h>
19
+
#include <linux/seq_file.h>
20
+
#include <linux/slab.h>
21
+
19
22
#include <linux/pinctrl/machine.h>
20
23
#include <linux/pinctrl/pinconf.h>
21
24
#include <linux/pinctrl/pinctrl.h>
22
25
#include <linux/pinctrl/pinmux.h>
23
-
#include <linux/slab.h>
24
26
25
27
#include "../core.h"
26
28
#include "pinctrl-imx1.h"
+253
-293
drivers/pinctrl/freescale/pinctrl-imxrt1050.c
+253
-293
drivers/pinctrl/freescale/pinctrl-imxrt1050.c
···
13
13
#include "pinctrl-imx.h"
14
14
15
15
enum imxrt1050_pads {
16
-
IMXRT1050_PAD_RESERVE0 = 0,
17
-
IMXRT1050_PAD_RESERVE1 = 1,
18
-
IMXRT1050_PAD_RESERVE2 = 2,
19
-
IMXRT1050_PAD_RESERVE3 = 3,
20
-
IMXRT1050_PAD_RESERVE4 = 4,
21
-
IMXRT1050_PAD_RESERVE5 = 5,
22
-
IMXRT1050_PAD_RESERVE6 = 6,
23
-
IMXRT1050_PAD_RESERVE7 = 7,
24
-
IMXRT1050_PAD_RESERVE8 = 8,
25
-
IMXRT1050_PAD_RESERVE9 = 9,
26
-
IMXRT1050_IOMUXC_GPIO1_IO00 = 10,
27
-
IMXRT1050_IOMUXC_GPIO1_IO01 = 11,
28
-
IMXRT1050_IOMUXC_GPIO1_IO02 = 12,
29
-
IMXRT1050_IOMUXC_GPIO1_IO03 = 13,
30
-
IMXRT1050_IOMUXC_GPIO1_IO04 = 14,
31
-
IMXRT1050_IOMUXC_GPIO1_IO05 = 15,
32
-
IMXRT1050_IOMUXC_GPIO1_IO06 = 16,
33
-
IMXRT1050_IOMUXC_GPIO1_IO07 = 17,
34
-
IMXRT1050_IOMUXC_GPIO1_IO08 = 18,
35
-
IMXRT1050_IOMUXC_GPIO1_IO09 = 19,
36
-
IMXRT1050_IOMUXC_GPIO1_IO10 = 20,
37
-
IMXRT1050_IOMUXC_GPIO1_IO11 = 21,
38
-
IMXRT1050_IOMUXC_GPIO1_IO12 = 22,
39
-
IMXRT1050_IOMUXC_GPIO1_IO13 = 23,
40
-
IMXRT1050_IOMUXC_GPIO1_IO14 = 24,
41
-
IMXRT1050_IOMUXC_GPIO1_IO15 = 25,
42
-
IMXRT1050_IOMUXC_ENET_MDC = 26,
43
-
IMXRT1050_IOMUXC_ENET_MDIO = 27,
44
-
IMXRT1050_IOMUXC_ENET_TD3 = 28,
45
-
IMXRT1050_IOMUXC_ENET_TD2 = 29,
46
-
IMXRT1050_IOMUXC_ENET_TD1 = 30,
47
-
IMXRT1050_IOMUXC_ENET_TD0 = 31,
48
-
IMXRT1050_IOMUXC_ENET_TX_CTL = 32,
49
-
IMXRT1050_IOMUXC_ENET_TXC = 33,
50
-
IMXRT1050_IOMUXC_ENET_RX_CTL = 34,
51
-
IMXRT1050_IOMUXC_ENET_RXC = 35,
52
-
IMXRT1050_IOMUXC_ENET_RD0 = 36,
53
-
IMXRT1050_IOMUXC_ENET_RD1 = 37,
54
-
IMXRT1050_IOMUXC_ENET_RD2 = 38,
55
-
IMXRT1050_IOMUXC_ENET_RD3 = 39,
56
-
IMXRT1050_IOMUXC_SD1_CLK = 40,
57
-
IMXRT1050_IOMUXC_SD1_CMD = 41,
58
-
IMXRT1050_IOMUXC_SD1_DATA0 = 42,
59
-
IMXRT1050_IOMUXC_SD1_DATA1 = 43,
60
-
IMXRT1050_IOMUXC_SD1_DATA2 = 44,
61
-
IMXRT1050_IOMUXC_SD1_DATA3 = 45,
62
-
IMXRT1050_IOMUXC_SD1_DATA4 = 46,
63
-
IMXRT1050_IOMUXC_SD1_DATA5 = 47,
64
-
IMXRT1050_IOMUXC_SD1_DATA6 = 48,
65
-
IMXRT1050_IOMUXC_SD1_DATA7 = 49,
66
-
IMXRT1050_IOMUXC_SD1_RESET_B = 50,
67
-
IMXRT1050_IOMUXC_SD1_STROBE = 51,
68
-
IMXRT1050_IOMUXC_SD2_CD_B = 52,
69
-
IMXRT1050_IOMUXC_SD2_CLK = 53,
70
-
IMXRT1050_IOMUXC_SD2_CMD = 54,
71
-
IMXRT1050_IOMUXC_SD2_DATA0 = 55,
72
-
IMXRT1050_IOMUXC_SD2_DATA1 = 56,
73
-
IMXRT1050_IOMUXC_SD2_DATA2 = 57,
74
-
IMXRT1050_IOMUXC_SD2_DATA3 = 58,
75
-
IMXRT1050_IOMUXC_SD2_RESET_B = 59,
76
-
IMXRT1050_IOMUXC_SD2_WP = 60,
77
-
IMXRT1050_IOMUXC_NAND_ALE = 61,
78
-
IMXRT1050_IOMUXC_NAND_CE0 = 62,
79
-
IMXRT1050_IOMUXC_NAND_CE1 = 63,
80
-
IMXRT1050_IOMUXC_NAND_CE2 = 64,
81
-
IMXRT1050_IOMUXC_NAND_CE3 = 65,
82
-
IMXRT1050_IOMUXC_NAND_CLE = 66,
83
-
IMXRT1050_IOMUXC_NAND_DATA00 = 67,
84
-
IMXRT1050_IOMUXC_NAND_DATA01 = 68,
85
-
IMXRT1050_IOMUXC_NAND_DATA02 = 69,
86
-
IMXRT1050_IOMUXC_NAND_DATA03 = 70,
87
-
IMXRT1050_IOMUXC_NAND_DATA04 = 71,
88
-
IMXRT1050_IOMUXC_NAND_DATA05 = 72,
89
-
IMXRT1050_IOMUXC_NAND_DATA06 = 73,
90
-
IMXRT1050_IOMUXC_NAND_DATA07 = 74,
91
-
IMXRT1050_IOMUXC_NAND_DQS = 75,
92
-
IMXRT1050_IOMUXC_NAND_RE_B = 76,
93
-
IMXRT1050_IOMUXC_NAND_READY_B = 77,
94
-
IMXRT1050_IOMUXC_NAND_WE_B = 78,
95
-
IMXRT1050_IOMUXC_NAND_WP_B = 79,
96
-
IMXRT1050_IOMUXC_SAI5_RXFS = 80,
97
-
IMXRT1050_IOMUXC_SAI5_RXC = 81,
98
-
IMXRT1050_IOMUXC_SAI5_RXD0 = 82,
99
-
IMXRT1050_IOMUXC_SAI5_RXD1 = 83,
100
-
IMXRT1050_IOMUXC_SAI5_RXD2 = 84,
101
-
IMXRT1050_IOMUXC_SAI5_RXD3 = 85,
102
-
IMXRT1050_IOMUXC_SAI5_MCLK = 86,
103
-
IMXRT1050_IOMUXC_SAI1_RXFS = 87,
104
-
IMXRT1050_IOMUXC_SAI1_RXC = 88,
105
-
IMXRT1050_IOMUXC_SAI1_RXD0 = 89,
106
-
IMXRT1050_IOMUXC_SAI1_RXD1 = 90,
107
-
IMXRT1050_IOMUXC_SAI1_RXD2 = 91,
108
-
IMXRT1050_IOMUXC_SAI1_RXD3 = 92,
109
-
IMXRT1050_IOMUXC_SAI1_RXD4 = 93,
110
-
IMXRT1050_IOMUXC_SAI1_RXD5 = 94,
111
-
IMXRT1050_IOMUXC_SAI1_RXD6 = 95,
112
-
IMXRT1050_IOMUXC_SAI1_RXD7 = 96,
113
-
IMXRT1050_IOMUXC_SAI1_TXFS = 97,
114
-
IMXRT1050_IOMUXC_SAI1_TXC = 98,
115
-
IMXRT1050_IOMUXC_SAI1_TXD0 = 99,
116
-
IMXRT1050_IOMUXC_SAI1_TXD1 = 100,
117
-
IMXRT1050_IOMUXC_SAI1_TXD2 = 101,
118
-
IMXRT1050_IOMUXC_SAI1_TXD3 = 102,
119
-
IMXRT1050_IOMUXC_SAI1_TXD4 = 103,
120
-
IMXRT1050_IOMUXC_SAI1_TXD5 = 104,
121
-
IMXRT1050_IOMUXC_SAI1_TXD6 = 105,
122
-
IMXRT1050_IOMUXC_SAI1_TXD7 = 106,
123
-
IMXRT1050_IOMUXC_SAI1_MCLK = 107,
124
-
IMXRT1050_IOMUXC_SAI2_RXFS = 108,
125
-
IMXRT1050_IOMUXC_SAI2_RXC = 109,
126
-
IMXRT1050_IOMUXC_SAI2_RXD0 = 110,
127
-
IMXRT1050_IOMUXC_SAI2_TXFS = 111,
128
-
IMXRT1050_IOMUXC_SAI2_TXC = 112,
129
-
IMXRT1050_IOMUXC_SAI2_TXD0 = 113,
130
-
IMXRT1050_IOMUXC_SAI2_MCLK = 114,
131
-
IMXRT1050_IOMUXC_SAI3_RXFS = 115,
132
-
IMXRT1050_IOMUXC_SAI3_RXC = 116,
133
-
IMXRT1050_IOMUXC_SAI3_RXD = 117,
134
-
IMXRT1050_IOMUXC_SAI3_TXFS = 118,
135
-
IMXRT1050_IOMUXC_SAI3_TXC = 119,
136
-
IMXRT1050_IOMUXC_SAI3_TXD = 120,
137
-
IMXRT1050_IOMUXC_SAI3_MCLK = 121,
138
-
IMXRT1050_IOMUXC_SPDIF_TX = 122,
139
-
IMXRT1050_IOMUXC_SPDIF_RX = 123,
140
-
IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124,
141
-
IMXRT1050_IOMUXC_ECSPI1_SCLK = 125,
142
-
IMXRT1050_IOMUXC_ECSPI1_MOSI = 126,
143
-
IMXRT1050_IOMUXC_ECSPI1_MISO = 127,
144
-
IMXRT1050_IOMUXC_ECSPI1_SS0 = 128,
145
-
IMXRT1050_IOMUXC_ECSPI2_SCLK = 129,
146
-
IMXRT1050_IOMUXC_ECSPI2_MOSI = 130,
147
-
IMXRT1050_IOMUXC_ECSPI2_MISO = 131,
148
-
IMXRT1050_IOMUXC_ECSPI2_SS0 = 132,
149
-
IMXRT1050_IOMUXC_I2C1_SCL = 133,
150
-
IMXRT1050_IOMUXC_I2C1_SDA = 134,
151
-
IMXRT1050_IOMUXC_I2C2_SCL = 135,
152
-
IMXRT1050_IOMUXC_I2C2_SDA = 136,
153
-
IMXRT1050_IOMUXC_I2C3_SCL = 137,
154
-
IMXRT1050_IOMUXC_I2C3_SDA = 138,
155
-
IMXRT1050_IOMUXC_I2C4_SCL = 139,
156
-
IMXRT1050_IOMUXC_I2C4_SDA = 140,
157
-
IMXRT1050_IOMUXC_UART1_RXD = 141,
158
-
IMXRT1050_IOMUXC_UART1_TXD = 142,
159
-
IMXRT1050_IOMUXC_UART2_RXD = 143,
160
-
IMXRT1050_IOMUXC_UART2_TXD = 144,
161
-
IMXRT1050_IOMUXC_UART3_RXD = 145,
162
-
IMXRT1050_IOMUXC_UART3_TXD = 146,
163
-
IMXRT1050_IOMUXC_UART4_RXD = 147,
164
-
IMXRT1050_IOMUXC_UART4_TXD = 148,
16
+
IMXRT1050_PAD_RESERVE0,
17
+
IMXRT1050_PAD_RESERVE1,
18
+
IMXRT1050_PAD_RESERVE2,
19
+
IMXRT1050_PAD_RESERVE3,
20
+
IMXRT1050_PAD_RESERVE4,
21
+
IMXRT1050_PAD_EMC_00,
22
+
IMXRT1050_PAD_EMC_01,
23
+
IMXRT1050_PAD_EMC_02,
24
+
IMXRT1050_PAD_EMC_03,
25
+
IMXRT1050_PAD_EMC_04,
26
+
IMXRT1050_PAD_EMC_05,
27
+
IMXRT1050_PAD_EMC_06,
28
+
IMXRT1050_PAD_EMC_07,
29
+
IMXRT1050_PAD_EMC_08,
30
+
IMXRT1050_PAD_EMC_09,
31
+
IMXRT1050_PAD_EMC_10,
32
+
IMXRT1050_PAD_EMC_11,
33
+
IMXRT1050_PAD_EMC_12,
34
+
IMXRT1050_PAD_EMC_13,
35
+
IMXRT1050_PAD_EMC_14,
36
+
IMXRT1050_PAD_EMC_15,
37
+
IMXRT1050_PAD_EMC_16,
38
+
IMXRT1050_PAD_EMC_17,
39
+
IMXRT1050_PAD_EMC_18,
40
+
IMXRT1050_PAD_EMC_19,
41
+
IMXRT1050_PAD_EMC_20,
42
+
IMXRT1050_PAD_EMC_21,
43
+
IMXRT1050_PAD_EMC_22,
44
+
IMXRT1050_PAD_EMC_23,
45
+
IMXRT1050_PAD_EMC_24,
46
+
IMXRT1050_PAD_EMC_25,
47
+
IMXRT1050_PAD_EMC_26,
48
+
IMXRT1050_PAD_EMC_27,
49
+
IMXRT1050_PAD_EMC_28,
50
+
IMXRT1050_PAD_EMC_29,
51
+
IMXRT1050_PAD_EMC_30,
52
+
IMXRT1050_PAD_EMC_31,
53
+
IMXRT1050_PAD_EMC_32,
54
+
IMXRT1050_PAD_EMC_33,
55
+
IMXRT1050_PAD_EMC_34,
56
+
IMXRT1050_PAD_EMC_35,
57
+
IMXRT1050_PAD_EMC_36,
58
+
IMXRT1050_PAD_EMC_37,
59
+
IMXRT1050_PAD_EMC_38,
60
+
IMXRT1050_PAD_EMC_39,
61
+
IMXRT1050_PAD_EMC_40,
62
+
IMXRT1050_PAD_EMC_41,
63
+
IMXRT1050_PAD_AD_B0_00,
64
+
IMXRT1050_PAD_AD_B0_01,
65
+
IMXRT1050_PAD_AD_B0_02,
66
+
IMXRT1050_PAD_AD_B0_03,
67
+
IMXRT1050_PAD_AD_B0_04,
68
+
IMXRT1050_PAD_AD_B0_05,
69
+
IMXRT1050_PAD_AD_B0_06,
70
+
IMXRT1050_PAD_AD_B0_07,
71
+
IMXRT1050_PAD_AD_B0_08,
72
+
IMXRT1050_PAD_AD_B0_09,
73
+
IMXRT1050_PAD_AD_B0_10,
74
+
IMXRT1050_PAD_AD_B0_11,
75
+
IMXRT1050_PAD_AD_B0_12,
76
+
IMXRT1050_PAD_AD_B0_13,
77
+
IMXRT1050_PAD_AD_B0_14,
78
+
IMXRT1050_PAD_AD_B0_15,
79
+
IMXRT1050_PAD_AD_B1_00,
80
+
IMXRT1050_PAD_AD_B1_01,
81
+
IMXRT1050_PAD_AD_B1_02,
82
+
IMXRT1050_PAD_AD_B1_03,
83
+
IMXRT1050_PAD_AD_B1_04,
84
+
IMXRT1050_PAD_AD_B1_05,
85
+
IMXRT1050_PAD_AD_B1_06,
86
+
IMXRT1050_PAD_AD_B1_07,
87
+
IMXRT1050_PAD_AD_B1_08,
88
+
IMXRT1050_PAD_AD_B1_09,
89
+
IMXRT1050_PAD_AD_B1_10,
90
+
IMXRT1050_PAD_AD_B1_11,
91
+
IMXRT1050_PAD_AD_B1_12,
92
+
IMXRT1050_PAD_AD_B1_13,
93
+
IMXRT1050_PAD_AD_B1_14,
94
+
IMXRT1050_PAD_AD_B1_15,
95
+
IMXRT1050_PAD_B0_00,
96
+
IMXRT1050_PAD_B0_01,
97
+
IMXRT1050_PAD_B0_02,
98
+
IMXRT1050_PAD_B0_03,
99
+
IMXRT1050_PAD_B0_04,
100
+
IMXRT1050_PAD_B0_05,
101
+
IMXRT1050_PAD_B0_06,
102
+
IMXRT1050_PAD_B0_07,
103
+
IMXRT1050_PAD_B0_08,
104
+
IMXRT1050_PAD_B0_09,
105
+
IMXRT1050_PAD_B0_10,
106
+
IMXRT1050_PAD_B0_11,
107
+
IMXRT1050_PAD_B0_12,
108
+
IMXRT1050_PAD_B0_13,
109
+
IMXRT1050_PAD_B0_14,
110
+
IMXRT1050_PAD_B0_15,
111
+
IMXRT1050_PAD_B1_00,
112
+
IMXRT1050_PAD_B1_01,
113
+
IMXRT1050_PAD_B1_02,
114
+
IMXRT1050_PAD_B1_03,
115
+
IMXRT1050_PAD_B1_04,
116
+
IMXRT1050_PAD_B1_05,
117
+
IMXRT1050_PAD_B1_06,
118
+
IMXRT1050_PAD_B1_07,
119
+
IMXRT1050_PAD_B1_08,
120
+
IMXRT1050_PAD_B1_09,
121
+
IMXRT1050_PAD_B1_10,
122
+
IMXRT1050_PAD_B1_11,
123
+
IMXRT1050_PAD_B1_12,
124
+
IMXRT1050_PAD_B1_13,
125
+
IMXRT1050_PAD_B1_14,
126
+
IMXRT1050_PAD_B1_15,
127
+
IMXRT1050_PAD_SD_B0_00,
128
+
IMXRT1050_PAD_SD_B0_01,
129
+
IMXRT1050_PAD_SD_B0_02,
130
+
IMXRT1050_PAD_SD_B0_03,
131
+
IMXRT1050_PAD_SD_B0_04,
132
+
IMXRT1050_PAD_SD_B0_05,
133
+
IMXRT1050_PAD_SD_B1_00,
134
+
IMXRT1050_PAD_SD_B1_01,
135
+
IMXRT1050_PAD_SD_B1_02,
136
+
IMXRT1050_PAD_SD_B1_03,
137
+
IMXRT1050_PAD_SD_B1_04,
138
+
IMXRT1050_PAD_SD_B1_05,
139
+
IMXRT1050_PAD_SD_B1_06,
140
+
IMXRT1050_PAD_SD_B1_07,
141
+
IMXRT1050_PAD_SD_B1_08,
142
+
IMXRT1050_PAD_SD_B1_09,
143
+
IMXRT1050_PAD_SD_B1_10,
144
+
IMXRT1050_PAD_SD_B1_11,
165
145
};
166
146
167
147
/* Pad names for the pinmux subsystem */
···
151
171
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2),
152
172
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3),
153
173
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4),
154
-
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5),
155
-
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6),
156
-
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7),
157
-
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8),
158
-
IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9),
159
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00),
160
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01),
161
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02),
162
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03),
163
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04),
164
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05),
165
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06),
166
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07),
167
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08),
168
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09),
169
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10),
170
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11),
171
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12),
172
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13),
173
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14),
174
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15),
175
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC),
176
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO),
177
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3),
178
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2),
179
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1),
180
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0),
181
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL),
182
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC),
183
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL),
184
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC),
185
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0),
186
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1),
187
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2),
188
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3),
189
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK),
190
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD),
191
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0),
192
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1),
193
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2),
194
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3),
195
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4),
196
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5),
197
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6),
198
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7),
199
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B),
200
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE),
201
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B),
202
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK),
203
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD),
204
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0),
205
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1),
206
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2),
207
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3),
208
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B),
209
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP),
210
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE),
211
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0),
212
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1),
213
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2),
214
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3),
215
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE),
216
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00),
217
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01),
218
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02),
219
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03),
220
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04),
221
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05),
222
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06),
223
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07),
224
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS),
225
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B),
226
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B),
227
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B),
228
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B),
229
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS),
230
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC),
231
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0),
232
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1),
233
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2),
234
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3),
235
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK),
236
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS),
237
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC),
238
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0),
239
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1),
240
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2),
241
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3),
242
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4),
243
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5),
244
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6),
245
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7),
246
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS),
247
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC),
248
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0),
249
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1),
250
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2),
251
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3),
252
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4),
253
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5),
254
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6),
255
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7),
256
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK),
257
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS),
258
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC),
259
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0),
260
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS),
261
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC),
262
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0),
263
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK),
264
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS),
265
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC),
266
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD),
267
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS),
268
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC),
269
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD),
270
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK),
271
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX),
272
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX),
273
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK),
274
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK),
275
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI),
276
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO),
277
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0),
278
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK),
279
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI),
280
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO),
281
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0),
282
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL),
283
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA),
284
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL),
285
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA),
286
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL),
287
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA),
288
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL),
289
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA),
290
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD),
291
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD),
292
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD),
293
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD),
294
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD),
295
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD),
296
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD),
297
-
IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD),
174
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00),
175
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01),
176
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02),
177
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03),
178
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04),
179
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05),
180
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06),
181
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07),
182
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08),
183
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09),
184
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10),
185
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11),
186
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12),
187
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13),
188
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14),
189
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15),
190
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16),
191
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17),
192
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18),
193
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19),
194
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20),
195
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21),
196
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22),
197
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23),
198
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24),
199
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25),
200
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26),
201
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27),
202
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28),
203
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29),
204
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30),
205
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31),
206
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32),
207
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33),
208
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34),
209
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35),
210
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36),
211
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37),
212
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38),
213
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39),
214
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40),
215
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41),
216
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00),
217
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01),
218
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02),
219
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03),
220
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04),
221
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05),
222
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06),
223
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07),
224
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08),
225
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09),
226
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10),
227
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11),
228
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12),
229
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13),
230
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14),
231
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15),
232
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00),
233
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01),
234
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02),
235
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03),
236
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04),
237
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05),
238
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06),
239
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07),
240
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08),
241
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09),
242
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10),
243
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11),
244
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12),
245
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13),
246
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14),
247
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15),
248
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00),
249
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01),
250
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02),
251
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03),
252
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04),
253
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05),
254
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06),
255
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07),
256
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08),
257
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09),
258
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10),
259
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11),
260
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12),
261
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13),
262
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14),
263
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15),
264
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00),
265
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01),
266
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02),
267
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03),
268
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04),
269
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05),
270
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06),
271
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07),
272
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08),
273
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09),
274
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10),
275
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11),
276
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12),
277
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13),
278
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14),
279
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15),
280
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00),
281
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01),
282
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02),
283
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03),
284
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04),
285
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05),
286
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00),
287
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01),
288
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02),
289
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03),
290
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04),
291
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05),
292
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06),
293
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07),
294
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08),
295
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09),
296
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10),
297
+
IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11),
298
298
};
299
299
300
300
static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = {
+5
-2
drivers/pinctrl/freescale/pinctrl-mxs.c
+5
-2
drivers/pinctrl/freescale/pinctrl-mxs.c
···
7
7
#include <linux/io.h>
8
8
#include <linux/of.h>
9
9
#include <linux/of_address.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/seq_file.h>
12
+
#include <linux/slab.h>
13
+
10
14
#include <linux/pinctrl/machine.h>
11
15
#include <linux/pinctrl/pinconf.h>
12
16
#include <linux/pinctrl/pinctrl.h>
13
17
#include <linux/pinctrl/pinmux.h>
14
-
#include <linux/platform_device.h>
15
-
#include <linux/slab.h>
18
+
16
19
#include "../core.h"
17
20
#include "pinctrl-mxs.h"
18
21
+30
drivers/pinctrl/freescale/pinctrl-scu.c
+30
drivers/pinctrl/freescale/pinctrl-scu.c
···
15
15
#include "../core.h"
16
16
#include "pinctrl-imx.h"
17
17
18
+
#define IMX_SC_PAD_FUNC_GET_WAKEUP 9
19
+
#define IMX_SC_PAD_FUNC_SET_WAKEUP 4
20
+
#define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */
21
+
#define IMX_SC_IRQ_PAD 2 /* Pad wakeup */
22
+
18
23
enum pad_func_e {
19
24
IMX_SC_PAD_FUNC_SET = 15,
20
25
IMX_SC_PAD_FUNC_GET = 16,
···
41
36
u32 val;
42
37
} __packed;
43
38
39
+
struct imx_sc_msg_gpio_set_pad_wakeup {
40
+
struct imx_sc_rpc_msg hdr;
41
+
u16 pad;
42
+
u8 wakeup;
43
+
} __packed __aligned(4);
44
+
44
45
static struct imx_sc_ipc *pinctrl_ipc_handle;
45
46
46
47
int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
47
48
{
49
+
imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE,
50
+
IMX_SC_IRQ_PAD, true);
48
51
return imx_scu_get_handle(&pinctrl_ipc_handle);
49
52
}
50
53
EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init);
···
93
80
unsigned int conf = configs[1];
94
81
unsigned int val;
95
82
int ret;
83
+
84
+
if (num_configs == 1) {
85
+
struct imx_sc_msg_gpio_set_pad_wakeup wmsg;
86
+
87
+
hdr = &wmsg.hdr;
88
+
hdr->ver = IMX_SC_RPC_VERSION;
89
+
hdr->svc = IMX_SC_RPC_SVC_PAD;
90
+
hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP;
91
+
hdr->size = 2;
92
+
wmsg.pad = pin_id;
93
+
wmsg.wakeup = *configs;
94
+
ret = imx_scu_call_rpc(pinctrl_ipc_handle, &wmsg, true);
95
+
96
+
dev_dbg(ipctl->dev, "wakeup pin_id: %d type: %ld\n",
97
+
pin_id, *configs);
98
+
return ret;
99
+
}
96
100
97
101
/*
98
102
* Set mux and conf together in one IPC call
+11
drivers/pinctrl/intel/Kconfig
+11
drivers/pinctrl/intel/Kconfig
···
47
47
interface that allows configuring of SoC pins and using them as
48
48
GPIOs.
49
49
50
+
config PINCTRL_MOOREFIELD
51
+
tristate "Intel Moorefield pinctrl driver"
52
+
depends on X86_INTEL_MID
53
+
select PINMUX
54
+
select PINCONF
55
+
select GENERIC_PINCONF
56
+
help
57
+
Moorefield Family-Level Interface Shim (FLIS) driver provides an
58
+
interface that allows configuring of SoC pins and using them as
59
+
GPIOs.
60
+
50
61
config PINCTRL_INTEL
51
62
tristate
52
63
select PINMUX
+1
drivers/pinctrl/intel/Makefile
+1
drivers/pinctrl/intel/Makefile
···
5
5
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
6
6
obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
7
7
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
8
+
obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o
8
9
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
9
10
obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o
10
11
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
+16
-24
drivers/pinctrl/intel/pinctrl-alderlake.c
+16
-24
drivers/pinctrl/intel/pinctrl-alderlake.c
···
34
34
.gpio_base = (g), \
35
35
}
36
36
37
-
#define ADL_N_COMMUNITY(b, s, e, g) \
38
-
{ \
39
-
.barno = (b), \
40
-
.padown_offset = ADL_N_PAD_OWN, \
41
-
.padcfglock_offset = ADL_N_PADCFGLOCK, \
42
-
.hostown_offset = ADL_N_HOSTSW_OWN, \
43
-
.is_offset = ADL_N_GPI_IS, \
44
-
.ie_offset = ADL_N_GPI_IE, \
45
-
.pin_base = (s), \
46
-
.npins = ((e) - (s) + 1), \
47
-
.gpps = (g), \
48
-
.ngpps = ARRAY_SIZE(g), \
37
+
#define ADL_COMMUNITY(b, s, e, g, v) \
38
+
{ \
39
+
.barno = (b), \
40
+
.padown_offset = ADL_##v##_PAD_OWN, \
41
+
.padcfglock_offset = ADL_##v##_PADCFGLOCK, \
42
+
.hostown_offset = ADL_##v##_HOSTSW_OWN, \
43
+
.is_offset = ADL_##v##_GPI_IS, \
44
+
.ie_offset = ADL_##v##_GPI_IE, \
45
+
.pin_base = (s), \
46
+
.npins = ((e) - (s) + 1), \
47
+
.gpps = (g), \
48
+
.ngpps = ARRAY_SIZE(g), \
49
49
}
50
50
51
+
#define ADL_N_COMMUNITY(b, s, e, g) \
52
+
ADL_COMMUNITY(b, s, e, g, N)
53
+
51
54
#define ADL_S_COMMUNITY(b, s, e, g) \
52
-
{ \
53
-
.barno = (b), \
54
-
.padown_offset = ADL_S_PAD_OWN, \
55
-
.padcfglock_offset = ADL_S_PADCFGLOCK, \
56
-
.hostown_offset = ADL_S_HOSTSW_OWN, \
57
-
.is_offset = ADL_S_GPI_IS, \
58
-
.ie_offset = ADL_S_GPI_IE, \
59
-
.pin_base = (s), \
60
-
.npins = ((e) - (s) + 1), \
61
-
.gpps = (g), \
62
-
.ngpps = ARRAY_SIZE(g), \
63
-
}
55
+
ADL_COMMUNITY(b, s, e, g, S)
64
56
65
57
/* Alder Lake-N */
66
58
static const struct pinctrl_pin_desc adln_pins[] = {
+4
-4
drivers/pinctrl/intel/pinctrl-cannonlake.c
+4
-4
drivers/pinctrl/intel/pinctrl-cannonlake.c
···
30
30
.gpio_base = (g), \
31
31
}
32
32
33
-
#define CNL_COMMUNITY(b, s, e, ho, g) \
33
+
#define CNL_COMMUNITY(b, s, e, g, v) \
34
34
{ \
35
35
.barno = (b), \
36
36
.padown_offset = CNL_PAD_OWN, \
37
37
.padcfglock_offset = CNL_PADCFGLOCK, \
38
-
.hostown_offset = (ho), \
38
+
.hostown_offset = CNL_##v##_HOSTSW_OWN, \
39
39
.is_offset = CNL_GPI_IS, \
40
40
.ie_offset = CNL_GPI_IE, \
41
41
.pin_base = (s), \
···
45
45
}
46
46
47
47
#define CNL_LP_COMMUNITY(b, s, e, g) \
48
-
CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
48
+
CNL_COMMUNITY(b, s, e, g, LP)
49
49
50
50
#define CNL_H_COMMUNITY(b, s, e, g) \
51
-
CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
51
+
CNL_COMMUNITY(b, s, e, g, H)
52
52
53
53
/* Cannon Lake-H */
54
54
static const struct pinctrl_pin_desc cnlh_pins[] = {
+4
-2
drivers/pinctrl/intel/pinctrl-cherryview.c
+4
-2
drivers/pinctrl/intel/pinctrl-cherryview.c
···
16
16
#include <linux/kernel.h>
17
17
#include <linux/module.h>
18
18
#include <linux/platform_device.h>
19
+
#include <linux/seq_file.h>
19
20
#include <linux/types.h>
20
21
22
+
#include <linux/pinctrl/consumer.h>
23
+
#include <linux/pinctrl/pinconf-generic.h>
24
+
#include <linux/pinctrl/pinconf.h>
21
25
#include <linux/pinctrl/pinctrl.h>
22
26
#include <linux/pinctrl/pinmux.h>
23
-
#include <linux/pinctrl/pinconf.h>
24
-
#include <linux/pinctrl/pinconf-generic.h>
25
27
26
28
#include "pinctrl-intel.h"
27
29
+4
-4
drivers/pinctrl/intel/pinctrl-icelake.c
+4
-4
drivers/pinctrl/intel/pinctrl-icelake.c
···
30
30
.gpio_base = (g), \
31
31
}
32
32
33
-
#define ICL_COMMUNITY(b, s, e, ie, g) \
33
+
#define ICL_COMMUNITY(b, s, e, g, v) \
34
34
{ \
35
35
.barno = (b), \
36
36
.padown_offset = ICL_PAD_OWN, \
37
37
.padcfglock_offset = ICL_PADCFGLOCK, \
38
38
.hostown_offset = ICL_HOSTSW_OWN, \
39
39
.is_offset = ICL_GPI_IS, \
40
-
.ie_offset = (ie), \
40
+
.ie_offset = ICL_##v##_GPI_IE, \
41
41
.pin_base = (s), \
42
42
.npins = ((e) - (s) + 1), \
43
43
.gpps = (g), \
···
45
45
}
46
46
47
47
#define ICL_LP_COMMUNITY(b, s, e, g) \
48
-
ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g)
48
+
ICL_COMMUNITY(b, s, e, g, LP)
49
49
50
50
#define ICL_N_COMMUNITY(b, s, e, g) \
51
-
ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g)
51
+
ICL_COMMUNITY(b, s, e, g, N)
52
52
53
53
/* Ice Lake-LP */
54
54
static const struct pinctrl_pin_desc icllp_pins[] = {
+47
-14
drivers/pinctrl/intel/pinctrl-intel.c
+47
-14
drivers/pinctrl/intel/pinctrl-intel.c
···
14
14
#include <linux/module.h>
15
15
#include <linux/platform_device.h>
16
16
#include <linux/property.h>
17
+
#include <linux/seq_file.h>
18
+
#include <linux/string_helpers.h>
17
19
#include <linux/time.h>
18
20
19
-
#include <linux/pinctrl/pinctrl.h>
20
-
#include <linux/pinctrl/pinmux.h>
21
+
#include <linux/pinctrl/consumer.h>
21
22
#include <linux/pinctrl/pinconf.h>
22
23
#include <linux/pinctrl/pinconf-generic.h>
24
+
#include <linux/pinctrl/pinctrl.h>
25
+
#include <linux/pinctrl/pinmux.h>
26
+
27
+
#include <linux/platform_data/x86/pwm-lpss.h>
23
28
24
29
#include "../core.h"
25
30
#include "pinctrl-intel.h"
···
50
45
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
51
46
#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
52
47
#define PADOWN_GPP(p) ((p) / 8)
48
+
49
+
#define PWMC 0x204
53
50
54
51
/* Offset from pad_regs */
55
52
#define PADCFG0 0x000
···
1177
1170
else
1178
1171
disable_irq_wake(pctrl->irq);
1179
1172
1180
-
dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1173
+
dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin);
1181
1174
return 0;
1182
1175
}
1183
1176
···
1511
1504
return 0;
1512
1505
}
1513
1506
1507
+
static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
1508
+
struct intel_community *community)
1509
+
{
1510
+
static const struct pwm_lpss_boardinfo info = {
1511
+
.clk_rate = 19200000,
1512
+
.npwm = 1,
1513
+
.base_unit_bits = 22,
1514
+
.bypass = true,
1515
+
};
1516
+
struct pwm_lpss_chip *pwm;
1517
+
1518
+
if (!(community->features & PINCTRL_FEATURE_PWM))
1519
+
return 0;
1520
+
1521
+
if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1522
+
return 0;
1523
+
1524
+
pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
1525
+
return PTR_ERR_OR_ZERO(pwm);
1526
+
}
1527
+
1514
1528
static int intel_pinctrl_probe(struct platform_device *pdev,
1515
1529
const struct intel_pinctrl_soc_data *soc_data)
1516
1530
{
1531
+
struct device *dev = &pdev->dev;
1517
1532
struct intel_pinctrl *pctrl;
1518
1533
int i, ret, irq;
1519
1534
1520
-
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1535
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1521
1536
if (!pctrl)
1522
1537
return -ENOMEM;
1523
1538
1524
-
pctrl->dev = &pdev->dev;
1539
+
pctrl->dev = dev;
1525
1540
pctrl->soc = soc_data;
1526
1541
raw_spin_lock_init(&pctrl->lock);
1527
1542
···
1552
1523
* to the registers.
1553
1524
*/
1554
1525
pctrl->ncommunities = pctrl->soc->ncommunities;
1555
-
pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1556
-
sizeof(*pctrl->communities), GFP_KERNEL);
1526
+
pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities,
1527
+
sizeof(*pctrl->communities), GFP_KERNEL);
1557
1528
if (!pctrl->communities)
1558
1529
return -ENOMEM;
1559
1530
···
1604
1575
offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1605
1576
} while (offset);
1606
1577
1607
-
dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
1578
+
dev_dbg(dev, "Community%d features: %#08x\n", i, community->features);
1608
1579
1609
1580
/* Read offset of the pad configuration registers */
1610
1581
offset = readl(regs + PADBAR);
···
1618
1589
ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1619
1590
if (ret)
1620
1591
return ret;
1592
+
1593
+
ret = intel_pinctrl_probe_pwm(pctrl, community);
1594
+
if (ret)
1595
+
return ret;
1621
1596
}
1622
1597
1623
1598
irq = platform_get_irq(pdev, 0);
···
1633
1600
return ret;
1634
1601
1635
1602
pctrl->pctldesc = intel_pinctrl_desc;
1636
-
pctrl->pctldesc.name = dev_name(&pdev->dev);
1603
+
pctrl->pctldesc.name = dev_name(dev);
1637
1604
pctrl->pctldesc.pins = pctrl->soc->pins;
1638
1605
pctrl->pctldesc.npins = pctrl->soc->npins;
1639
1606
1640
-
pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1641
-
pctrl);
1607
+
pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1642
1608
if (IS_ERR(pctrl->pctldev)) {
1643
-
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1609
+
dev_err(dev, "failed to register pinctrl driver\n");
1644
1610
return PTR_ERR(pctrl->pctldev);
1645
1611
}
1646
1612
···
1680
1648
{
1681
1649
const struct intel_pinctrl_soc_data * const *table;
1682
1650
const struct intel_pinctrl_soc_data *data = NULL;
1651
+
struct device *dev = &pdev->dev;
1683
1652
1684
-
table = device_get_match_data(&pdev->dev);
1653
+
table = device_get_match_data(dev);
1685
1654
if (table) {
1686
-
struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
1655
+
struct acpi_device *adev = ACPI_COMPANION(dev);
1687
1656
unsigned int i;
1688
1657
1689
1658
for (i = 0; table[i]; i++) {
+4
-2
drivers/pinctrl/intel/pinctrl-lynxpoint.c
+4
-2
drivers/pinctrl/intel/pinctrl-lynxpoint.c
···
16
16
#include <linux/module.h>
17
17
#include <linux/platform_device.h>
18
18
#include <linux/pm_runtime.h>
19
+
#include <linux/seq_file.h>
19
20
#include <linux/slab.h>
20
21
#include <linux/types.h>
21
22
23
+
#include <linux/pinctrl/consumer.h>
24
+
#include <linux/pinctrl/pinconf-generic.h>
25
+
#include <linux/pinctrl/pinconf.h>
22
26
#include <linux/pinctrl/pinctrl.h>
23
27
#include <linux/pinctrl/pinmux.h>
24
-
#include <linux/pinctrl/pinconf.h>
25
-
#include <linux/pinctrl/pinconf-generic.h>
26
28
27
29
#include "pinctrl-intel.h"
28
30
+10
-9
drivers/pinctrl/intel/pinctrl-merrifield.c
+10
-9
drivers/pinctrl/intel/pinctrl-merrifield.c
···
12
12
#include <linux/module.h>
13
13
#include <linux/mod_devicetable.h>
14
14
#include <linux/platform_device.h>
15
-
#include <linux/pinctrl/pinconf.h>
15
+
#include <linux/seq_file.h>
16
+
16
17
#include <linux/pinctrl/pinconf-generic.h>
18
+
#include <linux/pinctrl/pinconf.h>
17
19
#include <linux/pinctrl/pinctrl.h>
18
20
#include <linux/pinctrl/pinmux.h>
19
21
···
897
895
898
896
static int mrfld_pinctrl_probe(struct platform_device *pdev)
899
897
{
898
+
struct device *dev = &pdev->dev;
900
899
struct mrfld_family *families;
901
900
struct mrfld_pinctrl *mp;
902
901
void __iomem *regs;
903
902
size_t nfamilies;
904
903
unsigned int i;
905
904
906
-
mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
905
+
mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
907
906
if (!mp)
908
907
return -ENOMEM;
909
908
910
-
mp->dev = &pdev->dev;
909
+
mp->dev = dev;
911
910
raw_spin_lock_init(&mp->lock);
912
911
913
912
regs = devm_platform_ioremap_resource(pdev, 0);
···
920
917
* to the registers.
921
918
*/
922
919
nfamilies = ARRAY_SIZE(mrfld_families),
923
-
families = devm_kmemdup(&pdev->dev, mrfld_families,
924
-
sizeof(mrfld_families),
925
-
GFP_KERNEL);
920
+
families = devm_kmemdup(dev, mrfld_families, sizeof(mrfld_families), GFP_KERNEL);
926
921
if (!families)
927
922
return -ENOMEM;
928
923
···
938
937
mp->groups = mrfld_groups;
939
938
mp->ngroups = ARRAY_SIZE(mrfld_groups);
940
939
mp->pctldesc = mrfld_pinctrl_desc;
941
-
mp->pctldesc.name = dev_name(&pdev->dev);
940
+
mp->pctldesc.name = dev_name(dev);
942
941
mp->pctldesc.pins = mrfld_pins;
943
942
mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
944
943
945
-
mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
944
+
mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp);
946
945
if (IS_ERR(mp->pctldev)) {
947
-
dev_err(&pdev->dev, "failed to register pinctrl driver\n");
946
+
dev_err(dev, "failed to register pinctrl driver\n");
948
947
return PTR_ERR(mp->pctldev);
949
948
}
950
949
+916
drivers/pinctrl/intel/pinctrl-moorefield.c
+916
drivers/pinctrl/intel/pinctrl-moorefield.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Intel Moorefield SoC pinctrl driver
4
+
*
5
+
* Copyright (C) 2022, Intel Corporation
6
+
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7
+
*/
8
+
9
+
#include <linux/bits.h>
10
+
#include <linux/err.h>
11
+
#include <linux/io.h>
12
+
#include <linux/module.h>
13
+
#include <linux/mod_devicetable.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/seq_file.h>
16
+
17
+
#include <linux/pinctrl/pinconf-generic.h>
18
+
#include <linux/pinctrl/pinconf.h>
19
+
#include <linux/pinctrl/pinctrl.h>
20
+
#include <linux/pinctrl/pinmux.h>
21
+
22
+
#include "pinctrl-intel.h"
23
+
24
+
#define MOFLD_FAMILY_NR 64
25
+
#define MOFLD_FAMILY_LEN 0x400
26
+
27
+
#define SLEW_OFFSET 0x000
28
+
#define BUFCFG_OFFSET 0x100
29
+
#define MISC_OFFSET 0x300
30
+
31
+
#define BUFCFG_PINMODE_SHIFT 0
32
+
#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
33
+
#define BUFCFG_PINMODE_GPIO 0
34
+
#define BUFCFG_PUPD_VAL_SHIFT 4
35
+
#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
36
+
#define BUFCFG_PUPD_VAL_2K 0
37
+
#define BUFCFG_PUPD_VAL_20K 1
38
+
#define BUFCFG_PUPD_VAL_50K 2
39
+
#define BUFCFG_PUPD_VAL_910 3
40
+
#define BUFCFG_PU_EN BIT(8)
41
+
#define BUFCFG_PD_EN BIT(9)
42
+
#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
43
+
#define BUFCFG_SLEWSEL BIT(10)
44
+
#define BUFCFG_OVINEN BIT(12)
45
+
#define BUFCFG_OVINEN_EN BIT(13)
46
+
#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
47
+
#define BUFCFG_OVOUTEN BIT(14)
48
+
#define BUFCFG_OVOUTEN_EN BIT(15)
49
+
#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
50
+
#define BUFCFG_INDATAOV_VAL BIT(16)
51
+
#define BUFCFG_INDATAOV_EN BIT(17)
52
+
#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
53
+
#define BUFCFG_OUTDATAOV_VAL BIT(18)
54
+
#define BUFCFG_OUTDATAOV_EN BIT(19)
55
+
#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
56
+
#define BUFCFG_OD_EN BIT(21)
57
+
58
+
/**
59
+
* struct mofld_family - Intel pin family description
60
+
* @barno: MMIO BAR number where registers for this family reside
61
+
* @pin_base: Starting pin of pins in this family
62
+
* @npins: Number of pins in this family
63
+
* @protected: True if family is protected by access
64
+
* @regs: family specific common registers
65
+
*/
66
+
struct mofld_family {
67
+
unsigned int barno;
68
+
unsigned int pin_base;
69
+
size_t npins;
70
+
bool protected;
71
+
void __iomem *regs;
72
+
};
73
+
74
+
#define MOFLD_FAMILY(b, s, e) \
75
+
{ \
76
+
.barno = (b), \
77
+
.pin_base = (s), \
78
+
.npins = (e) - (s) + 1, \
79
+
}
80
+
81
+
static const struct pinctrl_pin_desc mofld_pins[] = {
82
+
/* ULPI (13 pins) */
83
+
PINCTRL_PIN(0, "GP101_ULPI_CLK"),
84
+
PINCTRL_PIN(1, "GP136_ULPI_D0"),
85
+
PINCTRL_PIN(2, "GP143_ULPI_D1"),
86
+
PINCTRL_PIN(3, "GP144_ULPI_D2"),
87
+
PINCTRL_PIN(4, "GP145_ULPI_D3"),
88
+
PINCTRL_PIN(5, "GP146_ULPI_D4"),
89
+
PINCTRL_PIN(6, "GP147_ULPI_D5"),
90
+
PINCTRL_PIN(7, "GP148_ULPI_D6"),
91
+
PINCTRL_PIN(8, "GP149_ULPI_D7"),
92
+
PINCTRL_PIN(9, "ULPI_DIR"),
93
+
PINCTRL_PIN(10, "ULPI_NXT"),
94
+
PINCTRL_PIN(11, "ULPI_REFCLK"),
95
+
PINCTRL_PIN(12, "ULPI_STP"),
96
+
/* eMMC (12 pins) */
97
+
PINCTRL_PIN(13, "EMMC_CLK"),
98
+
PINCTRL_PIN(14, "EMMC_CMD"),
99
+
PINCTRL_PIN(15, "EMMC_D0"),
100
+
PINCTRL_PIN(16, "EMMC_D1"),
101
+
PINCTRL_PIN(17, "EMMC_D2"),
102
+
PINCTRL_PIN(18, "EMMC_D3"),
103
+
PINCTRL_PIN(19, "EMMC_D4"),
104
+
PINCTRL_PIN(20, "EMMC_D5"),
105
+
PINCTRL_PIN(21, "EMMC_D6"),
106
+
PINCTRL_PIN(22, "EMMC_D7"),
107
+
PINCTRL_PIN(23, "EMMC_RST_N"),
108
+
PINCTRL_PIN(24, "EMMC_RCLK"),
109
+
/* SDIO (20 pins) */
110
+
PINCTRL_PIN(25, "GP77_SD_CD"),
111
+
PINCTRL_PIN(26, "GP78_SD_CLK"),
112
+
PINCTRL_PIN(27, "GP79_SD_CMD"),
113
+
PINCTRL_PIN(28, "GP80_SD_D0"),
114
+
PINCTRL_PIN(29, "GP81_SD_D1"),
115
+
PINCTRL_PIN(30, "GP82_SD_D2"),
116
+
PINCTRL_PIN(31, "GP83_SD_D3"),
117
+
PINCTRL_PIN(32, "GP84_SD_LS_CLK_FB"),
118
+
PINCTRL_PIN(33, "GP85_SD_LS_CMD_DIR"),
119
+
PINCTRL_PIN(34, "GP86_SD_LS_D_DIR"),
120
+
PINCTRL_PIN(35, "GP88_SD_LS_SEL"),
121
+
PINCTRL_PIN(36, "GP87_SD_PD"),
122
+
PINCTRL_PIN(37, "GP89_SD_WP"),
123
+
PINCTRL_PIN(38, "GP90_SDIO_CLK"),
124
+
PINCTRL_PIN(39, "GP91_SDIO_CMD"),
125
+
PINCTRL_PIN(40, "GP92_SDIO_D0"),
126
+
PINCTRL_PIN(41, "GP93_SDIO_D1"),
127
+
PINCTRL_PIN(42, "GP94_SDIO_D2"),
128
+
PINCTRL_PIN(43, "GP95_SDIO_D3"),
129
+
PINCTRL_PIN(44, "GP96_SDIO_PD"),
130
+
/* HSI (8 pins) */
131
+
PINCTRL_PIN(45, "HSI_ACDATA"),
132
+
PINCTRL_PIN(46, "HSI_ACFLAG"),
133
+
PINCTRL_PIN(47, "HSI_ACREADY"),
134
+
PINCTRL_PIN(48, "HSI_ACWAKE"),
135
+
PINCTRL_PIN(49, "HSI_CADATA"),
136
+
PINCTRL_PIN(50, "HSI_CAFLAG"),
137
+
PINCTRL_PIN(51, "HSI_CAREADY"),
138
+
PINCTRL_PIN(52, "HSI_CAWAKE"),
139
+
/* SSP Audio (14 pins) */
140
+
PINCTRL_PIN(53, "GP70"),
141
+
PINCTRL_PIN(54, "GP71"),
142
+
PINCTRL_PIN(55, "GP32_I2S_0_CLK"),
143
+
PINCTRL_PIN(56, "GP33_I2S_0_FS"),
144
+
PINCTRL_PIN(57, "GP34_I2S_0_RXD"),
145
+
PINCTRL_PIN(58, "GP35_I2S_0_TXD"),
146
+
PINCTRL_PIN(59, "GP36_I2S_1_CLK"),
147
+
PINCTRL_PIN(60, "GP37_I2S_1_FS"),
148
+
PINCTRL_PIN(61, "GP38_I2S_1_RXD"),
149
+
PINCTRL_PIN(62, "GP39_I2S_1_TXD"),
150
+
PINCTRL_PIN(63, "GP40_I2S_2_CLK"),
151
+
PINCTRL_PIN(64, "GP41_I2S_2_FS"),
152
+
PINCTRL_PIN(65, "GP42_I2S_2_RXD"),
153
+
PINCTRL_PIN(66, "GP43_I2S_2_TXD"),
154
+
/* GP SSP (22 pins) */
155
+
PINCTRL_PIN(67, "GP120_SPI_0_CLK"),
156
+
PINCTRL_PIN(68, "GP121_SPI_0_SS"),
157
+
PINCTRL_PIN(69, "GP122_SPI_0_RXD"),
158
+
PINCTRL_PIN(70, "GP123_SPI_0_TXD"),
159
+
PINCTRL_PIN(71, "GP102_SPI_1_CLK"),
160
+
PINCTRL_PIN(72, "GP103_SPI_1_SS0"),
161
+
PINCTRL_PIN(73, "GP104_SPI_1_SS1"),
162
+
PINCTRL_PIN(74, "GP105_SPI_1_SS2"),
163
+
PINCTRL_PIN(75, "GP106_SPI_1_SS3"),
164
+
PINCTRL_PIN(76, "GP107_SPI_1_RXD"),
165
+
PINCTRL_PIN(77, "GP108_SPI_1_TXD"),
166
+
PINCTRL_PIN(78, "GP109_SPI_2_CLK"),
167
+
PINCTRL_PIN(79, "GP110_SPI_2_SS0"),
168
+
PINCTRL_PIN(80, "GP111_SPI_2_SS1"),
169
+
PINCTRL_PIN(81, "GP112_SPI_2_SS2"),
170
+
PINCTRL_PIN(82, "GP113_SPI_2_SS3"),
171
+
PINCTRL_PIN(83, "GP114_SPI_2_RXD"),
172
+
PINCTRL_PIN(84, "GP115_SPI_2_TXD"),
173
+
PINCTRL_PIN(85, "GP116_SPI_3_CLK"),
174
+
PINCTRL_PIN(86, "GP117_SPI_3_SS"),
175
+
PINCTRL_PIN(87, "GP118_SPI_3_RXD"),
176
+
PINCTRL_PIN(88, "GP119_SPI_3_TXD"),
177
+
/* I2C (20 pins) */
178
+
PINCTRL_PIN(89, "I2C_0_SCL"),
179
+
PINCTRL_PIN(90, "I2C_0_SDA"),
180
+
PINCTRL_PIN(91, "GP19_I2C_1_SCL"),
181
+
PINCTRL_PIN(92, "GP20_I2C_1_SDA"),
182
+
PINCTRL_PIN(93, "GP21_I2C_2_SCL"),
183
+
PINCTRL_PIN(94, "GP22_I2C_2_SDA"),
184
+
PINCTRL_PIN(95, "GP17_I2C_3_SCL_HDMI"),
185
+
PINCTRL_PIN(96, "GP18_I2C_3_SDA_HDMI"),
186
+
PINCTRL_PIN(97, "GP23_I2C_4_SCL"),
187
+
PINCTRL_PIN(98, "GP24_I2C_4_SDA"),
188
+
PINCTRL_PIN(99, "GP25_I2C_5_SCL"),
189
+
PINCTRL_PIN(100, "GP26_I2C_5_SDA"),
190
+
PINCTRL_PIN(101, "GP27_I2C_6_SCL"),
191
+
PINCTRL_PIN(102, "GP28_I2C_6_SDA"),
192
+
PINCTRL_PIN(103, "GP29_I2C_7_SCL"),
193
+
PINCTRL_PIN(104, "GP30_I2C_7_SDA"),
194
+
PINCTRL_PIN(105, "I2C_8_SCL"),
195
+
PINCTRL_PIN(106, "I2C_8_SDA"),
196
+
PINCTRL_PIN(107, "I2C_9_SCL"),
197
+
PINCTRL_PIN(108, "I2C_9_SDA"),
198
+
/* UART (23 pins) */
199
+
PINCTRL_PIN(109, "GP124_UART_0_CTS"),
200
+
PINCTRL_PIN(110, "GP125_UART_0_RTS"),
201
+
PINCTRL_PIN(111, "GP126_UART_0_RX"),
202
+
PINCTRL_PIN(112, "GP127_UART_0_TX"),
203
+
PINCTRL_PIN(113, "GP128_UART_1_CTS"),
204
+
PINCTRL_PIN(114, "GP129_UART_1_RTS"),
205
+
PINCTRL_PIN(115, "GP130_UART_1_RX"),
206
+
PINCTRL_PIN(116, "GP131_UART_1_TX"),
207
+
PINCTRL_PIN(117, "GP132_UART_2_CTS"),
208
+
PINCTRL_PIN(118, "GP133_UART_2_RTS"),
209
+
PINCTRL_PIN(119, "GP134_UART_2_RX"),
210
+
PINCTRL_PIN(120, "GP135_UART_2_TX"),
211
+
PINCTRL_PIN(121, "GP97"),
212
+
PINCTRL_PIN(122, "GP154"),
213
+
PINCTRL_PIN(123, "GP155"),
214
+
PINCTRL_PIN(124, "GP156"),
215
+
PINCTRL_PIN(125, "GP157"),
216
+
PINCTRL_PIN(126, "GP158"),
217
+
PINCTRL_PIN(127, "GP159"),
218
+
PINCTRL_PIN(128, "GP160"),
219
+
PINCTRL_PIN(129, "GP161"),
220
+
PINCTRL_PIN(130, "GP12_PWM0"),
221
+
PINCTRL_PIN(131, "GP13_PWM1"),
222
+
/* GPIO South (20 pins) */
223
+
PINCTRL_PIN(132, "GP176"),
224
+
PINCTRL_PIN(133, "GP177"),
225
+
PINCTRL_PIN(134, "GP178"),
226
+
PINCTRL_PIN(135, "GP179"),
227
+
PINCTRL_PIN(136, "GP180"),
228
+
PINCTRL_PIN(137, "GP181"),
229
+
PINCTRL_PIN(138, "GP182_PWM2"),
230
+
PINCTRL_PIN(139, "GP183_PWM3"),
231
+
PINCTRL_PIN(140, "GP184"),
232
+
PINCTRL_PIN(141, "GP185"),
233
+
PINCTRL_PIN(142, "GP186"),
234
+
PINCTRL_PIN(143, "GP187"),
235
+
PINCTRL_PIN(144, "GP188"),
236
+
PINCTRL_PIN(145, "GP189"),
237
+
PINCTRL_PIN(146, "GP190"),
238
+
PINCTRL_PIN(147, "GP191"),
239
+
PINCTRL_PIN(148, "GP14"),
240
+
PINCTRL_PIN(149, "GP15"),
241
+
PINCTRL_PIN(150, "GP162"),
242
+
PINCTRL_PIN(151, "GP163"),
243
+
/* Camera Sideband (15 pins) */
244
+
PINCTRL_PIN(152, "GP0"),
245
+
PINCTRL_PIN(153, "GP1"),
246
+
PINCTRL_PIN(154, "GP2"),
247
+
PINCTRL_PIN(155, "GP3"),
248
+
PINCTRL_PIN(156, "GP4"),
249
+
PINCTRL_PIN(157, "GP5"),
250
+
PINCTRL_PIN(158, "GP6"),
251
+
PINCTRL_PIN(159, "GP7"),
252
+
PINCTRL_PIN(160, "GP8"),
253
+
PINCTRL_PIN(161, "GP9"),
254
+
PINCTRL_PIN(162, "GP10"),
255
+
PINCTRL_PIN(163, "GP11"),
256
+
PINCTRL_PIN(164, "GP16_HDMI_HPD"),
257
+
PINCTRL_PIN(165, "GP68_DSI_A_TE"),
258
+
PINCTRL_PIN(166, "GP69_DSI_C_TE"),
259
+
/* Clock (14 pins) */
260
+
PINCTRL_PIN(167, "GP137"),
261
+
PINCTRL_PIN(168, "GP138"),
262
+
PINCTRL_PIN(169, "GP139"),
263
+
PINCTRL_PIN(170, "GP140"),
264
+
PINCTRL_PIN(171, "GP141"),
265
+
PINCTRL_PIN(172, "GP142"),
266
+
PINCTRL_PIN(173, "GP98"),
267
+
PINCTRL_PIN(174, "OSC_CLK_CTRL0"),
268
+
PINCTRL_PIN(175, "OSC_CLK_CTRL1"),
269
+
PINCTRL_PIN(176, "OSC_CLK0"),
270
+
PINCTRL_PIN(177, "OSC_CLK1"),
271
+
PINCTRL_PIN(178, "OSC_CLK2"),
272
+
PINCTRL_PIN(179, "OSC_CLK3"),
273
+
PINCTRL_PIN(180, "OSC_CLK4"),
274
+
/* PMIC (15 pins) */
275
+
PINCTRL_PIN(181, "PROCHOT"),
276
+
PINCTRL_PIN(182, "RESETOUT"),
277
+
PINCTRL_PIN(183, "RTC_CLK"),
278
+
PINCTRL_PIN(184, "STANDBY"),
279
+
PINCTRL_PIN(185, "SVID_ALERT"),
280
+
PINCTRL_PIN(186, "SVID_CLK"),
281
+
PINCTRL_PIN(187, "SVID_D"),
282
+
PINCTRL_PIN(188, "THERMTRIP"),
283
+
PINCTRL_PIN(189, "PREQ"),
284
+
PINCTRL_PIN(190, "ZQ_A"),
285
+
PINCTRL_PIN(191, "ZQ_B"),
286
+
PINCTRL_PIN(192, "GP64_FAST_INT0"),
287
+
PINCTRL_PIN(193, "GP65_FAST_INT1"),
288
+
PINCTRL_PIN(194, "GP66_FAST_INT2"),
289
+
PINCTRL_PIN(195, "GP67_FAST_INT3"),
290
+
/* Keyboard (20 pins) */
291
+
PINCTRL_PIN(196, "GP44"),
292
+
PINCTRL_PIN(197, "GP45"),
293
+
PINCTRL_PIN(198, "GP46"),
294
+
PINCTRL_PIN(199, "GP47"),
295
+
PINCTRL_PIN(200, "GP48"),
296
+
PINCTRL_PIN(201, "GP49"),
297
+
PINCTRL_PIN(202, "GP50"),
298
+
PINCTRL_PIN(203, "GP51"),
299
+
PINCTRL_PIN(204, "GP52"),
300
+
PINCTRL_PIN(205, "GP53"),
301
+
PINCTRL_PIN(206, "GP54"),
302
+
PINCTRL_PIN(207, "GP55"),
303
+
PINCTRL_PIN(208, "GP56"),
304
+
PINCTRL_PIN(209, "GP57"),
305
+
PINCTRL_PIN(210, "GP58"),
306
+
PINCTRL_PIN(211, "GP59"),
307
+
PINCTRL_PIN(212, "GP60"),
308
+
PINCTRL_PIN(213, "GP61"),
309
+
PINCTRL_PIN(214, "GP62"),
310
+
PINCTRL_PIN(215, "GP63"),
311
+
/* GPIO North (13 pins) */
312
+
PINCTRL_PIN(216, "GP164"),
313
+
PINCTRL_PIN(217, "GP165"),
314
+
PINCTRL_PIN(218, "GP166"),
315
+
PINCTRL_PIN(219, "GP167"),
316
+
PINCTRL_PIN(220, "GP168_MJTAG_TCK"),
317
+
PINCTRL_PIN(221, "GP169_MJTAG_TDI"),
318
+
PINCTRL_PIN(222, "GP170_MJTAG_TDO"),
319
+
PINCTRL_PIN(223, "GP171_MJTAG_TMS"),
320
+
PINCTRL_PIN(224, "GP172_MJTAG_TRST"),
321
+
PINCTRL_PIN(225, "GP173"),
322
+
PINCTRL_PIN(226, "GP174"),
323
+
PINCTRL_PIN(227, "GP175"),
324
+
PINCTRL_PIN(228, "GP176"),
325
+
/* PTI (22 pins) */
326
+
PINCTRL_PIN(229, "GP72_PTI_CLK"),
327
+
PINCTRL_PIN(230, "GP73_PTI_D0"),
328
+
PINCTRL_PIN(231, "GP74_PTI_D1"),
329
+
PINCTRL_PIN(232, "GP75_PTI_D2"),
330
+
PINCTRL_PIN(233, "GP76_PTI_D3"),
331
+
PINCTRL_PIN(234, "GP164"),
332
+
PINCTRL_PIN(235, "GP165"),
333
+
PINCTRL_PIN(236, "GP166"),
334
+
PINCTRL_PIN(237, "GP167"),
335
+
PINCTRL_PIN(238, "GP168_MJTAG_TCK"),
336
+
PINCTRL_PIN(239, "GP169_MJTAG_TDI"),
337
+
PINCTRL_PIN(240, "GP170_MJTAG_TDO"),
338
+
PINCTRL_PIN(241, "GP171_MJTAG_TMS"),
339
+
PINCTRL_PIN(242, "GP172_MJTAG_TRST"),
340
+
PINCTRL_PIN(243, "GP173"),
341
+
PINCTRL_PIN(244, "GP174"),
342
+
PINCTRL_PIN(245, "GP175"),
343
+
PINCTRL_PIN(246, "JTAG_TCK"),
344
+
PINCTRL_PIN(247, "JTAG_TDI"),
345
+
PINCTRL_PIN(248, "JTAG_TDO"),
346
+
PINCTRL_PIN(249, "JTAG_TMS"),
347
+
PINCTRL_PIN(250, "JTAG_TRST"),
348
+
};
349
+
350
+
static const struct mofld_family mofld_families[] = {
351
+
MOFLD_FAMILY(0, 0, 12),
352
+
MOFLD_FAMILY(1, 13, 24),
353
+
MOFLD_FAMILY(2, 25, 44),
354
+
MOFLD_FAMILY(3, 45, 52),
355
+
MOFLD_FAMILY(4, 53, 66),
356
+
MOFLD_FAMILY(5, 67, 88),
357
+
MOFLD_FAMILY(6, 89, 108),
358
+
MOFLD_FAMILY(7, 109, 131),
359
+
MOFLD_FAMILY(8, 132, 151),
360
+
MOFLD_FAMILY(9, 152, 166),
361
+
MOFLD_FAMILY(10, 167, 180),
362
+
MOFLD_FAMILY(11, 181, 195),
363
+
MOFLD_FAMILY(12, 196, 215),
364
+
MOFLD_FAMILY(13, 216, 228),
365
+
MOFLD_FAMILY(14, 229, 250),
366
+
};
367
+
368
+
/**
369
+
* struct mofld_pinctrl - Intel Merrifield pinctrl private structure
370
+
* @dev: Pointer to the device structure
371
+
* @lock: Lock to serialize register access
372
+
* @pctldesc: Pin controller description
373
+
* @pctldev: Pointer to the pin controller device
374
+
* @families: Array of families this pinctrl handles
375
+
* @nfamilies: Number of families in the array
376
+
* @functions: Array of functions
377
+
* @nfunctions: Number of functions in the array
378
+
* @groups: Array of pin groups
379
+
* @ngroups: Number of groups in the array
380
+
* @pins: Array of pins this pinctrl controls
381
+
* @npins: Number of pins in the array
382
+
*/
383
+
struct mofld_pinctrl {
384
+
struct device *dev;
385
+
raw_spinlock_t lock;
386
+
struct pinctrl_desc pctldesc;
387
+
struct pinctrl_dev *pctldev;
388
+
389
+
/* Pin controller configuration */
390
+
const struct mofld_family *families;
391
+
size_t nfamilies;
392
+
const struct intel_function *functions;
393
+
size_t nfunctions;
394
+
const struct intel_pingroup *groups;
395
+
size_t ngroups;
396
+
const struct pinctrl_pin_desc *pins;
397
+
size_t npins;
398
+
};
399
+
400
+
#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
401
+
402
+
static const struct mofld_family *mofld_get_family(struct mofld_pinctrl *mp, unsigned int pin)
403
+
{
404
+
const struct mofld_family *family;
405
+
unsigned int i;
406
+
407
+
for (i = 0; i < mp->nfamilies; i++) {
408
+
family = &mp->families[i];
409
+
if (pin >= family->pin_base &&
410
+
pin < family->pin_base + family->npins)
411
+
return family;
412
+
}
413
+
414
+
dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
415
+
return NULL;
416
+
}
417
+
418
+
static bool mofld_buf_available(struct mofld_pinctrl *mp, unsigned int pin)
419
+
{
420
+
const struct mofld_family *family;
421
+
422
+
family = mofld_get_family(mp, pin);
423
+
if (!family)
424
+
return false;
425
+
426
+
return !family->protected;
427
+
}
428
+
429
+
static void __iomem *mofld_get_bufcfg(struct mofld_pinctrl *mp, unsigned int pin)
430
+
{
431
+
const struct mofld_family *family;
432
+
unsigned int bufno;
433
+
434
+
family = mofld_get_family(mp, pin);
435
+
if (!family)
436
+
return NULL;
437
+
438
+
bufno = pin_to_bufno(family, pin);
439
+
return family->regs + BUFCFG_OFFSET + bufno * 4;
440
+
}
441
+
442
+
static int mofld_read_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 *value)
443
+
{
444
+
void __iomem *bufcfg;
445
+
446
+
if (!mofld_buf_available(mp, pin))
447
+
return -EBUSY;
448
+
449
+
bufcfg = mofld_get_bufcfg(mp, pin);
450
+
*value = readl(bufcfg);
451
+
452
+
return 0;
453
+
}
454
+
455
+
static void mofld_update_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 bits, u32 mask)
456
+
{
457
+
void __iomem *bufcfg;
458
+
u32 value;
459
+
460
+
bufcfg = mofld_get_bufcfg(mp, pin);
461
+
value = readl(bufcfg);
462
+
463
+
value &= ~mask;
464
+
value |= bits & mask;
465
+
466
+
writel(value, bufcfg);
467
+
}
468
+
469
+
static int mofld_get_groups_count(struct pinctrl_dev *pctldev)
470
+
{
471
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
472
+
473
+
return mp->ngroups;
474
+
}
475
+
476
+
static const char *mofld_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
477
+
{
478
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
479
+
480
+
return mp->groups[group].grp.name;
481
+
}
482
+
483
+
static int mofld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
484
+
const unsigned int **pins, unsigned int *npins)
485
+
{
486
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
487
+
488
+
*pins = mp->groups[group].grp.pins;
489
+
*npins = mp->groups[group].grp.npins;
490
+
return 0;
491
+
}
492
+
493
+
static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
494
+
unsigned int pin)
495
+
{
496
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
497
+
u32 value, mode;
498
+
int ret;
499
+
500
+
ret = mofld_read_bufcfg(mp, pin, &value);
501
+
if (ret) {
502
+
seq_puts(s, "not available");
503
+
return;
504
+
}
505
+
506
+
mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
507
+
if (!mode)
508
+
seq_puts(s, "GPIO ");
509
+
else
510
+
seq_printf(s, "mode %d ", mode);
511
+
512
+
seq_printf(s, "0x%08x", value);
513
+
}
514
+
515
+
static const struct pinctrl_ops mofld_pinctrl_ops = {
516
+
.get_groups_count = mofld_get_groups_count,
517
+
.get_group_name = mofld_get_group_name,
518
+
.get_group_pins = mofld_get_group_pins,
519
+
.pin_dbg_show = mofld_pin_dbg_show,
520
+
};
521
+
522
+
static int mofld_get_functions_count(struct pinctrl_dev *pctldev)
523
+
{
524
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
525
+
526
+
return mp->nfunctions;
527
+
}
528
+
529
+
static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
530
+
{
531
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
532
+
533
+
return mp->functions[function].name;
534
+
}
535
+
536
+
static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
537
+
const char * const **groups, unsigned int * const ngroups)
538
+
{
539
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
540
+
541
+
*groups = mp->functions[function].groups;
542
+
*ngroups = mp->functions[function].ngroups;
543
+
return 0;
544
+
}
545
+
546
+
static int mofld_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
547
+
unsigned int group)
548
+
{
549
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
550
+
const struct intel_pingroup *grp = &mp->groups[group];
551
+
u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
552
+
u32 mask = BUFCFG_PINMODE_MASK;
553
+
unsigned long flags;
554
+
unsigned int i;
555
+
556
+
/*
557
+
* All pins in the groups needs to be accessible and writable
558
+
* before we can enable the mux for this group.
559
+
*/
560
+
for (i = 0; i < grp->grp.npins; i++) {
561
+
if (!mofld_buf_available(mp, grp->grp.pins[i]))
562
+
return -EBUSY;
563
+
}
564
+
565
+
/* Now enable the mux setting for each pin in the group */
566
+
raw_spin_lock_irqsave(&mp->lock, flags);
567
+
for (i = 0; i < grp->grp.npins; i++)
568
+
mofld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
569
+
raw_spin_unlock_irqrestore(&mp->lock, flags);
570
+
571
+
return 0;
572
+
}
573
+
574
+
static int mofld_gpio_request_enable(struct pinctrl_dev *pctldev,
575
+
struct pinctrl_gpio_range *range,
576
+
unsigned int pin)
577
+
{
578
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
579
+
u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
580
+
u32 mask = BUFCFG_PINMODE_MASK;
581
+
unsigned long flags;
582
+
583
+
if (!mofld_buf_available(mp, pin))
584
+
return -EBUSY;
585
+
586
+
raw_spin_lock_irqsave(&mp->lock, flags);
587
+
mofld_update_bufcfg(mp, pin, bits, mask);
588
+
raw_spin_unlock_irqrestore(&mp->lock, flags);
589
+
590
+
return 0;
591
+
}
592
+
593
+
static const struct pinmux_ops mofld_pinmux_ops = {
594
+
.get_functions_count = mofld_get_functions_count,
595
+
.get_function_name = mofld_get_function_name,
596
+
.get_function_groups = mofld_get_function_groups,
597
+
.set_mux = mofld_pinmux_set_mux,
598
+
.gpio_request_enable = mofld_gpio_request_enable,
599
+
};
600
+
601
+
static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
602
+
unsigned long *config)
603
+
{
604
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
605
+
enum pin_config_param param = pinconf_to_config_param(*config);
606
+
u32 value, term;
607
+
u16 arg = 0;
608
+
int ret;
609
+
610
+
ret = mofld_read_bufcfg(mp, pin, &value);
611
+
if (ret)
612
+
return -ENOTSUPP;
613
+
614
+
term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
615
+
616
+
switch (param) {
617
+
case PIN_CONFIG_BIAS_DISABLE:
618
+
if (value & BUFCFG_Px_EN_MASK)
619
+
return -EINVAL;
620
+
break;
621
+
622
+
case PIN_CONFIG_BIAS_PULL_UP:
623
+
if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
624
+
return -EINVAL;
625
+
626
+
switch (term) {
627
+
case BUFCFG_PUPD_VAL_910:
628
+
arg = 910;
629
+
break;
630
+
case BUFCFG_PUPD_VAL_2K:
631
+
arg = 2000;
632
+
break;
633
+
case BUFCFG_PUPD_VAL_20K:
634
+
arg = 20000;
635
+
break;
636
+
case BUFCFG_PUPD_VAL_50K:
637
+
arg = 50000;
638
+
break;
639
+
}
640
+
641
+
break;
642
+
643
+
case PIN_CONFIG_BIAS_PULL_DOWN:
644
+
if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
645
+
return -EINVAL;
646
+
647
+
switch (term) {
648
+
case BUFCFG_PUPD_VAL_910:
649
+
arg = 910;
650
+
break;
651
+
case BUFCFG_PUPD_VAL_2K:
652
+
arg = 2000;
653
+
break;
654
+
case BUFCFG_PUPD_VAL_20K:
655
+
arg = 20000;
656
+
break;
657
+
case BUFCFG_PUPD_VAL_50K:
658
+
arg = 50000;
659
+
break;
660
+
}
661
+
662
+
break;
663
+
664
+
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
665
+
if (!(value & BUFCFG_OD_EN))
666
+
return -EINVAL;
667
+
break;
668
+
669
+
case PIN_CONFIG_SLEW_RATE:
670
+
if (!(value & BUFCFG_SLEWSEL))
671
+
arg = 0;
672
+
else
673
+
arg = 1;
674
+
break;
675
+
676
+
default:
677
+
return -ENOTSUPP;
678
+
}
679
+
680
+
*config = pinconf_to_config_packed(param, arg);
681
+
return 0;
682
+
}
683
+
684
+
static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin,
685
+
unsigned long config)
686
+
{
687
+
unsigned int param = pinconf_to_config_param(config);
688
+
unsigned int arg = pinconf_to_config_argument(config);
689
+
u32 bits = 0, mask = 0;
690
+
unsigned long flags;
691
+
692
+
switch (param) {
693
+
case PIN_CONFIG_BIAS_DISABLE:
694
+
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
695
+
break;
696
+
697
+
case PIN_CONFIG_BIAS_PULL_UP:
698
+
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
699
+
bits |= BUFCFG_PU_EN;
700
+
701
+
switch (arg) {
702
+
case 50000:
703
+
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
704
+
break;
705
+
case 20000:
706
+
bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
707
+
break;
708
+
case 2000:
709
+
bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
710
+
break;
711
+
default:
712
+
return -EINVAL;
713
+
}
714
+
715
+
break;
716
+
717
+
case PIN_CONFIG_BIAS_PULL_DOWN:
718
+
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
719
+
bits |= BUFCFG_PD_EN;
720
+
721
+
switch (arg) {
722
+
case 50000:
723
+
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
724
+
break;
725
+
case 20000:
726
+
bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
727
+
break;
728
+
case 2000:
729
+
bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
730
+
break;
731
+
default:
732
+
return -EINVAL;
733
+
}
734
+
735
+
break;
736
+
737
+
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
738
+
mask |= BUFCFG_OD_EN;
739
+
if (arg)
740
+
bits |= BUFCFG_OD_EN;
741
+
break;
742
+
743
+
case PIN_CONFIG_SLEW_RATE:
744
+
mask |= BUFCFG_SLEWSEL;
745
+
if (arg)
746
+
bits |= BUFCFG_SLEWSEL;
747
+
break;
748
+
}
749
+
750
+
raw_spin_lock_irqsave(&mp->lock, flags);
751
+
mofld_update_bufcfg(mp, pin, bits, mask);
752
+
raw_spin_unlock_irqrestore(&mp->lock, flags);
753
+
754
+
return 0;
755
+
}
756
+
757
+
static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
758
+
unsigned long *configs, unsigned int nconfigs)
759
+
{
760
+
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
761
+
unsigned int i;
762
+
int ret;
763
+
764
+
if (!mofld_buf_available(mp, pin))
765
+
return -ENOTSUPP;
766
+
767
+
for (i = 0; i < nconfigs; i++) {
768
+
switch (pinconf_to_config_param(configs[i])) {
769
+
case PIN_CONFIG_BIAS_DISABLE:
770
+
case PIN_CONFIG_BIAS_PULL_UP:
771
+
case PIN_CONFIG_BIAS_PULL_DOWN:
772
+
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
773
+
case PIN_CONFIG_SLEW_RATE:
774
+
ret = mofld_config_set_pin(mp, pin, configs[i]);
775
+
if (ret)
776
+
return ret;
777
+
break;
778
+
779
+
default:
780
+
return -ENOTSUPP;
781
+
}
782
+
}
783
+
784
+
return 0;
785
+
}
786
+
787
+
static int mofld_config_group_get(struct pinctrl_dev *pctldev, unsigned int group,
788
+
unsigned long *config)
789
+
{
790
+
const unsigned int *pins;
791
+
unsigned int npins;
792
+
int ret;
793
+
794
+
ret = mofld_get_group_pins(pctldev, group, &pins, &npins);
795
+
if (ret)
796
+
return ret;
797
+
798
+
ret = mofld_config_get(pctldev, pins[0], config);
799
+
if (ret)
800
+
return ret;
801
+
802
+
return 0;
803
+
}
804
+
805
+
static int mofld_config_group_set(struct pinctrl_dev *pctldev, unsigned int group,
806
+
unsigned long *configs, unsigned int num_configs)
807
+
{
808
+
const unsigned int *pins;
809
+
unsigned int npins;
810
+
int i, ret;
811
+
812
+
ret = mofld_get_group_pins(pctldev, group, &pins, &npins);
813
+
if (ret)
814
+
return ret;
815
+
816
+
for (i = 0; i < npins; i++) {
817
+
ret = mofld_config_set(pctldev, pins[i], configs, num_configs);
818
+
if (ret)
819
+
return ret;
820
+
}
821
+
822
+
return 0;
823
+
}
824
+
825
+
static const struct pinconf_ops mofld_pinconf_ops = {
826
+
.is_generic = true,
827
+
.pin_config_get = mofld_config_get,
828
+
.pin_config_set = mofld_config_set,
829
+
.pin_config_group_get = mofld_config_group_get,
830
+
.pin_config_group_set = mofld_config_group_set,
831
+
};
832
+
833
+
static const struct pinctrl_desc mofld_pinctrl_desc = {
834
+
.pctlops = &mofld_pinctrl_ops,
835
+
.pmxops = &mofld_pinmux_ops,
836
+
.confops = &mofld_pinconf_ops,
837
+
.owner = THIS_MODULE,
838
+
};
839
+
840
+
static int mofld_pinctrl_probe(struct platform_device *pdev)
841
+
{
842
+
struct device *dev = &pdev->dev;
843
+
struct mofld_family *families;
844
+
struct mofld_pinctrl *mp;
845
+
void __iomem *regs;
846
+
size_t nfamilies;
847
+
unsigned int i;
848
+
849
+
mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
850
+
if (!mp)
851
+
return -ENOMEM;
852
+
853
+
mp->dev = dev;
854
+
raw_spin_lock_init(&mp->lock);
855
+
856
+
regs = devm_platform_ioremap_resource(pdev, 0);
857
+
if (IS_ERR(regs))
858
+
return PTR_ERR(regs);
859
+
860
+
nfamilies = ARRAY_SIZE(mofld_families),
861
+
families = devm_kmemdup(dev, mofld_families, sizeof(mofld_families), GFP_KERNEL);
862
+
if (!families)
863
+
return -ENOMEM;
864
+
865
+
/* Splice memory resource by chunk per family */
866
+
for (i = 0; i < nfamilies; i++) {
867
+
struct mofld_family *family = &families[i];
868
+
869
+
family->regs = regs + family->barno * MOFLD_FAMILY_LEN;
870
+
}
871
+
872
+
mp->families = families;
873
+
mp->nfamilies = nfamilies;
874
+
mp->pctldesc = mofld_pinctrl_desc;
875
+
mp->pctldesc.name = dev_name(dev);
876
+
mp->pctldesc.pins = mofld_pins;
877
+
mp->pctldesc.npins = ARRAY_SIZE(mofld_pins);
878
+
879
+
mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp);
880
+
if (IS_ERR(mp->pctldev))
881
+
return PTR_ERR(mp->pctldev);
882
+
883
+
platform_set_drvdata(pdev, mp);
884
+
return 0;
885
+
}
886
+
887
+
static const struct acpi_device_id mofld_acpi_table[] = {
888
+
{ "INTC1003" },
889
+
{ }
890
+
};
891
+
MODULE_DEVICE_TABLE(acpi, mofld_acpi_table);
892
+
893
+
static struct platform_driver mofld_pinctrl_driver = {
894
+
.probe = mofld_pinctrl_probe,
895
+
.driver = {
896
+
.name = "pinctrl-moorefield",
897
+
.acpi_match_table = mofld_acpi_table,
898
+
},
899
+
};
900
+
901
+
static int __init mofld_pinctrl_init(void)
902
+
{
903
+
return platform_driver_register(&mofld_pinctrl_driver);
904
+
}
905
+
subsys_initcall(mofld_pinctrl_init);
906
+
907
+
static void __exit mofld_pinctrl_exit(void)
908
+
{
909
+
platform_driver_unregister(&mofld_pinctrl_driver);
910
+
}
911
+
module_exit(mofld_pinctrl_exit);
912
+
913
+
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
914
+
MODULE_DESCRIPTION("Intel Moorefield SoC pinctrl driver");
915
+
MODULE_LICENSE("GPL v2");
916
+
MODULE_ALIAS("platform:pinctrl-moorefield");
+16
-16
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+16
-16
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
···
22
22
#define SPT_GPI_IS 0x100
23
23
#define SPT_GPI_IE 0x120
24
24
25
-
#define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \
26
-
{ \
27
-
.barno = (b), \
28
-
.padown_offset = SPT_PAD_OWN, \
29
-
.padcfglock_offset = (pl), \
30
-
.hostown_offset = SPT_HOSTSW_OWN, \
31
-
.is_offset = SPT_GPI_IS, \
32
-
.ie_offset = SPT_GPI_IE, \
33
-
.gpp_size = (gs), \
34
-
.gpp_num_padown_regs = (gn), \
35
-
.pin_base = (s), \
36
-
.npins = ((e) - (s) + 1), \
37
-
.gpps = (g), \
38
-
.ngpps = (n), \
25
+
#define SPT_COMMUNITY(b, s, e, g, n, v, gs, gn) \
26
+
{ \
27
+
.barno = (b), \
28
+
.padown_offset = SPT_PAD_OWN, \
29
+
.padcfglock_offset = SPT_##v##_PADCFGLOCK, \
30
+
.hostown_offset = SPT_HOSTSW_OWN, \
31
+
.is_offset = SPT_GPI_IS, \
32
+
.ie_offset = SPT_GPI_IE, \
33
+
.gpp_size = (gs), \
34
+
.gpp_num_padown_regs = (gn), \
35
+
.pin_base = (s), \
36
+
.npins = ((e) - (s) + 1), \
37
+
.gpps = (g), \
38
+
.ngpps = (n), \
39
39
}
40
40
41
41
#define SPT_LP_COMMUNITY(b, s, e) \
42
-
SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0)
42
+
SPT_COMMUNITY(b, s, e, NULL, 0, LP, 24, 4)
43
43
44
44
#define SPT_H_GPP(r, s, e, g) \
45
45
{ \
···
50
50
}
51
51
52
52
#define SPT_H_COMMUNITY(b, s, e, g) \
53
-
SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))
53
+
SPT_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), H, 0, 0)
54
54
55
55
/* Sunrisepoint-LP */
56
56
static const struct pinctrl_pin_desc sptlp_pins[] = {
+14
-14
drivers/pinctrl/intel/pinctrl-tigerlake.c
+14
-14
drivers/pinctrl/intel/pinctrl-tigerlake.c
···
31
31
.gpio_base = (g), \
32
32
}
33
33
34
-
#define TGL_COMMUNITY(b, s, e, pl, ho, g) \
35
-
{ \
36
-
.barno = (b), \
37
-
.padown_offset = TGL_PAD_OWN, \
38
-
.padcfglock_offset = (pl), \
39
-
.hostown_offset = (ho), \
40
-
.is_offset = TGL_GPI_IS, \
41
-
.ie_offset = TGL_GPI_IE, \
42
-
.pin_base = (s), \
43
-
.npins = ((e) - (s) + 1), \
44
-
.gpps = (g), \
45
-
.ngpps = ARRAY_SIZE(g), \
34
+
#define TGL_COMMUNITY(b, s, e, g, v) \
35
+
{ \
36
+
.barno = (b), \
37
+
.padown_offset = TGL_PAD_OWN, \
38
+
.padcfglock_offset = TGL_##v##_PADCFGLOCK, \
39
+
.hostown_offset = TGL_##v##_HOSTSW_OWN, \
40
+
.is_offset = TGL_GPI_IS, \
41
+
.ie_offset = TGL_GPI_IE, \
42
+
.pin_base = (s), \
43
+
.npins = ((e) - (s) + 1), \
44
+
.gpps = (g), \
45
+
.ngpps = ARRAY_SIZE(g), \
46
46
}
47
47
48
48
#define TGL_LP_COMMUNITY(b, s, e, g) \
49
-
TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g)
49
+
TGL_COMMUNITY(b, s, e, g, LP)
50
50
51
51
#define TGL_H_COMMUNITY(b, s, e, g) \
52
-
TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g)
52
+
TGL_COMMUNITY(b, s, e, g, H)
53
53
54
54
/* Tiger Lake-LP */
55
55
static const struct pinctrl_pin_desc tgllp_pins[] = {
+45
-7
drivers/pinctrl/mediatek/pinctrl-moore.c
+45
-7
drivers/pinctrl/mediatek/pinctrl-moore.c
···
8
8
*
9
9
*/
10
10
11
+
#include <dt-bindings/pinctrl/mt65xx.h>
11
12
#include <linux/gpio/driver.h>
13
+
14
+
#include <linux/pinctrl/consumer.h>
15
+
12
16
#include "pinctrl-moore.h"
13
17
14
18
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
···
109
105
{
110
106
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
111
107
u32 param = pinconf_to_config_param(*config);
112
-
int val, val2, err, reg, ret = 1;
108
+
int val, val2, err, pullup, reg, ret = 1;
113
109
const struct mtk_pin_desc *desc;
114
110
115
111
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
···
118
114
119
115
switch (param) {
120
116
case PIN_CONFIG_BIAS_DISABLE:
121
-
if (hw->soc->bias_disable_get) {
117
+
if (hw->soc->bias_get_combo) {
118
+
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
119
+
if (err)
120
+
return err;
121
+
if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
122
+
return -EINVAL;
123
+
} else if (hw->soc->bias_disable_get) {
122
124
err = hw->soc->bias_disable_get(hw, desc, &ret);
123
125
if (err)
124
126
return err;
···
133
123
}
134
124
break;
135
125
case PIN_CONFIG_BIAS_PULL_UP:
136
-
if (hw->soc->bias_get) {
126
+
if (hw->soc->bias_get_combo) {
127
+
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
128
+
if (err)
129
+
return err;
130
+
if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
131
+
return -EINVAL;
132
+
if (!pullup)
133
+
return -EINVAL;
134
+
} else if (hw->soc->bias_get) {
137
135
err = hw->soc->bias_get(hw, desc, 1, &ret);
138
136
if (err)
139
137
return err;
···
150
132
}
151
133
break;
152
134
case PIN_CONFIG_BIAS_PULL_DOWN:
153
-
if (hw->soc->bias_get) {
135
+
if (hw->soc->bias_get_combo) {
136
+
err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
137
+
if (err)
138
+
return err;
139
+
if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
140
+
return -EINVAL;
141
+
if (pullup)
142
+
return -EINVAL;
143
+
} else if (hw->soc->bias_get) {
154
144
err = hw->soc->bias_get(hw, desc, 0, &ret);
155
145
if (err)
156
146
return err;
···
261
235
262
236
switch (param) {
263
237
case PIN_CONFIG_BIAS_DISABLE:
264
-
if (hw->soc->bias_disable_set) {
238
+
if (hw->soc->bias_set_combo) {
239
+
err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
240
+
if (err)
241
+
return err;
242
+
} else if (hw->soc->bias_disable_set) {
265
243
err = hw->soc->bias_disable_set(hw, desc);
266
244
if (err)
267
245
return err;
···
274
244
}
275
245
break;
276
246
case PIN_CONFIG_BIAS_PULL_UP:
277
-
if (hw->soc->bias_set) {
247
+
if (hw->soc->bias_set_combo) {
248
+
err = hw->soc->bias_set_combo(hw, desc, 1, arg);
249
+
if (err)
250
+
return err;
251
+
} else if (hw->soc->bias_set) {
278
252
err = hw->soc->bias_set(hw, desc, 1);
279
253
if (err)
280
254
return err;
···
287
253
}
288
254
break;
289
255
case PIN_CONFIG_BIAS_PULL_DOWN:
290
-
if (hw->soc->bias_set) {
256
+
if (hw->soc->bias_set_combo) {
257
+
err = hw->soc->bias_set_combo(hw, desc, 0, arg);
258
+
if (err)
259
+
return err;
260
+
} else if (hw->soc->bias_set) {
291
261
err = hw->soc->bias_set(hw, desc, 0);
292
262
if (err)
293
263
return err;
+93
-19
drivers/pinctrl/mediatek/pinctrl-mt7986.c
+93
-19
drivers/pinctrl/mediatek/pinctrl-mt7986.c
···
316
316
PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
317
317
PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
318
318
PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
319
-
PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 22, 1),
320
-
PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 20, 1),
321
-
PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 26, 1),
322
-
PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 24, 1),
319
+
PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
320
+
PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
321
+
PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
322
+
PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
323
323
PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
324
324
PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
325
325
PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
···
354
354
PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
355
355
PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
356
356
PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
357
-
PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
358
-
PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
359
-
PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
360
-
PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
357
+
PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
358
+
PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
359
+
PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
360
+
PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
361
361
PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
362
362
PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
363
363
PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
···
392
392
PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
393
393
PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
394
394
PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
395
-
PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 22, 1),
396
-
PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 20, 1),
397
-
PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 26, 1),
398
-
PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 24, 1),
395
+
PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
396
+
PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
397
+
PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
398
+
PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
399
399
PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
400
400
PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
401
401
PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
···
405
405
PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
406
406
PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
407
407
PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
408
+
};
409
+
410
+
static const unsigned int mt7986_pull_type[] = {
411
+
MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
412
+
MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
413
+
MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
414
+
MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
415
+
MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
416
+
MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
417
+
MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
418
+
MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
419
+
MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
420
+
MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
421
+
MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
422
+
MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
423
+
MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
424
+
MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
425
+
MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
426
+
MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
427
+
MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
428
+
MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
429
+
MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
430
+
MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
431
+
MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
432
+
MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
433
+
MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
434
+
MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
435
+
MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
436
+
MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
437
+
MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
438
+
MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
439
+
MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
440
+
MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
441
+
MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
442
+
MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
443
+
MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
444
+
MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
445
+
MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
446
+
MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
447
+
MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
448
+
MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
449
+
MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
450
+
MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
451
+
MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
452
+
MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
453
+
MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
454
+
MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
455
+
MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
456
+
MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
457
+
MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
458
+
MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
459
+
MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
460
+
MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
461
+
MTK_PULL_PU_PD_TYPE,/*100*/
408
462
};
409
463
410
464
static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
···
729
675
static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
730
676
static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
731
677
732
-
static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
733
-
static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
678
+
static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
679
+
static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
734
680
735
-
static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
736
-
static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
681
+
static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
682
+
static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
683
+
684
+
static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
685
+
static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
686
+
687
+
static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
688
+
static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
737
689
738
690
static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
739
691
static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
···
767
707
768
708
static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
769
709
static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
710
+
711
+
static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
712
+
static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
713
+
714
+
static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
715
+
static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
770
716
771
717
static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
772
718
static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
···
815
749
PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
816
750
PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
817
751
PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
752
+
PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
753
+
PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
818
754
PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
819
755
PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
820
756
PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
···
828
760
PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
829
761
PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
830
762
PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
831
-
PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
832
-
PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
763
+
PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
764
+
PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
765
+
PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
766
+
PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
833
767
PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
834
768
PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
835
769
PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
···
870
800
static const char *mt7986_spi_groups[] = {
871
801
"spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
872
802
static const char *mt7986_uart_groups[] = {
873
-
"uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
803
+
"uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
804
+
"uart1_2_rx_tx", "uart1_2_cts_rts",
805
+
"uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
874
806
"uart2_0", "uart2_1", "uart0", "uart1", "uart2",
875
807
};
876
808
static const char *mt7986_wdt_groups[] = { "watchdog", };
···
922
850
.ies_present = false,
923
851
.base_names = mt7986_pinctrl_register_base_names,
924
852
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
853
+
.pull_type = mt7986_pull_type,
925
854
.bias_set_combo = mtk_pinconf_bias_set_combo,
926
855
.bias_get_combo = mtk_pinconf_bias_get_combo,
927
856
.drive_set = mtk_pinconf_drive_set_rev1,
···
944
871
.ies_present = false,
945
872
.base_names = mt7986_pinctrl_register_base_names,
946
873
.nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
874
+
.pull_type = mt7986_pull_type,
947
875
.bias_set_combo = mtk_pinconf_bias_set_combo,
948
876
.bias_get_combo = mtk_pinconf_bias_get_combo,
949
877
.drive_set = mtk_pinconf_drive_set_rev1,
+18
drivers/pinctrl/mediatek/pinctrl-mt8365.c
+18
drivers/pinctrl/mediatek/pinctrl-mt8365.c
···
416
416
MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22),
417
417
};
418
418
419
+
static int mt8365_set_clr_mode(struct regmap *regmap,
420
+
unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel,
421
+
bool enable, bool isup)
422
+
{
423
+
int ret;
424
+
425
+
ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit);
426
+
if (ret)
427
+
return -EINVAL;
428
+
429
+
ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit);
430
+
if (ret)
431
+
return -EINVAL;
432
+
433
+
return 0;
434
+
}
435
+
419
436
static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = {
420
437
.pins = mtk_pins_mt8365,
421
438
.npins = ARRAY_SIZE(mtk_pins_mt8365),
···
448
431
.n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd),
449
432
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
450
433
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
434
+
.mt8365_set_clr_mode = mt8365_set_clr_mode,
451
435
.dir_offset = 0x0140,
452
436
.dout_offset = 0x00A0,
453
437
.din_offset = 0x0000,
+15
-6
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+15
-6
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
···
330
330
return -EINVAL;
331
331
}
332
332
333
+
if (pctl->devdata->mt8365_set_clr_mode) {
334
+
bit = pin & pctl->devdata->mode_mask;
335
+
reg_pullen = mtk_get_port(pctl, pin) +
336
+
pctl->devdata->pullen_offset;
337
+
reg_pullsel = mtk_get_port(pctl, pin) +
338
+
pctl->devdata->pullsel_offset;
339
+
ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin),
340
+
bit, reg_pullen, reg_pullsel,
341
+
enable, isup);
342
+
if (ret)
343
+
return -EINVAL;
344
+
345
+
return 0;
346
+
}
347
+
333
348
bit = BIT(pin & pctl->devdata->mode_mask);
334
349
if (enable)
335
350
reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
···
1057
1042
struct pinctrl_pin_desc *pins;
1058
1043
struct mtk_pinctrl *pctl;
1059
1044
struct device_node *np = pdev->dev.of_node, *node;
1060
-
struct property *prop;
1061
1045
int ret, i;
1062
1046
1063
1047
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
···
1064
1050
return -ENOMEM;
1065
1051
1066
1052
platform_set_drvdata(pdev, pctl);
1067
-
1068
-
prop = of_find_property(np, "pins-are-numbered", NULL);
1069
-
if (!prop)
1070
-
return dev_err_probe(dev, -EINVAL,
1071
-
"only support pins-are-numbered format\n");
1072
1053
1073
1054
node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1074
1055
if (node) {
+7
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+7
-1
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
···
216
216
* @spec_dir_set: In very few SoCs, direction control registers are not
217
217
* arranged continuously, they may be cut to parts. So they need special
218
218
* dir setting.
219
-
219
+
* @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they
220
+
* need to use the main R/W register to read/update/write the modes instead of
221
+
* the SET/CLR register.
222
+
*
220
223
* @dir_offset: The direction register offset.
221
224
* @pullen_offset: The pull-up/pull-down enable register offset.
222
225
* @pinmux_offset: The pinmux register offset.
···
255
252
void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
256
253
unsigned int mode);
257
254
void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
255
+
int (*mt8365_set_clr_mode)(struct regmap *regmap,
256
+
unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel,
257
+
bool enable, bool isup);
258
258
unsigned int dir_offset;
259
259
unsigned int ies_offset;
260
260
unsigned int smt_offset;
+5
drivers/pinctrl/mediatek/pinctrl-paris.c
+5
drivers/pinctrl/mediatek/pinctrl-paris.c
···
11
11
12
12
#include <linux/gpio/driver.h>
13
13
#include <linux/module.h>
14
+
#include <linux/seq_file.h>
15
+
16
+
#include <linux/pinctrl/consumer.h>
17
+
14
18
#include <dt-bindings/pinctrl/mt65xx.h>
19
+
15
20
#include "pinctrl-paris.h"
16
21
17
22
#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
+8
-6
drivers/pinctrl/mvebu/pinctrl-mvebu.c
+8
-6
drivers/pinctrl/mvebu/pinctrl-mvebu.c
···
6
6
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7
7
*/
8
8
9
-
#include <linux/platform_device.h>
10
-
#include <linux/slab.h>
9
+
#include <linux/err.h>
10
+
#include <linux/gpio/driver.h>
11
11
#include <linux/io.h>
12
+
#include <linux/mfd/syscon.h>
12
13
#include <linux/of.h>
13
14
#include <linux/of_address.h>
14
15
#include <linux/of_platform.h>
15
-
#include <linux/err.h>
16
-
#include <linux/gpio/driver.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/regmap.h>
18
+
#include <linux/seq_file.h>
19
+
#include <linux/slab.h>
20
+
17
21
#include <linux/pinctrl/machine.h>
18
22
#include <linux/pinctrl/pinconf.h>
19
23
#include <linux/pinctrl/pinctrl.h>
20
24
#include <linux/pinctrl/pinmux.h>
21
-
#include <linux/mfd/syscon.h>
22
-
#include <linux/regmap.h>
23
25
24
26
#include "pinctrl-mvebu.h"
25
27
+8
-5
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+8
-5
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
···
11
11
#include <linux/of.h>
12
12
#include <linux/of_address.h>
13
13
#include <linux/of_irq.h>
14
-
#include <linux/pinctrl/machine.h>
15
-
#include <linux/pinctrl/pinconf.h>
16
-
#include <linux/pinctrl/pinconf-generic.h>
17
-
#include <linux/pinctrl/pinctrl.h>
18
-
#include <linux/pinctrl/pinmux.h>
19
14
#include <linux/platform_device.h>
20
15
#include <linux/property.h>
21
16
#include <linux/regmap.h>
17
+
#include <linux/seq_file.h>
18
+
19
+
#include <linux/pinctrl/consumer.h>
20
+
#include <linux/pinctrl/machine.h>
21
+
#include <linux/pinctrl/pinconf-generic.h>
22
+
#include <linux/pinctrl/pinconf.h>
23
+
#include <linux/pinctrl/pinctrl.h>
24
+
#include <linux/pinctrl/pinmux.h>
22
25
23
26
/* GCR registers */
24
27
#define NPCM7XX_GCR_PDID 0x00
+34
-14
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
+34
-14
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
···
49
49
struct wpcm450_gpio {
50
50
struct gpio_chip gc;
51
51
struct wpcm450_pinctrl *pctrl;
52
-
struct irq_chip irqc;
53
52
const struct wpcm450_bank *bank;
54
53
};
55
54
···
141
142
142
143
static void wpcm450_gpio_irq_mask(struct irq_data *d)
143
144
{
144
-
struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
145
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
146
+
struct wpcm450_gpio *gpio = gpiochip_get_data(gc);
145
147
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
146
148
unsigned long flags;
147
149
unsigned long even;
···
157
157
__assign_bit(bit, &even, 0);
158
158
iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
159
159
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
160
+
161
+
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
160
162
}
161
163
162
164
static void wpcm450_gpio_irq_unmask(struct irq_data *d)
163
165
{
164
-
struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
166
+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
167
+
struct wpcm450_gpio *gpio = gpiochip_get_data(gc);
165
168
struct wpcm450_pinctrl *pctrl = gpio->pctrl;
166
169
unsigned long flags;
167
170
unsigned long even;
···
173
170
bit = wpcm450_gpio_irq_bitnum(gpio, d);
174
171
if (bit < 0)
175
172
return;
173
+
174
+
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
176
175
177
176
raw_spin_lock_irqsave(&pctrl->lock, flags);
178
177
even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
···
298
293
.irq_unmask = wpcm450_gpio_irq_unmask,
299
294
.irq_mask = wpcm450_gpio_irq_mask,
300
295
.irq_set_type = wpcm450_gpio_set_irq_type,
296
+
.flags = IRQCHIP_IMMUTABLE,
297
+
GPIOCHIP_IRQ_RESOURCE_HELPERS,
301
298
};
302
299
303
300
static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
···
628
621
int fn1, reg1, bit1;
629
622
};
630
623
624
+
/* Add this value to bit0 or bit1 to indicate that the MFSEL bit is inverted */
625
+
#define INV BIT(5)
626
+
631
627
static const struct wpcm450_pincfg pincfg[] = {
632
628
/* PIN FUNCTION 1 FUNCTION 2 */
633
629
WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0),
···
668
658
669
659
WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0),
670
660
WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0),
671
-
WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0),
661
+
WPCM450_PINCFG(34, scs3, MFSEL1, 5 | INV, none, NONE, 0),
672
662
WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0),
673
663
WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0),
674
664
WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */
···
728
718
WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0),
729
719
WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0),
730
720
WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0),
731
-
WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0),
732
-
WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0),
721
+
WPCM450_PINCFG(93, kbcc, MFSEL1, 17 | INV, none, NONE, 0),
722
+
WPCM450_PINCFG(94, kbcc, MFSEL1, 17 | INV, none, NONE, 0),
733
723
WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0),
734
724
735
725
WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0),
···
803
793
WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127),
804
794
};
805
795
796
+
/* Helper function to update MFSEL field according to the selected function */
797
+
static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, int fn, int fn_selected)
798
+
{
799
+
bool value = (fn == fn_selected);
800
+
801
+
if (bit & INV) {
802
+
value = !value;
803
+
bit &= ~INV;
804
+
}
805
+
806
+
regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0);
807
+
}
808
+
806
809
/* Enable mode in pin group */
807
810
static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
808
811
int npins, int func)
···
827
804
cfg = &pincfg[pin[i]];
828
805
if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) {
829
806
if (cfg->reg0)
830
-
regmap_update_bits(gcr_regmap, cfg->reg0,
831
-
BIT(cfg->bit0),
832
-
(cfg->fn0 == func) ? BIT(cfg->bit0) : 0);
807
+
wpcm450_update_mfsel(gcr_regmap, cfg->reg0,
808
+
cfg->bit0, cfg->fn0, func);
833
809
if (cfg->reg1)
834
-
regmap_update_bits(gcr_regmap, cfg->reg1,
835
-
BIT(cfg->bit1),
836
-
(cfg->fn1 == func) ? BIT(cfg->bit1) : 0);
810
+
wpcm450_update_mfsel(gcr_regmap, cfg->reg1,
811
+
cfg->bit1, cfg->fn1, func);
837
812
}
838
813
}
839
814
}
···
1089
1068
gpio->gc.fwnode = child;
1090
1069
gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges;
1091
1070
1092
-
gpio->irqc = wpcm450_gpio_irqchip;
1093
1071
girq = &gpio->gc.irq;
1094
-
girq->chip = &gpio->irqc;
1072
+
gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip);
1095
1073
girq->parent_handler = wpcm450_gpio_irqhandler;
1096
1074
girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS,
1097
1075
sizeof(*girq->parents), GFP_KERNEL);
+3
-1
drivers/pinctrl/pinconf-generic.c
+3
-1
drivers/pinctrl/pinconf-generic.c
+10
drivers/pinctrl/pinconf.h
+10
drivers/pinctrl/pinconf.h
···
10
10
* Author: Linus Walleij <linus.walleij@linaro.org>
11
11
*/
12
12
13
+
#include <linux/errno.h>
14
+
15
+
struct dentry;
16
+
struct device_node;
17
+
struct seq_file;
18
+
19
+
struct pinctrl_dev;
20
+
struct pinctrl_map;
21
+
struct pinctrl_setting;
22
+
13
23
#ifdef CONFIG_PINCONF
14
24
15
25
int pinconf_check_ops(struct pinctrl_dev *pctldev);
+6
-4
drivers/pinctrl/pinctrl-amd.c
+6
-4
drivers/pinctrl/pinctrl-amd.c
···
628
628
/* Each status bit covers four pins */
629
629
for (i = 0; i < 4; i++) {
630
630
regval = readl(regs + i);
631
-
/* caused wake on resume context for shared IRQ */
632
-
if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) {
631
+
632
+
if (regval & PIN_IRQ_PENDING)
633
633
dev_dbg(&gpio_dev->pdev->dev,
634
-
"Waking due to GPIO %d: 0x%x",
634
+
"GPIO %d is active: 0x%x",
635
635
irqnr + i, regval);
636
+
637
+
/* caused wake on resume context for shared IRQ */
638
+
if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
636
639
return true;
637
-
}
638
640
639
641
if (!(regval & PIN_IRQ_PENDING) ||
640
642
!(regval & BIT(INTERRUPT_MASK_OFF)))
+5
-2
drivers/pinctrl/pinctrl-apple-gpio.c
+5
-2
drivers/pinctrl/pinctrl-apple-gpio.c
···
11
11
*/
12
12
13
13
#include <dt-bindings/pinctrl/apple.h>
14
+
15
+
#include <linux/bitfield.h>
14
16
#include <linux/bits.h>
15
17
#include <linux/gpio/driver.h>
16
18
#include <linux/interrupt.h>
···
20
18
#include <linux/module.h>
21
19
#include <linux/of.h>
22
20
#include <linux/of_irq.h>
23
-
#include <linux/pinctrl/pinctrl.h>
24
-
#include <linux/pinctrl/pinmux.h>
25
21
#include <linux/platform_device.h>
26
22
#include <linux/regmap.h>
23
+
24
+
#include <linux/pinctrl/pinctrl.h>
25
+
#include <linux/pinctrl/pinmux.h>
27
26
28
27
#include "pinctrl-utils.h"
29
28
#include "core.h"
+33
-3
drivers/pinctrl/pinctrl-at91-pio4.c
+33
-3
drivers/pinctrl/pinctrl-at91-pio4.c
···
7
7
*/
8
8
9
9
#include <dt-bindings/pinctrl/at91.h>
10
+
10
11
#include <linux/clk.h>
11
12
#include <linux/gpio/driver.h>
13
+
#include <linux/init.h>
12
14
#include <linux/interrupt.h>
13
15
#include <linux/io.h>
14
-
#include <linux/init.h>
15
16
#include <linux/of.h>
16
17
#include <linux/platform_device.h>
17
-
#include <linux/pinctrl/pinconf.h>
18
+
#include <linux/seq_file.h>
19
+
#include <linux/slab.h>
20
+
18
21
#include <linux/pinctrl/pinconf-generic.h>
22
+
#include <linux/pinctrl/pinconf.h>
19
23
#include <linux/pinctrl/pinctrl.h>
20
24
#include <linux/pinctrl/pinmux.h>
21
-
#include <linux/slab.h>
25
+
22
26
#include "core.h"
23
27
#include "pinconf.h"
24
28
#include "pinctrl-utils.h"
···
779
775
return -EINVAL;
780
776
arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
781
777
break;
778
+
case PIN_CONFIG_PERSIST_STATE:
779
+
return -ENOTSUPP;
782
780
default:
783
781
return -ENOTSUPP;
784
782
}
···
889
883
dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
890
884
}
891
885
break;
886
+
case PIN_CONFIG_PERSIST_STATE:
887
+
return -ENOTSUPP;
892
888
default:
893
889
dev_warn(pctldev->dev,
894
890
"unsupported configuration parameter: %u\n",
···
903
895
atmel_pin_config_write(pctldev, pin_id, conf);
904
896
905
897
return 0;
898
+
}
899
+
900
+
static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev,
901
+
unsigned pin,
902
+
unsigned long *configs,
903
+
unsigned num_configs)
904
+
{
905
+
struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);
906
+
907
+
return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs);
908
+
}
909
+
910
+
static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev,
911
+
unsigned pin,
912
+
unsigned long *configs)
913
+
{
914
+
struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin);
915
+
916
+
return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs);
906
917
}
907
918
908
919
static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
···
971
944
.pin_config_group_get = atmel_conf_pin_config_group_get,
972
945
.pin_config_group_set = atmel_conf_pin_config_group_set,
973
946
.pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
947
+
.pin_config_set = atmel_conf_pin_config_set,
948
+
.pin_config_get = atmel_conf_pin_config_get,
974
949
};
975
950
976
951
static struct pinctrl_desc atmel_pinctrl_desc = {
···
1163
1134
atmel_pioctrl->gpio_chip->label = dev_name(dev);
1164
1135
atmel_pioctrl->gpio_chip->parent = dev;
1165
1136
atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1137
+
atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config;
1166
1138
1167
1139
atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1168
1140
atmel_pioctrl->nbanks,
+11
-9
drivers/pinctrl/pinctrl-at91.c
+11
-9
drivers/pinctrl/pinctrl-at91.c
···
7
7
8
8
#include <linux/clk.h>
9
9
#include <linux/err.h>
10
+
#include <linux/gpio/driver.h>
10
11
#include <linux/init.h>
11
-
#include <linux/of.h>
12
-
#include <linux/of_device.h>
13
-
#include <linux/of_address.h>
14
-
#include <linux/of_irq.h>
15
-
#include <linux/slab.h>
16
12
#include <linux/interrupt.h>
17
13
#include <linux/io.h>
18
-
#include <linux/gpio/driver.h>
14
+
#include <linux/of.h>
15
+
#include <linux/of_address.h>
16
+
#include <linux/of_device.h>
17
+
#include <linux/of_irq.h>
18
+
#include <linux/pm.h>
19
+
#include <linux/seq_file.h>
20
+
#include <linux/slab.h>
21
+
22
+
/* Since we request GPIOs from ourself */
23
+
#include <linux/pinctrl/consumer.h>
19
24
#include <linux/pinctrl/machine.h>
20
25
#include <linux/pinctrl/pinconf.h>
21
26
#include <linux/pinctrl/pinctrl.h>
22
27
#include <linux/pinctrl/pinmux.h>
23
-
/* Since we request GPIOs from ourself */
24
-
#include <linux/pinctrl/consumer.h>
25
-
#include <linux/pm.h>
26
28
27
29
#include "pinctrl-at91.h"
28
30
#include "core.h"
+5
-3
drivers/pinctrl/pinctrl-axp209.c
+5
-3
drivers/pinctrl/pinctrl-axp209.c
···
16
16
#include <linux/module.h>
17
17
#include <linux/of.h>
18
18
#include <linux/of_device.h>
19
-
#include <linux/pinctrl/pinconf-generic.h>
20
-
#include <linux/pinctrl/pinctrl.h>
21
-
#include <linux/pinctrl/pinmux.h>
22
19
#include <linux/platform_device.h>
23
20
#include <linux/regmap.h>
24
21
#include <linux/slab.h>
22
+
23
+
#include <linux/pinctrl/consumer.h>
24
+
#include <linux/pinctrl/pinconf-generic.h>
25
+
#include <linux/pinctrl/pinctrl.h>
26
+
#include <linux/pinctrl/pinmux.h>
25
27
26
28
#define AXP20X_GPIO_FUNCTIONS 0x7
27
29
#define AXP20X_GPIO_FUNCTION_OUT_LOW 0
+4
-2
drivers/pinctrl/pinctrl-bm1880.c
+4
-2
drivers/pinctrl/pinctrl-bm1880.c
···
9
9
#include <linux/io.h>
10
10
#include <linux/of.h>
11
11
#include <linux/platform_device.h>
12
+
#include <linux/slab.h>
13
+
14
+
#include <linux/pinctrl/pinconf-generic.h>
15
+
#include <linux/pinctrl/pinconf.h>
12
16
#include <linux/pinctrl/pinctrl.h>
13
17
#include <linux/pinctrl/pinmux.h>
14
-
#include <linux/pinctrl/pinconf-generic.h>
15
-
#include <linux/slab.h>
16
18
17
19
#include "core.h"
18
20
#include "pinctrl-utils.h"
+85
-49
drivers/pinctrl/pinctrl-cy8c95x0.c
+85
-49
drivers/pinctrl/pinctrl-cy8c95x0.c
···
20
20
#include <linux/property.h>
21
21
#include <linux/regmap.h>
22
22
#include <linux/regulator/consumer.h>
23
+
#include <linux/seq_file.h>
23
24
24
-
#include <linux/pinctrl/pinctrl.h>
25
+
#include <linux/pinctrl/consumer.h>
25
26
#include <linux/pinctrl/pinconf.h>
26
27
#include <linux/pinctrl/pinconf-generic.h>
28
+
#include <linux/pinctrl/pinctrl.h>
27
29
#include <linux/pinctrl/pinmux.h>
28
30
29
31
/* Fast access registers */
···
553
551
554
552
static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
555
553
{
556
-
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
557
-
u8 port = cypress_get_port(chip, off);
558
-
u8 bit = cypress_get_pin_mask(chip, off);
559
-
int ret;
560
-
561
-
mutex_lock(&chip->i2c_lock);
562
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
563
-
if (ret)
564
-
goto out;
565
-
566
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
567
-
if (ret)
568
-
goto out;
569
-
570
-
if (test_bit(off, chip->push_pull)) {
571
-
/*
572
-
* Disable driving the pin by forcing it to HighZ. Only setting the
573
-
* direction register isn't sufficient in Push-Pull mode.
574
-
*/
575
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
576
-
if (ret)
577
-
goto out;
578
-
579
-
__clear_bit(off, chip->push_pull);
580
-
}
581
-
582
-
out:
583
-
mutex_unlock(&chip->i2c_lock);
584
-
585
-
return ret;
554
+
return pinctrl_gpio_direction_input(gc->base + off);
586
555
}
587
556
588
557
static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc,
···
570
597
if (ret)
571
598
return ret;
572
599
573
-
mutex_lock(&chip->i2c_lock);
574
-
/* Select port... */
575
-
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
576
-
if (ret)
577
-
goto out;
578
-
579
-
/* ...then direction */
580
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0);
581
-
582
-
out:
583
-
mutex_unlock(&chip->i2c_lock);
584
-
585
-
return ret;
600
+
return pinctrl_gpio_direction_output(gc->base + off);
586
601
}
587
602
588
603
static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
···
811
850
{
812
851
struct gpio_chip *gc = &chip->gpio_chip;
813
852
853
+
gc->request = gpiochip_generic_request;
854
+
gc->free = gpiochip_generic_free;
814
855
gc->direction_input = cy8c95x0_gpio_direction_input;
815
856
gc->direction_output = cy8c95x0_gpio_direction_output;
816
857
gc->get = cy8c95x0_gpio_get_value;
···
1087
1124
return 0;
1088
1125
}
1089
1126
1090
-
static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip,
1091
-
unsigned int val,
1092
-
unsigned long off)
1127
+
static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode)
1093
1128
{
1094
1129
u8 port = cypress_get_port(chip, off);
1095
1130
u8 bit = cypress_get_pin_mask(chip, off);
···
1098
1137
if (ret < 0)
1099
1138
return ret;
1100
1139
1101
-
ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0);
1140
+
return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0);
1141
+
}
1142
+
1143
+
static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip,
1144
+
unsigned int selector, unsigned int group)
1145
+
{
1146
+
u8 port = cypress_get_port(chip, group);
1147
+
u8 bit = cypress_get_pin_mask(chip, group);
1148
+
int ret;
1149
+
1150
+
ret = cy8c95x0_set_mode(chip, group, selector);
1102
1151
if (ret < 0)
1103
1152
return ret;
1153
+
1154
+
if (selector == 0)
1155
+
return 0;
1104
1156
1105
1157
/* Set direction to output & set output to 1 so that PWM can work */
1106
1158
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit);
···
1130
1156
int ret;
1131
1157
1132
1158
mutex_lock(&chip->i2c_lock);
1133
-
ret = cy8c95x0_pinmux_cfg(chip, selector, group);
1159
+
ret = cy8c95x0_pinmux_mode(chip, selector, group);
1160
+
mutex_unlock(&chip->i2c_lock);
1161
+
1162
+
return ret;
1163
+
}
1164
+
1165
+
static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev,
1166
+
struct pinctrl_gpio_range *range,
1167
+
unsigned int pin)
1168
+
{
1169
+
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1170
+
int ret;
1171
+
1172
+
mutex_lock(&chip->i2c_lock);
1173
+
ret = cy8c95x0_set_mode(chip, pin, false);
1174
+
mutex_unlock(&chip->i2c_lock);
1175
+
1176
+
return ret;
1177
+
}
1178
+
1179
+
static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip,
1180
+
unsigned int pin, bool input)
1181
+
{
1182
+
u8 port = cypress_get_port(chip, pin);
1183
+
u8 bit = cypress_get_pin_mask(chip, pin);
1184
+
int ret;
1185
+
1186
+
/* Select port... */
1187
+
ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port);
1188
+
if (ret)
1189
+
return ret;
1190
+
1191
+
/* ...then direction */
1192
+
ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0);
1193
+
if (ret)
1194
+
return ret;
1195
+
1196
+
/*
1197
+
* Disable driving the pin by forcing it to HighZ. Only setting
1198
+
* the direction register isn't sufficient in Push-Pull mode.
1199
+
*/
1200
+
if (input && test_bit(pin, chip->push_pull)) {
1201
+
ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit);
1202
+
if (ret)
1203
+
return ret;
1204
+
1205
+
__clear_bit(pin, chip->push_pull);
1206
+
}
1207
+
1208
+
return 0;
1209
+
}
1210
+
1211
+
static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev,
1212
+
struct pinctrl_gpio_range *range,
1213
+
unsigned int pin, bool input)
1214
+
{
1215
+
struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
1216
+
int ret;
1217
+
1218
+
mutex_lock(&chip->i2c_lock);
1219
+
ret = cy8c95x0_pinmux_direction(chip, pin, input);
1134
1220
mutex_unlock(&chip->i2c_lock);
1135
1221
1136
1222
return ret;
···
1201
1167
.get_function_name = cy8c95x0_get_function_name,
1202
1168
.get_function_groups = cy8c95x0_get_function_groups,
1203
1169
.set_mux = cy8c95x0_set_mux,
1170
+
.gpio_request_enable = cy8c95x0_gpio_request_enable,
1171
+
.gpio_set_direction = cy8c95x0_gpio_set_direction,
1204
1172
.strict = true,
1205
1173
};
1206
1174
+5
-4
drivers/pinctrl/pinctrl-falcon.c
+5
-4
drivers/pinctrl/pinctrl-falcon.c
···
7
7
* Copyright (C) 2012 John Crispin <john@phrozen.org>
8
8
*/
9
9
10
+
#include <linux/err.h>
11
+
#include <linux/export.h>
10
12
#include <linux/gpio/driver.h>
11
13
#include <linux/interrupt.h>
12
-
#include <linux/slab.h>
13
-
#include <linux/export.h>
14
-
#include <linux/err.h>
15
14
#include <linux/module.h>
16
15
#include <linux/of.h>
17
-
#include <linux/of_platform.h>
18
16
#include <linux/of_address.h>
19
17
#include <linux/of_gpio.h>
18
+
#include <linux/of_platform.h>
20
19
#include <linux/platform_device.h>
20
+
#include <linux/seq_file.h>
21
+
#include <linux/slab.h>
21
22
22
23
#include "pinctrl-lantiq.h"
23
24
+7
-5
drivers/pinctrl/pinctrl-gemini.c
+7
-5
drivers/pinctrl/pinctrl-gemini.c
···
10
10
#include <linux/io.h>
11
11
#include <linux/mfd/syscon.h>
12
12
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/regmap.h>
15
+
#include <linux/seq_file.h>
16
+
#include <linux/slab.h>
17
+
13
18
#include <linux/pinctrl/machine.h>
19
+
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/pinctrl/pinconf.h>
14
21
#include <linux/pinctrl/pinctrl.h>
15
22
#include <linux/pinctrl/pinmux.h>
16
-
#include <linux/pinctrl/pinconf.h>
17
-
#include <linux/pinctrl/pinconf-generic.h>
18
-
#include <linux/platform_device.h>
19
-
#include <linux/slab.h>
20
-
#include <linux/regmap.h>
21
23
22
24
#include "pinctrl-utils.h"
23
25
+6
-4
drivers/pinctrl/pinctrl-ingenic.c
+6
-4
drivers/pinctrl/pinctrl-ingenic.c
···
14
14
#include <linux/kernel.h>
15
15
#include <linux/mod_devicetable.h>
16
16
#include <linux/of.h>
17
-
#include <linux/pinctrl/pinctrl.h>
18
-
#include <linux/pinctrl/pinmux.h>
19
-
#include <linux/pinctrl/pinconf.h>
20
-
#include <linux/pinctrl/pinconf-generic.h>
21
17
#include <linux/platform_device.h>
22
18
#include <linux/property.h>
23
19
#include <linux/regmap.h>
24
20
#include <linux/seq_file.h>
25
21
#include <linux/slab.h>
22
+
23
+
#include <linux/pinctrl/consumer.h>
24
+
#include <linux/pinctrl/pinconf-generic.h>
25
+
#include <linux/pinctrl/pinconf.h>
26
+
#include <linux/pinctrl/pinctrl.h>
27
+
#include <linux/pinctrl/pinmux.h>
26
28
27
29
#include "core.h"
28
30
#include "pinconf.h"
+12
-8
drivers/pinctrl/pinctrl-k210.c
+12
-8
drivers/pinctrl/pinctrl-k210.c
···
3
3
* Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
4
4
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
5
5
*/
6
-
#include <linux/io.h>
7
-
#include <linux/of_device.h>
8
-
#include <linux/clk.h>
9
-
#include <linux/mfd/syscon.h>
10
-
#include <linux/platform_device.h>
11
6
#include <linux/bitfield.h>
7
+
#include <linux/clk.h>
8
+
#include <linux/io.h>
9
+
#include <linux/mfd/syscon.h>
10
+
#include <linux/of_device.h>
11
+
#include <linux/platform_device.h>
12
12
#include <linux/regmap.h>
13
+
#include <linux/seq_file.h>
13
14
#include <linux/slab.h>
15
+
16
+
#include <linux/pinctrl/pinconf-generic.h>
17
+
#include <linux/pinctrl/pinconf.h>
14
18
#include <linux/pinctrl/pinctrl.h>
15
19
#include <linux/pinctrl/pinmux.h>
16
-
#include <linux/pinctrl/pinconf.h>
17
-
#include <linux/pinctrl/pinconf-generic.h>
18
20
19
21
#include <dt-bindings/pinctrl/k210-fpioa.h>
20
22
···
864
862
for_each_available_child_of_node(np_config, np) {
865
863
ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map,
866
864
&reserved_maps, num_maps);
867
-
if (ret < 0)
865
+
if (ret < 0) {
866
+
of_node_put(np);
868
867
goto err;
868
+
}
869
869
}
870
870
return 0;
871
871
+4
-3
drivers/pinctrl/pinctrl-lantiq.c
+4
-3
drivers/pinctrl/pinctrl-lantiq.c
···
6
6
* Copyright (C) 2012 John Crispin <john@phrozen.org>
7
7
*/
8
8
9
-
#include <linux/module.h>
10
9
#include <linux/device.h>
11
10
#include <linux/io.h>
12
-
#include <linux/platform_device.h>
13
-
#include <linux/slab.h>
11
+
#include <linux/module.h>
14
12
#include <linux/of.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/seq_file.h>
15
+
#include <linux/slab.h>
15
16
16
17
#include "pinctrl-lantiq.h"
17
18
+4
-3
drivers/pinctrl/pinctrl-lantiq.h
+4
-3
drivers/pinctrl/pinctrl-lantiq.h
···
10
10
#define __PINCTRL_LANTIQ_H
11
11
12
12
#include <linux/clkdev.h>
13
-
#include <linux/pinctrl/pinctrl.h>
14
-
#include <linux/pinctrl/pinconf.h>
15
-
#include <linux/pinctrl/pinmux.h>
13
+
16
14
#include <linux/pinctrl/consumer.h>
17
15
#include <linux/pinctrl/machine.h>
16
+
#include <linux/pinctrl/pinconf.h>
17
+
#include <linux/pinctrl/pinctrl.h>
18
+
#include <linux/pinctrl/pinmux.h>
18
19
19
20
#include "core.h"
20
21
+311
drivers/pinctrl/pinctrl-loongson2.c
+311
drivers/pinctrl/pinctrl-loongson2.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Author: zhanghongchen <zhanghongchen@loongson.cn>
4
+
* Yinbo Zhu <zhuyinbo@loongson.cn>
5
+
* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
6
+
*/
7
+
8
+
#include <linux/init.h>
9
+
#include <linux/module.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/pinctrl/pinmux.h>
13
+
#include <linux/pinctrl/pinconf-generic.h>
14
+
#include <linux/pinctrl/pinctrl.h>
15
+
#include <linux/bitops.h>
16
+
#include <linux/io.h>
17
+
#include <linux/seq_file.h>
18
+
19
+
#include "core.h"
20
+
#include "pinctrl-utils.h"
21
+
22
+
#define PMX_GROUP(name, offset, bitv) \
23
+
{ \
24
+
.grp = PINCTRL_PINGROUP((#name), (name ## _pins), \
25
+
ARRAY_SIZE((name ## _pins))), \
26
+
.reg = offset, \
27
+
.bit = bitv, \
28
+
}
29
+
30
+
#define SPECIFIC_GROUP(group) \
31
+
static const char * const group##_groups[] = { \
32
+
#group \
33
+
}
34
+
35
+
#define FUNCTION(fn) \
36
+
{ \
37
+
.name = #fn, \
38
+
.groups = fn ## _groups, \
39
+
.num_groups = ARRAY_SIZE(fn ## _groups), \
40
+
}
41
+
42
+
struct loongson2_pinctrl {
43
+
struct device *dev;
44
+
struct pinctrl_dev *pcdev;
45
+
struct pinctrl_desc desc;
46
+
struct device_node *of_node;
47
+
spinlock_t lock;
48
+
void __iomem *reg_base;
49
+
};
50
+
51
+
struct loongson2_pmx_group {
52
+
struct pingroup grp;
53
+
unsigned int reg;
54
+
unsigned int bit;
55
+
};
56
+
57
+
struct loongson2_pmx_func {
58
+
const char *name;
59
+
const char * const *groups;
60
+
unsigned int num_groups;
61
+
};
62
+
63
+
#define LOONGSON2_PIN(x) PINCTRL_PIN(x, "gpio"#x)
64
+
static const struct pinctrl_pin_desc loongson2_pctrl_pins[] = {
65
+
LOONGSON2_PIN(0), LOONGSON2_PIN(1), LOONGSON2_PIN(2), LOONGSON2_PIN(3),
66
+
LOONGSON2_PIN(4), LOONGSON2_PIN(5), LOONGSON2_PIN(6), LOONGSON2_PIN(7),
67
+
LOONGSON2_PIN(8), LOONGSON2_PIN(9), LOONGSON2_PIN(10), LOONGSON2_PIN(11),
68
+
LOONGSON2_PIN(12), LOONGSON2_PIN(13), LOONGSON2_PIN(14),
69
+
LOONGSON2_PIN(16), LOONGSON2_PIN(17), LOONGSON2_PIN(18), LOONGSON2_PIN(19),
70
+
LOONGSON2_PIN(20), LOONGSON2_PIN(21), LOONGSON2_PIN(22), LOONGSON2_PIN(23),
71
+
LOONGSON2_PIN(24), LOONGSON2_PIN(25), LOONGSON2_PIN(26), LOONGSON2_PIN(27),
72
+
LOONGSON2_PIN(28), LOONGSON2_PIN(29), LOONGSON2_PIN(30),
73
+
LOONGSON2_PIN(32), LOONGSON2_PIN(33), LOONGSON2_PIN(34), LOONGSON2_PIN(35),
74
+
LOONGSON2_PIN(36), LOONGSON2_PIN(37), LOONGSON2_PIN(38), LOONGSON2_PIN(39),
75
+
LOONGSON2_PIN(40), LOONGSON2_PIN(41),
76
+
LOONGSON2_PIN(44), LOONGSON2_PIN(45), LOONGSON2_PIN(46), LOONGSON2_PIN(47),
77
+
LOONGSON2_PIN(48), LOONGSON2_PIN(49), LOONGSON2_PIN(50), LOONGSON2_PIN(51),
78
+
LOONGSON2_PIN(52), LOONGSON2_PIN(53), LOONGSON2_PIN(54), LOONGSON2_PIN(55),
79
+
LOONGSON2_PIN(56), LOONGSON2_PIN(57), LOONGSON2_PIN(58), LOONGSON2_PIN(59),
80
+
LOONGSON2_PIN(60), LOONGSON2_PIN(61), LOONGSON2_PIN(62), LOONGSON2_PIN(63),
81
+
};
82
+
83
+
static const unsigned int gpio_pins[] = {0, 1, 2, 3, 4, 5, 6, 7,
84
+
8, 9, 10, 11, 12, 13, 14,
85
+
16, 17, 18, 19, 20, 21, 22, 23,
86
+
24, 25, 26, 27, 28, 29, 30,
87
+
32, 33, 34, 35, 36, 37, 38, 39,
88
+
40, 43, 44, 45, 46, 47,
89
+
48, 49, 50, 51, 52, 53, 46, 55,
90
+
56, 57, 58, 59, 60, 61, 62, 63};
91
+
static const unsigned int sdio_pins[] = {36, 37, 38, 39, 40, 41};
92
+
static const unsigned int can1_pins[] = {34, 35};
93
+
static const unsigned int can0_pins[] = {32, 33};
94
+
static const unsigned int pwm3_pins[] = {23};
95
+
static const unsigned int pwm2_pins[] = {22};
96
+
static const unsigned int pwm1_pins[] = {21};
97
+
static const unsigned int pwm0_pins[] = {20};
98
+
static const unsigned int i2c1_pins[] = {18, 19};
99
+
static const unsigned int i2c0_pins[] = {16, 17};
100
+
static const unsigned int nand_pins[] = {44, 45, 46, 47, 48, 49, 50, 51,
101
+
52, 53, 54, 55, 56, 57, 58, 59, 60,
102
+
61, 62, 63};
103
+
static const unsigned int sata_led_pins[] = {14};
104
+
static const unsigned int i2s_pins[] = {24, 25, 26, 27, 28};
105
+
static const unsigned int hda_pins[] = {24, 25, 26, 27, 28, 29, 30};
106
+
107
+
static struct loongson2_pmx_group loongson2_pmx_groups[] = {
108
+
PMX_GROUP(gpio, 0x0, 64),
109
+
PMX_GROUP(sdio, 0x0, 20),
110
+
PMX_GROUP(can1, 0x0, 17),
111
+
PMX_GROUP(can0, 0x0, 16),
112
+
PMX_GROUP(pwm3, 0x0, 15),
113
+
PMX_GROUP(pwm2, 0x0, 14),
114
+
PMX_GROUP(pwm1, 0x0, 13),
115
+
PMX_GROUP(pwm0, 0x0, 12),
116
+
PMX_GROUP(i2c1, 0x0, 11),
117
+
PMX_GROUP(i2c0, 0x0, 10),
118
+
PMX_GROUP(nand, 0x0, 9),
119
+
PMX_GROUP(sata_led, 0x0, 8),
120
+
PMX_GROUP(i2s, 0x0, 6),
121
+
PMX_GROUP(hda, 0x0, 4),
122
+
};
123
+
124
+
SPECIFIC_GROUP(sdio);
125
+
SPECIFIC_GROUP(can1);
126
+
SPECIFIC_GROUP(can0);
127
+
SPECIFIC_GROUP(pwm3);
128
+
SPECIFIC_GROUP(pwm2);
129
+
SPECIFIC_GROUP(pwm1);
130
+
SPECIFIC_GROUP(pwm0);
131
+
SPECIFIC_GROUP(i2c1);
132
+
SPECIFIC_GROUP(i2c0);
133
+
SPECIFIC_GROUP(nand);
134
+
SPECIFIC_GROUP(sata_led);
135
+
SPECIFIC_GROUP(i2s);
136
+
SPECIFIC_GROUP(hda);
137
+
138
+
static const char * const gpio_groups[] = {
139
+
"sdio",
140
+
"can1", "can0",
141
+
"pwm3", "pwm2", "pwm1", "pwm0",
142
+
"i2c1", "i2c0",
143
+
"nand",
144
+
"sata_led",
145
+
"i2s",
146
+
"hda",
147
+
};
148
+
149
+
static const struct loongson2_pmx_func loongson2_pmx_functions[] = {
150
+
FUNCTION(gpio),
151
+
FUNCTION(sdio),
152
+
FUNCTION(can1),
153
+
FUNCTION(can0),
154
+
FUNCTION(pwm3),
155
+
FUNCTION(pwm2),
156
+
FUNCTION(pwm1),
157
+
FUNCTION(pwm0),
158
+
FUNCTION(i2c1),
159
+
FUNCTION(i2c0),
160
+
FUNCTION(nand),
161
+
FUNCTION(sata_led),
162
+
FUNCTION(i2s),
163
+
FUNCTION(hda),
164
+
};
165
+
166
+
static int loongson2_get_groups_count(struct pinctrl_dev *pcdev)
167
+
{
168
+
return ARRAY_SIZE(loongson2_pmx_groups);
169
+
}
170
+
171
+
static const char *loongson2_get_group_name(struct pinctrl_dev *pcdev,
172
+
unsigned int selector)
173
+
{
174
+
return loongson2_pmx_groups[selector].grp.name;
175
+
}
176
+
177
+
static int loongson2_get_group_pins(struct pinctrl_dev *pcdev, unsigned int selector,
178
+
const unsigned int **pins, unsigned int *num_pins)
179
+
{
180
+
*pins = loongson2_pmx_groups[selector].grp.pins;
181
+
*num_pins = loongson2_pmx_groups[selector].grp.npins;
182
+
183
+
return 0;
184
+
}
185
+
186
+
static void loongson2_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
187
+
unsigned int offset)
188
+
{
189
+
seq_printf(s, " %s", dev_name(pcdev->dev));
190
+
}
191
+
192
+
static const struct pinctrl_ops loongson2_pctrl_ops = {
193
+
.get_groups_count = loongson2_get_groups_count,
194
+
.get_group_name = loongson2_get_group_name,
195
+
.get_group_pins = loongson2_get_group_pins,
196
+
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
197
+
.dt_free_map = pinctrl_utils_free_map,
198
+
.pin_dbg_show = loongson2_pin_dbg_show,
199
+
};
200
+
201
+
static int loongson2_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned int func_num,
202
+
unsigned int group_num)
203
+
{
204
+
struct loongson2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pcdev);
205
+
void __iomem *reg = pctrl->reg_base +
206
+
loongson2_pmx_groups[group_num].reg;
207
+
unsigned int mux_bit = loongson2_pmx_groups[group_num].bit;
208
+
unsigned int val;
209
+
unsigned long flags;
210
+
211
+
spin_lock_irqsave(&pctrl->lock, flags);
212
+
val = readl(reg);
213
+
if (func_num == 0)
214
+
val &= ~BIT(mux_bit);
215
+
else
216
+
val |= BIT(mux_bit);
217
+
writel(val, reg);
218
+
spin_unlock_irqrestore(&pctrl->lock, flags);
219
+
220
+
return 0;
221
+
}
222
+
223
+
static int loongson2_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
224
+
{
225
+
return ARRAY_SIZE(loongson2_pmx_functions);
226
+
}
227
+
228
+
static const char *loongson2_pmx_get_func_name(struct pinctrl_dev *pcdev,
229
+
unsigned int selector)
230
+
{
231
+
return loongson2_pmx_functions[selector].name;
232
+
}
233
+
234
+
static int loongson2_pmx_get_groups(struct pinctrl_dev *pcdev,
235
+
unsigned int selector,
236
+
const char * const **groups,
237
+
unsigned int * const num_groups)
238
+
{
239
+
*groups = loongson2_pmx_functions[selector].groups;
240
+
*num_groups = loongson2_pmx_functions[selector].num_groups;
241
+
242
+
return 0;
243
+
}
244
+
245
+
static const struct pinmux_ops loongson2_pmx_ops = {
246
+
.set_mux = loongson2_pmx_set_mux,
247
+
.get_functions_count = loongson2_pmx_get_funcs_count,
248
+
.get_function_name = loongson2_pmx_get_func_name,
249
+
.get_function_groups = loongson2_pmx_get_groups,
250
+
};
251
+
252
+
static int loongson2_pinctrl_probe(struct platform_device *pdev)
253
+
{
254
+
struct device *dev = &pdev->dev;
255
+
struct loongson2_pinctrl *pctrl;
256
+
257
+
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
258
+
if (!pctrl)
259
+
return -ENOMEM;
260
+
261
+
pctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
262
+
if (IS_ERR(pctrl->reg_base))
263
+
return PTR_ERR(pctrl->reg_base);
264
+
265
+
spin_lock_init(&pctrl->lock);
266
+
267
+
pctrl->dev = dev;
268
+
pctrl->desc.name = "pinctrl-loongson2";
269
+
pctrl->desc.owner = THIS_MODULE;
270
+
pctrl->desc.pctlops = &loongson2_pctrl_ops;
271
+
pctrl->desc.pmxops = &loongson2_pmx_ops;
272
+
pctrl->desc.pins = loongson2_pctrl_pins;
273
+
pctrl->desc.npins = ARRAY_SIZE(loongson2_pctrl_pins);
274
+
275
+
pctrl->pcdev = devm_pinctrl_register(pctrl->dev, &pctrl->desc, pctrl);
276
+
if (IS_ERR(pctrl->pcdev))
277
+
return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->pcdev),
278
+
"can't register pinctrl device");
279
+
280
+
return 0;
281
+
}
282
+
283
+
static const struct of_device_id loongson2_pinctrl_dt_match[] = {
284
+
{
285
+
.compatible = "loongson,ls2k-pinctrl",
286
+
},
287
+
{ }
288
+
};
289
+
290
+
static struct platform_driver loongson2_pinctrl_driver = {
291
+
.probe = loongson2_pinctrl_probe,
292
+
.driver = {
293
+
.name = "loongson2-pinctrl",
294
+
.of_match_table = loongson2_pinctrl_dt_match,
295
+
},
296
+
};
297
+
298
+
static int __init loongson2_pinctrl_init(void)
299
+
{
300
+
return platform_driver_register(&loongson2_pinctrl_driver);
301
+
}
302
+
arch_initcall(loongson2_pinctrl_init);
303
+
304
+
static void __exit loongson2_pinctrl_exit(void)
305
+
{
306
+
platform_driver_unregister(&loongson2_pinctrl_driver);
307
+
}
308
+
module_exit(loongson2_pinctrl_exit);
309
+
310
+
MODULE_DESCRIPTION("Loongson2 Pinctrl driver");
311
+
MODULE_LICENSE("GPL");
+4
-2
drivers/pinctrl/pinctrl-lpc18xx.c
+4
-2
drivers/pinctrl/pinctrl-lpc18xx.c
···
10
10
11
11
#include <linux/bitops.h>
12
12
#include <linux/clk.h>
13
-
#include <linux/io.h>
14
13
#include <linux/init.h>
14
+
#include <linux/io.h>
15
15
#include <linux/of.h>
16
16
#include <linux/of_device.h>
17
+
18
+
#include <linux/pinctrl/pinconf-generic.h>
19
+
#include <linux/pinctrl/pinconf.h>
17
20
#include <linux/pinctrl/pinctrl.h>
18
21
#include <linux/pinctrl/pinmux.h>
19
-
#include <linux/pinctrl/pinconf-generic.h>
20
22
21
23
#include "core.h"
22
24
#include "pinctrl-utils.h"
+3
-1
drivers/pinctrl/pinctrl-microchip-sgpio.c
+3
-1
drivers/pinctrl/pinctrl-microchip-sgpio.c
···
15
15
#include <linux/mfd/ocelot.h>
16
16
#include <linux/mod_devicetable.h>
17
17
#include <linux/module.h>
18
-
#include <linux/pinctrl/pinmux.h>
19
18
#include <linux/platform_device.h>
20
19
#include <linux/property.h>
21
20
#include <linux/regmap.h>
22
21
#include <linux/reset.h>
23
22
#include <linux/spinlock.h>
23
+
24
+
#include <linux/pinctrl/pinconf.h>
25
+
#include <linux/pinctrl/pinmux.h>
24
26
25
27
#include "core.h"
26
28
#include "pinconf.h"
+16
-14
drivers/pinctrl/pinctrl-ocelot.c
+16
-14
drivers/pinctrl/pinctrl-ocelot.c
···
14
14
#include <linux/of_device.h>
15
15
#include <linux/of_irq.h>
16
16
#include <linux/of_platform.h>
17
-
#include <linux/pinctrl/pinctrl.h>
18
-
#include <linux/pinctrl/pinmux.h>
19
-
#include <linux/pinctrl/pinconf.h>
20
-
#include <linux/pinctrl/pinconf-generic.h>
21
17
#include <linux/platform_device.h>
22
18
#include <linux/regmap.h>
23
19
#include <linux/reset.h>
24
20
#include <linux/slab.h>
21
+
22
+
#include <linux/pinctrl/consumer.h>
23
+
#include <linux/pinctrl/pinconf-generic.h>
24
+
#include <linux/pinctrl/pinconf.h>
25
+
#include <linux/pinctrl/pinctrl.h>
26
+
#include <linux/pinctrl/pinmux.h>
25
27
26
28
#include "core.h"
27
29
#include "pinconf.h"
···
2049
2047
return devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
2050
2048
}
2051
2049
2050
+
static void ocelot_destroy_workqueue(void *data)
2051
+
{
2052
+
destroy_workqueue(data);
2053
+
}
2054
+
2052
2055
static int ocelot_pinctrl_probe(struct platform_device *pdev)
2053
2056
{
2054
2057
const struct ocelot_match_data *data;
···
2084
2077
info->wq = alloc_ordered_workqueue("ocelot_ordered", 0);
2085
2078
if (!info->wq)
2086
2079
return -ENOMEM;
2080
+
2081
+
ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue,
2082
+
info->wq);
2083
+
if (ret)
2084
+
return ret;
2087
2085
2088
2086
info->pincfg_data = &data->pincfg_data;
2089
2087
···
2131
2119
return 0;
2132
2120
}
2133
2121
2134
-
static int ocelot_pinctrl_remove(struct platform_device *pdev)
2135
-
{
2136
-
struct ocelot_pinctrl *info = platform_get_drvdata(pdev);
2137
-
2138
-
destroy_workqueue(info->wq);
2139
-
2140
-
return 0;
2141
-
}
2142
-
2143
2122
static struct platform_driver ocelot_pinctrl_driver = {
2144
2123
.driver = {
2145
2124
.name = "pinctrl-ocelot",
···
2138
2135
.suppress_bind_attrs = true,
2139
2136
},
2140
2137
.probe = ocelot_pinctrl_probe,
2141
-
.remove = ocelot_pinctrl_remove,
2142
2138
};
2143
2139
module_platform_driver(ocelot_pinctrl_driver);
2144
2140
+3
-3
drivers/pinctrl/pinctrl-single.c
+3
-3
drivers/pinctrl/pinctrl-single.c
···
16
16
#include <linux/err.h>
17
17
#include <linux/list.h>
18
18
#include <linux/interrupt.h>
19
-
20
19
#include <linux/irqchip/chained_irq.h>
21
-
22
20
#include <linux/of.h>
23
21
#include <linux/of_device.h>
24
22
#include <linux/of_address.h>
25
23
#include <linux/of_irq.h>
24
+
#include <linux/seq_file.h>
26
25
26
+
#include <linux/pinctrl/pinconf-generic.h>
27
+
#include <linux/pinctrl/pinconf.h>
27
28
#include <linux/pinctrl/pinctrl.h>
28
29
#include <linux/pinctrl/pinmux.h>
29
-
#include <linux/pinctrl/pinconf-generic.h>
30
30
31
31
#include <linux/platform_data/pinctrl-single.h>
32
32
+17
-12
drivers/pinctrl/pinctrl-st.c
+17
-12
drivers/pinctrl/pinctrl-st.c
···
5
5
* Srinivas Kandagatla <srinivas.kandagatla@st.com>
6
6
*/
7
7
8
-
#include <linux/init.h>
9
-
#include <linux/module.h>
10
-
#include <linux/slab.h>
11
8
#include <linux/err.h>
12
-
#include <linux/io.h>
13
-
#include <linux/of.h>
14
-
#include <linux/of_irq.h>
15
-
#include <linux/of_address.h>
16
9
#include <linux/gpio/driver.h>
17
-
#include <linux/regmap.h>
10
+
#include <linux/init.h>
11
+
#include <linux/io.h>
18
12
#include <linux/mfd/syscon.h>
13
+
#include <linux/module.h>
14
+
#include <linux/of.h>
15
+
#include <linux/of_address.h>
16
+
#include <linux/of_irq.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/regmap.h>
19
+
#include <linux/seq_file.h>
20
+
#include <linux/slab.h>
21
+
#include <linux/string_helpers.h>
22
+
23
+
#include <linux/pinctrl/consumer.h>
24
+
#include <linux/pinctrl/pinconf.h>
19
25
#include <linux/pinctrl/pinctrl.h>
20
26
#include <linux/pinctrl/pinmux.h>
21
-
#include <linux/pinctrl/pinconf.h>
22
-
#include <linux/platform_device.h>
27
+
23
28
#include "core.h"
24
29
25
30
/* PIO Block registers */
···
1180
1175
1181
1176
for (i = 0; i < info->nbanks; i++) {
1182
1177
chip = &info->banks[i].gpio_chip;
1183
-
if (chip->of_node == np) {
1178
+
if (chip->fwnode == of_fwnode_handle(np)) {
1184
1179
if (offset < chip->ngpio)
1185
1180
retval = chip->base + offset;
1186
1181
break;
···
1523
1518
bank->gpio_chip = st_gpio_template;
1524
1519
bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1525
1520
bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1526
-
bank->gpio_chip.of_node = np;
1521
+
bank->gpio_chip.fwnode = of_fwnode_handle(np);
1527
1522
bank->gpio_chip.parent = dev;
1528
1523
spin_lock_init(&bank->lock);
1529
1524
+2
drivers/pinctrl/pinctrl-stmfx.c
+2
drivers/pinctrl/pinctrl-stmfx.c
+6
-2
drivers/pinctrl/pinctrl-thunderbay.c
+6
-2
drivers/pinctrl/pinctrl-thunderbay.c
···
808
808
funcs[i].num_group_names,
809
809
funcs[i].data);
810
810
}
811
-
kfree(funcs);
811
+
812
812
return 0;
813
813
}
814
814
···
817
817
struct function_desc *thunderbay_funcs;
818
818
void *ptr;
819
819
int pin;
820
+
int ret;
820
821
821
822
/*
822
823
* Allocate maximum possible number of functions. Assume every pin
···
861
860
return -ENOMEM;
862
861
863
862
thunderbay_funcs = ptr;
864
-
return thunderbay_add_functions(tpc, thunderbay_funcs);
863
+
ret = thunderbay_add_functions(tpc, thunderbay_funcs);
864
+
865
+
kfree(thunderbay_funcs);
866
+
return ret;
865
867
}
866
868
867
869
static int thunderbay_pinconf_set_tristate(struct thunderbay_pinctrl *tpc,
+5
drivers/pinctrl/pinctrl-utils.h
+5
drivers/pinctrl/pinctrl-utils.h
···
9
9
#ifndef __PINCTRL_UTILS_H__
10
10
#define __PINCTRL_UTILS_H__
11
11
12
+
#include <linux/pinctrl/machine.h>
13
+
14
+
struct pinctrl_dev;
15
+
struct pinctrl_map;
16
+
12
17
int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev,
13
18
struct pinctrl_map **map, unsigned *reserved_maps,
14
19
unsigned *num_maps, unsigned reserve);
+4
-1
drivers/pinctrl/pinctrl-zynqmp.c
+4
-1
drivers/pinctrl/pinctrl-zynqmp.c
···
14
14
#include <linux/module.h>
15
15
#include <linux/of_address.h>
16
16
#include <linux/platform_device.h>
17
+
17
18
#include <linux/firmware/xlnx-zynqmp.h>
18
19
19
-
#include <linux/pinctrl/pinmux.h>
20
20
#include <linux/pinctrl/pinconf-generic.h>
21
+
#include <linux/pinctrl/pinconf.h>
22
+
#include <linux/pinctrl/pinctrl.h>
23
+
#include <linux/pinctrl/pinmux.h>
21
24
22
25
#include "core.h"
23
26
#include "pinctrl-utils.h"
+12
-9
drivers/pinctrl/pinmux.c
+12
-9
drivers/pinctrl/pinmux.c
···
13
13
#define pr_fmt(fmt) "pinmux core: " fmt
14
14
15
15
#include <linux/ctype.h>
16
-
#include <linux/kernel.h>
17
-
#include <linux/module.h>
18
-
#include <linux/init.h>
19
-
#include <linux/device.h>
20
-
#include <linux/slab.h>
21
-
#include <linux/radix-tree.h>
22
-
#include <linux/err.h>
23
-
#include <linux/list.h>
24
-
#include <linux/string.h>
25
16
#include <linux/debugfs.h>
17
+
#include <linux/device.h>
18
+
#include <linux/err.h>
19
+
#include <linux/init.h>
20
+
#include <linux/kernel.h>
21
+
#include <linux/list.h>
22
+
#include <linux/module.h>
23
+
#include <linux/radix-tree.h>
26
24
#include <linux/seq_file.h>
25
+
#include <linux/slab.h>
26
+
#include <linux/string.h>
27
+
27
28
#include <linux/pinctrl/machine.h>
29
+
#include <linux/pinctrl/pinctrl.h>
28
30
#include <linux/pinctrl/pinmux.h>
31
+
29
32
#include "core.h"
30
33
#include "pinmux.h"
31
34
+11
drivers/pinctrl/pinmux.h
+11
drivers/pinctrl/pinmux.h
···
9
9
*
10
10
* Author: Linus Walleij <linus.walleij@linaro.org>
11
11
*/
12
+
13
+
#include <linux/types.h>
14
+
15
+
struct dentry;
16
+
struct seq_file;
17
+
18
+
struct pinctrl_dev;
19
+
struct pinctrl_gpio_range;
20
+
struct pinctrl_map;
21
+
struct pinctrl_setting;
22
+
12
23
#ifdef CONFIG_PINMUX
13
24
14
25
int pinmux_check_ops(struct pinctrl_dev *pctldev);
+10
drivers/pinctrl/qcom/Kconfig
+10
drivers/pinctrl/qcom/Kconfig
···
308
308
Qualcomm Technologies Inc TLMM block found on the Qualcomm
309
309
Technologies Inc SDM660 platform.
310
310
311
+
config PINCTRL_SDM670
312
+
tristate "Qualcomm Technologies Inc SDM670 pin controller driver"
313
+
depends on OF
314
+
depends on ARM64 || COMPILE_TEST
315
+
depends on PINCTRL_MSM
316
+
help
317
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
318
+
Qualcomm Technologies Inc TLMM block found on the Qualcomm
319
+
Technologies Inc SDM670 platform.
320
+
311
321
config PINCTRL_SDM845
312
322
tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
313
323
depends on (OF || ACPI)
+1
drivers/pinctrl/qcom/Makefile
+1
drivers/pinctrl/qcom/Makefile
···
33
33
obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
34
34
obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
35
35
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
36
+
obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
36
37
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
37
38
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
38
39
obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
+5
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+5
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
···
4
4
* Copyright (c) 2020 Linaro Ltd.
5
5
*/
6
6
7
+
#include <linux/bitfield.h>
7
8
#include <linux/clk.h>
8
9
#include <linux/gpio/driver.h>
9
10
#include <linux/module.h>
10
11
#include <linux/of_device.h>
12
+
#include <linux/seq_file.h>
13
+
11
14
#include <linux/pinctrl/pinconf-generic.h>
12
15
#include <linux/pinctrl/pinconf.h>
13
16
#include <linux/pinctrl/pinmux.h>
17
+
14
18
#include "../pinctrl-utils.h"
19
+
15
20
#include "pinctrl-lpass-lpi.h"
16
21
17
22
#define MAX_LPI_NUM_CLKS 2
+7
-2
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+7
-2
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
···
6
6
#ifndef __PINCTRL_LPASS_LPI_H__
7
7
#define __PINCTRL_LPASS_LPI_H__
8
8
9
-
#include <linux/bitops.h>
10
-
#include <linux/bitfield.h>
9
+
#include <linux/bits.h>
10
+
#include <linux/kernel.h>
11
+
11
12
#include "../core.h"
13
+
14
+
struct platform_device;
15
+
16
+
struct pinctrl_pin_desc;
12
17
13
18
#define LPI_SLEW_RATE_CTL_REG 0xa000
14
19
#define LPI_TLMM_REG_OFFSET 0x1000
+15
-14
drivers/pinctrl/qcom/pinctrl-msm.c
+15
-14
drivers/pinctrl/qcom/pinctrl-msm.c
···
6
6
7
7
#include <linux/delay.h>
8
8
#include <linux/err.h>
9
+
#include <linux/gpio/driver.h>
10
+
#include <linux/interrupt.h>
9
11
#include <linux/io.h>
12
+
#include <linux/log2.h>
10
13
#include <linux/module.h>
11
14
#include <linux/of.h>
12
15
#include <linux/platform_device.h>
16
+
#include <linux/pm.h>
17
+
#include <linux/qcom_scm.h>
18
+
#include <linux/reboot.h>
19
+
#include <linux/seq_file.h>
20
+
#include <linux/slab.h>
21
+
#include <linux/spinlock.h>
22
+
13
23
#include <linux/pinctrl/machine.h>
24
+
#include <linux/pinctrl/pinconf-generic.h>
25
+
#include <linux/pinctrl/pinconf.h>
14
26
#include <linux/pinctrl/pinctrl.h>
15
27
#include <linux/pinctrl/pinmux.h>
16
-
#include <linux/pinctrl/pinconf.h>
17
-
#include <linux/pinctrl/pinconf-generic.h>
18
-
#include <linux/slab.h>
19
-
#include <linux/gpio/driver.h>
20
-
#include <linux/interrupt.h>
21
-
#include <linux/spinlock.h>
22
-
#include <linux/reboot.h>
23
-
#include <linux/pm.h>
24
-
#include <linux/log2.h>
25
-
#include <linux/qcom_scm.h>
26
28
27
29
#include <linux/soc/qcom/irq.h>
28
30
29
31
#include "../core.h"
30
32
#include "../pinconf.h"
31
-
#include "pinctrl-msm.h"
32
33
#include "../pinctrl-utils.h"
34
+
35
+
#include "pinctrl-msm.h"
33
36
34
37
#define MAX_NR_GPIO 300
35
38
#define MAX_NR_TILES 4
···
622
619
}
623
620
624
621
#ifdef CONFIG_DEBUG_FS
625
-
#include <linux/seq_file.h>
626
622
627
623
static void msm_gpio_dbg_show_one(struct seq_file *s,
628
624
struct pinctrl_dev *pctldev,
···
710
708
const int *reserved = pctrl->soc->reserved_gpios;
711
709
u16 *tmp;
712
710
713
-
/* Driver provided reserved list overrides DT and ACPI */
711
+
/* Remove driver-provided reserved GPIOs from valid_mask */
714
712
if (reserved) {
715
-
bitmap_fill(valid_mask, ngpios);
716
713
for (i = 0; reserved[i] >= 0; i++) {
717
714
if (i >= ngpios || reserved[i] >= ngpios) {
718
715
dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
+5
drivers/pinctrl/qcom/pinctrl-msm.h
+5
drivers/pinctrl/qcom/pinctrl-msm.h
+1345
drivers/pinctrl/qcom/pinctrl-sdm670.c
+1345
drivers/pinctrl/qcom/pinctrl-sdm670.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2022, Richard Acayan. All rights reserved.
5
+
*/
6
+
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/pinctrl/pinctrl.h>
11
+
12
+
#include "pinctrl-msm.h"
13
+
14
+
#define FUNCTION(fname) \
15
+
[msm_mux_##fname] = { \
16
+
.name = #fname, \
17
+
.groups = fname##_groups, \
18
+
.ngroups = ARRAY_SIZE(fname##_groups), \
19
+
}
20
+
21
+
#define NORTH 0x00500000
22
+
#define SOUTH 0x00900000
23
+
#define WEST 0x00100000
24
+
25
+
#define REG_SIZE 0x1000
26
+
#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
27
+
{ \
28
+
.name = "gpio" #id, \
29
+
.pins = gpio##id##_pins, \
30
+
.npins = ARRAY_SIZE(gpio##id##_pins), \
31
+
.funcs = (int[]){ \
32
+
msm_mux_gpio, /* gpio mode */ \
33
+
msm_mux_##f1, \
34
+
msm_mux_##f2, \
35
+
msm_mux_##f3, \
36
+
msm_mux_##f4, \
37
+
msm_mux_##f5, \
38
+
msm_mux_##f6, \
39
+
msm_mux_##f7, \
40
+
msm_mux_##f8, \
41
+
msm_mux_##f9 \
42
+
}, \
43
+
.nfuncs = 10, \
44
+
.ctl_reg = base + REG_SIZE * id, \
45
+
.io_reg = base + 0x4 + REG_SIZE * id, \
46
+
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
47
+
.intr_status_reg = base + 0xc + REG_SIZE * id, \
48
+
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
49
+
.mux_bit = 2, \
50
+
.pull_bit = 0, \
51
+
.drv_bit = 6, \
52
+
.oe_bit = 9, \
53
+
.in_bit = 0, \
54
+
.out_bit = 1, \
55
+
.intr_enable_bit = 0, \
56
+
.intr_status_bit = 0, \
57
+
.intr_target_bit = 5, \
58
+
.intr_target_kpss_val = 3, \
59
+
.intr_raw_status_bit = 4, \
60
+
.intr_polarity_bit = 1, \
61
+
.intr_detection_bit = 2, \
62
+
.intr_detection_width = 2, \
63
+
}
64
+
65
+
/*
66
+
* A dummy pingroup is a pin group that cannot be assigned a function and has
67
+
* no registers to control or monitor it.
68
+
*/
69
+
#define PINGROUP_DUMMY(id) \
70
+
{ \
71
+
.name = "gpio" #id, \
72
+
.pins = gpio##id##_pins, \
73
+
.npins = ARRAY_SIZE(gpio##id##_pins), \
74
+
.ctl_reg = 0, \
75
+
.io_reg = 0, \
76
+
.intr_cfg_reg = 0, \
77
+
.intr_status_reg = 0, \
78
+
.intr_target_reg = 0, \
79
+
.mux_bit = -1, \
80
+
.pull_bit = -1, \
81
+
.drv_bit = -1, \
82
+
.oe_bit = -1, \
83
+
.in_bit = -1, \
84
+
.out_bit = -1, \
85
+
.intr_enable_bit = -1, \
86
+
.intr_status_bit = -1, \
87
+
.intr_target_bit = -1, \
88
+
.intr_raw_status_bit = -1, \
89
+
.intr_polarity_bit = -1, \
90
+
.intr_detection_bit = -1, \
91
+
.intr_detection_width = -1, \
92
+
}
93
+
94
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
95
+
{ \
96
+
.name = #pg_name, \
97
+
.pins = pg_name##_pins, \
98
+
.npins = ARRAY_SIZE(pg_name##_pins), \
99
+
.ctl_reg = ctl, \
100
+
.io_reg = 0, \
101
+
.intr_cfg_reg = 0, \
102
+
.intr_status_reg = 0, \
103
+
.intr_target_reg = 0, \
104
+
.mux_bit = -1, \
105
+
.pull_bit = pull, \
106
+
.drv_bit = drv, \
107
+
.oe_bit = -1, \
108
+
.in_bit = -1, \
109
+
.out_bit = -1, \
110
+
.intr_enable_bit = -1, \
111
+
.intr_status_bit = -1, \
112
+
.intr_target_bit = -1, \
113
+
.intr_raw_status_bit = -1, \
114
+
.intr_polarity_bit = -1, \
115
+
.intr_detection_bit = -1, \
116
+
.intr_detection_width = -1, \
117
+
}
118
+
119
+
#define UFS_RESET(pg_name, offset) \
120
+
{ \
121
+
.name = #pg_name, \
122
+
.pins = pg_name##_pins, \
123
+
.npins = ARRAY_SIZE(pg_name##_pins), \
124
+
.ctl_reg = offset, \
125
+
.io_reg = offset + 0x4, \
126
+
.intr_cfg_reg = 0, \
127
+
.intr_status_reg = 0, \
128
+
.intr_target_reg = 0, \
129
+
.mux_bit = -1, \
130
+
.pull_bit = 3, \
131
+
.drv_bit = 0, \
132
+
.oe_bit = -1, \
133
+
.in_bit = -1, \
134
+
.out_bit = 0, \
135
+
.intr_enable_bit = -1, \
136
+
.intr_status_bit = -1, \
137
+
.intr_target_bit = -1, \
138
+
.intr_raw_status_bit = -1, \
139
+
.intr_polarity_bit = -1, \
140
+
.intr_detection_bit = -1, \
141
+
.intr_detection_width = -1, \
142
+
}
143
+
144
+
static const struct pinctrl_pin_desc sdm670_pins[] = {
145
+
PINCTRL_PIN(0, "GPIO_0"),
146
+
PINCTRL_PIN(1, "GPIO_1"),
147
+
PINCTRL_PIN(2, "GPIO_2"),
148
+
PINCTRL_PIN(3, "GPIO_3"),
149
+
PINCTRL_PIN(4, "GPIO_4"),
150
+
PINCTRL_PIN(5, "GPIO_5"),
151
+
PINCTRL_PIN(6, "GPIO_6"),
152
+
PINCTRL_PIN(7, "GPIO_7"),
153
+
PINCTRL_PIN(8, "GPIO_8"),
154
+
PINCTRL_PIN(9, "GPIO_9"),
155
+
PINCTRL_PIN(10, "GPIO_10"),
156
+
PINCTRL_PIN(11, "GPIO_11"),
157
+
PINCTRL_PIN(12, "GPIO_12"),
158
+
PINCTRL_PIN(13, "GPIO_13"),
159
+
PINCTRL_PIN(14, "GPIO_14"),
160
+
PINCTRL_PIN(15, "GPIO_15"),
161
+
PINCTRL_PIN(16, "GPIO_16"),
162
+
PINCTRL_PIN(17, "GPIO_17"),
163
+
PINCTRL_PIN(18, "GPIO_18"),
164
+
PINCTRL_PIN(19, "GPIO_19"),
165
+
PINCTRL_PIN(20, "GPIO_20"),
166
+
PINCTRL_PIN(21, "GPIO_21"),
167
+
PINCTRL_PIN(22, "GPIO_22"),
168
+
PINCTRL_PIN(23, "GPIO_23"),
169
+
PINCTRL_PIN(24, "GPIO_24"),
170
+
PINCTRL_PIN(25, "GPIO_25"),
171
+
PINCTRL_PIN(26, "GPIO_26"),
172
+
PINCTRL_PIN(27, "GPIO_27"),
173
+
PINCTRL_PIN(28, "GPIO_28"),
174
+
PINCTRL_PIN(29, "GPIO_29"),
175
+
PINCTRL_PIN(30, "GPIO_30"),
176
+
PINCTRL_PIN(31, "GPIO_31"),
177
+
PINCTRL_PIN(32, "GPIO_32"),
178
+
PINCTRL_PIN(33, "GPIO_33"),
179
+
PINCTRL_PIN(34, "GPIO_34"),
180
+
PINCTRL_PIN(35, "GPIO_35"),
181
+
PINCTRL_PIN(36, "GPIO_36"),
182
+
PINCTRL_PIN(37, "GPIO_37"),
183
+
PINCTRL_PIN(38, "GPIO_38"),
184
+
PINCTRL_PIN(39, "GPIO_39"),
185
+
PINCTRL_PIN(40, "GPIO_40"),
186
+
PINCTRL_PIN(41, "GPIO_41"),
187
+
PINCTRL_PIN(42, "GPIO_42"),
188
+
PINCTRL_PIN(43, "GPIO_43"),
189
+
PINCTRL_PIN(44, "GPIO_44"),
190
+
PINCTRL_PIN(45, "GPIO_45"),
191
+
PINCTRL_PIN(46, "GPIO_46"),
192
+
PINCTRL_PIN(47, "GPIO_47"),
193
+
PINCTRL_PIN(48, "GPIO_48"),
194
+
PINCTRL_PIN(49, "GPIO_49"),
195
+
PINCTRL_PIN(50, "GPIO_50"),
196
+
PINCTRL_PIN(51, "GPIO_51"),
197
+
PINCTRL_PIN(52, "GPIO_52"),
198
+
PINCTRL_PIN(53, "GPIO_53"),
199
+
PINCTRL_PIN(54, "GPIO_54"),
200
+
PINCTRL_PIN(55, "GPIO_55"),
201
+
PINCTRL_PIN(56, "GPIO_56"),
202
+
PINCTRL_PIN(57, "GPIO_57"),
203
+
PINCTRL_PIN(58, "GPIO_58"),
204
+
PINCTRL_PIN(59, "GPIO_59"),
205
+
PINCTRL_PIN(60, "GPIO_60"),
206
+
PINCTRL_PIN(61, "GPIO_61"),
207
+
PINCTRL_PIN(62, "GPIO_62"),
208
+
PINCTRL_PIN(63, "GPIO_63"),
209
+
PINCTRL_PIN(64, "GPIO_64"),
210
+
PINCTRL_PIN(65, "GPIO_65"),
211
+
PINCTRL_PIN(66, "GPIO_66"),
212
+
PINCTRL_PIN(67, "GPIO_67"),
213
+
PINCTRL_PIN(68, "GPIO_68"),
214
+
PINCTRL_PIN(69, "GPIO_69"),
215
+
PINCTRL_PIN(70, "GPIO_70"),
216
+
PINCTRL_PIN(71, "GPIO_71"),
217
+
PINCTRL_PIN(72, "GPIO_72"),
218
+
PINCTRL_PIN(73, "GPIO_73"),
219
+
PINCTRL_PIN(74, "GPIO_74"),
220
+
PINCTRL_PIN(75, "GPIO_75"),
221
+
PINCTRL_PIN(76, "GPIO_76"),
222
+
PINCTRL_PIN(77, "GPIO_77"),
223
+
PINCTRL_PIN(78, "GPIO_78"),
224
+
PINCTRL_PIN(79, "GPIO_79"),
225
+
PINCTRL_PIN(80, "GPIO_80"),
226
+
PINCTRL_PIN(81, "GPIO_81"),
227
+
PINCTRL_PIN(82, "GPIO_82"),
228
+
PINCTRL_PIN(83, "GPIO_83"),
229
+
PINCTRL_PIN(84, "GPIO_84"),
230
+
PINCTRL_PIN(85, "GPIO_85"),
231
+
PINCTRL_PIN(86, "GPIO_86"),
232
+
PINCTRL_PIN(87, "GPIO_87"),
233
+
PINCTRL_PIN(88, "GPIO_88"),
234
+
PINCTRL_PIN(89, "GPIO_89"),
235
+
PINCTRL_PIN(90, "GPIO_90"),
236
+
PINCTRL_PIN(91, "GPIO_91"),
237
+
PINCTRL_PIN(92, "GPIO_92"),
238
+
PINCTRL_PIN(93, "GPIO_93"),
239
+
PINCTRL_PIN(94, "GPIO_94"),
240
+
PINCTRL_PIN(95, "GPIO_95"),
241
+
PINCTRL_PIN(96, "GPIO_96"),
242
+
PINCTRL_PIN(97, "GPIO_97"),
243
+
PINCTRL_PIN(98, "GPIO_98"),
244
+
PINCTRL_PIN(99, "GPIO_99"),
245
+
PINCTRL_PIN(100, "GPIO_100"),
246
+
PINCTRL_PIN(101, "GPIO_101"),
247
+
PINCTRL_PIN(102, "GPIO_102"),
248
+
PINCTRL_PIN(103, "GPIO_103"),
249
+
PINCTRL_PIN(104, "GPIO_104"),
250
+
PINCTRL_PIN(105, "GPIO_105"),
251
+
PINCTRL_PIN(106, "GPIO_106"),
252
+
PINCTRL_PIN(107, "GPIO_107"),
253
+
PINCTRL_PIN(108, "GPIO_108"),
254
+
PINCTRL_PIN(109, "GPIO_109"),
255
+
PINCTRL_PIN(110, "GPIO_110"),
256
+
PINCTRL_PIN(111, "GPIO_111"),
257
+
PINCTRL_PIN(112, "GPIO_112"),
258
+
PINCTRL_PIN(113, "GPIO_113"),
259
+
PINCTRL_PIN(114, "GPIO_114"),
260
+
PINCTRL_PIN(115, "GPIO_115"),
261
+
PINCTRL_PIN(116, "GPIO_116"),
262
+
PINCTRL_PIN(117, "GPIO_117"),
263
+
PINCTRL_PIN(118, "GPIO_118"),
264
+
PINCTRL_PIN(119, "GPIO_119"),
265
+
PINCTRL_PIN(120, "GPIO_120"),
266
+
PINCTRL_PIN(121, "GPIO_121"),
267
+
PINCTRL_PIN(122, "GPIO_122"),
268
+
PINCTRL_PIN(123, "GPIO_123"),
269
+
PINCTRL_PIN(124, "GPIO_124"),
270
+
PINCTRL_PIN(125, "GPIO_125"),
271
+
PINCTRL_PIN(126, "GPIO_126"),
272
+
PINCTRL_PIN(127, "GPIO_127"),
273
+
PINCTRL_PIN(128, "GPIO_128"),
274
+
PINCTRL_PIN(129, "GPIO_129"),
275
+
PINCTRL_PIN(130, "GPIO_130"),
276
+
PINCTRL_PIN(131, "GPIO_131"),
277
+
PINCTRL_PIN(132, "GPIO_132"),
278
+
PINCTRL_PIN(133, "GPIO_133"),
279
+
PINCTRL_PIN(134, "GPIO_134"),
280
+
PINCTRL_PIN(135, "GPIO_135"),
281
+
PINCTRL_PIN(136, "GPIO_136"),
282
+
PINCTRL_PIN(137, "GPIO_137"),
283
+
PINCTRL_PIN(138, "GPIO_138"),
284
+
PINCTRL_PIN(139, "GPIO_139"),
285
+
PINCTRL_PIN(140, "GPIO_140"),
286
+
PINCTRL_PIN(141, "GPIO_141"),
287
+
PINCTRL_PIN(142, "GPIO_142"),
288
+
PINCTRL_PIN(143, "GPIO_143"),
289
+
PINCTRL_PIN(144, "GPIO_144"),
290
+
PINCTRL_PIN(145, "GPIO_145"),
291
+
PINCTRL_PIN(146, "GPIO_146"),
292
+
PINCTRL_PIN(147, "GPIO_147"),
293
+
PINCTRL_PIN(148, "GPIO_148"),
294
+
PINCTRL_PIN(149, "GPIO_149"),
295
+
PINCTRL_PIN(150, "UFS_RESET"),
296
+
PINCTRL_PIN(151, "SDC1_RCLK"),
297
+
PINCTRL_PIN(152, "SDC1_CLK"),
298
+
PINCTRL_PIN(153, "SDC1_CMD"),
299
+
PINCTRL_PIN(154, "SDC1_DATA"),
300
+
PINCTRL_PIN(155, "SDC2_CLK"),
301
+
PINCTRL_PIN(156, "SDC2_CMD"),
302
+
PINCTRL_PIN(157, "SDC2_DATA"),
303
+
};
304
+
305
+
#define DECLARE_MSM_GPIO_PINS(pin) \
306
+
static const unsigned int gpio##pin##_pins[] = { pin }
307
+
DECLARE_MSM_GPIO_PINS(0);
308
+
DECLARE_MSM_GPIO_PINS(1);
309
+
DECLARE_MSM_GPIO_PINS(2);
310
+
DECLARE_MSM_GPIO_PINS(3);
311
+
DECLARE_MSM_GPIO_PINS(4);
312
+
DECLARE_MSM_GPIO_PINS(5);
313
+
DECLARE_MSM_GPIO_PINS(6);
314
+
DECLARE_MSM_GPIO_PINS(7);
315
+
DECLARE_MSM_GPIO_PINS(8);
316
+
DECLARE_MSM_GPIO_PINS(9);
317
+
DECLARE_MSM_GPIO_PINS(10);
318
+
DECLARE_MSM_GPIO_PINS(11);
319
+
DECLARE_MSM_GPIO_PINS(12);
320
+
DECLARE_MSM_GPIO_PINS(13);
321
+
DECLARE_MSM_GPIO_PINS(14);
322
+
DECLARE_MSM_GPIO_PINS(15);
323
+
DECLARE_MSM_GPIO_PINS(16);
324
+
DECLARE_MSM_GPIO_PINS(17);
325
+
DECLARE_MSM_GPIO_PINS(18);
326
+
DECLARE_MSM_GPIO_PINS(19);
327
+
DECLARE_MSM_GPIO_PINS(20);
328
+
DECLARE_MSM_GPIO_PINS(21);
329
+
DECLARE_MSM_GPIO_PINS(22);
330
+
DECLARE_MSM_GPIO_PINS(23);
331
+
DECLARE_MSM_GPIO_PINS(24);
332
+
DECLARE_MSM_GPIO_PINS(25);
333
+
DECLARE_MSM_GPIO_PINS(26);
334
+
DECLARE_MSM_GPIO_PINS(27);
335
+
DECLARE_MSM_GPIO_PINS(28);
336
+
DECLARE_MSM_GPIO_PINS(29);
337
+
DECLARE_MSM_GPIO_PINS(30);
338
+
DECLARE_MSM_GPIO_PINS(31);
339
+
DECLARE_MSM_GPIO_PINS(32);
340
+
DECLARE_MSM_GPIO_PINS(33);
341
+
DECLARE_MSM_GPIO_PINS(34);
342
+
DECLARE_MSM_GPIO_PINS(35);
343
+
DECLARE_MSM_GPIO_PINS(36);
344
+
DECLARE_MSM_GPIO_PINS(37);
345
+
DECLARE_MSM_GPIO_PINS(38);
346
+
DECLARE_MSM_GPIO_PINS(39);
347
+
DECLARE_MSM_GPIO_PINS(40);
348
+
DECLARE_MSM_GPIO_PINS(41);
349
+
DECLARE_MSM_GPIO_PINS(42);
350
+
DECLARE_MSM_GPIO_PINS(43);
351
+
DECLARE_MSM_GPIO_PINS(44);
352
+
DECLARE_MSM_GPIO_PINS(45);
353
+
DECLARE_MSM_GPIO_PINS(46);
354
+
DECLARE_MSM_GPIO_PINS(47);
355
+
DECLARE_MSM_GPIO_PINS(48);
356
+
DECLARE_MSM_GPIO_PINS(49);
357
+
DECLARE_MSM_GPIO_PINS(50);
358
+
DECLARE_MSM_GPIO_PINS(51);
359
+
DECLARE_MSM_GPIO_PINS(52);
360
+
DECLARE_MSM_GPIO_PINS(53);
361
+
DECLARE_MSM_GPIO_PINS(54);
362
+
DECLARE_MSM_GPIO_PINS(55);
363
+
DECLARE_MSM_GPIO_PINS(56);
364
+
DECLARE_MSM_GPIO_PINS(57);
365
+
DECLARE_MSM_GPIO_PINS(58);
366
+
DECLARE_MSM_GPIO_PINS(59);
367
+
DECLARE_MSM_GPIO_PINS(60);
368
+
DECLARE_MSM_GPIO_PINS(61);
369
+
DECLARE_MSM_GPIO_PINS(62);
370
+
DECLARE_MSM_GPIO_PINS(63);
371
+
DECLARE_MSM_GPIO_PINS(64);
372
+
DECLARE_MSM_GPIO_PINS(65);
373
+
DECLARE_MSM_GPIO_PINS(66);
374
+
DECLARE_MSM_GPIO_PINS(67);
375
+
DECLARE_MSM_GPIO_PINS(68);
376
+
DECLARE_MSM_GPIO_PINS(69);
377
+
DECLARE_MSM_GPIO_PINS(70);
378
+
DECLARE_MSM_GPIO_PINS(71);
379
+
DECLARE_MSM_GPIO_PINS(72);
380
+
DECLARE_MSM_GPIO_PINS(73);
381
+
DECLARE_MSM_GPIO_PINS(74);
382
+
DECLARE_MSM_GPIO_PINS(75);
383
+
DECLARE_MSM_GPIO_PINS(76);
384
+
DECLARE_MSM_GPIO_PINS(77);
385
+
DECLARE_MSM_GPIO_PINS(78);
386
+
DECLARE_MSM_GPIO_PINS(79);
387
+
DECLARE_MSM_GPIO_PINS(80);
388
+
DECLARE_MSM_GPIO_PINS(81);
389
+
DECLARE_MSM_GPIO_PINS(82);
390
+
DECLARE_MSM_GPIO_PINS(83);
391
+
DECLARE_MSM_GPIO_PINS(84);
392
+
DECLARE_MSM_GPIO_PINS(85);
393
+
DECLARE_MSM_GPIO_PINS(86);
394
+
DECLARE_MSM_GPIO_PINS(87);
395
+
DECLARE_MSM_GPIO_PINS(88);
396
+
DECLARE_MSM_GPIO_PINS(89);
397
+
DECLARE_MSM_GPIO_PINS(90);
398
+
DECLARE_MSM_GPIO_PINS(91);
399
+
DECLARE_MSM_GPIO_PINS(92);
400
+
DECLARE_MSM_GPIO_PINS(93);
401
+
DECLARE_MSM_GPIO_PINS(94);
402
+
DECLARE_MSM_GPIO_PINS(95);
403
+
DECLARE_MSM_GPIO_PINS(96);
404
+
DECLARE_MSM_GPIO_PINS(97);
405
+
DECLARE_MSM_GPIO_PINS(98);
406
+
DECLARE_MSM_GPIO_PINS(99);
407
+
DECLARE_MSM_GPIO_PINS(100);
408
+
DECLARE_MSM_GPIO_PINS(101);
409
+
DECLARE_MSM_GPIO_PINS(102);
410
+
DECLARE_MSM_GPIO_PINS(103);
411
+
DECLARE_MSM_GPIO_PINS(104);
412
+
DECLARE_MSM_GPIO_PINS(105);
413
+
DECLARE_MSM_GPIO_PINS(106);
414
+
DECLARE_MSM_GPIO_PINS(107);
415
+
DECLARE_MSM_GPIO_PINS(108);
416
+
DECLARE_MSM_GPIO_PINS(109);
417
+
DECLARE_MSM_GPIO_PINS(110);
418
+
DECLARE_MSM_GPIO_PINS(111);
419
+
DECLARE_MSM_GPIO_PINS(112);
420
+
DECLARE_MSM_GPIO_PINS(113);
421
+
DECLARE_MSM_GPIO_PINS(114);
422
+
DECLARE_MSM_GPIO_PINS(115);
423
+
DECLARE_MSM_GPIO_PINS(116);
424
+
DECLARE_MSM_GPIO_PINS(117);
425
+
DECLARE_MSM_GPIO_PINS(118);
426
+
DECLARE_MSM_GPIO_PINS(119);
427
+
DECLARE_MSM_GPIO_PINS(120);
428
+
DECLARE_MSM_GPIO_PINS(121);
429
+
DECLARE_MSM_GPIO_PINS(122);
430
+
DECLARE_MSM_GPIO_PINS(123);
431
+
DECLARE_MSM_GPIO_PINS(124);
432
+
DECLARE_MSM_GPIO_PINS(125);
433
+
DECLARE_MSM_GPIO_PINS(126);
434
+
DECLARE_MSM_GPIO_PINS(127);
435
+
DECLARE_MSM_GPIO_PINS(128);
436
+
DECLARE_MSM_GPIO_PINS(129);
437
+
DECLARE_MSM_GPIO_PINS(130);
438
+
DECLARE_MSM_GPIO_PINS(131);
439
+
DECLARE_MSM_GPIO_PINS(132);
440
+
DECLARE_MSM_GPIO_PINS(133);
441
+
DECLARE_MSM_GPIO_PINS(134);
442
+
DECLARE_MSM_GPIO_PINS(135);
443
+
DECLARE_MSM_GPIO_PINS(136);
444
+
DECLARE_MSM_GPIO_PINS(137);
445
+
DECLARE_MSM_GPIO_PINS(138);
446
+
DECLARE_MSM_GPIO_PINS(139);
447
+
DECLARE_MSM_GPIO_PINS(140);
448
+
DECLARE_MSM_GPIO_PINS(141);
449
+
DECLARE_MSM_GPIO_PINS(142);
450
+
DECLARE_MSM_GPIO_PINS(143);
451
+
DECLARE_MSM_GPIO_PINS(144);
452
+
DECLARE_MSM_GPIO_PINS(145);
453
+
DECLARE_MSM_GPIO_PINS(146);
454
+
DECLARE_MSM_GPIO_PINS(147);
455
+
DECLARE_MSM_GPIO_PINS(148);
456
+
DECLARE_MSM_GPIO_PINS(149);
457
+
458
+
static const unsigned int ufs_reset_pins[] = { 150 };
459
+
static const unsigned int sdc1_rclk_pins[] = { 151 };
460
+
static const unsigned int sdc1_clk_pins[] = { 152 };
461
+
static const unsigned int sdc1_cmd_pins[] = { 153 };
462
+
static const unsigned int sdc1_data_pins[] = { 154 };
463
+
static const unsigned int sdc2_clk_pins[] = { 155 };
464
+
static const unsigned int sdc2_cmd_pins[] = { 156 };
465
+
static const unsigned int sdc2_data_pins[] = { 157 };
466
+
467
+
enum sdm670_functions {
468
+
msm_mux_gpio,
469
+
msm_mux_adsp_ext,
470
+
msm_mux_agera_pll,
471
+
msm_mux_atest_char,
472
+
msm_mux_atest_tsens,
473
+
msm_mux_atest_tsens2,
474
+
msm_mux_atest_usb1,
475
+
msm_mux_atest_usb10,
476
+
msm_mux_atest_usb11,
477
+
msm_mux_atest_usb12,
478
+
msm_mux_atest_usb13,
479
+
msm_mux_atest_usb2,
480
+
msm_mux_atest_usb20,
481
+
msm_mux_atest_usb21,
482
+
msm_mux_atest_usb22,
483
+
msm_mux_atest_usb23,
484
+
msm_mux_cam_mclk,
485
+
msm_mux_cci_async,
486
+
msm_mux_cci_i2c,
487
+
msm_mux_cci_timer0,
488
+
msm_mux_cci_timer1,
489
+
msm_mux_cci_timer2,
490
+
msm_mux_cci_timer3,
491
+
msm_mux_cci_timer4,
492
+
msm_mux_copy_gp,
493
+
msm_mux_copy_phase,
494
+
msm_mux_dbg_out,
495
+
msm_mux_ddr_bist,
496
+
msm_mux_ddr_pxi0,
497
+
msm_mux_ddr_pxi1,
498
+
msm_mux_ddr_pxi2,
499
+
msm_mux_ddr_pxi3,
500
+
msm_mux_edp_hot,
501
+
msm_mux_edp_lcd,
502
+
msm_mux_gcc_gp1,
503
+
msm_mux_gcc_gp2,
504
+
msm_mux_gcc_gp3,
505
+
msm_mux_gp_pdm0,
506
+
msm_mux_gp_pdm1,
507
+
msm_mux_gp_pdm2,
508
+
msm_mux_gps_tx,
509
+
msm_mux_jitter_bist,
510
+
msm_mux_ldo_en,
511
+
msm_mux_ldo_update,
512
+
msm_mux_lpass_slimbus,
513
+
msm_mux_m_voc,
514
+
msm_mux_mdp_vsync,
515
+
msm_mux_mdp_vsync0,
516
+
msm_mux_mdp_vsync1,
517
+
msm_mux_mdp_vsync2,
518
+
msm_mux_mdp_vsync3,
519
+
msm_mux_mss_lte,
520
+
msm_mux_nav_pps,
521
+
msm_mux_pa_indicator,
522
+
msm_mux_pci_e0,
523
+
msm_mux_pci_e1,
524
+
msm_mux_phase_flag,
525
+
msm_mux_pll_bist,
526
+
msm_mux_pll_bypassnl,
527
+
msm_mux_pll_reset,
528
+
msm_mux_pri_mi2s,
529
+
msm_mux_pri_mi2s_ws,
530
+
msm_mux_prng_rosc,
531
+
msm_mux_qdss_cti,
532
+
msm_mux_qdss,
533
+
msm_mux_qlink_enable,
534
+
msm_mux_qlink_request,
535
+
msm_mux_qua_mi2s,
536
+
msm_mux_qup0,
537
+
msm_mux_qup1,
538
+
msm_mux_qup10,
539
+
msm_mux_qup11,
540
+
msm_mux_qup12,
541
+
msm_mux_qup13,
542
+
msm_mux_qup14,
543
+
msm_mux_qup15,
544
+
msm_mux_qup2,
545
+
msm_mux_qup3,
546
+
msm_mux_qup4,
547
+
msm_mux_qup5,
548
+
msm_mux_qup6,
549
+
msm_mux_qup7,
550
+
msm_mux_qup8,
551
+
msm_mux_qup9,
552
+
msm_mux_qup_l4,
553
+
msm_mux_qup_l5,
554
+
msm_mux_qup_l6,
555
+
msm_mux_sd_write,
556
+
msm_mux_sdc4_clk,
557
+
msm_mux_sdc4_cmd,
558
+
msm_mux_sdc4_data,
559
+
msm_mux_sec_mi2s,
560
+
msm_mux_ter_mi2s,
561
+
msm_mux_tgu_ch0,
562
+
msm_mux_tgu_ch1,
563
+
msm_mux_tgu_ch2,
564
+
msm_mux_tgu_ch3,
565
+
msm_mux_tsif1_clk,
566
+
msm_mux_tsif1_data,
567
+
msm_mux_tsif1_en,
568
+
msm_mux_tsif1_error,
569
+
msm_mux_tsif1_sync,
570
+
msm_mux_tsif2_clk,
571
+
msm_mux_tsif2_data,
572
+
msm_mux_tsif2_en,
573
+
msm_mux_tsif2_error,
574
+
msm_mux_tsif2_sync,
575
+
msm_mux_uim1_clk,
576
+
msm_mux_uim1_data,
577
+
msm_mux_uim1_present,
578
+
msm_mux_uim1_reset,
579
+
msm_mux_uim2_clk,
580
+
msm_mux_uim2_data,
581
+
msm_mux_uim2_present,
582
+
msm_mux_uim2_reset,
583
+
msm_mux_uim_batt,
584
+
msm_mux_usb_phy,
585
+
msm_mux_vfr_1,
586
+
msm_mux_vsense_trigger,
587
+
msm_mux_wlan1_adc0,
588
+
msm_mux_wlan1_adc1,
589
+
msm_mux_wlan2_adc0,
590
+
msm_mux_wlan2_adc1,
591
+
msm_mux_wsa_clk,
592
+
msm_mux_wsa_data,
593
+
msm_mux__,
594
+
};
595
+
596
+
static const char * const gpio_groups[] = {
597
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
598
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
599
+
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
600
+
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
601
+
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
602
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
603
+
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
604
+
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
605
+
"gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76",
606
+
"gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
607
+
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
608
+
"gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97",
609
+
"gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
610
+
"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
611
+
"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
612
+
"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
613
+
"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
614
+
"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
615
+
"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
616
+
"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
617
+
"gpio147", "gpio148", "gpio149",
618
+
};
619
+
static const char * const qup0_groups[] = {
620
+
"gpio0", "gpio1", "gpio2", "gpio3",
621
+
};
622
+
static const char * const qup9_groups[] = {
623
+
"gpio4", "gpio5", "gpio6", "gpio7",
624
+
};
625
+
static const char * const qdss_cti_groups[] = {
626
+
"gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91",
627
+
};
628
+
static const char * const ddr_pxi0_groups[] = {
629
+
"gpio6", "gpio7",
630
+
};
631
+
static const char * const ddr_bist_groups[] = {
632
+
"gpio7", "gpio8", "gpio9", "gpio10",
633
+
};
634
+
static const char * const atest_tsens2_groups[] = {
635
+
"gpio7",
636
+
};
637
+
static const char * const vsense_trigger_groups[] = {
638
+
"gpio7",
639
+
};
640
+
static const char * const atest_usb1_groups[] = {
641
+
"gpio7",
642
+
};
643
+
static const char * const qup_l4_groups[] = {
644
+
"gpio8", "gpio35", "gpio75", "gpio105", "gpio123",
645
+
};
646
+
static const char * const gp_pdm1_groups[] = {
647
+
"gpio8", "gpio66",
648
+
};
649
+
static const char * const qup_l5_groups[] = {
650
+
"gpio9", "gpio36", "gpio76", "gpio106", "gpio124",
651
+
};
652
+
static const char * const mdp_vsync_groups[] = {
653
+
"gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
654
+
};
655
+
static const char * const qup_l6_groups[] = {
656
+
"gpio10", "gpio37", "gpio77", "gpio107", "gpio125",
657
+
};
658
+
static const char * const wlan2_adc1_groups[] = {
659
+
"gpio10",
660
+
};
661
+
static const char * const atest_usb11_groups[] = {
662
+
"gpio10",
663
+
};
664
+
static const char * const ddr_pxi2_groups[] = {
665
+
"gpio10", "gpio11",
666
+
};
667
+
static const char * const edp_lcd_groups[] = {
668
+
"gpio11",
669
+
};
670
+
static const char * const dbg_out_groups[] = {
671
+
"gpio11",
672
+
};
673
+
static const char * const wlan2_adc0_groups[] = {
674
+
"gpio11",
675
+
};
676
+
static const char * const atest_usb10_groups[] = {
677
+
"gpio11",
678
+
};
679
+
static const char * const m_voc_groups[] = {
680
+
"gpio12",
681
+
};
682
+
static const char * const tsif1_sync_groups[] = {
683
+
"gpio12",
684
+
};
685
+
static const char * const ddr_pxi3_groups[] = {
686
+
"gpio12", "gpio13",
687
+
};
688
+
static const char * const cam_mclk_groups[] = {
689
+
"gpio13", "gpio14", "gpio15", "gpio16",
690
+
};
691
+
static const char * const pll_bypassnl_groups[] = {
692
+
"gpio13",
693
+
};
694
+
static const char * const qdss_groups[] = {
695
+
"gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
696
+
"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
697
+
"gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
698
+
"gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
699
+
"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
700
+
"gpio123", "gpio124",
701
+
};
702
+
static const char * const pll_reset_groups[] = {
703
+
"gpio14",
704
+
};
705
+
static const char * const cci_i2c_groups[] = {
706
+
"gpio17", "gpio18", "gpio19", "gpio20",
707
+
};
708
+
static const char * const qup1_groups[] = {
709
+
"gpio17", "gpio18", "gpio19", "gpio20",
710
+
};
711
+
static const char * const cci_timer0_groups[] = {
712
+
"gpio21",
713
+
};
714
+
static const char * const gcc_gp2_groups[] = {
715
+
"gpio21",
716
+
};
717
+
static const char * const cci_timer1_groups[] = {
718
+
"gpio22",
719
+
};
720
+
static const char * const gcc_gp3_groups[] = {
721
+
"gpio22",
722
+
};
723
+
static const char * const cci_timer2_groups[] = {
724
+
"gpio23",
725
+
};
726
+
static const char * const cci_timer3_groups[] = {
727
+
"gpio24",
728
+
};
729
+
static const char * const cci_async_groups[] = {
730
+
"gpio24", "gpio25", "gpio26",
731
+
};
732
+
static const char * const cci_timer4_groups[] = {
733
+
"gpio25",
734
+
};
735
+
static const char * const jitter_bist_groups[] = {
736
+
"gpio26", "gpio35",
737
+
};
738
+
static const char * const qup2_groups[] = {
739
+
"gpio27", "gpio28", "gpio29", "gpio30",
740
+
};
741
+
static const char * const pll_bist_groups[] = {
742
+
"gpio27", "gpio36",
743
+
};
744
+
static const char * const agera_pll_groups[] = {
745
+
"gpio28", "gpio37",
746
+
};
747
+
static const char * const atest_tsens_groups[] = {
748
+
"gpio29",
749
+
};
750
+
static const char * const phase_flag_groups[] = {
751
+
"gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
752
+
"gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96",
753
+
"gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139",
754
+
"gpio140", "gpio141", "gpio142", "gpio143",
755
+
};
756
+
static const char * const qup11_groups[] = {
757
+
"gpio31", "gpio32", "gpio33", "gpio34",
758
+
};
759
+
static const char * const qup14_groups[] = {
760
+
"gpio31", "gpio32", "gpio33", "gpio34",
761
+
};
762
+
static const char * const pci_e0_groups[] = {
763
+
"gpio35", "gpio36",
764
+
};
765
+
static const char * const usb_phy_groups[] = {
766
+
"gpio38",
767
+
};
768
+
static const char * const lpass_slimbus_groups[] = {
769
+
"gpio39",
770
+
};
771
+
static const char * const sd_write_groups[] = {
772
+
"gpio40",
773
+
};
774
+
static const char * const tsif1_error_groups[] = {
775
+
"gpio40",
776
+
};
777
+
static const char * const qup3_groups[] = {
778
+
"gpio41", "gpio42", "gpio43", "gpio44",
779
+
};
780
+
static const char * const qup6_groups[] = {
781
+
"gpio45", "gpio46", "gpio47", "gpio48",
782
+
};
783
+
static const char * const qup12_groups[] = {
784
+
"gpio49", "gpio50", "gpio51", "gpio52",
785
+
};
786
+
static const char * const qup10_groups[] = {
787
+
"gpio53", "gpio54", "gpio55", "gpio56",
788
+
};
789
+
static const char * const gp_pdm0_groups[] = {
790
+
"gpio54", "gpio95",
791
+
};
792
+
static const char * const wlan1_adc1_groups[] = {
793
+
"gpio54",
794
+
};
795
+
static const char * const atest_usb13_groups[] = {
796
+
"gpio54",
797
+
};
798
+
static const char * const ddr_pxi1_groups[] = {
799
+
"gpio54", "gpio55",
800
+
};
801
+
static const char * const wlan1_adc0_groups[] = {
802
+
"gpio55",
803
+
};
804
+
static const char * const atest_usb12_groups[] = {
805
+
"gpio55",
806
+
};
807
+
static const char * const qua_mi2s_groups[] = {
808
+
"gpio57",
809
+
};
810
+
static const char * const gcc_gp1_groups[] = {
811
+
"gpio57", "gpio78",
812
+
};
813
+
static const char * const pri_mi2s_groups[] = {
814
+
"gpio65", "gpio67", "gpio68",
815
+
};
816
+
static const char * const qup8_groups[] = {
817
+
"gpio65", "gpio66", "gpio67", "gpio68",
818
+
};
819
+
static const char * const wsa_clk_groups[] = {
820
+
"gpio65",
821
+
};
822
+
static const char * const pri_mi2s_ws_groups[] = {
823
+
"gpio66",
824
+
};
825
+
static const char * const wsa_data_groups[] = {
826
+
"gpio66",
827
+
};
828
+
static const char * const atest_usb2_groups[] = {
829
+
"gpio67",
830
+
};
831
+
static const char * const atest_usb23_groups[] = {
832
+
"gpio68",
833
+
};
834
+
static const char * const ter_mi2s_groups[] = {
835
+
"gpio75", "gpio76", "gpio77", "gpio78",
836
+
};
837
+
static const char * const atest_usb22_groups[] = {
838
+
"gpio75",
839
+
};
840
+
static const char * const atest_usb21_groups[] = {
841
+
"gpio76",
842
+
};
843
+
static const char * const atest_usb20_groups[] = {
844
+
"gpio77",
845
+
};
846
+
static const char * const sec_mi2s_groups[] = {
847
+
"gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
848
+
};
849
+
static const char * const gp_pdm2_groups[] = {
850
+
"gpio79",
851
+
};
852
+
static const char * const qup15_groups[] = {
853
+
"gpio81", "gpio82", "gpio83", "gpio84",
854
+
};
855
+
static const char * const qup5_groups[] = {
856
+
"gpio85", "gpio86", "gpio87", "gpio88",
857
+
};
858
+
static const char * const copy_gp_groups[] = {
859
+
"gpio86",
860
+
};
861
+
static const char * const tsif1_clk_groups[] = {
862
+
"gpio89",
863
+
};
864
+
static const char * const qup4_groups[] = {
865
+
"gpio89", "gpio90", "gpio91", "gpio92",
866
+
};
867
+
static const char * const tgu_ch3_groups[] = {
868
+
"gpio89",
869
+
};
870
+
static const char * const tsif1_en_groups[] = {
871
+
"gpio90",
872
+
};
873
+
static const char * const mdp_vsync0_groups[] = {
874
+
"gpio90",
875
+
};
876
+
static const char * const mdp_vsync1_groups[] = {
877
+
"gpio90",
878
+
};
879
+
static const char * const mdp_vsync2_groups[] = {
880
+
"gpio90",
881
+
};
882
+
static const char * const mdp_vsync3_groups[] = {
883
+
"gpio90",
884
+
};
885
+
static const char * const tgu_ch0_groups[] = {
886
+
"gpio90",
887
+
};
888
+
static const char * const tsif1_data_groups[] = {
889
+
"gpio91",
890
+
};
891
+
static const char * const sdc4_cmd_groups[] = {
892
+
"gpio91",
893
+
};
894
+
static const char * const tgu_ch1_groups[] = {
895
+
"gpio91",
896
+
};
897
+
static const char * const tsif2_error_groups[] = {
898
+
"gpio92",
899
+
};
900
+
static const char * const vfr_1_groups[] = {
901
+
"gpio92",
902
+
};
903
+
static const char * const tgu_ch2_groups[] = {
904
+
"gpio92",
905
+
};
906
+
static const char * const sdc4_data_groups[] = {
907
+
"gpio92", "gpio94", "gpio95", "gpio96",
908
+
};
909
+
static const char * const tsif2_clk_groups[] = {
910
+
"gpio93",
911
+
};
912
+
static const char * const sdc4_clk_groups[] = {
913
+
"gpio93",
914
+
};
915
+
static const char * const qup7_groups[] = {
916
+
"gpio93", "gpio94", "gpio95", "gpio96",
917
+
};
918
+
static const char * const tsif2_en_groups[] = {
919
+
"gpio94",
920
+
};
921
+
static const char * const tsif2_data_groups[] = {
922
+
"gpio95",
923
+
};
924
+
static const char * const tsif2_sync_groups[] = {
925
+
"gpio96",
926
+
};
927
+
static const char * const ldo_en_groups[] = {
928
+
"gpio97",
929
+
};
930
+
static const char * const ldo_update_groups[] = {
931
+
"gpio98",
932
+
};
933
+
static const char * const prng_rosc_groups[] = {
934
+
"gpio99", "gpio102",
935
+
};
936
+
static const char * const pci_e1_groups[] = {
937
+
"gpio102", "gpio103",
938
+
};
939
+
static const char * const copy_phase_groups[] = {
940
+
"gpio103",
941
+
};
942
+
static const char * const uim2_data_groups[] = {
943
+
"gpio105",
944
+
};
945
+
static const char * const qup13_groups[] = {
946
+
"gpio105", "gpio106", "gpio107", "gpio108",
947
+
};
948
+
static const char * const uim2_clk_groups[] = {
949
+
"gpio106",
950
+
};
951
+
static const char * const uim2_reset_groups[] = {
952
+
"gpio107",
953
+
};
954
+
static const char * const uim2_present_groups[] = {
955
+
"gpio108",
956
+
};
957
+
static const char * const uim1_data_groups[] = {
958
+
"gpio109",
959
+
};
960
+
static const char * const uim1_clk_groups[] = {
961
+
"gpio110",
962
+
};
963
+
static const char * const uim1_reset_groups[] = {
964
+
"gpio111",
965
+
};
966
+
static const char * const uim1_present_groups[] = {
967
+
"gpio112",
968
+
};
969
+
static const char * const uim_batt_groups[] = {
970
+
"gpio113",
971
+
};
972
+
static const char * const edp_hot_groups[] = {
973
+
"gpio113",
974
+
};
975
+
static const char * const nav_pps_groups[] = {
976
+
"gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
977
+
"gpio129", "gpio129", "gpio143", "gpio143",
978
+
};
979
+
static const char * const gps_tx_groups[] = {
980
+
"gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145",
981
+
};
982
+
static const char * const atest_char_groups[] = {
983
+
"gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
984
+
};
985
+
static const char * const adsp_ext_groups[] = {
986
+
"gpio118",
987
+
};
988
+
static const char * const qlink_request_groups[] = {
989
+
"gpio130",
990
+
};
991
+
static const char * const qlink_enable_groups[] = {
992
+
"gpio131",
993
+
};
994
+
static const char * const pa_indicator_groups[] = {
995
+
"gpio135",
996
+
};
997
+
static const char * const mss_lte_groups[] = {
998
+
"gpio144", "gpio145",
999
+
};
1000
+
1001
+
static const struct msm_function sdm670_functions[] = {
1002
+
FUNCTION(gpio),
1003
+
FUNCTION(adsp_ext),
1004
+
FUNCTION(agera_pll),
1005
+
FUNCTION(atest_char),
1006
+
FUNCTION(atest_tsens),
1007
+
FUNCTION(atest_tsens2),
1008
+
FUNCTION(atest_usb1),
1009
+
FUNCTION(atest_usb10),
1010
+
FUNCTION(atest_usb11),
1011
+
FUNCTION(atest_usb12),
1012
+
FUNCTION(atest_usb13),
1013
+
FUNCTION(atest_usb2),
1014
+
FUNCTION(atest_usb20),
1015
+
FUNCTION(atest_usb21),
1016
+
FUNCTION(atest_usb22),
1017
+
FUNCTION(atest_usb23),
1018
+
FUNCTION(cam_mclk),
1019
+
FUNCTION(cci_async),
1020
+
FUNCTION(cci_i2c),
1021
+
FUNCTION(cci_timer0),
1022
+
FUNCTION(cci_timer1),
1023
+
FUNCTION(cci_timer2),
1024
+
FUNCTION(cci_timer3),
1025
+
FUNCTION(cci_timer4),
1026
+
FUNCTION(copy_gp),
1027
+
FUNCTION(copy_phase),
1028
+
FUNCTION(dbg_out),
1029
+
FUNCTION(ddr_bist),
1030
+
FUNCTION(ddr_pxi0),
1031
+
FUNCTION(ddr_pxi1),
1032
+
FUNCTION(ddr_pxi2),
1033
+
FUNCTION(ddr_pxi3),
1034
+
FUNCTION(edp_hot),
1035
+
FUNCTION(edp_lcd),
1036
+
FUNCTION(gcc_gp1),
1037
+
FUNCTION(gcc_gp2),
1038
+
FUNCTION(gcc_gp3),
1039
+
FUNCTION(gp_pdm0),
1040
+
FUNCTION(gp_pdm1),
1041
+
FUNCTION(gp_pdm2),
1042
+
FUNCTION(gps_tx),
1043
+
FUNCTION(jitter_bist),
1044
+
FUNCTION(ldo_en),
1045
+
FUNCTION(ldo_update),
1046
+
FUNCTION(lpass_slimbus),
1047
+
FUNCTION(m_voc),
1048
+
FUNCTION(mdp_vsync),
1049
+
FUNCTION(mdp_vsync0),
1050
+
FUNCTION(mdp_vsync1),
1051
+
FUNCTION(mdp_vsync2),
1052
+
FUNCTION(mdp_vsync3),
1053
+
FUNCTION(mss_lte),
1054
+
FUNCTION(nav_pps),
1055
+
FUNCTION(pa_indicator),
1056
+
FUNCTION(pci_e0),
1057
+
FUNCTION(pci_e1),
1058
+
FUNCTION(phase_flag),
1059
+
FUNCTION(pll_bist),
1060
+
FUNCTION(pll_bypassnl),
1061
+
FUNCTION(pll_reset),
1062
+
FUNCTION(pri_mi2s),
1063
+
FUNCTION(pri_mi2s_ws),
1064
+
FUNCTION(prng_rosc),
1065
+
FUNCTION(qdss_cti),
1066
+
FUNCTION(qdss),
1067
+
FUNCTION(qlink_enable),
1068
+
FUNCTION(qlink_request),
1069
+
FUNCTION(qua_mi2s),
1070
+
FUNCTION(qup0),
1071
+
FUNCTION(qup1),
1072
+
FUNCTION(qup10),
1073
+
FUNCTION(qup11),
1074
+
FUNCTION(qup12),
1075
+
FUNCTION(qup13),
1076
+
FUNCTION(qup14),
1077
+
FUNCTION(qup15),
1078
+
FUNCTION(qup2),
1079
+
FUNCTION(qup3),
1080
+
FUNCTION(qup4),
1081
+
FUNCTION(qup5),
1082
+
FUNCTION(qup6),
1083
+
FUNCTION(qup7),
1084
+
FUNCTION(qup8),
1085
+
FUNCTION(qup9),
1086
+
FUNCTION(qup_l4),
1087
+
FUNCTION(qup_l5),
1088
+
FUNCTION(qup_l6),
1089
+
FUNCTION(sdc4_clk),
1090
+
FUNCTION(sdc4_cmd),
1091
+
FUNCTION(sdc4_data),
1092
+
FUNCTION(sd_write),
1093
+
FUNCTION(sec_mi2s),
1094
+
FUNCTION(ter_mi2s),
1095
+
FUNCTION(tgu_ch0),
1096
+
FUNCTION(tgu_ch1),
1097
+
FUNCTION(tgu_ch2),
1098
+
FUNCTION(tgu_ch3),
1099
+
FUNCTION(tsif1_clk),
1100
+
FUNCTION(tsif1_data),
1101
+
FUNCTION(tsif1_en),
1102
+
FUNCTION(tsif1_error),
1103
+
FUNCTION(tsif1_sync),
1104
+
FUNCTION(tsif2_clk),
1105
+
FUNCTION(tsif2_data),
1106
+
FUNCTION(tsif2_en),
1107
+
FUNCTION(tsif2_error),
1108
+
FUNCTION(tsif2_sync),
1109
+
FUNCTION(uim1_clk),
1110
+
FUNCTION(uim1_data),
1111
+
FUNCTION(uim1_present),
1112
+
FUNCTION(uim1_reset),
1113
+
FUNCTION(uim2_clk),
1114
+
FUNCTION(uim2_data),
1115
+
FUNCTION(uim2_present),
1116
+
FUNCTION(uim2_reset),
1117
+
FUNCTION(uim_batt),
1118
+
FUNCTION(usb_phy),
1119
+
FUNCTION(vfr_1),
1120
+
FUNCTION(vsense_trigger),
1121
+
FUNCTION(wlan1_adc0),
1122
+
FUNCTION(wlan1_adc1),
1123
+
FUNCTION(wlan2_adc0),
1124
+
FUNCTION(wlan2_adc1),
1125
+
FUNCTION(wsa_clk),
1126
+
FUNCTION(wsa_data),
1127
+
};
1128
+
1129
+
/*
1130
+
* Each pin is individually controlled by its own group and gpios that cannot
1131
+
* be requested are represented by the PINGROUP_DUMMY macro so that the group
1132
+
* numbers and names correspond to their respective gpio. These dummy pins do
1133
+
* not have a valid set of pinfuncs or a valid ctl_reg and should not be
1134
+
* requested.
1135
+
*/
1136
+
static const struct msm_pingroup sdm670_groups[] = {
1137
+
PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
1138
+
PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
1139
+
PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
1140
+
PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
1141
+
PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),
1142
+
PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),
1143
+
PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _),
1144
+
PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _),
1145
+
PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _),
1146
+
PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _),
1147
+
PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _),
1148
+
PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _),
1149
+
PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _),
1150
+
PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _),
1151
+
PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
1152
+
PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _),
1153
+
PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _),
1154
+
PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _),
1155
+
PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1156
+
PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1157
+
PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),
1158
+
PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
1159
+
PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
1160
+
PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _),
1161
+
PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _),
1162
+
PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _),
1163
+
PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _),
1164
+
PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _),
1165
+
PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _),
1166
+
PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _),
1167
+
PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _),
1168
+
PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _),
1169
+
PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _),
1170
+
PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _),
1171
+
PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _),
1172
+
PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _),
1173
+
PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _),
1174
+
PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _),
1175
+
PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _),
1176
+
PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _),
1177
+
PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _),
1178
+
PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1179
+
PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1180
+
PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1181
+
PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _),
1182
+
PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _),
1183
+
PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _),
1184
+
PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _),
1185
+
PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _),
1186
+
PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _),
1187
+
PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _),
1188
+
PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
1189
+
PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _),
1190
+
PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _),
1191
+
PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1192
+
PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _),
1193
+
PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _),
1194
+
PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _),
1195
+
PINGROUP_DUMMY(58),
1196
+
PINGROUP_DUMMY(59),
1197
+
PINGROUP_DUMMY(60),
1198
+
PINGROUP_DUMMY(61),
1199
+
PINGROUP_DUMMY(62),
1200
+
PINGROUP_DUMMY(63),
1201
+
PINGROUP_DUMMY(64),
1202
+
PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _),
1203
+
PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _),
1204
+
PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _),
1205
+
PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _),
1206
+
PINGROUP_DUMMY(69),
1207
+
PINGROUP_DUMMY(70),
1208
+
PINGROUP_DUMMY(71),
1209
+
PINGROUP_DUMMY(72),
1210
+
PINGROUP_DUMMY(73),
1211
+
PINGROUP_DUMMY(74),
1212
+
PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _),
1213
+
PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _),
1214
+
PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _),
1215
+
PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1216
+
PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _),
1217
+
PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _),
1218
+
PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1219
+
PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1220
+
PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),
1221
+
PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _),
1222
+
PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _),
1223
+
PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _),
1224
+
PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _),
1225
+
PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _),
1226
+
PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _),
1227
+
PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1228
+
PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _),
1229
+
PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _),
1230
+
PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _),
1231
+
PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _),
1232
+
PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _),
1233
+
PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _),
1234
+
PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _),
1235
+
PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _),
1236
+
PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _),
1237
+
PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _),
1238
+
PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _),
1239
+
PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _),
1240
+
PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _),
1241
+
PINGROUP_DUMMY(104),
1242
+
PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _),
1243
+
PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _),
1244
+
PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _),
1245
+
PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _),
1246
+
PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
1247
+
PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
1248
+
PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
1249
+
PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
1250
+
PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _),
1251
+
PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1252
+
PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),
1253
+
PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _),
1254
+
PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1255
+
PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _),
1256
+
PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1257
+
PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1258
+
PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _),
1259
+
PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _),
1260
+
PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _),
1261
+
PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _),
1262
+
PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _),
1263
+
PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _),
1264
+
PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
1265
+
PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),
1266
+
PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),
1267
+
PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _),
1268
+
PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _),
1269
+
PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _),
1270
+
PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _),
1271
+
PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _),
1272
+
PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
1273
+
PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
1274
+
PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _),
1275
+
PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _),
1276
+
PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _),
1277
+
PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _),
1278
+
PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _),
1279
+
PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _),
1280
+
PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _),
1281
+
PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
1282
+
PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _),
1283
+
PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1284
+
PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1285
+
PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1286
+
PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1287
+
UFS_RESET(ufs_reset, 0x99d000),
1288
+
SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0),
1289
+
SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6),
1290
+
SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3),
1291
+
SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0),
1292
+
SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6),
1293
+
SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3),
1294
+
SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0),
1295
+
};
1296
+
1297
+
static const int sdm670_reserved_gpios[] = {
1298
+
58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1
1299
+
};
1300
+
1301
+
static const struct msm_pinctrl_soc_data sdm670_pinctrl = {
1302
+
.pins = sdm670_pins,
1303
+
.npins = ARRAY_SIZE(sdm670_pins),
1304
+
.functions = sdm670_functions,
1305
+
.nfunctions = ARRAY_SIZE(sdm670_functions),
1306
+
.groups = sdm670_groups,
1307
+
.ngroups = ARRAY_SIZE(sdm670_groups),
1308
+
.ngpios = 151,
1309
+
.reserved_gpios = sdm670_reserved_gpios,
1310
+
};
1311
+
1312
+
static int sdm670_pinctrl_probe(struct platform_device *pdev)
1313
+
{
1314
+
return msm_pinctrl_probe(pdev, &sdm670_pinctrl);
1315
+
}
1316
+
1317
+
static const struct of_device_id sdm670_pinctrl_of_match[] = {
1318
+
{ .compatible = "qcom,sdm670-tlmm", },
1319
+
{ },
1320
+
};
1321
+
MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match);
1322
+
1323
+
static struct platform_driver sdm670_pinctrl_driver = {
1324
+
.driver = {
1325
+
.name = "sdm670-pinctrl",
1326
+
.of_match_table = sdm670_pinctrl_of_match,
1327
+
},
1328
+
.probe = sdm670_pinctrl_probe,
1329
+
.remove = msm_pinctrl_remove,
1330
+
};
1331
+
1332
+
static int __init sdm670_pinctrl_init(void)
1333
+
{
1334
+
return platform_driver_register(&sdm670_pinctrl_driver);
1335
+
}
1336
+
arch_initcall(sdm670_pinctrl_init);
1337
+
1338
+
static void __exit sdm670_pinctrl_exit(void)
1339
+
{
1340
+
platform_driver_unregister(&sdm670_pinctrl_driver);
1341
+
}
1342
+
module_exit(sdm670_pinctrl_exit);
1343
+
1344
+
MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver");
1345
+
MODULE_LICENSE("GPL");
+5
-3
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+5
-3
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
···
9
9
#include <linux/module.h>
10
10
#include <linux/of.h>
11
11
#include <linux/of_irq.h>
12
-
#include <linux/pinctrl/pinconf-generic.h>
13
-
#include <linux/pinctrl/pinconf.h>
14
-
#include <linux/pinctrl/pinmux.h>
15
12
#include <linux/platform_device.h>
16
13
#include <linux/regmap.h>
14
+
#include <linux/seq_file.h>
17
15
#include <linux/slab.h>
18
16
#include <linux/spmi.h>
19
17
#include <linux/types.h>
18
+
19
+
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/pinctrl/pinconf.h>
21
+
#include <linux/pinctrl/pinmux.h>
20
22
21
23
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
22
24
+6
-4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+6
-4
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
···
7
7
#include <linux/module.h>
8
8
#include <linux/of.h>
9
9
#include <linux/of_irq.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/regmap.h>
12
+
#include <linux/seq_file.h>
13
+
#include <linux/slab.h>
14
+
#include <linux/types.h>
15
+
10
16
#include <linux/pinctrl/pinconf-generic.h>
11
17
#include <linux/pinctrl/pinconf.h>
12
18
#include <linux/pinctrl/pinmux.h>
13
-
#include <linux/platform_device.h>
14
-
#include <linux/regmap.h>
15
-
#include <linux/slab.h>
16
-
#include <linux/types.h>
17
19
18
20
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
19
21
+10
-9
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+10
-9
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
···
4
4
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
5
5
*/
6
6
7
-
#include <linux/module.h>
8
-
#include <linux/platform_device.h>
9
-
#include <linux/pinctrl/pinctrl.h>
10
-
#include <linux/pinctrl/pinmux.h>
11
-
#include <linux/pinctrl/pinconf.h>
12
-
#include <linux/pinctrl/pinconf-generic.h>
13
-
#include <linux/slab.h>
14
-
#include <linux/regmap.h>
15
7
#include <linux/gpio/driver.h>
16
8
#include <linux/interrupt.h>
9
+
#include <linux/module.h>
17
10
#include <linux/of_device.h>
18
11
#include <linux/of_irq.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/seq_file.h>
15
+
#include <linux/slab.h>
16
+
17
+
#include <linux/pinctrl/pinconf-generic.h>
18
+
#include <linux/pinctrl/pinconf.h>
19
+
#include <linux/pinctrl/pinctrl.h>
20
+
#include <linux/pinctrl/pinmux.h>
19
21
20
22
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
21
23
···
536
534
537
535
538
536
#ifdef CONFIG_DEBUG_FS
539
-
#include <linux/seq_file.h>
540
537
541
538
static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
542
539
struct pinctrl_dev *pctldev,
+10
-9
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+10
-9
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
···
4
4
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
5
5
*/
6
6
7
-
#include <linux/module.h>
8
-
#include <linux/platform_device.h>
9
-
#include <linux/pinctrl/pinctrl.h>
10
-
#include <linux/pinctrl/pinmux.h>
11
-
#include <linux/pinctrl/pinconf.h>
12
-
#include <linux/pinctrl/pinconf-generic.h>
13
-
#include <linux/slab.h>
14
-
#include <linux/regmap.h>
15
7
#include <linux/gpio/driver.h>
16
8
#include <linux/interrupt.h>
9
+
#include <linux/module.h>
17
10
#include <linux/of_device.h>
18
11
#include <linux/of_irq.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/seq_file.h>
15
+
#include <linux/slab.h>
16
+
17
+
#include <linux/pinctrl/pinconf-generic.h>
18
+
#include <linux/pinctrl/pinconf.h>
19
+
#include <linux/pinctrl/pinctrl.h>
20
+
#include <linux/pinctrl/pinmux.h>
19
21
20
22
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
21
23
···
536
534
537
535
538
536
#ifdef CONFIG_DEBUG_FS
539
-
#include <linux/seq_file.h>
540
537
541
538
static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
542
539
struct pinctrl_dev *pctldev,
+5
-5
drivers/pinctrl/renesas/gpio.c
+5
-5
drivers/pinctrl/renesas/gpio.c
···
135
135
if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
136
136
return -EINVAL;
137
137
138
-
return pinctrl_gpio_request(offset);
138
+
return pinctrl_gpio_request(gc->base + offset);
139
139
}
140
140
141
141
static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
142
142
{
143
-
return pinctrl_gpio_free(offset);
143
+
return pinctrl_gpio_free(gc->base + offset);
144
144
}
145
145
146
146
static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
···
164
164
165
165
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
166
166
{
167
-
return pinctrl_gpio_direction_input(offset);
167
+
return pinctrl_gpio_direction_input(gc->base + offset);
168
168
}
169
169
170
170
static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
···
172
172
{
173
173
gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
174
174
175
-
return pinctrl_gpio_direction_output(offset);
175
+
return pinctrl_gpio_direction_output(gc->base + offset);
176
176
}
177
177
178
178
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
···
238
238
gc->label = pfc->info->name;
239
239
gc->parent = pfc->dev;
240
240
gc->owner = THIS_MODULE;
241
-
gc->base = 0;
241
+
gc->base = IS_ENABLED(CONFIG_PINCTRL_SH_FUNC_GPIO) ? 0 : -1;
242
242
gc->ngpio = pfc->nr_gpio_pins;
243
243
244
244
return 0;
+6
-4
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+6
-4
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
8
8
#include <linux/bitops.h>
9
9
#include <linux/clk.h>
10
10
#include <linux/gpio/driver.h>
11
-
#include <linux/io.h>
12
11
#include <linux/interrupt.h>
12
+
#include <linux/io.h>
13
13
#include <linux/module.h>
14
14
#include <linux/of_device.h>
15
15
#include <linux/of_irq.h>
16
+
#include <linux/seq_file.h>
17
+
#include <linux/spinlock.h>
18
+
19
+
#include <linux/pinctrl/consumer.h>
16
20
#include <linux/pinctrl/pinconf-generic.h>
17
21
#include <linux/pinctrl/pinconf.h>
18
22
#include <linux/pinctrl/pinctrl.h>
19
23
#include <linux/pinctrl/pinmux.h>
20
-
#include <linux/spinlock.h>
21
24
22
25
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
23
26
···
438
435
ret = -EINVAL;
439
436
440
437
done:
441
-
if (ret < 0)
442
-
rzg2l_dt_free_map(pctldev, *map, *num_maps);
438
+
rzg2l_dt_free_map(pctldev, *map, *num_maps);
443
439
444
440
return ret;
445
441
}
+7
-3
drivers/pinctrl/renesas/pinctrl-rzn1.c
+7
-3
drivers/pinctrl/renesas/pinctrl-rzn1.c
···
7
7
*/
8
8
9
9
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
10
+
10
11
#include <linux/clk.h>
11
12
#include <linux/device.h>
12
13
#include <linux/io.h>
13
14
#include <linux/module.h>
14
15
#include <linux/of.h>
15
-
#include <linux/pinctrl/pinconf-generic.h>
16
-
#include <linux/pinctrl/pinctrl.h>
17
-
#include <linux/pinctrl/pinmux.h>
18
16
#include <linux/platform_device.h>
19
17
#include <linux/slab.h>
18
+
19
+
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/pinctrl/pinconf.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
#include <linux/pinctrl/pinmux.h>
23
+
20
24
#include "../core.h"
21
25
#include "../pinconf.h"
22
26
#include "../pinctrl-utils.h"
+4
-3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
+4
-3
drivers/pinctrl/renesas/pinctrl-rzv2m.c
···
15
15
#include <linux/io.h>
16
16
#include <linux/module.h>
17
17
#include <linux/of_device.h>
18
+
#include <linux/spinlock.h>
19
+
20
+
#include <linux/pinctrl/consumer.h>
18
21
#include <linux/pinctrl/pinconf-generic.h>
19
22
#include <linux/pinctrl/pinconf.h>
20
23
#include <linux/pinctrl/pinctrl.h>
21
24
#include <linux/pinctrl/pinmux.h>
22
-
#include <linux/spinlock.h>
23
25
24
26
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
25
27
···
399
397
ret = -EINVAL;
400
398
401
399
done:
402
-
if (ret < 0)
403
-
rzv2m_dt_free_map(pctldev, *map, *num_maps);
400
+
rzv2m_dt_free_map(pctldev, *map, *num_maps);
404
401
405
402
return ret;
406
403
}
+8
-6
drivers/pinctrl/renesas/pinctrl.c
+8
-6
drivers/pinctrl/renesas/pinctrl.c
···
12
12
#include <linux/io.h>
13
13
#include <linux/module.h>
14
14
#include <linux/of.h>
15
-
#include <linux/pinctrl/consumer.h>
16
-
#include <linux/pinctrl/machine.h>
17
-
#include <linux/pinctrl/pinconf.h>
18
-
#include <linux/pinctrl/pinconf-generic.h>
19
-
#include <linux/pinctrl/pinctrl.h>
20
-
#include <linux/pinctrl/pinmux.h>
15
+
#include <linux/seq_file.h>
21
16
#include <linux/slab.h>
22
17
#include <linux/spinlock.h>
18
+
19
+
#include <linux/pinctrl/consumer.h>
20
+
#include <linux/pinctrl/machine.h>
21
+
#include <linux/pinctrl/pinconf-generic.h>
22
+
#include <linux/pinctrl/pinconf.h>
23
+
#include <linux/pinctrl/pinctrl.h>
24
+
#include <linux/pinctrl/pinmux.h>
23
25
24
26
#include "core.h"
25
27
#include "../core.h"
+6
-5
drivers/pinctrl/samsung/pinctrl-samsung.c
+6
-5
drivers/pinctrl/samsung/pinctrl-samsung.c
···
15
15
// but provides extensions to which platform specific implementation of the gpio
16
16
// and wakeup interrupts can be hooked to.
17
17
18
-
#include <linux/init.h>
19
-
#include <linux/platform_device.h>
20
-
#include <linux/io.h>
21
-
#include <linux/property.h>
22
-
#include <linux/slab.h>
23
18
#include <linux/err.h>
24
19
#include <linux/gpio/driver.h>
20
+
#include <linux/init.h>
21
+
#include <linux/io.h>
25
22
#include <linux/irqdomain.h>
26
23
#include <linux/of_device.h>
24
+
#include <linux/platform_device.h>
25
+
#include <linux/property.h>
26
+
#include <linux/seq_file.h>
27
+
#include <linux/slab.h>
27
28
#include <linux/spinlock.h>
28
29
29
30
#include "../core.h"
+4
-2
drivers/pinctrl/spear/pinctrl-spear.c
+4
-2
drivers/pinctrl/spear/pinctrl-spear.c
···
19
19
#include <linux/of.h>
20
20
#include <linux/of_address.h>
21
21
#include <linux/of_gpio.h>
22
+
#include <linux/platform_device.h>
23
+
#include <linux/seq_file.h>
24
+
#include <linux/slab.h>
25
+
22
26
#include <linux/pinctrl/machine.h>
23
27
#include <linux/pinctrl/pinctrl.h>
24
28
#include <linux/pinctrl/pinmux.h>
25
-
#include <linux/platform_device.h>
26
-
#include <linux/slab.h>
27
29
28
30
#include "pinctrl-spear.h"
29
31
+5
-2
drivers/pinctrl/sprd/pinctrl-sprd.c
+5
-2
drivers/pinctrl/sprd/pinctrl-sprd.c
···
13
13
#include <linux/of.h>
14
14
#include <linux/of_device.h>
15
15
#include <linux/platform_device.h>
16
+
#include <linux/seq_file.h>
17
+
#include <linux/slab.h>
18
+
19
+
#include <linux/pinctrl/consumer.h>
16
20
#include <linux/pinctrl/machine.h>
17
-
#include <linux/pinctrl/pinconf.h>
18
21
#include <linux/pinctrl/pinconf-generic.h>
22
+
#include <linux/pinctrl/pinconf.h>
19
23
#include <linux/pinctrl/pinctrl.h>
20
24
#include <linux/pinctrl/pinmux.h>
21
-
#include <linux/slab.h>
22
25
23
26
#include "../core.h"
24
27
#include "../pinmux.h"
+5
-2
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+5
-2
drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
···
15
15
#include <linux/of.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/reset.h>
18
+
#include <linux/seq_file.h>
18
19
#include <linux/spinlock.h>
19
20
21
+
#include <linux/pinctrl/consumer.h>
22
+
#include <linux/pinctrl/pinconf.h>
20
23
#include <linux/pinctrl/pinctrl.h>
21
24
#include <linux/pinctrl/pinmux.h>
22
25
···
1082
1079
writel_relaxed(value, ie);
1083
1080
raw_spin_unlock_irqrestore(&sfp->lock, flags);
1084
1081
1085
-
gpiochip_disable_irq(&sfp->gc, d->hwirq);
1082
+
gpiochip_disable_irq(&sfp->gc, gpio);
1086
1083
}
1087
1084
1088
1085
static void starfive_irq_mask_ack(struct irq_data *d)
···
1111
1108
unsigned long flags;
1112
1109
u32 value;
1113
1110
1114
-
gpiochip_enable_irq(&sfp->gc, d->hwirq);
1111
+
gpiochip_enable_irq(&sfp->gc, gpio);
1115
1112
1116
1113
raw_spin_lock_irqsave(&sfp->lock, flags);
1117
1114
value = readl_relaxed(ie) | mask;
+9
-12
drivers/pinctrl/stm32/pinctrl-stm32.c
+9
-12
drivers/pinctrl/stm32/pinctrl-stm32.c
···
13
13
#include <linux/irq.h>
14
14
#include <linux/mfd/syscon.h>
15
15
#include <linux/module.h>
16
-
#include <linux/of.h>
17
16
#include <linux/of_address.h>
18
17
#include <linux/of_device.h>
18
+
#include <linux/of.h>
19
19
#include <linux/of_irq.h>
20
-
#include <linux/pinctrl/consumer.h>
21
-
#include <linux/pinctrl/machine.h>
22
-
#include <linux/pinctrl/pinconf.h>
23
-
#include <linux/pinctrl/pinconf-generic.h>
24
-
#include <linux/pinctrl/pinctrl.h>
25
-
#include <linux/pinctrl/pinmux.h>
26
20
#include <linux/platform_device.h>
27
21
#include <linux/property.h>
28
22
#include <linux/regmap.h>
29
23
#include <linux/reset.h>
24
+
#include <linux/seq_file.h>
30
25
#include <linux/slab.h>
26
+
27
+
#include <linux/pinctrl/consumer.h>
28
+
#include <linux/pinctrl/machine.h>
29
+
#include <linux/pinctrl/pinconf-generic.h>
30
+
#include <linux/pinctrl/pinconf.h>
31
+
#include <linux/pinctrl/pinctrl.h>
32
+
#include <linux/pinctrl/pinmux.h>
31
33
32
34
#include "../core.h"
33
35
#include "../pinconf.h"
···
1498
1496
match_data = device_get_match_data(dev);
1499
1497
if (!match_data)
1500
1498
return -EINVAL;
1501
-
1502
-
if (!device_property_present(dev, "pins-are-numbered")) {
1503
-
dev_err(dev, "only support pins-are-numbered format\n");
1504
-
return -EINVAL;
1505
-
}
1506
1499
1507
1500
pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1508
1501
if (!pctl)
+4
drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
+4
drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c
···
47
47
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN2 */
48
48
SUNXI_FUNCTION(0x6, "lcd0"), /* D18 */
49
49
SUNXI_FUNCTION(0x7, "uart4"), /* TX */
50
+
SUNXI_FUNCTION(0x8, "can0"), /* TX */
50
51
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 2)),
51
52
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
52
53
SUNXI_FUNCTION(0x0, "gpio_in"),
···
58
57
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN0 */
59
58
SUNXI_FUNCTION(0x6, "lcd0"), /* D19 */
60
59
SUNXI_FUNCTION(0x7, "uart4"), /* RX */
60
+
SUNXI_FUNCTION(0x8, "can0"), /* RX */
61
61
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)),
62
62
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
63
63
SUNXI_FUNCTION(0x0, "gpio_in"),
···
69
67
SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN1 */
70
68
SUNXI_FUNCTION(0x6, "lcd0"), /* D20 */
71
69
SUNXI_FUNCTION(0x7, "uart5"), /* TX */
70
+
SUNXI_FUNCTION(0x8, "can1"), /* TX */
72
71
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 4)),
73
72
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
74
73
SUNXI_FUNCTION(0x0, "gpio_in"),
···
80
77
SUNXI_FUNCTION(0x5, "pwm0"),
81
78
SUNXI_FUNCTION(0x6, "lcd0"), /* D21 */
82
79
SUNXI_FUNCTION(0x7, "uart5"), /* RX */
80
+
SUNXI_FUNCTION(0x8, "can1"), /* RX */
83
81
SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 5)),
84
82
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
85
83
SUNXI_FUNCTION(0x0, "gpio_in"),
+10
-8
drivers/pinctrl/sunxi/pinctrl-sunxi.c
+10
-8
drivers/pinctrl/sunxi/pinctrl-sunxi.c
···
10
10
* warranty of any kind, whether express or implied.
11
11
*/
12
12
13
-
#include <linux/io.h>
14
13
#include <linux/clk.h>
14
+
#include <linux/export.h>
15
15
#include <linux/gpio/driver.h>
16
16
#include <linux/interrupt.h>
17
-
#include <linux/irqdomain.h>
17
+
#include <linux/io.h>
18
18
#include <linux/irqchip/chained_irq.h>
19
-
#include <linux/export.h>
19
+
#include <linux/irqdomain.h>
20
20
#include <linux/of.h>
21
-
#include <linux/of_clk.h>
22
21
#include <linux/of_address.h>
22
+
#include <linux/of_clk.h>
23
23
#include <linux/of_device.h>
24
24
#include <linux/of_irq.h>
25
+
#include <linux/platform_device.h>
26
+
#include <linux/regulator/consumer.h>
27
+
#include <linux/slab.h>
28
+
25
29
#include <linux/pinctrl/consumer.h>
26
30
#include <linux/pinctrl/machine.h>
27
-
#include <linux/pinctrl/pinctrl.h>
28
31
#include <linux/pinctrl/pinconf-generic.h>
32
+
#include <linux/pinctrl/pinconf.h>
33
+
#include <linux/pinctrl/pinctrl.h>
29
34
#include <linux/pinctrl/pinmux.h>
30
-
#include <linux/regulator/consumer.h>
31
-
#include <linux/platform_device.h>
32
-
#include <linux/slab.h>
33
35
34
36
#include <dt-bindings/pinctrl/sun4i-a10.h>
35
37
+5
-2
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
+5
-2
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
···
8
8
#include <linux/module.h>
9
9
#include <linux/of.h>
10
10
#include <linux/phy/phy.h>
11
-
#include <linux/pinctrl/pinctrl.h>
12
-
#include <linux/pinctrl/pinmux.h>
13
11
#include <linux/platform_device.h>
14
12
#include <linux/reset.h>
13
+
#include <linux/seq_file.h>
15
14
#include <linux/slab.h>
15
+
16
+
#include <linux/pinctrl/pinconf.h>
17
+
#include <linux/pinctrl/pinctrl.h>
18
+
#include <linux/pinctrl/pinmux.h>
16
19
17
20
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
18
21
+18
-21
drivers/pinctrl/tegra/pinctrl-tegra.c
+18
-21
drivers/pinctrl/tegra/pinctrl-tegra.c
···
15
15
#include <linux/io.h>
16
16
#include <linux/of.h>
17
17
#include <linux/platform_device.h>
18
+
#include <linux/seq_file.h>
19
+
#include <linux/slab.h>
20
+
18
21
#include <linux/pinctrl/machine.h>
22
+
#include <linux/pinctrl/pinconf.h>
19
23
#include <linux/pinctrl/pinctrl.h>
20
24
#include <linux/pinctrl/pinmux.h>
21
-
#include <linux/pinctrl/pinconf.h>
22
-
#include <linux/slab.h>
23
25
24
26
#include "../core.h"
25
27
#include "../pinctrl-utils.h"
···
670
668
#endif
671
669
};
672
670
673
-
static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
674
-
.name = "Tegra GPIOs",
675
-
.id = 0,
676
-
.base = 0,
677
-
};
678
-
679
-
static struct pinctrl_desc tegra_pinctrl_desc = {
680
-
.pctlops = &tegra_pinctrl_ops,
681
-
.pmxops = &tegra_pinmux_ops,
682
-
.confops = &tegra_pinconf_ops,
683
-
.owner = THIS_MODULE,
684
-
};
685
-
686
671
static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
687
672
{
688
673
int i = 0;
···
820
831
}
821
832
}
822
833
823
-
tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
824
-
tegra_pinctrl_desc.name = dev_name(&pdev->dev);
825
-
tegra_pinctrl_desc.pins = pmx->soc->pins;
826
-
tegra_pinctrl_desc.npins = pmx->soc->npins;
834
+
pmx->gpio_range.name = "Tegra GPIOs";
835
+
pmx->gpio_range.id = 0;
836
+
pmx->gpio_range.base = 0;
837
+
pmx->gpio_range.npins = pmx->soc->ngpios;
838
+
839
+
pmx->desc.pctlops = &tegra_pinctrl_ops;
840
+
pmx->desc.pmxops = &tegra_pinmux_ops;
841
+
pmx->desc.confops = &tegra_pinconf_ops;
842
+
pmx->desc.owner = THIS_MODULE;
843
+
pmx->desc.name = dev_name(&pdev->dev);
844
+
pmx->desc.pins = pmx->soc->pins;
845
+
pmx->desc.npins = pmx->soc->npins;
827
846
828
847
for (i = 0; ; i++) {
829
848
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
···
857
860
return PTR_ERR(pmx->regs[i]);
858
861
}
859
862
860
-
pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
863
+
pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
861
864
if (IS_ERR(pmx->pctl)) {
862
865
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
863
866
return PTR_ERR(pmx->pctl);
···
866
869
tegra_pinctrl_clear_parked_bits(pmx);
867
870
868
871
if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
869
-
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
872
+
pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
870
873
871
874
platform_set_drvdata(pdev, pmx);
872
875
+2
drivers/pinctrl/tegra/pinctrl-tegra.h
+2
drivers/pinctrl/tegra/pinctrl-tegra.h
+157
-129
drivers/pinctrl/tegra/pinctrl-tegra194.c
+157
-129
drivers/pinctrl/tegra/pinctrl-tegra194.c
···
16
16
17
17
#include <linux/init.h>
18
18
#include <linux/of.h>
19
+
#include <linux/of_device.h>
19
20
#include <linux/platform_device.h>
20
21
#include <linux/pinctrl/pinctrl.h>
21
22
#include <linux/pinctrl/pinmux.h>
···
24
23
#include "pinctrl-tegra.h"
25
24
26
25
/* Define unique ID for each pins */
27
-
enum pin_id {
26
+
enum {
28
27
TEGRA_PIN_DAP6_SCLK_PA0,
29
28
TEGRA_PIN_DAP6_DOUT_PA1,
30
29
TEGRA_PIN_DAP6_DIN_PA2,
···
190
189
TEGRA_PIN_SPI1_MOSI_PZ5,
191
190
TEGRA_PIN_SPI1_CS0_PZ6,
192
191
TEGRA_PIN_SPI1_CS1_PZ7,
192
+
TEGRA_PIN_UFS0_REF_CLK_PFF0,
193
+
TEGRA_PIN_UFS0_RST_PFF1,
194
+
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
195
+
TEGRA_PIN_PEX_L5_RST_N_PGG1,
196
+
TEGRA_PIN_DIRECTDC_COMP,
197
+
TEGRA_PIN_SDMMC4_CLK,
198
+
TEGRA_PIN_SDMMC4_CMD,
199
+
TEGRA_PIN_SDMMC4_DQS,
200
+
TEGRA_PIN_SDMMC4_DAT7,
201
+
TEGRA_PIN_SDMMC4_DAT6,
202
+
TEGRA_PIN_SDMMC4_DAT5,
203
+
TEGRA_PIN_SDMMC4_DAT4,
204
+
TEGRA_PIN_SDMMC4_DAT3,
205
+
TEGRA_PIN_SDMMC4_DAT2,
206
+
TEGRA_PIN_SDMMC4_DAT1,
207
+
TEGRA_PIN_SDMMC4_DAT0,
208
+
TEGRA_PIN_SDMMC1_COMP,
209
+
TEGRA_PIN_SDMMC1_HV_TRIM,
210
+
TEGRA_PIN_SDMMC3_COMP,
211
+
TEGRA_PIN_SDMMC3_HV_TRIM,
212
+
TEGRA_PIN_EQOS_COMP,
213
+
TEGRA_PIN_QSPI_COMP,
214
+
};
215
+
216
+
enum {
193
217
TEGRA_PIN_CAN1_DOUT_PAA0,
194
218
TEGRA_PIN_CAN1_DIN_PAA1,
195
219
TEGRA_PIN_CAN0_DOUT_PAA2,
···
245
219
TEGRA_PIN_POWER_ON_PEE4,
246
220
TEGRA_PIN_PWR_I2C_SCL_PEE5,
247
221
TEGRA_PIN_PWR_I2C_SDA_PEE6,
248
-
TEGRA_PIN_UFS0_REF_CLK_PFF0,
249
-
TEGRA_PIN_UFS0_RST_PFF1,
250
-
TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
251
-
TEGRA_PIN_PEX_L5_RST_N_PGG1,
252
-
TEGRA_PIN_DIRECTDC_COMP,
253
-
TEGRA_PIN_SDMMC4_CLK,
254
-
TEGRA_PIN_SDMMC4_CMD,
255
-
TEGRA_PIN_SDMMC4_DQS,
256
-
TEGRA_PIN_SDMMC4_DAT7,
257
-
TEGRA_PIN_SDMMC4_DAT6,
258
-
TEGRA_PIN_SDMMC4_DAT5,
259
-
TEGRA_PIN_SDMMC4_DAT4,
260
-
TEGRA_PIN_SDMMC4_DAT3,
261
-
TEGRA_PIN_SDMMC4_DAT2,
262
-
TEGRA_PIN_SDMMC4_DAT1,
263
-
TEGRA_PIN_SDMMC4_DAT0,
264
-
TEGRA_PIN_SDMMC1_COMP,
265
-
TEGRA_PIN_SDMMC1_HV_TRIM,
266
-
TEGRA_PIN_SDMMC3_COMP,
267
-
TEGRA_PIN_SDMMC3_HV_TRIM,
268
-
TEGRA_PIN_EQOS_COMP,
269
-
TEGRA_PIN_QSPI_COMP,
270
222
TEGRA_PIN_SYS_RESET_N,
271
223
TEGRA_PIN_SHUTDOWN_N,
272
224
TEGRA_PIN_PMU_INT_N,
···
419
415
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),
420
416
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),
421
417
PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),
422
-
PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
423
-
PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
424
-
PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
425
-
PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
426
-
PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
427
-
PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
428
-
PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
429
-
PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
430
-
PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
431
-
PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
432
-
PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
433
-
PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
434
-
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
435
-
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
436
-
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
437
-
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
438
-
PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
439
-
PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
440
-
PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
441
-
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
442
-
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
443
-
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
444
-
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
445
-
PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
446
-
PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
447
-
PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
448
-
PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
449
-
PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
450
-
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
451
-
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
452
418
PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"),
453
419
PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"),
454
420
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
···
441
467
PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"),
442
468
PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
443
469
PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
444
-
PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
445
-
PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
446
-
PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
447
-
PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
448
-
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
449
470
};
450
471
451
472
static const unsigned int dap6_sclk_pa0_pins[] = {
···
1348
1379
.drvtype_bit = 13, \
1349
1380
.lpdr_bit = e_lpdr, \
1350
1381
1351
-
#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1352
-
#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1353
-
#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1354
-
#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1355
-
#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1356
-
#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1357
-
#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1358
-
#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1359
-
#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1360
-
#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1361
-
#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1362
-
#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1363
-
#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1364
-
#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1365
-
#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1366
-
#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1367
-
#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1368
-
#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1369
-
#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1370
-
#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1371
-
#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1372
-
#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1373
-
#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
1382
+
/* main drive pin groups */
1374
1383
#define drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1375
1384
#define drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1376
1385
#define drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
···
1456
1509
#define drive_sdmmc3_dat0_po2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1457
1510
#define drive_sdmmc3_cmd_po1 DRV_PINGROUP_ENTRY_Y(0xa02c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1458
1511
#define drive_sdmmc3_clk_po0 DRV_PINGROUP_ENTRY_Y(0xa034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1459
-
#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1460
-
#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1461
-
#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1462
-
#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1463
-
#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1464
-
#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1465
-
#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1466
-
#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1467
-
#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1468
-
#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1469
-
#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1470
1512
#define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xD004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1471
1513
#define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xD00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1472
1514
#define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xD014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
···
1536
1600
#define drive_directdc1_in_pv1 DRV_PINGROUP_ENTRY_N(no_entry)
1537
1601
#define drive_directdc1_clk_pv0 DRV_PINGROUP_ENTRY_N(no_entry)
1538
1602
1603
+
/* AON drive pin groups */
1604
+
#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1605
+
#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1606
+
#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1607
+
#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1608
+
#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1609
+
#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1610
+
#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1611
+
#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1612
+
#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1613
+
#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1614
+
#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1615
+
#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1616
+
#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1617
+
#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1618
+
#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1619
+
#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1620
+
#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1621
+
#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1622
+
#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1623
+
#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1624
+
#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1625
+
#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1626
+
#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1627
+
#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1628
+
#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1629
+
#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1630
+
#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1631
+
#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1632
+
#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1633
+
#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1634
+
#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1635
+
#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1636
+
#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1637
+
#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1638
+
1539
1639
#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1540
1640
gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail) \
1541
1641
{ \
···
1594
1622
}
1595
1623
1596
1624
static const struct tegra_pingroup tegra194_groups[] = {
1597
-
1598
-
PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1599
-
PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1600
-
PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1601
-
PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1602
-
PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1603
-
PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1604
-
PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1605
-
PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1606
-
PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1607
-
PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1608
-
PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1609
-
PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1610
-
PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1611
-
PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1612
-
PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1613
-
PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1614
-
PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1615
-
PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1616
-
PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1617
-
PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1618
-
PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1619
-
PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1620
-
PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1621
1625
PINGROUP(soc_gpio33_pt0, RSVD0, SPDIF, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1622
1626
PINGROUP(soc_gpio32_ps7, RSVD0, SPDIF, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
1623
1627
PINGROUP(soc_gpio31_ps6, RSVD0, SDMMC1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
···
1753
1805
PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1754
1806
PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1755
1807
PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
1756
-
PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 1, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1757
-
PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1758
-
PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1759
-
PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1760
-
PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1761
-
PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1762
-
PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 1, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1763
-
PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1764
-
PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1765
-
PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1766
-
PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1767
1808
PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1768
1809
PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
1769
1810
PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
···
1794
1857
.sfsel_in_mux = true,
1795
1858
};
1796
1859
1860
+
static const struct pinctrl_pin_desc tegra194_aon_pins[] = {
1861
+
PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
1862
+
PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
1863
+
PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
1864
+
PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
1865
+
PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
1866
+
PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
1867
+
PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
1868
+
PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
1869
+
PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
1870
+
PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
1871
+
PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
1872
+
PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
1873
+
PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
1874
+
PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
1875
+
PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
1876
+
PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
1877
+
PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
1878
+
PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
1879
+
PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
1880
+
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
1881
+
PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
1882
+
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
1883
+
PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
1884
+
PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
1885
+
PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
1886
+
PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
1887
+
PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
1888
+
PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
1889
+
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
1890
+
PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
1891
+
PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
1892
+
PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
1893
+
PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
1894
+
PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
1895
+
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
1896
+
};
1897
+
1898
+
static const struct tegra_pingroup tegra194_aon_groups[] = {
1899
+
PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1900
+
PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1901
+
PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1902
+
PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1903
+
PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1904
+
PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1905
+
PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
1906
+
PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1907
+
PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1908
+
PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1909
+
PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
1910
+
PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1911
+
PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1912
+
PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1913
+
PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1914
+
PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1915
+
PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1916
+
PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1917
+
PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1918
+
PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1919
+
PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1920
+
PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
1921
+
PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1922
+
PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1923
+
PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1924
+
PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1925
+
PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1926
+
PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1927
+
PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1928
+
PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1929
+
PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1930
+
PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1931
+
PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1932
+
PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
1933
+
};
1934
+
1935
+
static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = {
1936
+
.pins = tegra194_aon_pins,
1937
+
.npins = ARRAY_SIZE(tegra194_aon_pins),
1938
+
.functions = tegra194_functions,
1939
+
.nfunctions = ARRAY_SIZE(tegra194_functions),
1940
+
.groups = tegra194_aon_groups,
1941
+
.ngroups = ARRAY_SIZE(tegra194_aon_groups),
1942
+
.hsm_in_mux = true,
1943
+
.schmitt_in_mux = true,
1944
+
.drvtype_in_mux = true,
1945
+
.sfsel_in_mux = true,
1946
+
};
1947
+
1797
1948
static int tegra194_pinctrl_probe(struct platform_device *pdev)
1798
1949
{
1799
-
return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
1950
+
const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);
1951
+
1952
+
return tegra_pinctrl_probe(pdev, soc);
1800
1953
}
1801
1954
1802
1955
static const struct of_device_id tegra194_pinctrl_of_match[] = {
1803
-
{ .compatible = "nvidia,tegra194-pinmux", },
1956
+
{ .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl },
1957
+
{ .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon },
1804
1958
{ },
1805
1959
};
1806
1960
+5
-3
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
+5
-3
drivers/pinctrl/ti/pinctrl-ti-iodelay.c
···
15
15
#include <linux/module.h>
16
16
#include <linux/of.h>
17
17
#include <linux/of_device.h>
18
-
#include <linux/pinctrl/pinconf.h>
19
-
#include <linux/pinctrl/pinconf-generic.h>
20
-
#include <linux/pinctrl/pinctrl.h>
21
18
#include <linux/regmap.h>
19
+
#include <linux/seq_file.h>
22
20
#include <linux/slab.h>
21
+
22
+
#include <linux/pinctrl/pinconf-generic.h>
23
+
#include <linux/pinctrl/pinconf.h>
24
+
#include <linux/pinctrl/pinctrl.h>
23
25
24
26
#include "../core.h"
25
27
#include "../devicetree.h"
+6
-4
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+6
-4
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
···
6
6
#include <linux/list.h>
7
7
#include <linux/mfd/syscon.h>
8
8
#include <linux/of.h>
9
-
#include <linux/pinctrl/pinconf.h>
10
-
#include <linux/pinctrl/pinconf-generic.h>
11
-
#include <linux/pinctrl/pinctrl.h>
12
-
#include <linux/pinctrl/pinmux.h>
13
9
#include <linux/platform_device.h>
14
10
#include <linux/regmap.h>
11
+
#include <linux/seq_file.h>
12
+
13
+
#include <linux/pinctrl/pinconf-generic.h>
14
+
#include <linux/pinctrl/pinconf.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include <linux/pinctrl/pinmux.h>
15
17
16
18
#include "../core.h"
17
19
#include "../pinctrl-utils.h"
+1
-1
drivers/pwm/pwm-lpss-pci.c
+1
-1
drivers/pwm/pwm-lpss-pci.c
+1
-1
drivers/pwm/pwm-lpss-platform.c
+1
-1
drivers/pwm/pwm-lpss-platform.c
+4
-4
drivers/pwm/pwm-lpss.c
+4
-4
drivers/pwm/pwm-lpss.c
···
244
244
.owner = THIS_MODULE,
245
245
};
246
246
247
-
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
248
-
const struct pwm_lpss_boardinfo *info)
247
+
struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
248
+
const struct pwm_lpss_boardinfo *info)
249
249
{
250
250
struct pwm_lpss_chip *lpwm;
251
251
unsigned long c;
252
252
int i, ret;
253
253
u32 ctrl;
254
254
255
-
if (WARN_ON(info->npwm > MAX_PWMS))
255
+
if (WARN_ON(info->npwm > LPSS_MAX_PWMS))
256
256
return ERR_PTR(-ENODEV);
257
257
258
258
lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
···
284
284
285
285
return lpwm;
286
286
}
287
-
EXPORT_SYMBOL_GPL(pwm_lpss_probe);
287
+
EXPORT_SYMBOL_GPL(devm_pwm_lpss_probe);
288
288
289
289
MODULE_DESCRIPTION("PWM driver for Intel LPSS");
290
290
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+4
-22
drivers/pwm/pwm-lpss.h
+4
-22
drivers/pwm/pwm-lpss.h
···
10
10
#ifndef __PWM_LPSS_H
11
11
#define __PWM_LPSS_H
12
12
13
-
#include <linux/device.h>
14
13
#include <linux/pwm.h>
14
+
#include <linux/types.h>
15
15
16
-
#define MAX_PWMS 4
16
+
#include <linux/platform_data/x86/pwm-lpss.h>
17
+
18
+
#define LPSS_MAX_PWMS 4
17
19
18
20
struct pwm_lpss_chip {
19
21
struct pwm_chip chip;
···
23
21
const struct pwm_lpss_boardinfo *info;
24
22
};
25
23
26
-
struct pwm_lpss_boardinfo {
27
-
unsigned long clk_rate;
28
-
unsigned int npwm;
29
-
unsigned long base_unit_bits;
30
-
/*
31
-
* Some versions of the IP may stuck in the state machine if enable
32
-
* bit is not set, and hence update bit will show busy status till
33
-
* the reset. For the rest it may be otherwise.
34
-
*/
35
-
bool bypass;
36
-
/*
37
-
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
38
-
* messes with the PWM0 controllers state,
39
-
*/
40
-
bool other_devices_aml_touches_pwm_regs;
41
-
};
42
-
43
24
extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info;
44
25
extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info;
45
26
extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info;
46
27
extern const struct pwm_lpss_boardinfo pwm_lpss_tng_info;
47
-
48
-
struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
49
-
const struct pwm_lpss_boardinfo *info);
50
28
51
29
#endif /* __PWM_LPSS_H */
+3
-1
drivers/soc/fsl/qe/gpio.c
+3
-1
drivers/soc/fsl/qe/gpio.c
···
18
18
#include <linux/gpio/driver.h>
19
19
#include <linux/slab.h>
20
20
#include <linux/export.h>
21
+
#include <linux/property.h>
22
+
21
23
#include <soc/fsl/qe/qe.h>
22
24
23
25
struct qe_gpio_chip {
···
197
195
*/
198
196
qe_pin->num = gpio_num - gc->base;
199
197
200
-
if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
198
+
if (!fwnode_device_is_compatible(gc->fwnode, "fsl,mpc8323-qe-pario-bank")) {
201
199
dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__);
202
200
err = -EINVAL;
203
201
goto err0;
+2
-2
include/dt-bindings/pinctrl/mt6795-pinfunc.h
+2
-2
include/dt-bindings/pinctrl/mt6795-pinfunc.h
+1
-1
include/linux/gpio.h
+1
-1
include/linux/gpio.h
+4
include/linux/gpio/aspeed.h
+4
include/linux/gpio/aspeed.h
+1
-1
include/linux/gpio/driver.h
+1
-1
include/linux/gpio/driver.h
···
7
7
#include <linux/irqchip/chained_irq.h>
8
8
#include <linux/irqdomain.h>
9
9
#include <linux/lockdep.h>
10
-
#include <linux/pinctrl/pinctrl.h>
11
10
#include <linux/pinctrl/pinconf-generic.h>
11
+
#include <linux/pinctrl/pinctrl.h>
12
12
#include <linux/property.h>
13
13
#include <linux/types.h>
14
14
+4
include/linux/gpio/gpio-reg.h
+4
include/linux/gpio/gpio-reg.h
···
2
2
#ifndef GPIO_REG_H
3
3
#define GPIO_REG_H
4
4
5
+
#include <linux/types.h>
6
+
5
7
struct device;
6
8
struct irq_domain;
9
+
10
+
struct gpio_chip;
7
11
8
12
struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg,
9
13
int base, int num, const char *label, u32 direction, u32 def_out,
-1
include/linux/gpio/machine.h
-1
include/linux/gpio/machine.h
+14
-17
include/linux/pinctrl/consumer.h
+14
-17
include/linux/pinctrl/consumer.h
···
12
12
#define __LINUX_PINCTRL_CONSUMER_H
13
13
14
14
#include <linux/err.h>
15
-
#include <linux/list.h>
16
-
#include <linux/seq_file.h>
15
+
#include <linux/types.h>
16
+
17
17
#include <linux/pinctrl/pinctrl-state.h>
18
+
19
+
struct device;
18
20
19
21
/* This struct is private to the core and should be regarded as a cookie */
20
22
struct pinctrl;
21
23
struct pinctrl_state;
22
-
struct device;
23
24
24
25
#ifdef CONFIG_PINCTRL
25
26
···
34
33
35
34
extern struct pinctrl * __must_check pinctrl_get(struct device *dev);
36
35
extern void pinctrl_put(struct pinctrl *p);
37
-
extern struct pinctrl_state * __must_check pinctrl_lookup_state(
38
-
struct pinctrl *p,
39
-
const char *name);
36
+
extern struct pinctrl_state * __must_check pinctrl_lookup_state(struct pinctrl *p,
37
+
const char *name);
40
38
extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
41
39
42
40
extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
···
101
101
{
102
102
}
103
103
104
-
static inline struct pinctrl_state * __must_check pinctrl_lookup_state(
105
-
struct pinctrl *p,
106
-
const char *name)
104
+
static inline struct pinctrl_state * __must_check pinctrl_lookup_state(struct pinctrl *p,
105
+
const char *name)
107
106
{
108
107
return NULL;
109
108
}
···
144
145
145
146
#endif /* CONFIG_PINCTRL */
146
147
147
-
static inline struct pinctrl * __must_check pinctrl_get_select(
148
-
struct device *dev, const char *name)
148
+
static inline struct pinctrl * __must_check pinctrl_get_select(struct device *dev,
149
+
const char *name)
149
150
{
150
151
struct pinctrl *p;
151
152
struct pinctrl_state *s;
···
170
171
return p;
171
172
}
172
173
173
-
static inline struct pinctrl * __must_check pinctrl_get_select_default(
174
-
struct device *dev)
174
+
static inline struct pinctrl * __must_check pinctrl_get_select_default(struct device *dev)
175
175
{
176
176
return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
177
177
}
178
178
179
-
static inline struct pinctrl * __must_check devm_pinctrl_get_select(
180
-
struct device *dev, const char *name)
179
+
static inline struct pinctrl * __must_check devm_pinctrl_get_select(struct device *dev,
180
+
const char *name)
181
181
{
182
182
struct pinctrl *p;
183
183
struct pinctrl_state *s;
···
201
203
return p;
202
204
}
203
205
204
-
static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
205
-
struct device *dev)
206
+
static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(struct device *dev)
206
207
{
207
208
return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
208
209
}
+4
-2
include/linux/pinctrl/devinfo.h
+4
-2
include/linux/pinctrl/devinfo.h
···
14
14
#ifndef PINCTRL_DEVINFO_H
15
15
#define PINCTRL_DEVINFO_H
16
16
17
+
struct device;
18
+
17
19
#ifdef CONFIG_PINCTRL
18
20
19
21
/* The device core acts as a consumer toward pinctrl */
20
22
#include <linux/pinctrl/consumer.h>
23
+
24
+
struct pinctrl;
21
25
22
26
/**
23
27
* struct dev_pin_info - pin state container for devices
···
45
41
extern int pinctrl_init_done(struct device *dev);
46
42
47
43
#else
48
-
49
-
struct device;
50
44
51
45
/* Stubs if we're not using pinctrl */
52
46
+5
-3
include/linux/pinctrl/machine.h
+5
-3
include/linux/pinctrl/machine.h
···
11
11
#ifndef __LINUX_PINCTRL_MACHINE_H
12
12
#define __LINUX_PINCTRL_MACHINE_H
13
13
14
-
#include <linux/bug.h>
14
+
#include <linux/kernel.h> /* ARRAY_SIZE() */
15
15
16
16
#include <linux/pinctrl/pinctrl-state.h>
17
17
···
149
149
#define PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(dev, grp, cfgs) \
150
150
PIN_MAP_CONFIGS_GROUP(dev, PINCTRL_STATE_DEFAULT, dev, grp, cfgs)
151
151
152
+
struct pinctrl_map;
153
+
152
154
#ifdef CONFIG_PINCTRL
153
155
154
156
extern int pinctrl_register_mappings(const struct pinctrl_map *map,
155
-
unsigned num_maps);
157
+
unsigned num_maps);
156
158
extern void pinctrl_unregister_mappings(const struct pinctrl_map *map);
157
159
extern void pinctrl_provide_dummies(void);
158
160
#else
159
161
160
162
static inline int pinctrl_register_mappings(const struct pinctrl_map *map,
161
-
unsigned num_maps)
163
+
unsigned num_maps)
162
164
{
163
165
return 0;
164
166
}
+17
-12
include/linux/pinctrl/pinconf-generic.h
+17
-12
include/linux/pinctrl/pinconf-generic.h
···
11
11
#ifndef __LINUX_PINCTRL_PINCONF_GENERIC_H
12
12
#define __LINUX_PINCTRL_PINCONF_GENERIC_H
13
13
14
-
#include <linux/device.h>
14
+
#include <linux/types.h>
15
+
15
16
#include <linux/pinctrl/machine.h>
17
+
18
+
struct device_node;
16
19
17
20
struct pinctrl_dev;
18
21
struct pinctrl_map;
···
38
35
* impedance.
39
36
* @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
40
37
* impedance to GROUND). If the argument is != 0 pull-down is enabled,
41
-
* if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
38
+
* the value is interpreted by the driver and can be custom or an SI unit
39
+
* such as Ohms.
42
40
* @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: the pin will be pulled up or down based
43
41
* on embedded knowledge of the controller hardware, like current mux
44
42
* function. The pull direction and possibly strength too will normally
···
50
46
* @PIN_CONFIG_BIAS_DISABLE.
51
47
* @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
52
48
* impedance to VDD). If the argument is != 0 pull-up is enabled,
53
-
* if it is 0, pull-up is total, i.e. the pin is connected to VDD.
49
+
* the value is interpreted by the driver and can be custom or an SI unit
50
+
* such as Ohms.
54
51
* @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
55
52
* collector) which means it is usually wired with other output ports
56
53
* which are then pulled up with an external resistor. Setting this
···
201
196
void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev,
202
197
struct pinctrl_map *map, unsigned num_maps);
203
198
204
-
static inline int pinconf_generic_dt_node_to_map_group(
205
-
struct pinctrl_dev *pctldev, struct device_node *np_config,
206
-
struct pinctrl_map **map, unsigned *num_maps)
199
+
static inline int pinconf_generic_dt_node_to_map_group(struct pinctrl_dev *pctldev,
200
+
struct device_node *np_config, struct pinctrl_map **map,
201
+
unsigned *num_maps)
207
202
{
208
203
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
209
204
PIN_MAP_TYPE_CONFIGS_GROUP);
210
205
}
211
206
212
-
static inline int pinconf_generic_dt_node_to_map_pin(
213
-
struct pinctrl_dev *pctldev, struct device_node *np_config,
214
-
struct pinctrl_map **map, unsigned *num_maps)
207
+
static inline int pinconf_generic_dt_node_to_map_pin(struct pinctrl_dev *pctldev,
208
+
struct device_node *np_config, struct pinctrl_map **map,
209
+
unsigned *num_maps)
215
210
{
216
211
return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps,
217
212
PIN_MAP_TYPE_CONFIGS_PIN);
218
213
}
219
214
220
-
static inline int pinconf_generic_dt_node_to_map_all(
221
-
struct pinctrl_dev *pctldev, struct device_node *np_config,
222
-
struct pinctrl_map **map, unsigned *num_maps)
215
+
static inline int pinconf_generic_dt_node_to_map_all(struct pinctrl_dev *pctldev,
216
+
struct device_node *np_config, struct pinctrl_map **map,
217
+
unsigned *num_maps)
223
218
{
224
219
/*
225
220
* passing the type as PIN_MAP_TYPE_INVALID causes the underlying parser
+10
-10
include/linux/pinctrl/pinctrl.h
+10
-10
include/linux/pinctrl/pinctrl.h
···
11
11
#ifndef __LINUX_PINCTRL_PINCTRL_H
12
12
#define __LINUX_PINCTRL_PINCTRL_H
13
13
14
-
#include <linux/radix-tree.h>
15
-
#include <linux/list.h>
16
-
#include <linux/seq_file.h>
17
-
#include <linux/pinctrl/pinctrl-state.h>
18
-
#include <linux/pinctrl/devinfo.h>
14
+
#include <linux/types.h>
19
15
20
16
struct device;
17
+
struct device_node;
18
+
struct gpio_chip;
19
+
struct module;
20
+
struct seq_file;
21
+
22
+
struct pin_config_item;
23
+
struct pinconf_generic_params;
24
+
struct pinconf_ops;
21
25
struct pinctrl_dev;
22
26
struct pinctrl_map;
23
27
struct pinmux_ops;
24
-
struct pinconf_ops;
25
-
struct pin_config_item;
26
-
struct gpio_chip;
27
-
struct device_node;
28
28
29
29
/**
30
30
* struct pingroup - provides information on pingroup
···
40
40
41
41
/* Convenience macro to define a single named or anonymous pingroup */
42
42
#define PINCTRL_PINGROUP(_name, _pins, _npins) \
43
-
(struct pingroup){ \
43
+
(struct pingroup) { \
44
44
.name = _name, \
45
45
.pins = _pins, \
46
46
.npins = _npins, \
+2
-3
include/linux/pinctrl/pinmux.h
+2
-3
include/linux/pinctrl/pinmux.h
···
11
11
#ifndef __LINUX_PINCTRL_PINMUX_H
12
12
#define __LINUX_PINCTRL_PINMUX_H
13
13
14
-
#include <linux/list.h>
15
-
#include <linux/seq_file.h>
16
-
#include <linux/pinctrl/pinctrl.h>
14
+
#include <linux/types.h>
17
15
18
16
struct pinctrl_dev;
17
+
struct pinctrl_gpio_range;
19
18
20
19
/**
21
20
* struct pinmux_ops - pinmux operations, to be implemented by pin controller
+33
include/linux/platform_data/x86/pwm-lpss.h
+33
include/linux/platform_data/x86/pwm-lpss.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Intel Low Power Subsystem PWM controller driver */
3
+
4
+
#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H
5
+
#define __PLATFORM_DATA_X86_PWM_LPSS_H
6
+
7
+
#include <linux/types.h>
8
+
9
+
struct device;
10
+
11
+
struct pwm_lpss_chip;
12
+
13
+
struct pwm_lpss_boardinfo {
14
+
unsigned long clk_rate;
15
+
unsigned int npwm;
16
+
unsigned long base_unit_bits;
17
+
/*
18
+
* Some versions of the IP may stuck in the state machine if enable
19
+
* bit is not set, and hence update bit will show busy status till
20
+
* the reset. For the rest it may be otherwise.
21
+
*/
22
+
bool bypass;
23
+
/*
24
+
* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
25
+
* messes with the PWM0 controllers state,
26
+
*/
27
+
bool other_devices_aml_touches_pwm_regs;
28
+
};
29
+
30
+
struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
31
+
const struct pwm_lpss_boardinfo *info);
32
+
33
+
#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */
+9
-1
include/linux/property.h
+9
-1
include/linux/property.h
···
50
50
int device_property_match_string(struct device *dev,
51
51
const char *propname, const char *string);
52
52
53
-
bool fwnode_device_is_available(const struct fwnode_handle *fwnode);
54
53
bool fwnode_property_present(const struct fwnode_handle *fwnode,
55
54
const char *propname);
56
55
int fwnode_property_read_u8_array(const struct fwnode_handle *fwnode,
···
71
72
const char *propname, const char **val);
72
73
int fwnode_property_match_string(const struct fwnode_handle *fwnode,
73
74
const char *propname, const char *string);
75
+
76
+
bool fwnode_device_is_available(const struct fwnode_handle *fwnode);
77
+
78
+
static inline
79
+
bool fwnode_device_is_compatible(const struct fwnode_handle *fwnode, const char *compat)
80
+
{
81
+
return fwnode_property_match_string(fwnode, "compatible", compat) >= 0;
82
+
}
83
+
74
84
int fwnode_property_get_reference_args(const struct fwnode_handle *fwnode,
75
85
const char *prop, const char *nargs_prop,
76
86
unsigned int nargs, unsigned int index,
+5
include/linux/pwm.h
+5
include/linux/pwm.h
···
478
478
return -EINVAL;
479
479
}
480
480
481
+
static inline int devm_pwmchip_add(struct device *dev, struct pwm_chip *chip)
482
+
{
483
+
return -EINVAL;
484
+
}
485
+
481
486
static inline struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip,
482
487
unsigned int index,
483
488
const char *label)