+3 -7

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 913 913 amdgpu_rreg64_t pcie_rreg64; 914 914 amdgpu_wreg64_t pcie_wreg64; 915 915 amdgpu_rreg64_ext_t pcie_rreg64_ext; 916 916 - amdgpu_wreg64_ext_t pcie_wreg64_ext; 917 917 - /* protects concurrent UVD register access */ 918 918 - spinlock_t uvd_ctx_idx_lock; 919 919 - amdgpu_rreg_t uvd_ctx_rreg; 920 920 - amdgpu_wreg_t uvd_ctx_wreg; 916 916 + amdgpu_wreg64_ext_t pcie_wreg64_ext; 921 917 /* protects concurrent DIDT register access */ 922 918 spinlock_t didt_idx_lock; 923 919 amdgpu_rreg_t didt_rreg; ··· 1336 1340 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1337 1341 #define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) 1338 1342 #define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) 1339 1339 - #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1340 1340 - #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1343 1343 + #define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) 1344 1344 + #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1341 1345 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1342 1346 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1343 1347 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 3842 3842 adev->pcie_wreg64 = &amdgpu_invalid_wreg64; 3843 3843 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; 3844 3844 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; 3845 3845 - adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; 3846 3846 - adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; 3847 3845 adev->didt_rreg = &amdgpu_invalid_rreg; 3848 3846 adev->didt_wreg = &amdgpu_invalid_wreg; 3849 3847 adev->gc_cac_rreg = &amdgpu_invalid_rreg; ··· 3893 3895 3894 3896 spin_lock_init(&adev->mmio_idx_lock); 3895 3897 spin_lock_init(&adev->pcie_idx_lock); 3896 3896 - spin_lock_init(&adev->uvd_ctx_idx_lock); 3897 3898 spin_lock_init(&adev->didt_idx_lock); 3898 3899 spin_lock_init(&adev->gc_cac_idx_lock); 3899 3900 spin_lock_init(&adev->se_cac_idx_lock);

+25

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

reviewed

··· 38 38 spin_lock_init(&adev->reg.smc.lock); 39 39 adev->reg.smc.rreg = NULL; 40 40 adev->reg.smc.wreg = NULL; 41 41 + 42 42 + spin_lock_init(&adev->reg.uvd_ctx.lock); 43 43 + adev->reg.uvd_ctx.rreg = NULL; 44 44 + adev->reg.uvd_ctx.wreg = NULL; 41 45 } 42 46 43 47 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) ··· 60 56 return; 61 57 } 62 58 adev->reg.smc.wreg(adev, reg, v); 59 59 + } 60 60 + 61 61 + uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg) 62 62 + { 63 63 + if (!adev->reg.uvd_ctx.rreg) { 64 64 + dev_err_once(adev->dev, 65 65 + "UVD_CTX register read not supported\n"); 66 66 + return 0; 67 67 + } 68 68 + return adev->reg.uvd_ctx.rreg(adev, reg); 69 69 + } 70 70 + 71 71 + void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, 72 72 + uint32_t v) 73 73 + { 74 74 + if (!adev->reg.uvd_ctx.wreg) { 75 75 + dev_err_once(adev->dev, 76 76 + "UVD_CTX register write not supported\n"); 77 77 + return; 78 78 + } 79 79 + adev->reg.uvd_ctx.wreg(adev, reg, v); 63 80 } 64 81 65 82 /*

+3

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

reviewed

··· 40 40 41 41 struct amdgpu_reg_access { 42 42 struct amdgpu_reg_ind smc; 43 43 + struct amdgpu_reg_ind uvd_ctx; 43 44 }; 44 45 45 46 void amdgpu_reg_access_init(struct amdgpu_device *adev); 46 47 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); 47 48 void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 49 49 + uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); 50 50 + void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 48 51 49 52 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 50 53 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);

+6 -6

drivers/gpu/drm/amd/amdgpu/cik.c

reviewed

··· 201 201 unsigned long flags; 202 202 u32 r; 203 203 204 204 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 204 204 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 205 205 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 206 206 r = RREG32(mmUVD_CTX_DATA); 207 207 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 207 207 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 208 208 return r; 209 209 } 210 210 ··· 212 212 { 213 213 unsigned long flags; 214 214 215 215 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 215 215 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 216 216 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 217 217 WREG32(mmUVD_CTX_DATA, (v)); 218 218 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 218 218 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 219 219 } 220 220 221 221 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) ··· 1988 1988 adev->reg.smc.wreg = cik_smc_wreg; 1989 1989 adev->pcie_rreg = &cik_pcie_rreg; 1990 1990 adev->pcie_wreg = &cik_pcie_wreg; 1991 1991 - adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; 1992 1992 - adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; 1991 1991 + adev->reg.uvd_ctx.rreg = &cik_uvd_ctx_rreg; 1992 1992 + adev->reg.uvd_ctx.wreg = &cik_uvd_ctx_wreg; 1993 1993 adev->didt_rreg = &cik_didt_rreg; 1994 1994 adev->didt_wreg = &cik_didt_wreg; 1995 1995

-4

drivers/gpu/drm/amd/amdgpu/nv.c

reviewed

··· 642 642 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 643 643 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 644 644 645 645 - /* TODO: will add them during VCN v2 implementation */ 646 646 - adev->uvd_ctx_rreg = NULL; 647 647 - adev->uvd_ctx_wreg = NULL; 648 648 - 649 645 adev->didt_rreg = &nv_didt_rreg; 650 646 adev->didt_wreg = &nv_didt_wreg; 651 647

+6 -6

drivers/gpu/drm/amd/amdgpu/si.c

reviewed

··· 1099 1099 unsigned long flags; 1100 1100 u32 r; 1101 1101 1102 1102 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 1102 1102 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 1103 1103 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 1104 1104 r = RREG32(mmUVD_CTX_DATA); 1105 1105 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 1105 1105 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 1106 1106 return r; 1107 1107 } 1108 1108 ··· 1110 1110 { 1111 1111 unsigned long flags; 1112 1112 1113 1113 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 1113 1113 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 1114 1114 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 1115 1115 WREG32(mmUVD_CTX_DATA, (v)); 1116 1116 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 1116 1116 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 1117 1117 } 1118 1118 1119 1119 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { ··· 2043 2043 adev->pcie_wreg = &si_pcie_wreg; 2044 2044 adev->pciep_rreg = &si_pciep_rreg; 2045 2045 adev->pciep_wreg = &si_pciep_wreg; 2046 2046 - adev->uvd_ctx_rreg = si_uvd_ctx_rreg; 2047 2047 - adev->uvd_ctx_wreg = si_uvd_ctx_wreg; 2046 2046 + adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; 2047 2047 + adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; 2048 2048 adev->didt_rreg = NULL; 2049 2049 adev->didt_wreg = NULL; 2050 2050

+6 -6

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 245 245 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 246 246 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 247 247 248 248 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 248 248 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 249 249 WREG32(address, ((reg) & 0x1ff)); 250 250 r = RREG32(data); 251 251 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 251 251 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 252 252 return r; 253 253 } 254 254 ··· 259 259 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 260 260 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 261 261 262 262 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 262 262 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 263 263 WREG32(address, ((reg) & 0x1ff)); 264 264 WREG32(data, (v)); 265 265 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 265 265 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 266 266 } 267 267 268 268 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) ··· 969 969 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 970 970 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 971 971 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 972 972 - adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 973 973 - adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 972 972 + adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; 973 973 + adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; 974 974 adev->didt_rreg = &soc15_didt_rreg; 975 975 adev->didt_wreg = &soc15_didt_wreg; 976 976 adev->gc_cac_rreg = &soc15_gc_cac_rreg;

-4

drivers/gpu/drm/amd/amdgpu/soc21.c

reviewed

··· 596 596 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 597 597 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 598 598 599 599 - /* TODO: will add them during VCN v2 implementation */ 600 600 - adev->uvd_ctx_rreg = NULL; 601 601 - adev->uvd_ctx_wreg = NULL; 602 602 - 603 599 adev->didt_rreg = &soc21_didt_rreg; 604 600 adev->didt_wreg = &soc21_didt_wreg; 605 601

-2

drivers/gpu/drm/amd/amdgpu/soc24.c

reviewed

··· 368 368 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 369 369 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 370 370 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 371 371 - adev->uvd_ctx_rreg = NULL; 372 372 - adev->uvd_ctx_wreg = NULL; 373 371 adev->didt_rreg = NULL; 374 372 adev->didt_wreg = NULL; 375 373

-2

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

reviewed

··· 260 260 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 261 261 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 262 262 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 263 263 - adev->uvd_ctx_rreg = NULL; 264 264 - adev->uvd_ctx_wreg = NULL; 265 263 adev->didt_rreg = NULL; 266 264 adev->didt_wreg = NULL; 267 265

+6 -6

drivers/gpu/drm/amd/amdgpu/vi.c

reviewed

··· 372 372 unsigned long flags; 373 373 u32 r; 374 374 375 375 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 375 375 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 376 376 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 377 377 r = RREG32(mmUVD_CTX_DATA); 378 378 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 378 378 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 379 379 return r; 380 380 } 381 381 ··· 383 383 { 384 384 unsigned long flags; 385 385 386 386 - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 386 386 + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 387 387 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 388 388 WREG32(mmUVD_CTX_DATA, (v)); 389 389 - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 389 389 + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 390 390 } 391 391 392 392 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) ··· 1462 1462 } 1463 1463 adev->pcie_rreg = &vi_pcie_rreg; 1464 1464 adev->pcie_wreg = &vi_pcie_wreg; 1465 1465 - adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1466 1466 - adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; 1465 1465 + adev->reg.uvd_ctx.rreg = &vi_uvd_ctx_rreg; 1466 1466 + adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; 1467 1467 adev->didt_rreg = &vi_didt_rreg; 1468 1468 adev->didt_wreg = &vi_didt_wreg; 1469 1469 adev->gc_cac_rreg = &vi_gc_cac_rreg;