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drm/amdgpu: Generalize HQD and VMID mask calculation for MES

Generalize the calculation for determining the HQD mask and VMID mask
passed to MES during initialization.

v2: rebase (Alex)

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Mukul Joshi and committed by
Alex Deucher
36b266bd d09c7e26

+12 -2
+12 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
··· 31 31 32 32 #define AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 33 33 #define AMDGPU_ONE_DOORBELL_SIZE 8 34 + #define AMDGPU_MES_RESERVED_QUEUES 2 34 35 35 36 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev) 36 37 { ··· 93 92 { 94 93 int i, r, num_pipes; 95 94 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 95 + u32 total_vmid_mask, reserved_vmid_mask; 96 + u32 queue_mask, reserved_queue_mask; 96 97 97 98 adev->mes.adev = adev; 98 99 ··· 109 106 spin_lock_init(&adev->mes.ring_lock[i]); 110 107 111 108 adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; 109 + total_vmid_mask = (u32)((1UL << 16) - 1); 110 + reserved_vmid_mask = (u32)((1UL << adev->vm_manager.first_kfd_vmid) - 1); 111 + 112 112 adev->mes.vmid_mask_mmhub = 0xFF00; 113 - adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xFFFE : 0xFF00; 113 + adev->mes.vmid_mask_gfxhub = total_vmid_mask & ~reserved_vmid_mask; 114 + 115 + queue_mask = (u32)(1UL << adev->gfx.mec.num_queue_per_pipe) - 1; 116 + reserved_queue_mask = (u32)(1UL << AMDGPU_MES_RESERVED_QUEUES) - 1; 114 117 115 118 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; 116 119 if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) ··· 152 143 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) { 153 144 if (i >= num_pipes) 154 145 break; 155 - adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC; 146 + adev->mes.compute_hqd_mask[i] = 147 + adev->gfx.disable_kq ? 0xF : (queue_mask & ~reserved_queue_mask); 156 148 } 157 149 158 150 num_pipes = adev->sdma.num_instances;