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drm/amd/pm: unified lock protections in amdgpu_dpm.c

As the only entry point, it's now safe and reasonable to
enforce the lock protections in amdgpu_dpm.c. And with
this, we can drop other internal used power locks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by
Alex Deucher 3712e7a4 61d7d0d5

+526 -213
+524 -183
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
··· 39 39 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40 40 { 41 41 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 42 + int ret = 0; 42 43 43 - return pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); 44 + if (!pp_funcs->get_sclk) 45 + return 0; 46 + 47 + mutex_lock(&adev->pm.mutex); 48 + ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, 49 + low); 50 + mutex_unlock(&adev->pm.mutex); 51 + 52 + return ret; 44 53 } 45 54 46 55 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) 47 56 { 48 57 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 58 + int ret = 0; 49 59 50 - return pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); 60 + if (!pp_funcs->get_mclk) 61 + return 0; 62 + 63 + mutex_lock(&adev->pm.mutex); 64 + ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, 65 + low); 66 + mutex_unlock(&adev->pm.mutex); 67 + 68 + return ret; 51 69 } 52 70 53 71 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) ··· 80 62 return 0; 81 63 } 82 64 65 + mutex_lock(&adev->pm.mutex); 66 + 83 67 switch (block_type) { 84 68 case AMD_IP_BLOCK_TYPE_UVD: 85 69 case AMD_IP_BLOCK_TYPE_VCE: 86 - if (pp_funcs && pp_funcs->set_powergating_by_smu) { 87 - /* 88 - * TODO: need a better lock mechanism 89 - * 90 - * Here adev->pm.mutex lock protection is enforced on 91 - * UVD and VCE cases only. Since for other cases, there 92 - * may be already lock protection in amdgpu_pm.c. 93 - * This is a quick fix for the deadlock issue below. 94 - * NFO: task ocltst:2028 blocked for more than 120 seconds. 95 - * Tainted: G OE 5.0.0-37-generic #40~18.04.1-Ubuntu 96 - * echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. 97 - * cltst D 0 2028 2026 0x00000000 98 - * all Trace: 99 - * __schedule+0x2c0/0x870 100 - * schedule+0x2c/0x70 101 - * schedule_preempt_disabled+0xe/0x10 102 - * __mutex_lock.isra.9+0x26d/0x4e0 103 - * __mutex_lock_slowpath+0x13/0x20 104 - * ? __mutex_lock_slowpath+0x13/0x20 105 - * mutex_lock+0x2f/0x40 106 - * amdgpu_dpm_set_powergating_by_smu+0x64/0xe0 [amdgpu] 107 - * gfx_v8_0_enable_gfx_static_mg_power_gating+0x3c/0x70 [amdgpu] 108 - * gfx_v8_0_set_powergating_state+0x66/0x260 [amdgpu] 109 - * amdgpu_device_ip_set_powergating_state+0x62/0xb0 [amdgpu] 110 - * pp_dpm_force_performance_level+0xe7/0x100 [amdgpu] 111 - * amdgpu_set_dpm_forced_performance_level+0x129/0x330 [amdgpu] 112 - */ 113 - mutex_lock(&adev->pm.mutex); 114 - ret = (pp_funcs->set_powergating_by_smu( 115 - (adev)->powerplay.pp_handle, block_type, gate)); 116 - mutex_unlock(&adev->pm.mutex); 117 - } 118 - break; 119 70 case AMD_IP_BLOCK_TYPE_GFX: 120 71 case AMD_IP_BLOCK_TYPE_VCN: 121 72 case AMD_IP_BLOCK_TYPE_SDMA: 122 73 case AMD_IP_BLOCK_TYPE_JPEG: 123 74 case AMD_IP_BLOCK_TYPE_GMC: 124 75 case AMD_IP_BLOCK_TYPE_ACP: 125 - if (pp_funcs && pp_funcs->set_powergating_by_smu) { 76 + if (pp_funcs && pp_funcs->set_powergating_by_smu) 126 77 ret = (pp_funcs->set_powergating_by_smu( 127 78 (adev)->powerplay.pp_handle, block_type, gate)); 128 - } 129 79 break; 130 80 default: 131 81 break; ··· 101 115 102 116 if (!ret) 103 117 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); 118 + 119 + mutex_unlock(&adev->pm.mutex); 104 120 105 121 return ret; 106 122 } ··· 116 128 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 117 129 return -ENOENT; 118 130 131 + mutex_lock(&adev->pm.mutex); 132 + 119 133 /* enter BACO state */ 120 134 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 135 + 136 + mutex_unlock(&adev->pm.mutex); 121 137 122 138 return ret; 123 139 } ··· 135 143 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 136 144 return -ENOENT; 137 145 146 + mutex_lock(&adev->pm.mutex); 147 + 138 148 /* exit BACO state */ 139 149 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 150 + 151 + mutex_unlock(&adev->pm.mutex); 140 152 141 153 return ret; 142 154 } ··· 152 156 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 153 157 154 158 if (pp_funcs && pp_funcs->set_mp1_state) { 159 + mutex_lock(&adev->pm.mutex); 160 + 155 161 ret = pp_funcs->set_mp1_state( 156 162 adev->powerplay.pp_handle, 157 163 mp1_state); 164 + 165 + mutex_unlock(&adev->pm.mutex); 158 166 } 159 167 160 168 return ret; ··· 169 169 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 170 170 void *pp_handle = adev->powerplay.pp_handle; 171 171 bool baco_cap; 172 + int ret = 0; 172 173 173 174 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) 174 175 return false; 175 176 176 - if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap)) 177 - return false; 177 + mutex_lock(&adev->pm.mutex); 178 178 179 - return baco_cap; 179 + ret = pp_funcs->get_asic_baco_capability(pp_handle, 180 + &baco_cap); 181 + 182 + mutex_unlock(&adev->pm.mutex); 183 + 184 + return ret ? false : baco_cap; 180 185 } 181 186 182 187 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) 183 188 { 184 189 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 185 190 void *pp_handle = adev->powerplay.pp_handle; 191 + int ret = 0; 186 192 187 193 if (!pp_funcs || !pp_funcs->asic_reset_mode_2) 188 194 return -ENOENT; 189 195 190 - return pp_funcs->asic_reset_mode_2(pp_handle); 196 + mutex_lock(&adev->pm.mutex); 197 + 198 + ret = pp_funcs->asic_reset_mode_2(pp_handle); 199 + 200 + mutex_unlock(&adev->pm.mutex); 201 + 202 + return ret; 191 203 } 192 204 193 205 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) ··· 211 199 if (!pp_funcs || !pp_funcs->set_asic_baco_state) 212 200 return -ENOENT; 213 201 202 + mutex_lock(&adev->pm.mutex); 203 + 214 204 /* enter BACO state */ 215 205 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); 216 206 if (ret) 217 - return ret; 207 + goto out; 218 208 219 209 /* exit BACO state */ 220 210 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); 221 - if (ret) 222 - return ret; 223 211 224 - return 0; 212 + out: 213 + mutex_unlock(&adev->pm.mutex); 214 + return ret; 225 215 } 226 216 227 217 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 228 218 { 229 219 struct smu_context *smu = adev->powerplay.pp_handle; 220 + bool support_mode1_reset = false; 230 221 231 - if (is_support_sw_smu(adev)) 232 - return smu_mode1_reset_is_support(smu); 222 + if (is_support_sw_smu(adev)) { 223 + mutex_lock(&adev->pm.mutex); 224 + support_mode1_reset = smu_mode1_reset_is_support(smu); 225 + mutex_unlock(&adev->pm.mutex); 226 + } 233 227 234 - return false; 228 + return support_mode1_reset; 235 229 } 236 230 237 231 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) 238 232 { 239 233 struct smu_context *smu = adev->powerplay.pp_handle; 234 + int ret = -EOPNOTSUPP; 240 235 241 - if (is_support_sw_smu(adev)) 242 - return smu_mode1_reset(smu); 236 + if (is_support_sw_smu(adev)) { 237 + mutex_lock(&adev->pm.mutex); 238 + ret = smu_mode1_reset(smu); 239 + mutex_unlock(&adev->pm.mutex); 240 + } 243 241 244 - return -EOPNOTSUPP; 242 + return ret; 245 243 } 246 244 247 245 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, ··· 264 242 if (amdgpu_sriov_vf(adev)) 265 243 return 0; 266 244 267 - if (pp_funcs && pp_funcs->switch_power_profile) 245 + if (pp_funcs && pp_funcs->switch_power_profile) { 246 + mutex_lock(&adev->pm.mutex); 268 247 ret = pp_funcs->switch_power_profile( 269 248 adev->powerplay.pp_handle, type, en); 249 + mutex_unlock(&adev->pm.mutex); 250 + } 270 251 271 252 return ret; 272 253 } ··· 280 255 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 281 256 int ret = 0; 282 257 283 - if (pp_funcs && pp_funcs->set_xgmi_pstate) 258 + if (pp_funcs && pp_funcs->set_xgmi_pstate) { 259 + mutex_lock(&adev->pm.mutex); 284 260 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, 285 261 pstate); 262 + mutex_unlock(&adev->pm.mutex); 263 + } 286 264 287 265 return ret; 288 266 } ··· 297 269 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 298 270 void *pp_handle = adev->powerplay.pp_handle; 299 271 300 - if (pp_funcs && pp_funcs->set_df_cstate) 272 + if (pp_funcs && pp_funcs->set_df_cstate) { 273 + mutex_lock(&adev->pm.mutex); 301 274 ret = pp_funcs->set_df_cstate(pp_handle, cstate); 275 + mutex_unlock(&adev->pm.mutex); 276 + } 302 277 303 278 return ret; 304 279 } ··· 309 278 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en) 310 279 { 311 280 struct smu_context *smu = adev->powerplay.pp_handle; 281 + int ret = 0; 312 282 313 - if (is_support_sw_smu(adev)) 314 - return smu_allow_xgmi_power_down(smu, en); 283 + if (is_support_sw_smu(adev)) { 284 + mutex_lock(&adev->pm.mutex); 285 + ret = smu_allow_xgmi_power_down(smu, en); 286 + mutex_unlock(&adev->pm.mutex); 287 + } 315 288 316 - return 0; 289 + return ret; 317 290 } 318 291 319 292 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) ··· 327 292 adev->powerplay.pp_funcs; 328 293 int ret = 0; 329 294 330 - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) 295 + if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { 296 + mutex_lock(&adev->pm.mutex); 331 297 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); 298 + mutex_unlock(&adev->pm.mutex); 299 + } 332 300 333 301 return ret; 334 302 } ··· 344 306 adev->powerplay.pp_funcs; 345 307 int ret = 0; 346 308 347 - if (pp_funcs && pp_funcs->set_clockgating_by_smu) 309 + if (pp_funcs && pp_funcs->set_clockgating_by_smu) { 310 + mutex_lock(&adev->pm.mutex); 348 311 ret = pp_funcs->set_clockgating_by_smu(pp_handle, 349 312 msg_id); 313 + mutex_unlock(&adev->pm.mutex); 314 + } 350 315 351 316 return ret; 352 317 } ··· 362 321 adev->powerplay.pp_funcs; 363 322 int ret = -EOPNOTSUPP; 364 323 365 - if (pp_funcs && pp_funcs->smu_i2c_bus_access) 324 + if (pp_funcs && pp_funcs->smu_i2c_bus_access) { 325 + mutex_lock(&adev->pm.mutex); 366 326 ret = pp_funcs->smu_i2c_bus_access(pp_handle, 367 327 acquire); 328 + mutex_unlock(&adev->pm.mutex); 329 + } 368 330 369 331 return ret; 370 332 } ··· 380 336 adev->pm.ac_power = true; 381 337 else 382 338 adev->pm.ac_power = false; 339 + 383 340 if (adev->powerplay.pp_funcs && 384 341 adev->powerplay.pp_funcs->enable_bapm) 385 342 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 386 - mutex_unlock(&adev->pm.mutex); 387 343 388 344 if (is_support_sw_smu(adev)) 389 345 smu_set_ac_dc(adev->powerplay.pp_handle); 346 + 347 + mutex_unlock(&adev->pm.mutex); 390 348 } 391 349 } 392 350 ··· 396 350 void *data, uint32_t *size) 397 351 { 398 352 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 399 - int ret = 0; 353 + int ret = -EINVAL; 400 354 401 355 if (!data || !size) 402 356 return -EINVAL; 403 357 404 - if (pp_funcs && pp_funcs->read_sensor) 405 - ret = pp_funcs->read_sensor((adev)->powerplay.pp_handle, 406 - sensor, data, size); 407 - else 408 - ret = -EINVAL; 358 + if (pp_funcs && pp_funcs->read_sensor) { 359 + mutex_lock(&adev->pm.mutex); 360 + ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, 361 + sensor, 362 + data, 363 + size); 364 + mutex_unlock(&adev->pm.mutex); 365 + } 409 366 410 367 return ret; 411 368 } ··· 423 374 if (!pp_funcs->pm_compute_clocks) 424 375 return; 425 376 377 + mutex_lock(&adev->pm.mutex); 426 378 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); 379 + mutex_unlock(&adev->pm.mutex); 427 380 } 428 381 429 382 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) ··· 460 409 461 410 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 462 411 { 463 - int r; 412 + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 413 + int r = 0; 464 414 465 - if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) { 466 - r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle); 467 - if (r) { 468 - pr_err("smu firmware loading failed\n"); 469 - return r; 470 - } 415 + if (!pp_funcs->load_firmware) 416 + return 0; 471 417 472 - if (smu_version) 473 - *smu_version = adev->pm.fw_version; 418 + mutex_lock(&adev->pm.mutex); 419 + r = pp_funcs->load_firmware(adev->powerplay.pp_handle); 420 + if (r) { 421 + pr_err("smu firmware loading failed\n"); 422 + goto out; 474 423 } 475 424 476 - return 0; 425 + if (smu_version) 426 + *smu_version = adev->pm.fw_version; 427 + 428 + out: 429 + mutex_unlock(&adev->pm.mutex); 430 + return r; 477 431 } 478 432 479 433 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) 480 434 { 481 - return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); 435 + int ret = 0; 436 + 437 + if (is_support_sw_smu(adev)) { 438 + mutex_lock(&adev->pm.mutex); 439 + ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, 440 + enable); 441 + mutex_unlock(&adev->pm.mutex); 442 + } 443 + 444 + return ret; 482 445 } 483 446 484 447 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) 485 448 { 486 449 struct smu_context *smu = adev->powerplay.pp_handle; 450 + int ret = 0; 487 451 488 - return smu_send_hbm_bad_pages_num(smu, size); 452 + mutex_lock(&adev->pm.mutex); 453 + ret = smu_send_hbm_bad_pages_num(smu, size); 454 + mutex_unlock(&adev->pm.mutex); 455 + 456 + return ret; 489 457 } 490 458 491 459 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, ··· 512 442 uint32_t *min, 513 443 uint32_t *max) 514 444 { 445 + int ret = 0; 446 + 447 + if (type != PP_SCLK) 448 + return -EINVAL; 449 + 515 450 if (!is_support_sw_smu(adev)) 516 451 return -EOPNOTSUPP; 517 452 518 - switch (type) { 519 - case PP_SCLK: 520 - return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); 521 - default: 522 - return -EINVAL; 523 - } 453 + mutex_lock(&adev->pm.mutex); 454 + ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, 455 + SMU_SCLK, 456 + min, 457 + max); 458 + mutex_unlock(&adev->pm.mutex); 459 + 460 + return ret; 524 461 } 525 462 526 463 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, ··· 536 459 uint32_t max) 537 460 { 538 461 struct smu_context *smu = adev->powerplay.pp_handle; 462 + int ret = 0; 463 + 464 + if (type != PP_SCLK) 465 + return -EINVAL; 539 466 540 467 if (!is_support_sw_smu(adev)) 541 468 return -EOPNOTSUPP; 542 469 543 - switch (type) { 544 - case PP_SCLK: 545 - return smu_set_soft_freq_range(smu, SMU_SCLK, min, max); 546 - default: 547 - return -EINVAL; 548 - } 470 + mutex_lock(&adev->pm.mutex); 471 + ret = smu_set_soft_freq_range(smu, 472 + SMU_SCLK, 473 + min, 474 + max); 475 + mutex_unlock(&adev->pm.mutex); 476 + 477 + return ret; 549 478 } 550 479 551 480 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) 552 481 { 553 482 struct smu_context *smu = adev->powerplay.pp_handle; 483 + int ret = 0; 554 484 555 485 if (!is_support_sw_smu(adev)) 556 486 return 0; 557 487 558 - return smu_write_watermarks_table(smu); 488 + mutex_lock(&adev->pm.mutex); 489 + ret = smu_write_watermarks_table(smu); 490 + mutex_unlock(&adev->pm.mutex); 491 + 492 + return ret; 559 493 } 560 494 561 495 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, ··· 574 486 uint64_t event_arg) 575 487 { 576 488 struct smu_context *smu = adev->powerplay.pp_handle; 489 + int ret = 0; 577 490 578 491 if (!is_support_sw_smu(adev)) 579 492 return -EOPNOTSUPP; 580 493 581 - return smu_wait_for_event(smu, event, event_arg); 494 + mutex_lock(&adev->pm.mutex); 495 + ret = smu_wait_for_event(smu, event, event_arg); 496 + mutex_unlock(&adev->pm.mutex); 497 + 498 + return ret; 582 499 } 583 500 584 501 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 585 502 { 586 503 struct smu_context *smu = adev->powerplay.pp_handle; 504 + int ret = 0; 587 505 588 506 if (!is_support_sw_smu(adev)) 589 507 return -EOPNOTSUPP; 590 508 591 - return smu_get_status_gfxoff(smu, value); 509 + mutex_lock(&adev->pm.mutex); 510 + ret = smu_get_status_gfxoff(smu, value); 511 + mutex_unlock(&adev->pm.mutex); 512 + 513 + return ret; 592 514 } 593 515 594 516 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) 595 517 { 596 518 struct smu_context *smu = adev->powerplay.pp_handle; 519 + 520 + if (!is_support_sw_smu(adev)) 521 + return 0; 597 522 598 523 return atomic64_read(&smu->throttle_int_counter); 599 524 } ··· 642 541 uint32_t idx) 643 542 { 644 543 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 544 + struct amd_vce_state *vstate = NULL; 645 545 646 546 if (!pp_funcs->get_vce_clock_state) 647 547 return NULL; 648 548 649 - return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 650 - idx); 549 + mutex_lock(&adev->pm.mutex); 550 + vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, 551 + idx); 552 + mutex_unlock(&adev->pm.mutex); 553 + 554 + return vstate; 651 555 } 652 556 653 557 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, ··· 660 554 { 661 555 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 662 556 557 + mutex_lock(&adev->pm.mutex); 558 + 663 559 if (!pp_funcs->get_current_power_state) { 664 560 *state = adev->pm.dpm.user_state; 665 - return; 561 + goto out; 666 562 } 667 563 668 564 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); 669 565 if (*state < POWER_STATE_TYPE_DEFAULT || 670 566 *state > POWER_STATE_TYPE_INTERNAL_3DPERF) 671 567 *state = adev->pm.dpm.user_state; 568 + 569 + out: 570 + mutex_unlock(&adev->pm.mutex); 672 571 } 673 572 674 573 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 675 574 enum amd_pm_state_type state) 676 575 { 576 + mutex_lock(&adev->pm.mutex); 677 577 adev->pm.dpm.user_state = state; 578 + mutex_unlock(&adev->pm.mutex); 678 579 679 580 if (is_support_sw_smu(adev)) 680 581 return; ··· 697 584 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 698 585 enum amd_dpm_forced_level level; 699 586 587 + mutex_lock(&adev->pm.mutex); 700 588 if (pp_funcs->get_performance_level) 701 589 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); 702 590 else 703 591 level = adev->pm.dpm.forced_level; 592 + mutex_unlock(&adev->pm.mutex); 704 593 705 594 return level; 706 595 } ··· 711 596 enum amd_dpm_forced_level level) 712 597 { 713 598 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 599 + int ret = 0; 714 600 715 - if (pp_funcs->force_performance_level) { 716 - if (adev->pm.dpm.thermal_active) 717 - return -EINVAL; 601 + if (!pp_funcs->force_performance_level) 602 + return 0; 718 603 719 - if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 720 - level)) 721 - return -EINVAL; 604 + mutex_lock(&adev->pm.mutex); 722 605 723 - adev->pm.dpm.forced_level = level; 606 + if (adev->pm.dpm.thermal_active) { 607 + ret = -EINVAL; 608 + goto out; 724 609 } 725 610 726 - return 0; 611 + if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, 612 + level)) 613 + ret = -EINVAL; 614 + 615 + if (!ret) 616 + adev->pm.dpm.forced_level = level; 617 + 618 + out: 619 + mutex_unlock(&adev->pm.mutex); 620 + 621 + return ret; 727 622 } 728 623 729 624 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 730 625 struct pp_states_info *states) 731 626 { 732 627 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 628 + int ret = 0; 733 629 734 630 if (!pp_funcs->get_pp_num_states) 735 631 return -EOPNOTSUPP; 736 632 737 - return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); 633 + mutex_lock(&adev->pm.mutex); 634 + ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, 635 + states); 636 + mutex_unlock(&adev->pm.mutex); 637 + 638 + return ret; 738 639 } 739 640 740 641 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, ··· 758 627 enum amd_pm_state_type *user_state) 759 628 { 760 629 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 630 + int ret = 0; 761 631 762 632 if (!pp_funcs->dispatch_tasks) 763 633 return -EOPNOTSUPP; 764 634 765 - return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); 635 + mutex_lock(&adev->pm.mutex); 636 + ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, 637 + task_id, 638 + user_state); 639 + mutex_unlock(&adev->pm.mutex); 640 + 641 + return ret; 766 642 } 767 643 768 644 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) 769 645 { 770 646 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 647 + int ret = 0; 771 648 772 649 if (!pp_funcs->get_pp_table) 773 650 return 0; 774 651 775 - return pp_funcs->get_pp_table(adev->powerplay.pp_handle, table); 652 + mutex_lock(&adev->pm.mutex); 653 + ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, 654 + table); 655 + mutex_unlock(&adev->pm.mutex); 656 + 657 + return ret; 776 658 } 777 659 778 660 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, ··· 794 650 uint32_t size) 795 651 { 796 652 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 653 + int ret = 0; 797 654 798 655 if (!pp_funcs->set_fine_grain_clk_vol) 799 656 return 0; 800 657 801 - return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 802 - type, 803 - input, 804 - size); 658 + mutex_lock(&adev->pm.mutex); 659 + ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, 660 + type, 661 + input, 662 + size); 663 + mutex_unlock(&adev->pm.mutex); 664 + 665 + return ret; 805 666 } 806 667 807 668 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, ··· 815 666 uint32_t size) 816 667 { 817 668 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 669 + int ret = 0; 818 670 819 671 if (!pp_funcs->odn_edit_dpm_table) 820 672 return 0; 821 673 822 - return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 823 - type, 824 - input, 825 - size); 674 + mutex_lock(&adev->pm.mutex); 675 + ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, 676 + type, 677 + input, 678 + size); 679 + mutex_unlock(&adev->pm.mutex); 680 + 681 + return ret; 826 682 } 827 683 828 684 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, ··· 835 681 char *buf) 836 682 { 837 683 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 684 + int ret = 0; 838 685 839 686 if (!pp_funcs->print_clock_levels) 840 687 return 0; 841 688 842 - return pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 843 - type, 844 - buf); 689 + mutex_lock(&adev->pm.mutex); 690 + ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, 691 + type, 692 + buf); 693 + mutex_unlock(&adev->pm.mutex); 694 + 695 + return ret; 845 696 } 846 697 847 698 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 848 699 uint64_t ppfeature_masks) 849 700 { 850 701 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 702 + int ret = 0; 851 703 852 704 if (!pp_funcs->set_ppfeature_status) 853 705 return 0; 854 706 855 - return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 856 - ppfeature_masks); 707 + mutex_lock(&adev->pm.mutex); 708 + ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, 709 + ppfeature_masks); 710 + mutex_unlock(&adev->pm.mutex); 711 + 712 + return ret; 857 713 } 858 714 859 715 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) 860 716 { 861 717 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 718 + int ret = 0; 862 719 863 720 if (!pp_funcs->get_ppfeature_status) 864 721 return 0; 865 722 866 - return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 867 - buf); 723 + mutex_lock(&adev->pm.mutex); 724 + ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, 725 + buf); 726 + mutex_unlock(&adev->pm.mutex); 727 + 728 + return ret; 868 729 } 869 730 870 731 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, ··· 887 718 uint32_t mask) 888 719 { 889 720 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 721 + int ret = 0; 890 722 891 723 if (!pp_funcs->force_clock_level) 892 724 return 0; 893 725 894 - return pp_funcs->force_clock_level(adev->powerplay.pp_handle, 895 - type, 896 - mask); 726 + mutex_lock(&adev->pm.mutex); 727 + ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, 728 + type, 729 + mask); 730 + mutex_unlock(&adev->pm.mutex); 731 + 732 + return ret; 897 733 } 898 734 899 735 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) 900 736 { 901 737 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 738 + int ret = 0; 902 739 903 740 if (!pp_funcs->get_sclk_od) 904 741 return 0; 905 742 906 - return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 743 + mutex_lock(&adev->pm.mutex); 744 + ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); 745 + mutex_unlock(&adev->pm.mutex); 746 + 747 + return ret; 907 748 } 908 749 909 750 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) ··· 923 744 if (is_support_sw_smu(adev)) 924 745 return 0; 925 746 747 + mutex_lock(&adev->pm.mutex); 926 748 if (pp_funcs->set_sclk_od) 927 749 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); 750 + mutex_unlock(&adev->pm.mutex); 928 751 929 752 if (amdgpu_dpm_dispatch_task(adev, 930 753 AMD_PP_TASK_READJUST_POWER_STATE, ··· 941 760 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) 942 761 { 943 762 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 763 + int ret = 0; 944 764 945 765 if (!pp_funcs->get_mclk_od) 946 766 return 0; 947 767 948 - return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 768 + mutex_lock(&adev->pm.mutex); 769 + ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); 770 + mutex_unlock(&adev->pm.mutex); 771 + 772 + return ret; 949 773 } 950 774 951 775 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) ··· 960 774 if (is_support_sw_smu(adev)) 961 775 return 0; 962 776 777 + mutex_lock(&adev->pm.mutex); 963 778 if (pp_funcs->set_mclk_od) 964 779 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); 780 + mutex_unlock(&adev->pm.mutex); 965 781 966 782 if (amdgpu_dpm_dispatch_task(adev, 967 783 AMD_PP_TASK_READJUST_POWER_STATE, ··· 979 791 char *buf) 980 792 { 981 793 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 794 + int ret = 0; 982 795 983 796 if (!pp_funcs->get_power_profile_mode) 984 797 return -EOPNOTSUPP; 985 798 986 - return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 987 - buf); 799 + mutex_lock(&adev->pm.mutex); 800 + ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, 801 + buf); 802 + mutex_unlock(&adev->pm.mutex); 803 + 804 + return ret; 988 805 } 989 806 990 807 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 991 808 long *input, uint32_t size) 992 809 { 993 810 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 811 + int ret = 0; 994 812 995 813 if (!pp_funcs->set_power_profile_mode) 996 814 return 0; 997 815 998 - return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 999 - input, 1000 - size); 816 + mutex_lock(&adev->pm.mutex); 817 + ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, 818 + input, 819 + size); 820 + mutex_unlock(&adev->pm.mutex); 821 + 822 + return ret; 1001 823 } 1002 824 1003 825 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) 1004 826 { 1005 827 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 828 + int ret = 0; 1006 829 1007 830 if (!pp_funcs->get_gpu_metrics) 1008 831 return 0; 1009 832 1010 - return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); 833 + mutex_lock(&adev->pm.mutex); 834 + ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, 835 + table); 836 + mutex_unlock(&adev->pm.mutex); 837 + 838 + return ret; 1011 839 } 1012 840 1013 841 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, ··· 1034 830 if (!pp_funcs->get_fan_control_mode) 1035 831 return -EOPNOTSUPP; 1036 832 833 + mutex_lock(&adev->pm.mutex); 1037 834 *fan_mode = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle); 835 + mutex_unlock(&adev->pm.mutex); 1038 836 1039 837 return 0; 1040 838 } ··· 1045 839 uint32_t speed) 1046 840 { 1047 841 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 842 + int ret = 0; 1048 843 1049 844 if (!pp_funcs->set_fan_speed_pwm) 1050 845 return -EINVAL; 1051 846 1052 - return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); 847 + mutex_lock(&adev->pm.mutex); 848 + ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, 849 + speed); 850 + mutex_unlock(&adev->pm.mutex); 851 + 852 + return ret; 1053 853 } 1054 854 1055 855 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 1056 856 uint32_t *speed) 1057 857 { 1058 858 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 859 + int ret = 0; 1059 860 1060 861 if (!pp_funcs->get_fan_speed_pwm) 1061 862 return -EINVAL; 1062 863 1063 - return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); 864 + mutex_lock(&adev->pm.mutex); 865 + ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, 866 + speed); 867 + mutex_unlock(&adev->pm.mutex); 868 + 869 + return ret; 1064 870 } 1065 871 1066 872 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 1067 873 uint32_t *speed) 1068 874 { 1069 875 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 876 + int ret = 0; 1070 877 1071 878 if (!pp_funcs->get_fan_speed_rpm) 1072 879 return -EINVAL; 1073 880 1074 - return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); 881 + mutex_lock(&adev->pm.mutex); 882 + ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, 883 + speed); 884 + mutex_unlock(&adev->pm.mutex); 885 + 886 + return ret; 1075 887 } 1076 888 1077 889 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 1078 890 uint32_t speed) 1079 891 { 1080 892 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 893 + int ret = 0; 1081 894 1082 895 if (!pp_funcs->set_fan_speed_rpm) 1083 896 return -EINVAL; 1084 897 1085 - return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); 898 + mutex_lock(&adev->pm.mutex); 899 + ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, 900 + speed); 901 + mutex_unlock(&adev->pm.mutex); 902 + 903 + return ret; 1086 904 } 1087 905 1088 906 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, ··· 1117 887 if (!pp_funcs->set_fan_control_mode) 1118 888 return -EOPNOTSUPP; 1119 889 1120 - pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); 890 + mutex_lock(&adev->pm.mutex); 891 + pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, 892 + mode); 893 + mutex_unlock(&adev->pm.mutex); 1121 894 1122 895 return 0; 1123 896 } ··· 1131 898 enum pp_power_type power_type) 1132 899 { 1133 900 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 901 + int ret = 0; 1134 902 1135 903 if (!pp_funcs->get_power_limit) 1136 904 return -ENODATA; 1137 905 1138 - return pp_funcs->get_power_limit(adev->powerplay.pp_handle, 1139 - limit, 1140 - pp_limit_level, 1141 - power_type); 906 + mutex_lock(&adev->pm.mutex); 907 + ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, 908 + limit, 909 + pp_limit_level, 910 + power_type); 911 + mutex_unlock(&adev->pm.mutex); 912 + 913 + return ret; 1142 914 } 1143 915 1144 916 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 1145 917 uint32_t limit) 1146 918 { 1147 919 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 920 + int ret = 0; 1148 921 1149 922 if (!pp_funcs->set_power_limit) 1150 923 return -EINVAL; 1151 924 1152 - return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit); 925 + mutex_lock(&adev->pm.mutex); 926 + ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, 927 + limit); 928 + mutex_unlock(&adev->pm.mutex); 929 + 930 + return ret; 1153 931 } 1154 932 1155 933 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) 1156 934 { 935 + bool cclk_dpm_supported = false; 936 + 1157 937 if (!is_support_sw_smu(adev)) 1158 938 return false; 1159 939 1160 - return is_support_cclk_dpm(adev); 940 + mutex_lock(&adev->pm.mutex); 941 + cclk_dpm_supported = is_support_cclk_dpm(adev); 942 + mutex_unlock(&adev->pm.mutex); 943 + 944 + return (int)cclk_dpm_supported; 1161 945 } 1162 946 1163 947 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, ··· 1185 935 if (!pp_funcs->debugfs_print_current_performance_level) 1186 936 return -EOPNOTSUPP; 1187 937 938 + mutex_lock(&adev->pm.mutex); 1188 939 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, 1189 940 m); 941 + mutex_unlock(&adev->pm.mutex); 1190 942 1191 943 return 0; 1192 944 } ··· 1198 946 size_t *size) 1199 947 { 1200 948 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 949 + int ret = 0; 1201 950 1202 951 if (!pp_funcs->get_smu_prv_buf_details) 1203 952 return -ENOSYS; 1204 953 1205 - return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 1206 - addr, 1207 - size); 954 + mutex_lock(&adev->pm.mutex); 955 + ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, 956 + addr, 957 + size); 958 + mutex_unlock(&adev->pm.mutex); 959 + 960 + return ret; 1208 961 } 1209 962 1210 963 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) ··· 1230 973 size_t size) 1231 974 { 1232 975 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 976 + int ret = 0; 1233 977 1234 978 if (!pp_funcs->set_pp_table) 1235 979 return -EOPNOTSUPP; 1236 980 1237 - return pp_funcs->set_pp_table(adev->powerplay.pp_handle, 1238 - buf, 1239 - size); 981 + mutex_lock(&adev->pm.mutex); 982 + ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, 983 + buf, 984 + size); 985 + mutex_unlock(&adev->pm.mutex); 986 + 987 + return ret; 1240 988 } 1241 989 1242 990 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) 1243 991 { 1244 992 struct smu_context *smu = adev->powerplay.pp_handle; 993 + 994 + if (!is_support_sw_smu(adev)) 995 + return INT_MAX; 1245 996 1246 997 return smu->cpu_core_num; 1247 998 } ··· 1266 1001 const struct amd_pp_display_configuration *input) 1267 1002 { 1268 1003 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1004 + int ret = 0; 1269 1005 1270 1006 if (!pp_funcs->display_configuration_change) 1271 1007 return 0; 1272 1008 1273 - return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 1274 - input); 1009 + mutex_lock(&adev->pm.mutex); 1010 + ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, 1011 + input); 1012 + mutex_unlock(&adev->pm.mutex); 1013 + 1014 + return ret; 1275 1015 } 1276 1016 1277 1017 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, ··· 1284 1014 struct amd_pp_clocks *clocks) 1285 1015 { 1286 1016 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1017 + int ret = 0; 1287 1018 1288 1019 if (!pp_funcs->get_clock_by_type) 1289 1020 return 0; 1290 1021 1291 - return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 1292 - type, 1293 - clocks); 1022 + mutex_lock(&adev->pm.mutex); 1023 + ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, 1024 + type, 1025 + clocks); 1026 + mutex_unlock(&adev->pm.mutex); 1027 + 1028 + return ret; 1294 1029 } 1295 1030 1296 1031 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 1297 1032 struct amd_pp_simple_clock_info *clocks) 1298 1033 { 1299 1034 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1035 + int ret = 0; 1300 1036 1301 1037 if (!pp_funcs->get_display_mode_validation_clocks) 1302 1038 return 0; 1303 1039 1304 - return pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 1305 - clocks); 1040 + mutex_lock(&adev->pm.mutex); 1041 + ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, 1042 + clocks); 1043 + mutex_unlock(&adev->pm.mutex); 1044 + 1045 + return ret; 1306 1046 } 1307 1047 1308 1048 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, ··· 1320 1040 struct pp_clock_levels_with_latency *clocks) 1321 1041 { 1322 1042 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1043 + int ret = 0; 1323 1044 1324 1045 if (!pp_funcs->get_clock_by_type_with_latency) 1325 1046 return 0; 1326 1047 1327 - return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 1328 - type, 1329 - clocks); 1048 + mutex_lock(&adev->pm.mutex); 1049 + ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, 1050 + type, 1051 + clocks); 1052 + mutex_unlock(&adev->pm.mutex); 1053 + 1054 + return ret; 1330 1055 } 1331 1056 1332 1057 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, ··· 1339 1054 struct pp_clock_levels_with_voltage *clocks) 1340 1055 { 1341 1056 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1057 + int ret = 0; 1342 1058 1343 1059 if (!pp_funcs->get_clock_by_type_with_voltage) 1344 1060 return 0; 1345 1061 1346 - return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 1347 - type, 1348 - clocks); 1062 + mutex_lock(&adev->pm.mutex); 1063 + ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, 1064 + type, 1065 + clocks); 1066 + mutex_unlock(&adev->pm.mutex); 1067 + 1068 + return ret; 1349 1069 } 1350 1070 1351 1071 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 1352 1072 void *clock_ranges) 1353 1073 { 1354 1074 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1075 + int ret = 0; 1355 1076 1356 1077 if (!pp_funcs->set_watermarks_for_clocks_ranges) 1357 1078 return -EOPNOTSUPP; 1358 1079 1359 - return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 1360 - clock_ranges); 1080 + mutex_lock(&adev->pm.mutex); 1081 + ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, 1082 + clock_ranges); 1083 + mutex_unlock(&adev->pm.mutex); 1084 + 1085 + return ret; 1361 1086 } 1362 1087 1363 1088 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 1364 1089 struct pp_display_clock_request *clock) 1365 1090 { 1366 1091 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1092 + int ret = 0; 1367 1093 1368 1094 if (!pp_funcs->display_clock_voltage_request) 1369 1095 return -EOPNOTSUPP; 1370 1096 1371 - return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 1372 - clock); 1097 + mutex_lock(&adev->pm.mutex); 1098 + ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, 1099 + clock); 1100 + mutex_unlock(&adev->pm.mutex); 1101 + 1102 + return ret; 1373 1103 } 1374 1104 1375 1105 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 1376 1106 struct amd_pp_clock_info *clocks) 1377 1107 { 1378 1108 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1109 + int ret = 0; 1379 1110 1380 1111 if (!pp_funcs->get_current_clocks) 1381 1112 return -EOPNOTSUPP; 1382 1113 1383 - return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 1384 - clocks); 1114 + mutex_lock(&adev->pm.mutex); 1115 + ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, 1116 + clocks); 1117 + mutex_unlock(&adev->pm.mutex); 1118 + 1119 + return ret; 1385 1120 } 1386 1121 1387 1122 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) ··· 1411 1106 if (!pp_funcs->notify_smu_enable_pwe) 1412 1107 return; 1413 1108 1109 + mutex_lock(&adev->pm.mutex); 1414 1110 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); 1111 + mutex_unlock(&adev->pm.mutex); 1415 1112 } 1416 1113 1417 1114 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 1418 1115 uint32_t count) 1419 1116 { 1420 1117 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1118 + int ret = 0; 1421 1119 1422 1120 if (!pp_funcs->set_active_display_count) 1423 1121 return -EOPNOTSUPP; 1424 1122 1425 - return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 1426 - count); 1123 + mutex_lock(&adev->pm.mutex); 1124 + ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, 1125 + count); 1126 + mutex_unlock(&adev->pm.mutex); 1127 + 1128 + return ret; 1427 1129 } 1428 1130 1429 1131 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 1430 1132 uint32_t clock) 1431 1133 { 1432 1134 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1135 + int ret = 0; 1433 1136 1434 1137 if (!pp_funcs->set_min_deep_sleep_dcefclk) 1435 1138 return -EOPNOTSUPP; 1436 1139 1437 - return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 1438 - clock); 1140 + mutex_lock(&adev->pm.mutex); 1141 + ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, 1142 + clock); 1143 + mutex_unlock(&adev->pm.mutex); 1144 + 1145 + return ret; 1439 1146 } 1440 1147 1441 1148 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, ··· 1458 1141 if (!pp_funcs->set_hard_min_dcefclk_by_freq) 1459 1142 return; 1460 1143 1144 + mutex_lock(&adev->pm.mutex); 1461 1145 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, 1462 1146 clock); 1147 + mutex_unlock(&adev->pm.mutex); 1463 1148 } 1464 1149 1465 1150 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, ··· 1472 1153 if (!pp_funcs->set_hard_min_fclk_by_freq) 1473 1154 return; 1474 1155 1156 + mutex_lock(&adev->pm.mutex); 1475 1157 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, 1476 1158 clock); 1159 + mutex_unlock(&adev->pm.mutex); 1477 1160 } 1478 1161 1479 1162 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 1480 1163 bool disable_memory_clock_switch) 1481 1164 { 1482 1165 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1166 + int ret = 0; 1483 1167 1484 1168 if (!pp_funcs->display_disable_memory_clock_switch) 1485 1169 return 0; 1486 1170 1487 - return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 1488 - disable_memory_clock_switch); 1171 + mutex_lock(&adev->pm.mutex); 1172 + ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, 1173 + disable_memory_clock_switch); 1174 + mutex_unlock(&adev->pm.mutex); 1175 + 1176 + return ret; 1489 1177 } 1490 1178 1491 1179 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 1492 1180 struct pp_smu_nv_clock_table *max_clocks) 1493 1181 { 1494 1182 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1183 + int ret = 0; 1495 1184 1496 1185 if (!pp_funcs->get_max_sustainable_clocks_by_dc) 1497 1186 return -EOPNOTSUPP; 1498 1187 1499 - return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 1500 - max_clocks); 1188 + mutex_lock(&adev->pm.mutex); 1189 + ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, 1190 + max_clocks); 1191 + mutex_unlock(&adev->pm.mutex); 1192 + 1193 + return ret; 1501 1194 } 1502 1195 1503 1196 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, ··· 1517 1186 unsigned int *num_states) 1518 1187 { 1519 1188 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1189 + int ret = 0; 1520 1190 1521 1191 if (!pp_funcs->get_uclk_dpm_states) 1522 1192 return -EOPNOTSUPP; 1523 1193 1524 - return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 1525 - clock_values_in_khz, 1526 - num_states); 1194 + mutex_lock(&adev->pm.mutex); 1195 + ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, 1196 + clock_values_in_khz, 1197 + num_states); 1198 + mutex_unlock(&adev->pm.mutex); 1199 + 1200 + return ret; 1527 1201 } 1528 1202 1529 1203 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 1530 1204 struct dpm_clocks *clock_table) 1531 1205 { 1532 1206 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 1207 + int ret = 0; 1533 1208 1534 1209 if (!pp_funcs->get_dpm_clock_table) 1535 1210 return -EOPNOTSUPP; 1536 1211 1537 - return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 1538 - clock_table); 1212 + mutex_lock(&adev->pm.mutex); 1213 + ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, 1214 + clock_table); 1215 + mutex_unlock(&adev->pm.mutex); 1216 + 1217 + return ret; 1539 1218 }
+1 -15
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
··· 3040 3040 return 0; 3041 3041 3042 3042 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 3043 - mutex_lock(&adev->pm.mutex); 3044 3043 ret = kv_dpm_init(adev); 3045 3044 if (ret) 3046 3045 goto dpm_failed; 3047 3046 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 3048 3047 if (amdgpu_dpm == 1) 3049 3048 amdgpu_pm_print_power_states(adev); 3050 - mutex_unlock(&adev->pm.mutex); 3051 3049 DRM_INFO("amdgpu: dpm initialized\n"); 3052 3050 3053 3051 return 0; 3054 3052 3055 3053 dpm_failed: 3056 3054 kv_dpm_fini(adev); 3057 - mutex_unlock(&adev->pm.mutex); 3058 3055 DRM_ERROR("amdgpu: dpm initialization failed\n"); 3059 3056 return ret; 3060 3057 } ··· 3062 3065 3063 3066 flush_work(&adev->pm.dpm.thermal.work); 3064 3067 3065 - mutex_lock(&adev->pm.mutex); 3066 3068 kv_dpm_fini(adev); 3067 - mutex_unlock(&adev->pm.mutex); 3068 3069 3069 3070 return 0; 3070 3071 } ··· 3075 3080 if (!amdgpu_dpm) 3076 3081 return 0; 3077 3082 3078 - mutex_lock(&adev->pm.mutex); 3079 3083 kv_dpm_setup_asic(adev); 3080 3084 ret = kv_dpm_enable(adev); 3081 3085 if (ret) 3082 3086 adev->pm.dpm_enabled = false; 3083 3087 else 3084 3088 adev->pm.dpm_enabled = true; 3085 - mutex_unlock(&adev->pm.mutex); 3086 3089 amdgpu_legacy_dpm_compute_clocks(adev); 3087 3090 return ret; 3088 3091 } ··· 3089 3096 { 3090 3097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3091 3098 3092 - if (adev->pm.dpm_enabled) { 3093 - mutex_lock(&adev->pm.mutex); 3099 + if (adev->pm.dpm_enabled) 3094 3100 kv_dpm_disable(adev); 3095 - mutex_unlock(&adev->pm.mutex); 3096 - } 3097 3101 3098 3102 return 0; 3099 3103 } ··· 3100 3110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3101 3111 3102 3112 if (adev->pm.dpm_enabled) { 3103 - mutex_lock(&adev->pm.mutex); 3104 3113 /* disable dpm */ 3105 3114 kv_dpm_disable(adev); 3106 3115 /* reset the power state */ 3107 3116 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 3108 - mutex_unlock(&adev->pm.mutex); 3109 3117 } 3110 3118 return 0; 3111 3119 } ··· 3115 3127 3116 3128 if (adev->pm.dpm_enabled) { 3117 3129 /* asic init will reset to the boot state */ 3118 - mutex_lock(&adev->pm.mutex); 3119 3130 kv_dpm_setup_asic(adev); 3120 3131 ret = kv_dpm_enable(adev); 3121 3132 if (ret) 3122 3133 adev->pm.dpm_enabled = false; 3123 3134 else 3124 3135 adev->pm.dpm_enabled = true; 3125 - mutex_unlock(&adev->pm.mutex); 3126 3136 if (adev->pm.dpm_enabled) 3127 3137 amdgpu_legacy_dpm_compute_clocks(adev); 3128 3138 }
+1 -15
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
··· 7786 7786 return ret; 7787 7787 7788 7788 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7789 - mutex_lock(&adev->pm.mutex); 7790 7789 ret = si_dpm_init(adev); 7791 7790 if (ret) 7792 7791 goto dpm_failed; 7793 7792 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7794 7793 if (amdgpu_dpm == 1) 7795 7794 amdgpu_pm_print_power_states(adev); 7796 - mutex_unlock(&adev->pm.mutex); 7797 7795 DRM_INFO("amdgpu: dpm initialized\n"); 7798 7796 7799 7797 return 0; 7800 7798 7801 7799 dpm_failed: 7802 7800 si_dpm_fini(adev); 7803 - mutex_unlock(&adev->pm.mutex); 7804 7801 DRM_ERROR("amdgpu: dpm initialization failed\n"); 7805 7802 return ret; 7806 7803 } ··· 7808 7811 7809 7812 flush_work(&adev->pm.dpm.thermal.work); 7810 7813 7811 - mutex_lock(&adev->pm.mutex); 7812 7814 si_dpm_fini(adev); 7813 - mutex_unlock(&adev->pm.mutex); 7814 7815 7815 7816 return 0; 7816 7817 } ··· 7822 7827 if (!amdgpu_dpm) 7823 7828 return 0; 7824 7829 7825 - mutex_lock(&adev->pm.mutex); 7826 7830 si_dpm_setup_asic(adev); 7827 7831 ret = si_dpm_enable(adev); 7828 7832 if (ret) 7829 7833 adev->pm.dpm_enabled = false; 7830 7834 else 7831 7835 adev->pm.dpm_enabled = true; 7832 - mutex_unlock(&adev->pm.mutex); 7833 7836 amdgpu_legacy_dpm_compute_clocks(adev); 7834 7837 return ret; 7835 7838 } ··· 7836 7843 { 7837 7844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7838 7845 7839 - if (adev->pm.dpm_enabled) { 7840 - mutex_lock(&adev->pm.mutex); 7846 + if (adev->pm.dpm_enabled) 7841 7847 si_dpm_disable(adev); 7842 - mutex_unlock(&adev->pm.mutex); 7843 - } 7844 7848 7845 7849 return 0; 7846 7850 } ··· 7847 7857 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7848 7858 7849 7859 if (adev->pm.dpm_enabled) { 7850 - mutex_lock(&adev->pm.mutex); 7851 7860 /* disable dpm */ 7852 7861 si_dpm_disable(adev); 7853 7862 /* reset the power state */ 7854 7863 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7855 - mutex_unlock(&adev->pm.mutex); 7856 7864 } 7857 7865 return 0; 7858 7866 } ··· 7862 7874 7863 7875 if (adev->pm.dpm_enabled) { 7864 7876 /* asic init will reset to the boot state */ 7865 - mutex_lock(&adev->pm.mutex); 7866 7877 si_dpm_setup_asic(adev); 7867 7878 ret = si_dpm_enable(adev); 7868 7879 if (ret) 7869 7880 adev->pm.dpm_enabled = false; 7870 7881 else 7871 7882 adev->pm.dpm_enabled = true; 7872 - mutex_unlock(&adev->pm.mutex); 7873 7883 if (adev->pm.dpm_enabled) 7874 7884 amdgpu_legacy_dpm_compute_clocks(adev); 7875 7885 }