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drm/amd/pm: revise the performance level setting APIs

Avoid cross callings which make lock protection enforcement
on amdgpu_dpm_force_performance_level() impossible.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Evan Quan and committed by
Alex Deucher 61d7d0d5 3bce90bf

+34 -42
-2
drivers/gpu/drm/amd/include/amd_shared.h
··· 268 268 * @set_clockgating_state: enable/disable cg for the IP block 269 269 * @set_powergating_state: enable/disable pg for the IP block 270 270 * @get_clockgating_state: get current clockgating status 271 - * @enable_umd_pstate: enable UMD powerstate 272 271 * 273 272 * These hooks provide an interface for controlling the operational state 274 273 * of IP blocks. After acquiring a list of IP blocks for the GPU in use, ··· 298 299 int (*set_powergating_state)(void *handle, 299 300 enum amd_powergating_state state); 300 301 void (*get_clockgating_state)(void *handle, u32 *flags); 301 - int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level); 302 302 }; 303 303 304 304
+25 -4
drivers/gpu/drm/amd/pm/amdgpu_pm.c
··· 300 300 struct amdgpu_device *adev = drm_to_adev(ddev); 301 301 enum amd_dpm_forced_level level; 302 302 enum amd_dpm_forced_level current_level; 303 + uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 304 + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 305 + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 306 + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 303 307 int ret = 0; 304 308 305 309 if (amdgpu_in_reset(adev)) ··· 358 354 } 359 355 360 356 /* profile_exit setting is valid only when current mode is in profile mode */ 361 - if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 362 - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 363 - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 364 - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) && 357 + if (!(current_level & profile_mode_mask) && 365 358 (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) { 366 359 pr_err("Currently not in any profile mode!\n"); 367 360 pm_runtime_mark_last_busy(ddev->dev); 368 361 pm_runtime_put_autosuspend(ddev->dev); 369 362 return -EINVAL; 363 + } 364 + 365 + if (!(current_level & profile_mode_mask) && 366 + (level & profile_mode_mask)) { 367 + /* enter UMD Pstate */ 368 + amdgpu_device_ip_set_powergating_state(adev, 369 + AMD_IP_BLOCK_TYPE_GFX, 370 + AMD_PG_STATE_UNGATE); 371 + amdgpu_device_ip_set_clockgating_state(adev, 372 + AMD_IP_BLOCK_TYPE_GFX, 373 + AMD_CG_STATE_UNGATE); 374 + } else if ((current_level & profile_mode_mask) && 375 + !(level & profile_mode_mask)) { 376 + /* exit UMD Pstate */ 377 + amdgpu_device_ip_set_clockgating_state(adev, 378 + AMD_IP_BLOCK_TYPE_GFX, 379 + AMD_CG_STATE_GATE); 380 + amdgpu_device_ip_set_powergating_state(adev, 381 + AMD_IP_BLOCK_TYPE_GFX, 382 + AMD_PG_STATE_GATE); 370 383 } 371 384 372 385 if (amdgpu_dpm_force_performance_level(adev, level)) {
+9 -8
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
··· 953 953 954 954 static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) 955 955 { 956 + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 956 957 struct amdgpu_ps *ps; 957 958 enum amd_pm_state_type dpm_state; 958 959 int ret; ··· 977 976 else 978 977 return -EINVAL; 979 978 980 - if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) { 979 + if (amdgpu_dpm == 1 && pp_funcs->print_power_state) { 981 980 printk("switching from power state:\n"); 982 981 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); 983 982 printk("switching to power state:\n"); ··· 986 985 987 986 /* update whether vce is active */ 988 987 ps->vce_active = adev->pm.dpm.vce_active; 989 - if (adev->powerplay.pp_funcs->display_configuration_changed) 988 + if (pp_funcs->display_configuration_changed) 990 989 amdgpu_dpm_display_configuration_changed(adev); 991 990 992 991 ret = amdgpu_dpm_pre_set_power_state(adev); 993 992 if (ret) 994 993 return ret; 995 994 996 - if (adev->powerplay.pp_funcs->check_state_equal) { 995 + if (pp_funcs->check_state_equal) { 997 996 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)) 998 997 equal = false; 999 998 } ··· 1001 1000 if (equal) 1002 1001 return 0; 1003 1002 1004 - if (adev->powerplay.pp_funcs->set_power_state) 1005 - adev->powerplay.pp_funcs->set_power_state(adev->powerplay.pp_handle); 1003 + if (pp_funcs->set_power_state) 1004 + pp_funcs->set_power_state(adev->powerplay.pp_handle); 1006 1005 1007 1006 amdgpu_dpm_post_set_power_state(adev); 1008 1007 1009 1008 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; 1010 1009 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; 1011 1010 1012 - if (adev->powerplay.pp_funcs->force_performance_level) { 1011 + if (pp_funcs->force_performance_level) { 1013 1012 if (adev->pm.dpm.thermal_active) { 1014 1013 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; 1015 1014 /* force low perf level for thermal */ 1016 - amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW); 1015 + pp_funcs->force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW); 1017 1016 /* save the user's level */ 1018 1017 adev->pm.dpm.forced_level = level; 1019 1018 } else { 1020 1019 /* otherwise, user selected level */ 1021 - amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); 1020 + pp_funcs->force_performance_level(adev, adev->pm.dpm.forced_level); 1022 1021 } 1023 1022 } 1024 1023
-12
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
··· 323 323 if (*level & profile_mode_mask) { 324 324 hwmgr->saved_dpm_level = hwmgr->dpm_level; 325 325 hwmgr->en_umd_pstate = true; 326 - amdgpu_device_ip_set_powergating_state(hwmgr->adev, 327 - AMD_IP_BLOCK_TYPE_GFX, 328 - AMD_PG_STATE_UNGATE); 329 - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, 330 - AMD_IP_BLOCK_TYPE_GFX, 331 - AMD_CG_STATE_UNGATE); 332 326 } 333 327 } else { 334 328 /* exit umd pstate, restore level, enable gfx cg*/ ··· 330 336 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 331 337 *level = hwmgr->saved_dpm_level; 332 338 hwmgr->en_umd_pstate = false; 333 - amdgpu_device_ip_set_clockgating_state(hwmgr->adev, 334 - AMD_IP_BLOCK_TYPE_GFX, 335 - AMD_CG_STATE_GATE); 336 - amdgpu_device_ip_set_powergating_state(hwmgr->adev, 337 - AMD_IP_BLOCK_TYPE_GFX, 338 - AMD_PG_STATE_GATE); 339 339 } 340 340 } 341 341 }
-15
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 1677 1677 /* enter umd pstate, save current level, disable gfx cg*/ 1678 1678 if (*level & profile_mode_mask) { 1679 1679 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1680 - smu_dpm_ctx->enable_umd_pstate = true; 1681 1680 smu_gpo_control(smu, false); 1682 - amdgpu_device_ip_set_powergating_state(smu->adev, 1683 - AMD_IP_BLOCK_TYPE_GFX, 1684 - AMD_PG_STATE_UNGATE); 1685 - amdgpu_device_ip_set_clockgating_state(smu->adev, 1686 - AMD_IP_BLOCK_TYPE_GFX, 1687 - AMD_CG_STATE_UNGATE); 1688 1681 smu_gfx_ulv_control(smu, false); 1689 1682 smu_deep_sleep_control(smu, false); 1690 1683 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); ··· 1687 1694 if (!(*level & profile_mode_mask)) { 1688 1695 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1689 1696 *level = smu_dpm_ctx->saved_dpm_level; 1690 - smu_dpm_ctx->enable_umd_pstate = false; 1691 1697 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1692 1698 smu_deep_sleep_control(smu, true); 1693 1699 smu_gfx_ulv_control(smu, true); 1694 - amdgpu_device_ip_set_clockgating_state(smu->adev, 1695 - AMD_IP_BLOCK_TYPE_GFX, 1696 - AMD_CG_STATE_GATE); 1697 - amdgpu_device_ip_set_powergating_state(smu->adev, 1698 - AMD_IP_BLOCK_TYPE_GFX, 1699 - AMD_PG_STATE_GATE); 1700 1700 smu_gpo_control(smu, true); 1701 1701 } 1702 1702 } ··· 2135 2149 .soft_reset = NULL, 2136 2150 .set_clockgating_state = smu_set_clockgating_state, 2137 2151 .set_powergating_state = smu_set_powergating_state, 2138 - .enable_umd_pstate = smu_enable_umd_pstate, 2139 2152 }; 2140 2153 2141 2154 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
-1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 363 363 uint32_t dpm_context_size; 364 364 void *dpm_context; 365 365 void *golden_dpm_context; 366 - bool enable_umd_pstate; 367 366 enum amd_dpm_forced_level dpm_level; 368 367 enum amd_dpm_forced_level saved_dpm_level; 369 368 enum amd_dpm_forced_level requested_dpm_level;