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drm/amd/display: Silence type conversion warnings in dml2

[Why]
Compiler build generates type conversion warnings throughout dc/dml2_0
where values are implicitly narrowed (e.g. int/uint32_t/uint64_t assigned
to uint8_t, unsigned char, char, bool, or dml_bool_t), cluttering build
output and masking genuine issues.

[How]
Add explicit casts at each narrowing assignment with ASSERT guards
to catch out-of-range values in debug builds:
- uint8_t: otg_inst, num_planes, pipe_idx, vblank_index fields
- unsigned char: pipe_dlg_param.otg_inst from tg->inst
- char: mcache num_pipes from num_dpps_required
- bool/dml_bool_t: INTERLACE bitfield and fams2 enable flag use != 0
- uint64_t: widen min_hardware_refresh_in_uhz to hold div64_u64 result,
then cast to unsigned long for min_refresh_uhz with ASSERT

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Gaghik Khachatrian and committed by
Alex Deucher 3722df98 c3f327a9

+41 -19
+9 -4
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
··· 90 90 struct pipe_ctx *pipe_ctx, 91 91 struct dml2_context *dml_ctx) 92 92 { 93 - unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz; 93 + unsigned int hblank_start, vblank_start; 94 + uint64_t min_hardware_refresh_in_uhz; 94 95 uint32_t pix_clk_100hz; 95 96 96 97 timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; ··· 106 105 timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding; 107 106 timing->v_total = stream->timing.v_total; 108 107 timing->h_sync_width = stream->timing.h_sync_width; 109 - timing->interlaced = stream->timing.flags.INTERLACE; 108 + timing->interlaced = (stream->timing.flags.INTERLACE != 0); 110 109 111 110 hblank_start = stream->timing.h_total - stream->timing.h_front_porch; 112 111 ··· 138 137 (timing->h_total * (long long)calc_max_hardware_v_total(stream))); 139 138 } 140 139 141 - timing->drr_config.min_refresh_uhz = max(stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz); 140 + { 141 + uint64_t min_refresh = max((uint64_t)stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz); 142 + ASSERT(min_refresh <= ULONG_MAX); 143 + timing->drr_config.min_refresh_uhz = (unsigned long)min_refresh; 144 + } 142 145 143 146 if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase && 144 147 stream->ctx->dc->config.enable_fpo_flicker_detection == 1) ··· 702 697 703 698 if (!dml21_wrapper_get_plane_id(context, stream_id, plane, &plane_id)) { 704 699 ASSERT(false); 705 - return -1; 700 + return UINT_MAX; 706 701 } 707 702 708 703 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
+11 -4
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
··· 420 420 type = static_base_state->stream_v1.base.type; 421 421 422 422 /* get information from context */ 423 - static_base_state->stream_v1.base.num_planes = context->stream_status[dc_stream_idx].plane_count; 424 - static_base_state->stream_v1.base.otg_inst = context->stream_status[dc_stream_idx].primary_otg_inst; 423 + ASSERT(context->stream_status[dc_stream_idx].plane_count >= 0 && 424 + context->stream_status[dc_stream_idx].plane_count <= 0xFF); 425 + ASSERT(context->stream_status[dc_stream_idx].primary_otg_inst >= 0 && 426 + context->stream_status[dc_stream_idx].primary_otg_inst <= 0xFF); 427 + static_base_state->stream_v1.base.num_planes = (uint8_t)context->stream_status[dc_stream_idx].plane_count; 428 + static_base_state->stream_v1.base.otg_inst = (uint8_t)context->stream_status[dc_stream_idx].primary_otg_inst; 425 429 426 430 /* populate pipe masks for planes */ 427 431 for (dc_plane_idx = 0; dc_plane_idx < context->stream_status[dc_stream_idx].plane_count; dc_plane_idx++) { ··· 462 458 switch (dc->debug.fams_version.minor) { 463 459 case 1: 464 460 default: 465 - static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; 461 + ASSERT(phantom_status->primary_otg_inst >= 0 && 462 + phantom_status->primary_otg_inst <= 0xFF); 463 + static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = (uint8_t)phantom_status->primary_otg_inst; 466 464 467 465 /* populate pipe masks for phantom planes */ 468 466 for (dc_plane_idx = 0; dc_plane_idx < phantom_status->plane_count; dc_plane_idx++) { ··· 522 516 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; 523 517 } 524 518 525 - context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; 519 + context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = 520 + (context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0); 526 521 } 527 522 528 523 bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format)
+4 -2
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper_fpu.c
··· 297 297 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 298 298 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 299 299 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_prog_idx]; 300 - mcache_config->num_pipes = pln_prog->num_dpps_required; 300 + ASSERT(pln_prog->num_dpps_required <= 0x7F); 301 + mcache_config->num_pipes = (char)pln_prog->num_dpps_required; 301 302 l->build_mcache_programming_params.num_configurations++; 302 303 303 304 if (pln_prog->num_dpps_required == 0) { ··· 325 324 memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor)); 326 325 mcache_config->plane_descriptor = pln_prog->plane_descriptor; 327 326 mcache_config->mcache_allocation = &context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx]; 328 - mcache_config->num_pipes = pln_prog->num_dpps_required; 327 + ASSERT(pln_prog->num_dpps_required <= 0x7F); 328 + mcache_config->num_pipes = (char)pln_prog->num_dpps_required; 329 329 l->build_mcache_programming_params.num_configurations++; 330 330 331 331 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
+12 -6
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c
··· 366 366 if (!is_plane_using_pipe(pipe)) { 367 367 pipes_needed--; 368 368 // TODO: This doens't make sense really, pipe_idx should always be valid 369 - pipe->pipe_idx = preferred_pipe_candidates[i]; 369 + ASSERT(preferred_pipe_candidates[i] <= 0xFF); 370 + pipe->pipe_idx = (uint8_t)preferred_pipe_candidates[i]; 370 371 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 371 372 } 372 373 } ··· 383 382 if (!is_plane_using_pipe(pipe)) { 384 383 pipes_needed--; 385 384 // TODO: This doens't make sense really, pipe_idx should always be valid 386 - pipe->pipe_idx = i; 385 + ASSERT(i >= 0 && i <= 0xFF); 386 + pipe->pipe_idx = (uint8_t)i; 387 387 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 388 388 } 389 389 } ··· 395 393 if (!is_plane_using_pipe(pipe)) { 396 394 pipes_needed--; 397 395 // TODO: This doens't make sense really, pipe_idx should always be valid 398 - pipe->pipe_idx = last_resort_pipe_candidates[i]; 396 + ASSERT(last_resort_pipe_candidates[i] <= 0xFF); 397 + pipe->pipe_idx = (uint8_t)last_resort_pipe_candidates[i]; 399 398 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 400 399 } 401 400 } ··· 435 432 if (is_pipe_free(pipe)) { 436 433 pipes_needed--; 437 434 // TODO: This doens't make sense really, pipe_idx should always be valid 438 - pipe->pipe_idx = preferred_pipe_candidates[i]; 435 + ASSERT(preferred_pipe_candidates[i] <= 0xFF); 436 + pipe->pipe_idx = (uint8_t)preferred_pipe_candidates[i]; 439 437 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 440 438 } 441 439 } ··· 452 448 if (is_pipe_free(pipe)) { 453 449 pipes_needed--; 454 450 // TODO: This doens't make sense really, pipe_idx should always be valid 455 - pipe->pipe_idx = i; 451 + ASSERT(i >= 0 && i <= 0xFF); 452 + pipe->pipe_idx = (uint8_t)i; 456 453 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 457 454 } 458 455 } ··· 464 459 if (is_pipe_free(pipe)) { 465 460 pipes_needed--; 466 461 // TODO: This doens't make sense really, pipe_idx should always be valid 467 - pipe->pipe_idx = last_resort_pipe_candidates[i]; 462 + ASSERT(last_resort_pipe_candidates[i] <= 0xFF); 463 + pipe->pipe_idx = (uint8_t)last_resort_pipe_candidates[i]; 468 464 assigned_pipes[(*assigned_pipe_count)++] = pipe->pipe_idx; 469 465 } 470 466 }
+2 -1
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
··· 555 555 556 556 if (!found && pipe_mall_type == SUBVP_NONE) { 557 557 // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). 558 - vblank_index = i; 558 + ASSERT(i <= 0xFF); 559 + vblank_index = (uint8_t)i; 559 560 found = true; 560 561 } 561 562
+1 -1
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
··· 765 765 out->PixelClock[location] *= 2; 766 766 out->HTotal[location] = in->timing.h_total; 767 767 out->VTotal[location] = in->timing.v_total; 768 - out->Interlace[location] = in->timing.flags.INTERLACE; 768 + out->Interlace[location] = (in->timing.flags.INTERLACE != 0); 769 769 hblank_start = in->timing.h_total - in->timing.h_front_porch; 770 770 out->HBlankEnd[location] = hblank_start 771 771 - in->timing.h_addressable
+2 -1
drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
··· 255 255 pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx); 256 256 pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx); 257 257 258 - pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst; 258 + ASSERT(pipe_ctx->stream_res.tg->inst >= 0 && pipe_ctx->stream_res.tg->inst <= 0xFF); 259 + pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst; 259 260 260 261 pipe_ctx->pipe_dlg_param.hactive = hactive; 261 262 pipe_ctx->pipe_dlg_param.vactive = vactive;