+2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

reviewed

··· 194 194 const struct dmub_window *cw6, 195 195 const struct dmub_window *region6) 196 196 { 197 197 + (void)region6; 197 198 union dmub_addr offset; 198 199 uint64_t fb_base, fb_offset; 199 200 ··· 397 396 398 397 void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 399 398 { 399 399 + (void)params; 400 400 union dmub_fw_boot_options boot_options = {0}; 401 401 402 402 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);

+1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

reviewed

··· 127 127 const struct dmub_window *cw6, 128 128 const struct dmub_window *region6) 129 129 { 130 130 + (void)region6; 130 131 union dmub_addr offset; 131 132 132 133 /* sienna_cichlid has hardwired virtual addressing for CW2-CW7 */

+2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

reviewed

··· 195 195 const struct dmub_window *cw6, 196 196 const struct dmub_window *region6) 197 197 { 198 198 + (void)cw2; 199 199 + (void)region6; 198 200 union dmub_addr offset; 199 201 200 202 offset = cw3->offset;

+2

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

reviewed

··· 237 237 const struct dmub_window *cw6, 238 238 const struct dmub_window *region6) 239 239 { 240 240 + (void)cw2; 241 241 + (void)region6; 240 242 union dmub_addr offset; 241 243 242 244 offset = cw3->offset;

+1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

reviewed

··· 222 222 const struct dmub_window *cw6, 223 223 const struct dmub_window *region6) 224 224 { 225 225 + (void)cw2; 225 226 union dmub_addr offset; 226 227 227 228 offset = cw3->offset;

+1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

reviewed

··· 213 213 const struct dmub_window *cw6, 214 214 const struct dmub_window *region6) 215 215 { 216 216 + (void)cw2; 216 217 union dmub_addr offset; 217 218 218 219 offset = cw3->offset;

+1

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

reviewed

··· 229 229 const struct dmub_window *cw6, 230 230 const struct dmub_window *region6) 231 231 { 232 232 + (void)cw2; 232 233 union dmub_addr offset; 233 234 234 235 offset = cw3->offset;

+1

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

reviewed

··· 45 45 uint32_t mask1, uint32_t field_value1, 46 46 va_list ap) 47 47 { 48 48 + (void)addr; 48 49 uint32_t shift, mask, field_value; 49 50 int i = 1; 50 51