Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rockchip: inno_hdmi: Refactor register macros to make checkpatch happy
1. Prefer using the BIT macro
2. Macro argument 'n' as '(n)' to avoid precedence issues
3. Add a blank line after enum declarations
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250512124615.2848731-3-andyshrk@163.com
authored by
Andy Yan
and committed by
Heiko Stuebner
372a927f
9c3111df
+113
-101
+113
-101
drivers/gpu/drm/rockchip/inno_hdmi.c
+113
-101
drivers/gpu/drm/rockchip/inno_hdmi.c
···
39
39
#define DDC_BUS_FREQ_H 0x4c
40
40
41
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#define HDMI_SYS_CTRL 0x00
42
-
#define m_RST_ANALOG (1 << 6)
42
+
#define m_RST_ANALOG BIT(6)
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#define v_RST_ANALOG (0 << 6)
44
-
#define v_NOT_RST_ANALOG (1 << 6)
45
-
#define m_RST_DIGITAL (1 << 5)
44
+
#define v_NOT_RST_ANALOG BIT(6)
45
+
#define m_RST_DIGITAL BIT(5)
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#define v_RST_DIGITAL (0 << 5)
47
-
#define v_NOT_RST_DIGITAL (1 << 5)
48
-
#define m_REG_CLK_INV (1 << 4)
47
+
#define v_NOT_RST_DIGITAL BIT(5)
48
+
#define m_REG_CLK_INV BIT(4)
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#define v_REG_CLK_NOT_INV (0 << 4)
50
-
#define v_REG_CLK_INV (1 << 4)
51
-
#define m_VCLK_INV (1 << 3)
50
+
#define v_REG_CLK_INV BIT(4)
51
+
#define m_VCLK_INV BIT(3)
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#define v_VCLK_NOT_INV (0 << 3)
53
-
#define v_VCLK_INV (1 << 3)
54
-
#define m_REG_CLK_SOURCE (1 << 2)
53
+
#define v_VCLK_INV BIT(3)
54
+
#define m_REG_CLK_SOURCE BIT(2)
55
55
#define v_REG_CLK_SOURCE_TMDS (0 << 2)
56
-
#define v_REG_CLK_SOURCE_SYS (1 << 2)
57
-
#define m_POWER (1 << 1)
56
+
#define v_REG_CLK_SOURCE_SYS BIT(2)
57
+
#define m_POWER BIT(1)
58
58
#define v_PWR_ON (0 << 1)
59
-
#define v_PWR_OFF (1 << 1)
60
-
#define m_INT_POL (1 << 0)
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+
#define v_PWR_OFF BIT(1)
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+
#define m_INT_POL BIT(0)
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#define v_INT_POL_HIGH 1
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#define v_INT_POL_LOW 0
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#define HDMI_VIDEO_CONTRL1 0x01
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#define m_VIDEO_INPUT_FORMAT (7 << 1)
66
-
#define m_DE_SOURCE (1 << 0)
67
-
#define v_VIDEO_INPUT_FORMAT(n) (n << 1)
66
+
#define m_DE_SOURCE BIT(0)
67
+
#define v_VIDEO_INPUT_FORMAT(n) ((n) << 1)
68
68
#define v_DE_EXTERNAL 1
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#define v_DE_INTERNAL 0
70
70
enum {
···
76
76
#define HDMI_VIDEO_CONTRL2 0x02
77
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#define m_VIDEO_OUTPUT_COLOR (3 << 6)
78
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#define m_VIDEO_INPUT_BITS (3 << 4)
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-
#define m_VIDEO_INPUT_CSP (1 << 0)
79
+
#define m_VIDEO_INPUT_CSP BIT(0)
80
80
#define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
81
-
#define v_VIDEO_INPUT_BITS(n) (n << 4)
82
-
#define v_VIDEO_INPUT_CSP(n) (n << 0)
81
+
#define v_VIDEO_INPUT_BITS(n) ((n) << 4)
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#define v_VIDEO_INPUT_CSP(n) ((n) << 0)
83
83
enum {
84
84
VIDEO_INPUT_12BITS = 0,
85
85
VIDEO_INPUT_10BITS = 1,
···
88
88
};
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90
#define HDMI_VIDEO_CONTRL 0x03
91
-
#define m_VIDEO_AUTO_CSC (1 << 7)
92
-
#define v_VIDEO_AUTO_CSC(n) (n << 7)
93
-
#define m_VIDEO_C0_C2_SWAP (1 << 0)
94
-
#define v_VIDEO_C0_C2_SWAP(n) (n << 0)
91
+
#define m_VIDEO_AUTO_CSC BIT(7)
92
+
#define v_VIDEO_AUTO_CSC(n) ((n) << 7)
93
+
#define m_VIDEO_C0_C2_SWAP BIT(0)
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+
#define v_VIDEO_C0_C2_SWAP(n) ((n) << 0)
95
95
enum {
96
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C0_C2_CHANGE_ENABLE = 0,
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C0_C2_CHANGE_DISABLE = 1,
···
100
100
};
101
101
102
102
#define HDMI_VIDEO_CONTRL3 0x04
103
-
#define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
104
-
#define m_SOF (1 << 3)
105
-
#define m_COLOR_RANGE (1 << 2)
106
-
#define m_CSC (1 << 0)
103
+
#define m_COLOR_DEPTH_NOT_INDICATED BIT(4)
104
+
#define m_SOF BIT(3)
105
+
#define m_COLOR_RANGE BIT(2)
106
+
#define m_CSC BIT(0)
107
107
#define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
108
108
#define v_SOF_ENABLE (0 << 3)
109
-
#define v_SOF_DISABLE (1 << 3)
110
-
#define v_COLOR_RANGE_FULL (1 << 2)
109
+
#define v_SOF_DISABLE BIT(3)
110
+
#define v_COLOR_RANGE_FULL BIT(2)
111
111
#define v_COLOR_RANGE_LIMITED (0 << 2)
112
112
#define v_CSC_ENABLE 1
113
113
#define v_CSC_DISABLE 0
114
114
115
115
#define HDMI_AV_MUTE 0x05
116
-
#define m_AVMUTE_CLEAR (1 << 7)
117
-
#define m_AVMUTE_ENABLE (1 << 6)
118
-
#define m_AUDIO_MUTE (1 << 1)
119
-
#define m_VIDEO_BLACK (1 << 0)
120
-
#define v_AVMUTE_CLEAR(n) (n << 7)
121
-
#define v_AVMUTE_ENABLE(n) (n << 6)
122
-
#define v_AUDIO_MUTE(n) (n << 1)
123
-
#define v_VIDEO_MUTE(n) (n << 0)
116
+
#define m_AVMUTE_CLEAR BIT(7)
117
+
#define m_AVMUTE_ENABLE BIT(6)
118
+
#define m_AUDIO_MUTE BIT(1)
119
+
#define m_VIDEO_BLACK BIT(0)
120
+
#define v_AVMUTE_CLEAR(n) ((n) << 7)
121
+
#define v_AVMUTE_ENABLE(n) ((n) << 6)
122
+
#define v_AUDIO_MUTE(n) ((n) << 1)
123
+
#define v_VIDEO_MUTE(n) ((n) << 0)
124
124
125
125
#define HDMI_VIDEO_TIMING_CTL 0x08
126
-
#define v_HSYNC_POLARITY(n) (n << 3)
127
-
#define v_VSYNC_POLARITY(n) (n << 2)
128
-
#define v_INETLACE(n) (n << 1)
129
-
#define v_EXTERANL_VIDEO(n) (n << 0)
126
+
#define v_HSYNC_POLARITY(n) ((n) << 3)
127
+
#define v_VSYNC_POLARITY(n) ((n) << 2)
128
+
#define v_INETLACE(n) ((n) << 1)
129
+
#define v_EXTERANL_VIDEO(n) ((n) << 0)
130
130
131
131
#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
132
132
#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
···
149
149
CTS_SOURCE_INTERNAL = 0,
150
150
CTS_SOURCE_EXTERNAL = 1,
151
151
};
152
-
#define v_CTS_SOURCE(n) (n << 7)
152
+
153
+
#define v_CTS_SOURCE(n) ((n) << 7)
153
154
154
155
enum {
155
156
DOWNSAMPLE_DISABLE = 0,
156
157
DOWNSAMPLE_1_2 = 1,
157
158
DOWNSAMPLE_1_4 = 2,
158
159
};
159
-
#define v_DOWN_SAMPLE(n) (n << 5)
160
+
161
+
#define v_DOWN_SAMPLE(n) ((n) << 5)
160
162
161
163
enum {
162
164
AUDIO_SOURCE_IIS = 0,
163
165
AUDIO_SOURCE_SPDIF = 1,
164
166
};
165
-
#define v_AUDIO_SOURCE(n) (n << 3)
166
167
167
-
#define v_MCLK_ENABLE(n) (n << 2)
168
+
#define v_AUDIO_SOURCE(n) ((n) << 3)
169
+
170
+
#define v_MCLK_ENABLE(n) ((n) << 2)
171
+
168
172
enum {
169
173
MCLK_128FS = 0,
170
174
MCLK_256FS = 1,
171
175
MCLK_384FS = 2,
172
176
MCLK_512FS = 3,
173
177
};
178
+
174
179
#define v_MCLK_RATIO(n) (n)
175
180
176
181
#define AUDIO_SAMPLE_RATE 0x37
182
+
177
183
enum {
178
184
AUDIO_32K = 0x3,
179
185
AUDIO_441K = 0x0,
···
191
185
};
192
186
193
187
#define AUDIO_I2S_MODE 0x38
188
+
194
189
enum {
195
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I2S_CHANNEL_1_2 = 1,
196
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I2S_CHANNEL_3_4 = 3,
197
192
I2S_CHANNEL_5_6 = 7,
198
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I2S_CHANNEL_7_8 = 0xf
199
194
};
195
+
200
196
#define v_I2S_CHANNEL(n) ((n) << 2)
197
+
201
198
enum {
202
199
I2S_STANDARD = 0,
203
200
I2S_LEFT_JUSTIFIED = 1,
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201
I2S_RIGHT_JUSTIFIED = 2,
205
202
};
203
+
206
204
#define v_I2S_MODE(n) (n)
207
205
208
206
#define AUDIO_I2S_MAP 0x39
···
222
212
#define N_192K 0x6000
223
213
224
214
#define HDMI_AUDIO_CHANNEL_STATUS 0x3e
225
-
#define m_AUDIO_STATUS_NLPCM (1 << 7)
226
-
#define m_AUDIO_STATUS_USE (1 << 6)
227
-
#define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
215
+
#define m_AUDIO_STATUS_NLPCM BIT(7)
216
+
#define m_AUDIO_STATUS_USE BIT(6)
217
+
#define m_AUDIO_STATUS_COPYRIGHT BIT(5)
228
218
#define m_AUDIO_STATUS_ADDITION (3 << 2)
229
219
#define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
230
-
#define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
220
+
#define v_AUDIO_STATUS_NLPCM(n) (((n) & 1) << 7)
231
221
#define AUDIO_N_H 0x3f
232
222
#define AUDIO_N_M 0x40
233
223
#define AUDIO_N_L 0x41
···
246
236
247
237
#define HDMI_PACKET_SEND_MANUAL 0x9c
248
238
#define HDMI_PACKET_SEND_AUTO 0x9d
249
-
#define m_PACKET_GCP_EN (1 << 7)
250
-
#define m_PACKET_MSI_EN (1 << 6)
251
-
#define m_PACKET_SDI_EN (1 << 5)
252
-
#define m_PACKET_VSI_EN (1 << 4)
253
-
#define v_PACKET_GCP_EN(n) ((n & 1) << 7)
254
-
#define v_PACKET_MSI_EN(n) ((n & 1) << 6)
255
-
#define v_PACKET_SDI_EN(n) ((n & 1) << 5)
256
-
#define v_PACKET_VSI_EN(n) ((n & 1) << 4)
239
+
#define m_PACKET_GCP_EN BIT(7)
240
+
#define m_PACKET_MSI_EN BIT(6)
241
+
#define m_PACKET_SDI_EN BIT(5)
242
+
#define m_PACKET_VSI_EN BIT(4)
243
+
#define v_PACKET_GCP_EN(n) (((n) & 1) << 7)
244
+
#define v_PACKET_MSI_EN(n) (((n) & 1) << 6)
245
+
#define v_PACKET_SDI_EN(n) (((n) & 1) << 5)
246
+
#define v_PACKET_VSI_EN(n) (((n) & 1) << 4)
257
247
258
248
#define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
249
+
259
250
enum {
260
251
INFOFRAME_VSI = 0x05,
261
252
INFOFRAME_AVI = 0x06,
···
265
254
266
255
#define HDMI_CONTROL_PACKET_ADDR 0xa0
267
256
#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
257
+
268
258
enum {
269
259
AVI_COLOR_MODE_RGB = 0,
270
260
AVI_COLOR_MODE_YCBCR422 = 1,
···
287
275
};
288
276
289
277
#define HDMI_HDCP_CTRL 0x52
290
-
#define m_HDMI_DVI (1 << 1)
291
-
#define v_HDMI_DVI(n) (n << 1)
278
+
#define m_HDMI_DVI BIT(1)
279
+
#define v_HDMI_DVI(n) ((n) << 1)
292
280
293
281
#define HDMI_INTERRUPT_MASK1 0xc0
294
282
#define HDMI_INTERRUPT_STATUS1 0xc1
295
-
#define m_INT_ACTIVE_VSYNC (1 << 5)
296
-
#define m_INT_EDID_READY (1 << 2)
283
+
#define m_INT_ACTIVE_VSYNC BIT(5)
284
+
#define m_INT_EDID_READY BIT(2)
297
285
298
286
#define HDMI_INTERRUPT_MASK2 0xc2
299
287
#define HDMI_INTERRUPT_STATUS2 0xc3
300
-
#define m_INT_HDCP_ERR (1 << 7)
301
-
#define m_INT_BKSV_FLAG (1 << 6)
302
-
#define m_INT_HDCP_OK (1 << 4)
288
+
#define m_INT_HDCP_ERR BIT(7)
289
+
#define m_INT_BKSV_FLAG BIT(6)
290
+
#define m_INT_HDCP_OK BIT(4)
303
291
304
292
#define HDMI_STATUS 0xc8
305
-
#define m_HOTPLUG (1 << 7)
306
-
#define m_MASK_INT_HOTPLUG (1 << 5)
307
-
#define m_INT_HOTPLUG (1 << 1)
308
-
#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
293
+
#define m_HOTPLUG BIT(7)
294
+
#define m_MASK_INT_HOTPLUG BIT(5)
295
+
#define m_INT_HOTPLUG BIT(1)
296
+
#define v_MASK_INT_HOTPLUG(n) (((n) & 0x1) << 5)
309
297
310
298
#define HDMI_COLORBAR 0xc9
311
299
312
300
#define HDMI_PHY_SYNC 0xce
313
301
#define HDMI_PHY_SYS_CTL 0xe0
314
-
#define m_TMDS_CLK_SOURCE (1 << 5)
302
+
#define m_TMDS_CLK_SOURCE BIT(5)
315
303
#define v_TMDS_FROM_PLL (0 << 5)
316
-
#define v_TMDS_FROM_GEN (1 << 5)
317
-
#define m_PHASE_CLK (1 << 4)
304
+
#define v_TMDS_FROM_GEN BIT(5)
305
+
#define m_PHASE_CLK BIT(4)
318
306
#define v_DEFAULT_PHASE (0 << 4)
319
-
#define v_SYNC_PHASE (1 << 4)
320
-
#define m_TMDS_CURRENT_PWR (1 << 3)
307
+
#define v_SYNC_PHASE BIT(4)
308
+
#define m_TMDS_CURRENT_PWR BIT(3)
321
309
#define v_TURN_ON_CURRENT (0 << 3)
322
-
#define v_CAT_OFF_CURRENT (1 << 3)
323
-
#define m_BANDGAP_PWR (1 << 2)
310
+
#define v_CAT_OFF_CURRENT BIT(3)
311
+
#define m_BANDGAP_PWR BIT(2)
324
312
#define v_BANDGAP_PWR_UP (0 << 2)
325
-
#define v_BANDGAP_PWR_DOWN (1 << 2)
326
-
#define m_PLL_PWR (1 << 1)
313
+
#define v_BANDGAP_PWR_DOWN BIT(2)
314
+
#define m_PLL_PWR BIT(1)
327
315
#define v_PLL_PWR_UP (0 << 1)
328
-
#define v_PLL_PWR_DOWN (1 << 1)
329
-
#define m_TMDS_CHG_PWR (1 << 0)
316
+
#define v_PLL_PWR_DOWN BIT(1)
317
+
#define m_TMDS_CHG_PWR BIT(0)
330
318
#define v_TMDS_CHG_PWR_UP (0 << 0)
331
-
#define v_TMDS_CHG_PWR_DOWN (1 << 0)
319
+
#define v_TMDS_CHG_PWR_DOWN BIT(0)
332
320
333
321
#define HDMI_PHY_CHG_PWR 0xe1
334
-
#define v_CLK_CHG_PWR(n) ((n & 1) << 3)
335
-
#define v_DATA_CHG_PWR(n) ((n & 7) << 0)
322
+
#define v_CLK_CHG_PWR(n) (((n) & 1) << 3)
323
+
#define v_DATA_CHG_PWR(n) (((n) & 7) << 0)
336
324
337
325
#define HDMI_PHY_DRIVER 0xe2
338
-
#define v_CLK_MAIN_DRIVER(n) (n << 4)
339
-
#define v_DATA_MAIN_DRIVER(n) (n << 0)
326
+
#define v_CLK_MAIN_DRIVER(n) ((n) << 4)
327
+
#define v_DATA_MAIN_DRIVER(n) ((n) << 0)
340
328
341
329
#define HDMI_PHY_PRE_EMPHASIS 0xe3
342
-
#define v_PRE_EMPHASIS(n) ((n & 7) << 4)
343
-
#define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
344
-
#define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
330
+
#define v_PRE_EMPHASIS(n) (((n) & 7) << 4)
331
+
#define v_CLK_PRE_DRIVER(n) (((n) & 3) << 2)
332
+
#define v_DATA_PRE_DRIVER(n) (((n) & 3) << 0)
345
333
346
334
#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
347
-
#define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
335
+
#define v_FEEDBACK_DIV_LOW(n) ((n) & 0xff)
348
336
#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
349
-
#define v_FEEDBACK_DIV_HIGH(n) (n & 1)
337
+
#define v_FEEDBACK_DIV_HIGH(n) ((n) & 1)
350
338
351
339
#define HDMI_PHY_PRE_DIV_RATIO 0xed
352
-
#define v_PRE_DIV_RATIO(n) (n & 0x1f)
340
+
#define v_PRE_DIV_RATIO(n) ((n) & 0x1f)
353
341
354
342
#define HDMI_CEC_CTRL 0xd0
355
-
#define m_ADJUST_FOR_HISENSE (1 << 6)
356
-
#define m_REJECT_RX_BROADCAST (1 << 5)
357
-
#define m_BUSFREETIME_ENABLE (1 << 2)
358
-
#define m_REJECT_RX (1 << 1)
359
-
#define m_START_TX (1 << 0)
343
+
#define m_ADJUST_FOR_HISENSE BIT(6)
344
+
#define m_REJECT_RX_BROADCAST BIT(5)
345
+
#define m_BUSFREETIME_ENABLE BIT(2)
346
+
#define m_REJECT_RX BIT(1)
347
+
#define m_START_TX BIT(0)
360
348
361
349
#define HDMI_CEC_DATA 0xd1
362
350
#define HDMI_CEC_TX_OFFSET 0xd2
···
366
354
#define HDMI_CEC_TX_LENGTH 0xd6
367
355
#define HDMI_CEC_RX_LENGTH 0xd7
368
356
#define HDMI_CEC_TX_INT_MASK 0xd8
369
-
#define m_TX_DONE (1 << 3)
370
-
#define m_TX_NOACK (1 << 2)
371
-
#define m_TX_BROADCAST_REJ (1 << 1)
372
-
#define m_TX_BUSNOTFREE (1 << 0)
357
+
#define m_TX_DONE BIT(3)
358
+
#define m_TX_NOACK BIT(2)
359
+
#define m_TX_BROADCAST_REJ BIT(1)
360
+
#define m_TX_BUSNOTFREE BIT(0)
373
361
374
362
#define HDMI_CEC_RX_INT_MASK 0xd9
375
-
#define m_RX_LA_ERR (1 << 4)
376
-
#define m_RX_GLITCH (1 << 3)
377
-
#define m_RX_DONE (1 << 0)
363
+
#define m_RX_LA_ERR BIT(4)
364
+
#define m_RX_GLITCH BIT(3)
365
+
#define m_RX_DONE BIT(0)
378
366
379
367
#define HDMI_CEC_TX_INT 0xda
380
368
#define HDMI_CEC_RX_INT 0xdb