Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rockchip: inno_hdmi: Merge register definition to c file
Since this register definition is only use in one single c
file, there is no need to put it in a separate header.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250512124615.2848731-2-andyshrk@163.com
authored by
Andy Yan
and committed by
Heiko Stuebner
9c3111df
52008d6f
+340
-352
+340
-3
drivers/gpu/drm/rockchip/inno_hdmi.c
+340
-3
drivers/gpu/drm/rockchip/inno_hdmi.c
···
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#include "rockchip_drm_drv.h"
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#include "inno_hdmi.h"
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#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
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+
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#define DDC_SEGMENT_ADDR 0x30
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#define HDMI_SCL_RATE (100 * 1000)
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+
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#define DDC_BUS_FREQ_L 0x4b
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#define DDC_BUS_FREQ_H 0x4c
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#define HDMI_SYS_CTRL 0x00
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#define m_RST_ANALOG (1 << 6)
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#define v_RST_ANALOG (0 << 6)
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#define v_NOT_RST_ANALOG (1 << 6)
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#define m_RST_DIGITAL (1 << 5)
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#define v_RST_DIGITAL (0 << 5)
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#define v_NOT_RST_DIGITAL (1 << 5)
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#define m_REG_CLK_INV (1 << 4)
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#define v_REG_CLK_NOT_INV (0 << 4)
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#define v_REG_CLK_INV (1 << 4)
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#define m_VCLK_INV (1 << 3)
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#define v_VCLK_NOT_INV (0 << 3)
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#define v_VCLK_INV (1 << 3)
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#define m_REG_CLK_SOURCE (1 << 2)
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#define v_REG_CLK_SOURCE_TMDS (0 << 2)
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#define v_REG_CLK_SOURCE_SYS (1 << 2)
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#define m_POWER (1 << 1)
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#define v_PWR_ON (0 << 1)
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#define v_PWR_OFF (1 << 1)
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#define m_INT_POL (1 << 0)
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#define v_INT_POL_HIGH 1
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#define v_INT_POL_LOW 0
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+
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#define HDMI_VIDEO_CONTRL1 0x01
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#define m_VIDEO_INPUT_FORMAT (7 << 1)
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#define m_DE_SOURCE (1 << 0)
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#define v_VIDEO_INPUT_FORMAT(n) (n << 1)
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#define v_DE_EXTERNAL 1
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#define v_DE_INTERNAL 0
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enum {
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VIDEO_INPUT_SDR_RGB444 = 0,
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VIDEO_INPUT_DDR_RGB444 = 5,
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VIDEO_INPUT_DDR_YCBCR422 = 6
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};
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#define HDMI_VIDEO_CONTRL2 0x02
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#define m_VIDEO_OUTPUT_COLOR (3 << 6)
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#define m_VIDEO_INPUT_BITS (3 << 4)
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#define m_VIDEO_INPUT_CSP (1 << 0)
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#define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
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#define v_VIDEO_INPUT_BITS(n) (n << 4)
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#define v_VIDEO_INPUT_CSP(n) (n << 0)
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enum {
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VIDEO_INPUT_12BITS = 0,
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VIDEO_INPUT_10BITS = 1,
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VIDEO_INPUT_REVERT = 2,
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VIDEO_INPUT_8BITS = 3,
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};
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#define HDMI_VIDEO_CONTRL 0x03
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#define m_VIDEO_AUTO_CSC (1 << 7)
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#define v_VIDEO_AUTO_CSC(n) (n << 7)
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#define m_VIDEO_C0_C2_SWAP (1 << 0)
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#define v_VIDEO_C0_C2_SWAP(n) (n << 0)
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enum {
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C0_C2_CHANGE_ENABLE = 0,
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C0_C2_CHANGE_DISABLE = 1,
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AUTO_CSC_DISABLE = 0,
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AUTO_CSC_ENABLE = 1,
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};
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#define HDMI_VIDEO_CONTRL3 0x04
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#define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
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#define m_SOF (1 << 3)
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#define m_COLOR_RANGE (1 << 2)
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#define m_CSC (1 << 0)
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#define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
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#define v_SOF_ENABLE (0 << 3)
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#define v_SOF_DISABLE (1 << 3)
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#define v_COLOR_RANGE_FULL (1 << 2)
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#define v_COLOR_RANGE_LIMITED (0 << 2)
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#define v_CSC_ENABLE 1
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#define v_CSC_DISABLE 0
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#define HDMI_AV_MUTE 0x05
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#define m_AVMUTE_CLEAR (1 << 7)
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#define m_AVMUTE_ENABLE (1 << 6)
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#define m_AUDIO_MUTE (1 << 1)
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#define m_VIDEO_BLACK (1 << 0)
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#define v_AVMUTE_CLEAR(n) (n << 7)
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#define v_AVMUTE_ENABLE(n) (n << 6)
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#define v_AUDIO_MUTE(n) (n << 1)
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#define v_VIDEO_MUTE(n) (n << 0)
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#define HDMI_VIDEO_TIMING_CTL 0x08
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#define v_HSYNC_POLARITY(n) (n << 3)
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#define v_VSYNC_POLARITY(n) (n << 2)
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#define v_INETLACE(n) (n << 1)
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#define v_EXTERANL_VIDEO(n) (n << 0)
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#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
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#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
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#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
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#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
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#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
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#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
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#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
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#define HDMI_VIDEO_EXT_HDURATION_H 0x10
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#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
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#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
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#define HDMI_VIDEO_EXT_VBLANK 0x13
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#define HDMI_VIDEO_EXT_VDELAY 0x14
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#define HDMI_VIDEO_EXT_VDURATION 0x15
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#define HDMI_VIDEO_CSC_COEF 0x18
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#define HDMI_AUDIO_CTRL1 0x35
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enum {
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CTS_SOURCE_INTERNAL = 0,
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CTS_SOURCE_EXTERNAL = 1,
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};
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#define v_CTS_SOURCE(n) (n << 7)
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enum {
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DOWNSAMPLE_DISABLE = 0,
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DOWNSAMPLE_1_2 = 1,
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DOWNSAMPLE_1_4 = 2,
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};
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#define v_DOWN_SAMPLE(n) (n << 5)
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enum {
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AUDIO_SOURCE_IIS = 0,
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AUDIO_SOURCE_SPDIF = 1,
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};
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#define v_AUDIO_SOURCE(n) (n << 3)
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#define v_MCLK_ENABLE(n) (n << 2)
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enum {
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MCLK_128FS = 0,
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MCLK_256FS = 1,
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MCLK_384FS = 2,
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MCLK_512FS = 3,
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};
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#define v_MCLK_RATIO(n) (n)
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#define AUDIO_SAMPLE_RATE 0x37
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enum {
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AUDIO_32K = 0x3,
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AUDIO_441K = 0x0,
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AUDIO_48K = 0x2,
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AUDIO_882K = 0x8,
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AUDIO_96K = 0xa,
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AUDIO_1764K = 0xc,
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AUDIO_192K = 0xe,
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};
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#define AUDIO_I2S_MODE 0x38
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enum {
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I2S_CHANNEL_1_2 = 1,
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I2S_CHANNEL_3_4 = 3,
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I2S_CHANNEL_5_6 = 7,
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I2S_CHANNEL_7_8 = 0xf
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};
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#define v_I2S_CHANNEL(n) ((n) << 2)
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enum {
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I2S_STANDARD = 0,
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I2S_LEFT_JUSTIFIED = 1,
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I2S_RIGHT_JUSTIFIED = 2,
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};
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#define v_I2S_MODE(n) (n)
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#define AUDIO_I2S_MAP 0x39
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#define AUDIO_I2S_SWAPS_SPDIF 0x3a
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#define v_SPIDF_FREQ(n) (n)
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#define N_32K 0x1000
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#define N_441K 0x1880
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#define N_882K 0x3100
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#define N_1764K 0x6200
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#define N_48K 0x1800
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#define N_96K 0x3000
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#define N_192K 0x6000
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#define HDMI_AUDIO_CHANNEL_STATUS 0x3e
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#define m_AUDIO_STATUS_NLPCM (1 << 7)
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#define m_AUDIO_STATUS_USE (1 << 6)
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#define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
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#define m_AUDIO_STATUS_ADDITION (3 << 2)
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#define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
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#define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
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#define AUDIO_N_H 0x3f
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#define AUDIO_N_M 0x40
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#define AUDIO_N_L 0x41
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#define HDMI_AUDIO_CTS_H 0x45
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#define HDMI_AUDIO_CTS_M 0x46
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#define HDMI_AUDIO_CTS_L 0x47
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#define HDMI_DDC_CLK_L 0x4b
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#define HDMI_DDC_CLK_H 0x4c
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#define HDMI_EDID_SEGMENT_POINTER 0x4d
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#define HDMI_EDID_WORD_ADDR 0x4e
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#define HDMI_EDID_FIFO_OFFSET 0x4f
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#define HDMI_EDID_FIFO_ADDR 0x50
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#define HDMI_PACKET_SEND_MANUAL 0x9c
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#define HDMI_PACKET_SEND_AUTO 0x9d
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#define m_PACKET_GCP_EN (1 << 7)
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#define m_PACKET_MSI_EN (1 << 6)
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#define m_PACKET_SDI_EN (1 << 5)
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#define m_PACKET_VSI_EN (1 << 4)
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#define v_PACKET_GCP_EN(n) ((n & 1) << 7)
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#define v_PACKET_MSI_EN(n) ((n & 1) << 6)
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#define v_PACKET_SDI_EN(n) ((n & 1) << 5)
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#define v_PACKET_VSI_EN(n) ((n & 1) << 4)
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#define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
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enum {
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INFOFRAME_VSI = 0x05,
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INFOFRAME_AVI = 0x06,
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INFOFRAME_AAI = 0x08,
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};
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#define HDMI_CONTROL_PACKET_ADDR 0xa0
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#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
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enum {
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AVI_COLOR_MODE_RGB = 0,
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AVI_COLOR_MODE_YCBCR422 = 1,
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AVI_COLOR_MODE_YCBCR444 = 2,
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AVI_COLORIMETRY_NO_DATA = 0,
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AVI_COLORIMETRY_SMPTE_170M = 1,
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AVI_COLORIMETRY_ITU709 = 2,
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AVI_COLORIMETRY_EXTENDED = 3,
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AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
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AVI_CODED_FRAME_ASPECT_4_3 = 1,
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AVI_CODED_FRAME_ASPECT_16_9 = 2,
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ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
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ACTIVE_ASPECT_RATE_4_3 = 0x09,
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ACTIVE_ASPECT_RATE_16_9 = 0x0A,
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ACTIVE_ASPECT_RATE_14_9 = 0x0B,
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};
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#define HDMI_HDCP_CTRL 0x52
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#define m_HDMI_DVI (1 << 1)
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#define v_HDMI_DVI(n) (n << 1)
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#define HDMI_INTERRUPT_MASK1 0xc0
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#define HDMI_INTERRUPT_STATUS1 0xc1
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#define m_INT_ACTIVE_VSYNC (1 << 5)
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#define m_INT_EDID_READY (1 << 2)
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#define HDMI_INTERRUPT_MASK2 0xc2
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#define HDMI_INTERRUPT_STATUS2 0xc3
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#define m_INT_HDCP_ERR (1 << 7)
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#define m_INT_BKSV_FLAG (1 << 6)
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#define m_INT_HDCP_OK (1 << 4)
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#define HDMI_STATUS 0xc8
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#define m_HOTPLUG (1 << 7)
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#define m_MASK_INT_HOTPLUG (1 << 5)
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#define m_INT_HOTPLUG (1 << 1)
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#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
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#define HDMI_COLORBAR 0xc9
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#define HDMI_PHY_SYNC 0xce
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#define HDMI_PHY_SYS_CTL 0xe0
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#define m_TMDS_CLK_SOURCE (1 << 5)
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#define v_TMDS_FROM_PLL (0 << 5)
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#define v_TMDS_FROM_GEN (1 << 5)
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#define m_PHASE_CLK (1 << 4)
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#define v_DEFAULT_PHASE (0 << 4)
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#define v_SYNC_PHASE (1 << 4)
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#define m_TMDS_CURRENT_PWR (1 << 3)
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#define v_TURN_ON_CURRENT (0 << 3)
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#define v_CAT_OFF_CURRENT (1 << 3)
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#define m_BANDGAP_PWR (1 << 2)
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#define v_BANDGAP_PWR_UP (0 << 2)
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#define v_BANDGAP_PWR_DOWN (1 << 2)
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#define m_PLL_PWR (1 << 1)
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#define v_PLL_PWR_UP (0 << 1)
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#define v_PLL_PWR_DOWN (1 << 1)
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#define m_TMDS_CHG_PWR (1 << 0)
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#define v_TMDS_CHG_PWR_UP (0 << 0)
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#define v_TMDS_CHG_PWR_DOWN (1 << 0)
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#define HDMI_PHY_CHG_PWR 0xe1
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#define v_CLK_CHG_PWR(n) ((n & 1) << 3)
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#define v_DATA_CHG_PWR(n) ((n & 7) << 0)
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#define HDMI_PHY_DRIVER 0xe2
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#define v_CLK_MAIN_DRIVER(n) (n << 4)
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#define v_DATA_MAIN_DRIVER(n) (n << 0)
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#define HDMI_PHY_PRE_EMPHASIS 0xe3
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#define v_PRE_EMPHASIS(n) ((n & 7) << 4)
331
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#define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
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#define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
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#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
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#define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
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#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
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#define v_FEEDBACK_DIV_HIGH(n) (n & 1)
338
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#define HDMI_PHY_PRE_DIV_RATIO 0xed
340
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#define v_PRE_DIV_RATIO(n) (n & 0x1f)
341
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342
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#define HDMI_CEC_CTRL 0xd0
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#define m_ADJUST_FOR_HISENSE (1 << 6)
344
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#define m_REJECT_RX_BROADCAST (1 << 5)
345
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#define m_BUSFREETIME_ENABLE (1 << 2)
346
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#define m_REJECT_RX (1 << 1)
347
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#define m_START_TX (1 << 0)
348
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349
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#define HDMI_CEC_DATA 0xd1
350
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#define HDMI_CEC_TX_OFFSET 0xd2
351
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#define HDMI_CEC_RX_OFFSET 0xd3
352
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#define HDMI_CEC_CLK_H 0xd4
353
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#define HDMI_CEC_CLK_L 0xd5
354
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#define HDMI_CEC_TX_LENGTH 0xd6
355
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#define HDMI_CEC_RX_LENGTH 0xd7
356
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#define HDMI_CEC_TX_INT_MASK 0xd8
357
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#define m_TX_DONE (1 << 3)
358
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#define m_TX_NOACK (1 << 2)
359
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#define m_TX_BROADCAST_REJ (1 << 1)
360
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#define m_TX_BUSNOTFREE (1 << 0)
361
+
362
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#define HDMI_CEC_RX_INT_MASK 0xd9
363
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#define m_RX_LA_ERR (1 << 4)
364
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#define m_RX_GLITCH (1 << 3)
365
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#define m_RX_DONE (1 << 0)
366
+
367
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#define HDMI_CEC_TX_INT 0xda
368
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#define HDMI_CEC_RX_INT 0xdb
369
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#define HDMI_CEC_BUSFREETIME_L 0xdc
370
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#define HDMI_CEC_BUSFREETIME_H 0xdd
371
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#define HDMI_CEC_LOGICADDR 0xde
33
372
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#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
35
-
36
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#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
37
374
38
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#define RK3036_GRF_SOC_CON2 0x148
39
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#define RK3036_HDMI_PHSYNC BIT(4)
-349
drivers/gpu/drm/rockchip/inno_hdmi.h
-349
drivers/gpu/drm/rockchip/inno_hdmi.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-only */
2
-
/*
3
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* Copyright (C) Rockchip Electronics Co., Ltd.
4
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* Zheng Yang <zhengyang@rock-chips.com>
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* Yakir Yang <ykk@rock-chips.com>
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*/
7
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8
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#ifndef __INNO_HDMI_H__
9
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#define __INNO_HDMI_H__
10
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#define DDC_SEGMENT_ADDR 0x30
12
-
13
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#define HDMI_SCL_RATE (100*1000)
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#define DDC_BUS_FREQ_L 0x4b
15
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#define DDC_BUS_FREQ_H 0x4c
16
-
17
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#define HDMI_SYS_CTRL 0x00
18
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#define m_RST_ANALOG (1 << 6)
19
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#define v_RST_ANALOG (0 << 6)
20
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#define v_NOT_RST_ANALOG (1 << 6)
21
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#define m_RST_DIGITAL (1 << 5)
22
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#define v_RST_DIGITAL (0 << 5)
23
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#define v_NOT_RST_DIGITAL (1 << 5)
24
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#define m_REG_CLK_INV (1 << 4)
25
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#define v_REG_CLK_NOT_INV (0 << 4)
26
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#define v_REG_CLK_INV (1 << 4)
27
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#define m_VCLK_INV (1 << 3)
28
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#define v_VCLK_NOT_INV (0 << 3)
29
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#define v_VCLK_INV (1 << 3)
30
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#define m_REG_CLK_SOURCE (1 << 2)
31
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#define v_REG_CLK_SOURCE_TMDS (0 << 2)
32
-
#define v_REG_CLK_SOURCE_SYS (1 << 2)
33
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#define m_POWER (1 << 1)
34
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#define v_PWR_ON (0 << 1)
35
-
#define v_PWR_OFF (1 << 1)
36
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#define m_INT_POL (1 << 0)
37
-
#define v_INT_POL_HIGH 1
38
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#define v_INT_POL_LOW 0
39
-
40
-
#define HDMI_VIDEO_CONTRL1 0x01
41
-
#define m_VIDEO_INPUT_FORMAT (7 << 1)
42
-
#define m_DE_SOURCE (1 << 0)
43
-
#define v_VIDEO_INPUT_FORMAT(n) (n << 1)
44
-
#define v_DE_EXTERNAL 1
45
-
#define v_DE_INTERNAL 0
46
-
enum {
47
-
VIDEO_INPUT_SDR_RGB444 = 0,
48
-
VIDEO_INPUT_DDR_RGB444 = 5,
49
-
VIDEO_INPUT_DDR_YCBCR422 = 6
50
-
};
51
-
52
-
#define HDMI_VIDEO_CONTRL2 0x02
53
-
#define m_VIDEO_OUTPUT_COLOR (3 << 6)
54
-
#define m_VIDEO_INPUT_BITS (3 << 4)
55
-
#define m_VIDEO_INPUT_CSP (1 << 0)
56
-
#define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
57
-
#define v_VIDEO_INPUT_BITS(n) (n << 4)
58
-
#define v_VIDEO_INPUT_CSP(n) (n << 0)
59
-
enum {
60
-
VIDEO_INPUT_12BITS = 0,
61
-
VIDEO_INPUT_10BITS = 1,
62
-
VIDEO_INPUT_REVERT = 2,
63
-
VIDEO_INPUT_8BITS = 3,
64
-
};
65
-
66
-
#define HDMI_VIDEO_CONTRL 0x03
67
-
#define m_VIDEO_AUTO_CSC (1 << 7)
68
-
#define v_VIDEO_AUTO_CSC(n) (n << 7)
69
-
#define m_VIDEO_C0_C2_SWAP (1 << 0)
70
-
#define v_VIDEO_C0_C2_SWAP(n) (n << 0)
71
-
enum {
72
-
C0_C2_CHANGE_ENABLE = 0,
73
-
C0_C2_CHANGE_DISABLE = 1,
74
-
AUTO_CSC_DISABLE = 0,
75
-
AUTO_CSC_ENABLE = 1,
76
-
};
77
-
78
-
#define HDMI_VIDEO_CONTRL3 0x04
79
-
#define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
80
-
#define m_SOF (1 << 3)
81
-
#define m_COLOR_RANGE (1 << 2)
82
-
#define m_CSC (1 << 0)
83
-
#define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
84
-
#define v_SOF_ENABLE (0 << 3)
85
-
#define v_SOF_DISABLE (1 << 3)
86
-
#define v_COLOR_RANGE_FULL (1 << 2)
87
-
#define v_COLOR_RANGE_LIMITED (0 << 2)
88
-
#define v_CSC_ENABLE 1
89
-
#define v_CSC_DISABLE 0
90
-
91
-
#define HDMI_AV_MUTE 0x05
92
-
#define m_AVMUTE_CLEAR (1 << 7)
93
-
#define m_AVMUTE_ENABLE (1 << 6)
94
-
#define m_AUDIO_MUTE (1 << 1)
95
-
#define m_VIDEO_BLACK (1 << 0)
96
-
#define v_AVMUTE_CLEAR(n) (n << 7)
97
-
#define v_AVMUTE_ENABLE(n) (n << 6)
98
-
#define v_AUDIO_MUTE(n) (n << 1)
99
-
#define v_VIDEO_MUTE(n) (n << 0)
100
-
101
-
#define HDMI_VIDEO_TIMING_CTL 0x08
102
-
#define v_HSYNC_POLARITY(n) (n << 3)
103
-
#define v_VSYNC_POLARITY(n) (n << 2)
104
-
#define v_INETLACE(n) (n << 1)
105
-
#define v_EXTERANL_VIDEO(n) (n << 0)
106
-
107
-
#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
108
-
#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
109
-
#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
110
-
#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
111
-
#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
112
-
#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
113
-
#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
114
-
#define HDMI_VIDEO_EXT_HDURATION_H 0x10
115
-
#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
116
-
#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
117
-
#define HDMI_VIDEO_EXT_VBLANK 0x13
118
-
#define HDMI_VIDEO_EXT_VDELAY 0x14
119
-
#define HDMI_VIDEO_EXT_VDURATION 0x15
120
-
121
-
#define HDMI_VIDEO_CSC_COEF 0x18
122
-
123
-
#define HDMI_AUDIO_CTRL1 0x35
124
-
enum {
125
-
CTS_SOURCE_INTERNAL = 0,
126
-
CTS_SOURCE_EXTERNAL = 1,
127
-
};
128
-
#define v_CTS_SOURCE(n) (n << 7)
129
-
130
-
enum {
131
-
DOWNSAMPLE_DISABLE = 0,
132
-
DOWNSAMPLE_1_2 = 1,
133
-
DOWNSAMPLE_1_4 = 2,
134
-
};
135
-
#define v_DOWN_SAMPLE(n) (n << 5)
136
-
137
-
enum {
138
-
AUDIO_SOURCE_IIS = 0,
139
-
AUDIO_SOURCE_SPDIF = 1,
140
-
};
141
-
#define v_AUDIO_SOURCE(n) (n << 3)
142
-
143
-
#define v_MCLK_ENABLE(n) (n << 2)
144
-
enum {
145
-
MCLK_128FS = 0,
146
-
MCLK_256FS = 1,
147
-
MCLK_384FS = 2,
148
-
MCLK_512FS = 3,
149
-
};
150
-
#define v_MCLK_RATIO(n) (n)
151
-
152
-
#define AUDIO_SAMPLE_RATE 0x37
153
-
enum {
154
-
AUDIO_32K = 0x3,
155
-
AUDIO_441K = 0x0,
156
-
AUDIO_48K = 0x2,
157
-
AUDIO_882K = 0x8,
158
-
AUDIO_96K = 0xa,
159
-
AUDIO_1764K = 0xc,
160
-
AUDIO_192K = 0xe,
161
-
};
162
-
163
-
#define AUDIO_I2S_MODE 0x38
164
-
enum {
165
-
I2S_CHANNEL_1_2 = 1,
166
-
I2S_CHANNEL_3_4 = 3,
167
-
I2S_CHANNEL_5_6 = 7,
168
-
I2S_CHANNEL_7_8 = 0xf
169
-
};
170
-
#define v_I2S_CHANNEL(n) ((n) << 2)
171
-
enum {
172
-
I2S_STANDARD = 0,
173
-
I2S_LEFT_JUSTIFIED = 1,
174
-
I2S_RIGHT_JUSTIFIED = 2,
175
-
};
176
-
#define v_I2S_MODE(n) (n)
177
-
178
-
#define AUDIO_I2S_MAP 0x39
179
-
#define AUDIO_I2S_SWAPS_SPDIF 0x3a
180
-
#define v_SPIDF_FREQ(n) (n)
181
-
182
-
#define N_32K 0x1000
183
-
#define N_441K 0x1880
184
-
#define N_882K 0x3100
185
-
#define N_1764K 0x6200
186
-
#define N_48K 0x1800
187
-
#define N_96K 0x3000
188
-
#define N_192K 0x6000
189
-
190
-
#define HDMI_AUDIO_CHANNEL_STATUS 0x3e
191
-
#define m_AUDIO_STATUS_NLPCM (1 << 7)
192
-
#define m_AUDIO_STATUS_USE (1 << 6)
193
-
#define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
194
-
#define m_AUDIO_STATUS_ADDITION (3 << 2)
195
-
#define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
196
-
#define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
197
-
#define AUDIO_N_H 0x3f
198
-
#define AUDIO_N_M 0x40
199
-
#define AUDIO_N_L 0x41
200
-
201
-
#define HDMI_AUDIO_CTS_H 0x45
202
-
#define HDMI_AUDIO_CTS_M 0x46
203
-
#define HDMI_AUDIO_CTS_L 0x47
204
-
205
-
#define HDMI_DDC_CLK_L 0x4b
206
-
#define HDMI_DDC_CLK_H 0x4c
207
-
208
-
#define HDMI_EDID_SEGMENT_POINTER 0x4d
209
-
#define HDMI_EDID_WORD_ADDR 0x4e
210
-
#define HDMI_EDID_FIFO_OFFSET 0x4f
211
-
#define HDMI_EDID_FIFO_ADDR 0x50
212
-
213
-
#define HDMI_PACKET_SEND_MANUAL 0x9c
214
-
#define HDMI_PACKET_SEND_AUTO 0x9d
215
-
#define m_PACKET_GCP_EN (1 << 7)
216
-
#define m_PACKET_MSI_EN (1 << 6)
217
-
#define m_PACKET_SDI_EN (1 << 5)
218
-
#define m_PACKET_VSI_EN (1 << 4)
219
-
#define v_PACKET_GCP_EN(n) ((n & 1) << 7)
220
-
#define v_PACKET_MSI_EN(n) ((n & 1) << 6)
221
-
#define v_PACKET_SDI_EN(n) ((n & 1) << 5)
222
-
#define v_PACKET_VSI_EN(n) ((n & 1) << 4)
223
-
224
-
#define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
225
-
enum {
226
-
INFOFRAME_VSI = 0x05,
227
-
INFOFRAME_AVI = 0x06,
228
-
INFOFRAME_AAI = 0x08,
229
-
};
230
-
231
-
#define HDMI_CONTROL_PACKET_ADDR 0xa0
232
-
#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
233
-
enum {
234
-
AVI_COLOR_MODE_RGB = 0,
235
-
AVI_COLOR_MODE_YCBCR422 = 1,
236
-
AVI_COLOR_MODE_YCBCR444 = 2,
237
-
AVI_COLORIMETRY_NO_DATA = 0,
238
-
239
-
AVI_COLORIMETRY_SMPTE_170M = 1,
240
-
AVI_COLORIMETRY_ITU709 = 2,
241
-
AVI_COLORIMETRY_EXTENDED = 3,
242
-
243
-
AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
244
-
AVI_CODED_FRAME_ASPECT_4_3 = 1,
245
-
AVI_CODED_FRAME_ASPECT_16_9 = 2,
246
-
247
-
ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
248
-
ACTIVE_ASPECT_RATE_4_3 = 0x09,
249
-
ACTIVE_ASPECT_RATE_16_9 = 0x0A,
250
-
ACTIVE_ASPECT_RATE_14_9 = 0x0B,
251
-
};
252
-
253
-
#define HDMI_HDCP_CTRL 0x52
254
-
#define m_HDMI_DVI (1 << 1)
255
-
#define v_HDMI_DVI(n) (n << 1)
256
-
257
-
#define HDMI_INTERRUPT_MASK1 0xc0
258
-
#define HDMI_INTERRUPT_STATUS1 0xc1
259
-
#define m_INT_ACTIVE_VSYNC (1 << 5)
260
-
#define m_INT_EDID_READY (1 << 2)
261
-
262
-
#define HDMI_INTERRUPT_MASK2 0xc2
263
-
#define HDMI_INTERRUPT_STATUS2 0xc3
264
-
#define m_INT_HDCP_ERR (1 << 7)
265
-
#define m_INT_BKSV_FLAG (1 << 6)
266
-
#define m_INT_HDCP_OK (1 << 4)
267
-
268
-
#define HDMI_STATUS 0xc8
269
-
#define m_HOTPLUG (1 << 7)
270
-
#define m_MASK_INT_HOTPLUG (1 << 5)
271
-
#define m_INT_HOTPLUG (1 << 1)
272
-
#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
273
-
274
-
#define HDMI_COLORBAR 0xc9
275
-
276
-
#define HDMI_PHY_SYNC 0xce
277
-
#define HDMI_PHY_SYS_CTL 0xe0
278
-
#define m_TMDS_CLK_SOURCE (1 << 5)
279
-
#define v_TMDS_FROM_PLL (0 << 5)
280
-
#define v_TMDS_FROM_GEN (1 << 5)
281
-
#define m_PHASE_CLK (1 << 4)
282
-
#define v_DEFAULT_PHASE (0 << 4)
283
-
#define v_SYNC_PHASE (1 << 4)
284
-
#define m_TMDS_CURRENT_PWR (1 << 3)
285
-
#define v_TURN_ON_CURRENT (0 << 3)
286
-
#define v_CAT_OFF_CURRENT (1 << 3)
287
-
#define m_BANDGAP_PWR (1 << 2)
288
-
#define v_BANDGAP_PWR_UP (0 << 2)
289
-
#define v_BANDGAP_PWR_DOWN (1 << 2)
290
-
#define m_PLL_PWR (1 << 1)
291
-
#define v_PLL_PWR_UP (0 << 1)
292
-
#define v_PLL_PWR_DOWN (1 << 1)
293
-
#define m_TMDS_CHG_PWR (1 << 0)
294
-
#define v_TMDS_CHG_PWR_UP (0 << 0)
295
-
#define v_TMDS_CHG_PWR_DOWN (1 << 0)
296
-
297
-
#define HDMI_PHY_CHG_PWR 0xe1
298
-
#define v_CLK_CHG_PWR(n) ((n & 1) << 3)
299
-
#define v_DATA_CHG_PWR(n) ((n & 7) << 0)
300
-
301
-
#define HDMI_PHY_DRIVER 0xe2
302
-
#define v_CLK_MAIN_DRIVER(n) (n << 4)
303
-
#define v_DATA_MAIN_DRIVER(n) (n << 0)
304
-
305
-
#define HDMI_PHY_PRE_EMPHASIS 0xe3
306
-
#define v_PRE_EMPHASIS(n) ((n & 7) << 4)
307
-
#define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
308
-
#define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
309
-
310
-
#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
311
-
#define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
312
-
#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
313
-
#define v_FEEDBACK_DIV_HIGH(n) (n & 1)
314
-
315
-
#define HDMI_PHY_PRE_DIV_RATIO 0xed
316
-
#define v_PRE_DIV_RATIO(n) (n & 0x1f)
317
-
318
-
#define HDMI_CEC_CTRL 0xd0
319
-
#define m_ADJUST_FOR_HISENSE (1 << 6)
320
-
#define m_REJECT_RX_BROADCAST (1 << 5)
321
-
#define m_BUSFREETIME_ENABLE (1 << 2)
322
-
#define m_REJECT_RX (1 << 1)
323
-
#define m_START_TX (1 << 0)
324
-
325
-
#define HDMI_CEC_DATA 0xd1
326
-
#define HDMI_CEC_TX_OFFSET 0xd2
327
-
#define HDMI_CEC_RX_OFFSET 0xd3
328
-
#define HDMI_CEC_CLK_H 0xd4
329
-
#define HDMI_CEC_CLK_L 0xd5
330
-
#define HDMI_CEC_TX_LENGTH 0xd6
331
-
#define HDMI_CEC_RX_LENGTH 0xd7
332
-
#define HDMI_CEC_TX_INT_MASK 0xd8
333
-
#define m_TX_DONE (1 << 3)
334
-
#define m_TX_NOACK (1 << 2)
335
-
#define m_TX_BROADCAST_REJ (1 << 1)
336
-
#define m_TX_BUSNOTFREE (1 << 0)
337
-
338
-
#define HDMI_CEC_RX_INT_MASK 0xd9
339
-
#define m_RX_LA_ERR (1 << 4)
340
-
#define m_RX_GLITCH (1 << 3)
341
-
#define m_RX_DONE (1 << 0)
342
-
343
-
#define HDMI_CEC_TX_INT 0xda
344
-
#define HDMI_CEC_RX_INT 0xdb
345
-
#define HDMI_CEC_BUSFREETIME_L 0xdc
346
-
#define HDMI_CEC_BUSFREETIME_H 0xdd
347
-
#define HDMI_CEC_LOGICADDR 0xde
348
-
349
-
#endif /* __INNO_HDMI_H__ */