Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x:
ARM: mach-shmobile: sh7372 CMT3 and CMT4 clock support
ARM: mach-shmobile: sh7372 MSIOF clock support
ARM: mach-shmobile: clock-sh7372: fixup USB-DMAC1 settings
ARM: mach-shmobile: clock-sh73a0: tidyup CKSCR main clock selecter
ARM: mach-shmobile: Remove 3DG/SGX from sh7372 INTCS
ARM: mach-shmobile: mackerel: Add USB-DMA ID
mmc: sdhi, mmcif: zboot: Correct clock disable logic
ARM: mach-shmobile: ag5evm: SDHI requires waiting for idle
ARM: static should be at beginning of declaration
ARM: mach-shmobile: Use CMT2 for timer on sh7372
ARM: mach-shmobile: sh7372: Add USB-DMAC support
+199
-30
+1
-1
arch/arm/boot/compressed/mmcif-sh7372.c
+1
-1
arch/arm/boot/compressed/mmcif-sh7372.c
+1
-1
arch/arm/boot/compressed/sdhi-sh7372.c
+1
-1
arch/arm/boot/compressed/sdhi-sh7372.c
+2
-1
arch/arm/mach-shmobile/board-ag5evm.c
+2
-1
arch/arm/mach-shmobile/board-ag5evm.c
···
341
341
static struct sh_mobile_sdhi_info sdhi0_info = {
342
342
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
343
343
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
344
+
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
344
345
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
345
346
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
346
347
};
···
383
382
}
384
383
385
384
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
386
-
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
385
+
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
387
386
.tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
388
387
.tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
389
388
.set_pwr = ag5evm_sdhi1_set_pwr,
+4
arch/arm/mach-shmobile/board-mackerel.c
+4
arch/arm/mach-shmobile/board-mackerel.c
···
641
641
},
642
642
.driver_param = {
643
643
.buswait_bwait = 4,
644
+
.d0_tx_id = SHDMA_SLAVE_USB0_TX,
645
+
.d1_rx_id = SHDMA_SLAVE_USB0_RX,
644
646
},
645
647
},
646
648
};
···
812
810
.buswait_bwait = 4,
813
811
.pipe_type = usbhs1_pipe_cfg,
814
812
.pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
813
+
.d0_tx_id = SHDMA_SLAVE_USB1_TX,
814
+
.d1_rx_id = SHDMA_SLAVE_USB1_RX,
815
815
},
816
816
},
817
817
};
+22
-7
arch/arm/mach-shmobile/clock-sh7372.c
+22
-7
arch/arm/mach-shmobile/clock-sh7372.c
···
503
503
&sh7372_fsidivb_clk,
504
504
};
505
505
506
-
enum { MSTP001,
506
+
enum { MSTP001, MSTP000,
507
507
MSTP131, MSTP130,
508
508
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
509
509
MSTP118, MSTP117, MSTP116, MSTP113,
510
510
MSTP106, MSTP101, MSTP100,
511
511
MSTP223,
512
-
MSTP218, MSTP217, MSTP216,
513
-
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
514
-
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
515
-
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
512
+
MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
513
+
MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
514
+
MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
515
+
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
516
+
MSTP405, MSTP404, MSTP403, MSTP400,
516
517
MSTP_NR };
517
518
518
519
#define MSTP(_parent, _reg, _bit, _flags) \
···
521
520
522
521
static struct clk mstp_clks[MSTP_NR] = {
523
522
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
523
+
[MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
524
524
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
525
525
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
526
526
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
···
540
538
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
541
539
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
542
540
[MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
541
+
[MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
542
+
[MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
543
543
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
544
544
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
545
+
[MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
545
546
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
546
547
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
547
548
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
548
549
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
549
550
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
550
-
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
551
551
[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
552
552
[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
553
553
[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
···
561
557
[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
562
558
[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
563
559
[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
560
+
[MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
564
561
[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
562
+
[MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
563
+
[MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
565
564
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
565
+
[MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
566
566
};
567
567
568
568
static struct clk_lookup lookups[] = {
···
617
609
618
610
/* MSTP32 clocks */
619
611
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
612
+
CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
620
613
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
621
614
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
622
615
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
···
638
629
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
639
630
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
640
631
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
632
+
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
633
+
CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
641
634
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
642
635
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
636
+
CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
643
637
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
644
638
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
645
639
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
646
640
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
647
641
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
648
-
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
649
642
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
650
643
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
651
644
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
···
661
650
CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
662
651
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
663
652
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
653
+
CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
664
654
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
665
655
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
666
656
CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
657
+
CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
658
+
CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
667
659
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
660
+
CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
668
661
669
662
CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
670
663
&div6_reparent_clks[DIV6_HDMI]),
+1
-1
arch/arm/mach-shmobile/clock-sh73a0.c
+1
-1
arch/arm/mach-shmobile/clock-sh73a0.c
+4
arch/arm/mach-shmobile/include/mach/sh7372.h
+4
arch/arm/mach-shmobile/include/mach/sh7372.h
+3
-4
arch/arm/mach-shmobile/intc-sh7372.c
+3
-4
arch/arm/mach-shmobile/intc-sh7372.c
···
379
379
/* BBIF2 */
380
380
VPU,
381
381
TSIF1,
382
-
_3DG_SGX530,
382
+
/* 3DG */
383
383
_2DDMAC,
384
384
IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
385
385
IPMMU_IPMMUR, IPMMU_IPMMUR2,
···
436
436
/* BBIF2 */
437
437
INTCS_VECT(VPU, 0x980),
438
438
INTCS_VECT(TSIF1, 0x9a0),
439
-
INTCS_VECT(_3DG_SGX530, 0x9e0),
439
+
/* 3DG */
440
440
INTCS_VECT(_2DDMAC, 0xa00),
441
441
INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
442
442
INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
···
521
521
RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
522
522
{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
523
523
{ 0, 0, MSIOF, 0,
524
-
_3DG_SGX530, 0, 0, 0 } },
524
+
0, 0, 0, 0 } },
525
525
{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
526
526
{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
527
527
0, 0, 0, 0 } },
···
561
561
TMU_TUNI2, TSIF1 } },
562
562
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
563
563
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
564
-
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
565
564
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
566
565
{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
567
566
{ 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
+161
-15
arch/arm/mach-shmobile/setup-sh7372.c
+161
-15
arch/arm/mach-shmobile/setup-sh7372.c
···
169
169
};
170
170
171
171
/* CMT */
172
-
static struct sh_timer_config cmt10_platform_data = {
173
-
.name = "CMT10",
174
-
.channel_offset = 0x10,
175
-
.timer_bit = 0,
172
+
static struct sh_timer_config cmt2_platform_data = {
173
+
.name = "CMT2",
174
+
.channel_offset = 0x40,
175
+
.timer_bit = 5,
176
176
.clockevent_rating = 125,
177
177
.clocksource_rating = 125,
178
178
};
179
179
180
-
static struct resource cmt10_resources[] = {
180
+
static struct resource cmt2_resources[] = {
181
181
[0] = {
182
-
.name = "CMT10",
183
-
.start = 0xe6138010,
184
-
.end = 0xe613801b,
182
+
.name = "CMT2",
183
+
.start = 0xe6130040,
184
+
.end = 0xe613004b,
185
185
.flags = IORESOURCE_MEM,
186
186
},
187
187
[1] = {
188
-
.start = evt2irq(0x0b00), /* CMT1_CMT10 */
188
+
.start = evt2irq(0x0b80), /* CMT2 */
189
189
.flags = IORESOURCE_IRQ,
190
190
},
191
191
};
192
192
193
-
static struct platform_device cmt10_device = {
193
+
static struct platform_device cmt2_device = {
194
194
.name = "sh_cmt",
195
-
.id = 10,
195
+
.id = 2,
196
196
.dev = {
197
-
.platform_data = &cmt10_platform_data,
197
+
.platform_data = &cmt2_platform_data,
198
198
},
199
-
.resource = cmt10_resources,
200
-
.num_resources = ARRAY_SIZE(cmt10_resources),
199
+
.resource = cmt2_resources,
200
+
.num_resources = ARRAY_SIZE(cmt2_resources),
201
201
};
202
202
203
203
/* TMU */
···
602
602
},
603
603
};
604
604
605
+
/*
606
+
* USB-DMAC
607
+
*/
608
+
609
+
unsigned int usbts_shift[] = {3, 4, 5};
610
+
611
+
enum {
612
+
XMIT_SZ_8BYTE = 0,
613
+
XMIT_SZ_16BYTE = 1,
614
+
XMIT_SZ_32BYTE = 2,
615
+
};
616
+
617
+
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
618
+
619
+
static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
620
+
{
621
+
.offset = 0,
622
+
}, {
623
+
.offset = 0x20,
624
+
},
625
+
};
626
+
627
+
/* USB DMAC0 */
628
+
static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
629
+
{
630
+
.slave_id = SHDMA_SLAVE_USB0_TX,
631
+
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
632
+
}, {
633
+
.slave_id = SHDMA_SLAVE_USB0_RX,
634
+
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
635
+
},
636
+
};
637
+
638
+
static struct sh_dmae_pdata usb_dma0_platform_data = {
639
+
.slave = sh7372_usb_dmae0_slaves,
640
+
.slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
641
+
.channel = sh7372_usb_dmae_channels,
642
+
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
643
+
.ts_low_shift = 6,
644
+
.ts_low_mask = 0xc0,
645
+
.ts_high_shift = 0,
646
+
.ts_high_mask = 0,
647
+
.ts_shift = usbts_shift,
648
+
.ts_shift_num = ARRAY_SIZE(usbts_shift),
649
+
.dmaor_init = DMAOR_DME,
650
+
.chcr_offset = 0x14,
651
+
.chcr_ie_bit = 1 << 5,
652
+
.dmaor_is_32bit = 1,
653
+
.needs_tend_set = 1,
654
+
.no_dmars = 1,
655
+
};
656
+
657
+
static struct resource sh7372_usb_dmae0_resources[] = {
658
+
{
659
+
/* Channel registers and DMAOR */
660
+
.start = 0xe68a0020,
661
+
.end = 0xe68a0064 - 1,
662
+
.flags = IORESOURCE_MEM,
663
+
},
664
+
{
665
+
/* VCR/SWR/DMICR */
666
+
.start = 0xe68a0000,
667
+
.end = 0xe68a0014 - 1,
668
+
.flags = IORESOURCE_MEM,
669
+
},
670
+
{
671
+
/* IRQ for channels */
672
+
.start = evt2irq(0x0a00),
673
+
.end = evt2irq(0x0a00),
674
+
.flags = IORESOURCE_IRQ,
675
+
},
676
+
};
677
+
678
+
static struct platform_device usb_dma0_device = {
679
+
.name = "sh-dma-engine",
680
+
.id = 3,
681
+
.resource = sh7372_usb_dmae0_resources,
682
+
.num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
683
+
.dev = {
684
+
.platform_data = &usb_dma0_platform_data,
685
+
},
686
+
};
687
+
688
+
/* USB DMAC1 */
689
+
static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
690
+
{
691
+
.slave_id = SHDMA_SLAVE_USB1_TX,
692
+
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
693
+
}, {
694
+
.slave_id = SHDMA_SLAVE_USB1_RX,
695
+
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
696
+
},
697
+
};
698
+
699
+
static struct sh_dmae_pdata usb_dma1_platform_data = {
700
+
.slave = sh7372_usb_dmae1_slaves,
701
+
.slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
702
+
.channel = sh7372_usb_dmae_channels,
703
+
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
704
+
.ts_low_shift = 6,
705
+
.ts_low_mask = 0xc0,
706
+
.ts_high_shift = 0,
707
+
.ts_high_mask = 0,
708
+
.ts_shift = usbts_shift,
709
+
.ts_shift_num = ARRAY_SIZE(usbts_shift),
710
+
.dmaor_init = DMAOR_DME,
711
+
.chcr_offset = 0x14,
712
+
.chcr_ie_bit = 1 << 5,
713
+
.dmaor_is_32bit = 1,
714
+
.needs_tend_set = 1,
715
+
.no_dmars = 1,
716
+
};
717
+
718
+
static struct resource sh7372_usb_dmae1_resources[] = {
719
+
{
720
+
/* Channel registers and DMAOR */
721
+
.start = 0xe68c0020,
722
+
.end = 0xe68c0064 - 1,
723
+
.flags = IORESOURCE_MEM,
724
+
},
725
+
{
726
+
/* VCR/SWR/DMICR */
727
+
.start = 0xe68c0000,
728
+
.end = 0xe68c0014 - 1,
729
+
.flags = IORESOURCE_MEM,
730
+
},
731
+
{
732
+
/* IRQ for channels */
733
+
.start = evt2irq(0x1d00),
734
+
.end = evt2irq(0x1d00),
735
+
.flags = IORESOURCE_IRQ,
736
+
},
737
+
};
738
+
739
+
static struct platform_device usb_dma1_device = {
740
+
.name = "sh-dma-engine",
741
+
.id = 4,
742
+
.resource = sh7372_usb_dmae1_resources,
743
+
.num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
744
+
.dev = {
745
+
.platform_data = &usb_dma1_platform_data,
746
+
},
747
+
};
748
+
605
749
/* VPU */
606
750
static struct uio_info vpu_platform_data = {
607
751
.name = "VPU5HG",
···
962
818
&scif4_device,
963
819
&scif5_device,
964
820
&scif6_device,
965
-
&cmt10_device,
821
+
&cmt2_device,
966
822
&tmu00_device,
967
823
&tmu01_device,
968
824
};
···
973
829
&dma0_device,
974
830
&dma1_device,
975
831
&dma2_device,
832
+
&usb_dma0_device,
833
+
&usb_dma1_device,
976
834
&vpu_device,
977
835
&veu0_device,
978
836
&veu1_device,