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clk: qcom: msm8996-cpu: Unify cluster order

The power cluster comes before the performance cluster. Make
everything in the driver follow this order.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-4-y.oudjana@protonmail.com

authored by

Yassine Oudjana and committed by
Bjorn Andersson
382139bf de37e021

+32 -32
+32 -32
drivers/clk/qcom/clk-cpu-8996.c
··· 111 111 .early_output_mask = BIT(3), 112 112 }; 113 113 114 - static struct clk_alpha_pll perfcl_pll = { 115 - .offset = PERFCL_REG_OFFSET, 116 - .regs = prim_pll_regs, 117 - .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 118 - .clkr.hw.init = &(struct clk_init_data){ 119 - .name = "perfcl_pll", 120 - .parent_names = (const char *[]){ "xo" }, 121 - .num_parents = 1, 122 - .ops = &clk_alpha_pll_huayra_ops, 123 - }, 124 - }; 125 - 126 114 static struct clk_alpha_pll pwrcl_pll = { 127 115 .offset = PWRCL_REG_OFFSET, 128 116 .regs = prim_pll_regs, 129 117 .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 130 118 .clkr.hw.init = &(struct clk_init_data){ 131 119 .name = "pwrcl_pll", 120 + .parent_names = (const char *[]){ "xo" }, 121 + .num_parents = 1, 122 + .ops = &clk_alpha_pll_huayra_ops, 123 + }, 124 + }; 125 + 126 + static struct clk_alpha_pll perfcl_pll = { 127 + .offset = PERFCL_REG_OFFSET, 128 + .regs = prim_pll_regs, 129 + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, 130 + .clkr.hw.init = &(struct clk_init_data){ 131 + .name = "perfcl_pll", 132 132 .parent_names = (const char *[]){ "xo" }, 133 133 .num_parents = 1, 134 134 .ops = &clk_alpha_pll_huayra_ops, ··· 181 181 .early_output_mask = BIT(3), 182 182 }; 183 183 184 - static struct clk_alpha_pll perfcl_alt_pll = { 185 - .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, 186 - .regs = alt_pll_regs, 187 - .vco_table = alt_pll_vco_modes, 188 - .num_vco = ARRAY_SIZE(alt_pll_vco_modes), 189 - .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 190 - .clkr.hw.init = &(struct clk_init_data) { 191 - .name = "perfcl_alt_pll", 192 - .parent_names = (const char *[]){ "xo" }, 193 - .num_parents = 1, 194 - .ops = &clk_alpha_pll_hwfsm_ops, 195 - }, 196 - }; 197 - 198 184 static struct clk_alpha_pll pwrcl_alt_pll = { 199 185 .offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET, 200 186 .regs = alt_pll_regs, ··· 189 203 .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 190 204 .clkr.hw.init = &(struct clk_init_data) { 191 205 .name = "pwrcl_alt_pll", 206 + .parent_names = (const char *[]){ "xo" }, 207 + .num_parents = 1, 208 + .ops = &clk_alpha_pll_hwfsm_ops, 209 + }, 210 + }; 211 + 212 + static struct clk_alpha_pll perfcl_alt_pll = { 213 + .offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET, 214 + .regs = alt_pll_regs, 215 + .vco_table = alt_pll_vco_modes, 216 + .num_vco = ARRAY_SIZE(alt_pll_vco_modes), 217 + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, 218 + .clkr.hw.init = &(struct clk_init_data) { 219 + .name = "perfcl_alt_pll", 192 220 .parent_names = (const char *[]){ "xo" }, 193 221 .num_parents = 1, 194 222 .ops = &clk_alpha_pll_hwfsm_ops, ··· 367 367 }; 368 368 369 369 static struct clk_regmap *cpu_msm8996_clks[] = { 370 - &perfcl_pll.clkr, 371 370 &pwrcl_pll.clkr, 372 - &perfcl_alt_pll.clkr, 371 + &perfcl_pll.clkr, 373 372 &pwrcl_alt_pll.clkr, 374 - &perfcl_smux.clkr, 373 + &perfcl_alt_pll.clkr, 375 374 &pwrcl_smux.clkr, 376 - &perfcl_pmux.clkr, 375 + &perfcl_smux.clkr, 377 376 &pwrcl_pmux.clkr, 377 + &perfcl_pmux.clkr, 378 378 }; 379 379 380 380 static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, ··· 403 403 return ret; 404 404 } 405 405 406 - clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); 407 406 clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); 408 - clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); 407 + clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); 409 408 clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); 409 + clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); 410 410 411 411 /* Enable alt PLLs */ 412 412 clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);