Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: msm8996-cpu: Statically define PLL dividers
This will allow for adding them to clk_parent_data arrays
in an upcoming patch.
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220621160621.24415-3-y.oudjana@protonmail.com
authored by
Yassine Oudjana
and committed by
Bjorn Andersson
de37e021
1ba0a3bb
+42
-24
+42
-24
drivers/clk/qcom/clk-cpu-8996.c
+42
-24
drivers/clk/qcom/clk-cpu-8996.c
···
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},
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};
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static struct clk_fixed_factor pwrcl_pll_postdiv = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "pwrcl_pll_postdiv",
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.parent_data = &(const struct clk_parent_data){
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.hw = &pwrcl_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_fixed_factor perfcl_pll_postdiv = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "perfcl_pll_postdiv",
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.parent_data = &(const struct clk_parent_data){
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.hw = &perfcl_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const struct pll_vco alt_pll_vco_modes[] = {
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VCO(3, 250000000, 500000000),
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VCO(2, 500000000, 750000000),
···
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.name = "pwrcl_smux",
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.parent_names = (const char *[]){
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"xo",
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"pwrcl_pll_main",
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"pwrcl_pll_postdiv",
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},
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.num_parents = 2,
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.ops = &clk_cpu_8996_mux_ops,
···
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.name = "perfcl_smux",
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.parent_names = (const char *[]){
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"xo",
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"perfcl_pll_main",
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"perfcl_pll_postdiv",
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},
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.num_parents = 2,
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.ops = &clk_cpu_8996_mux_ops,
···
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{
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int i, ret;
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perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
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"perfcl_pll",
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CLK_SET_RATE_PARENT,
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1, 2);
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if (IS_ERR(perfcl_smux.pll)) {
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dev_err(dev, "Failed to initialize perfcl_pll_main\n");
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return PTR_ERR(perfcl_smux.pll);
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ret = devm_clk_hw_register(dev, &pwrcl_pll_postdiv.hw);
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if (ret) {
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dev_err(dev, "Failed to register pwrcl_pll_postdiv: %d", ret);
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return ret;
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}
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pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
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"pwrcl_pll",
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CLK_SET_RATE_PARENT,
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1, 2);
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if (IS_ERR(pwrcl_smux.pll)) {
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dev_err(dev, "Failed to initialize pwrcl_pll_main\n");
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clk_hw_unregister(perfcl_smux.pll);
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return PTR_ERR(pwrcl_smux.pll);
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ret = devm_clk_hw_register(dev, &perfcl_pll_postdiv.hw);
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if (ret) {
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dev_err(dev, "Failed to register perfcl_pll_postdiv: %d", ret);
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return ret;
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}
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pwrcl_smux.pll = &pwrcl_pll_postdiv.hw;
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perfcl_smux.pll = &perfcl_pll_postdiv.hw;
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for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
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ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
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if (ret) {
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clk_hw_unregister(perfcl_smux.pll);
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clk_hw_unregister(pwrcl_smux.pll);
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if (ret)
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return ret;
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}
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}
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clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
···
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ret = clk_notifier_unregister(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
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if (ret)
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return ret;
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clk_hw_unregister(perfcl_smux.pll);
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clk_hw_unregister(pwrcl_smux.pll);
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return 0;
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}