Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
riscv: Implement cmpxchg32/64() using Zacas
This adds runtime support for Zacas in cmpxchg operations.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-4-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
authored by
Alexandre Ghiti
and committed by
Palmer Dabbelt
38acdee3
af042c45
+50
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arch/riscv/Kconfig
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arch/riscv/Kconfig
···
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use of these instructions in the kernel when the Zawrs extension is
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detected at boot.
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config TOOLCHAIN_HAS_ZACAS
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bool
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default y
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depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zacas)
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depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zacas)
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depends on AS_HAS_OPTION_ARCH
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config RISCV_ISA_ZACAS
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bool "Zacas extension support for atomic CAS"
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depends on TOOLCHAIN_HAS_ZACAS
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depends on RISCV_ALTERNATIVE
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default y
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help
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Enable the use of the Zacas ISA-extension to implement kernel atomic
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cmpxchg operations when it is detected at boot.
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If you don't know what to do here, say Y.
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config TOOLCHAIN_HAS_ZBB
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arch/riscv/Makefile
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arch/riscv/Makefile
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riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
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endif
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# Check if the toolchain supports Zacas
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riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
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# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
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# matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
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KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
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arch/riscv/include/asm/cmpxchg.h
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arch/riscv/include/asm/cmpxchg.h
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#include <asm/fence.h>
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#include <asm/hwcap.h>
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#include <asm/insn-def.h>
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#include <asm/cpufeature-macros.h>
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#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n) \
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({ \
···
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r = (__typeof__(*(p)))((__retx & __mask) >> __s); \
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})
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#define __arch_cmpxchg(lr_sfx, sc_sfx, prepend, append, r, p, co, o, n) \
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#define __arch_cmpxchg(lr_sfx, sc_cas_sfx, prepend, append, r, p, co, o, n) \
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({ \
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register unsigned int __rc; \
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZACAS) && \
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riscv_has_extension_unlikely(RISCV_ISA_EXT_ZACAS)) { \
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r = o; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr" lr_sfx " %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc" sc_sfx " %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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append \
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"1:\n" \
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: "=&r" (r), "=&r" (__rc), "+A" (*(p)) \
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: "rJ" (co o), "rJ" (n) \
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: "memory"); \
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__asm__ __volatile__ ( \
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prepend \
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" amocas" sc_cas_sfx " %0, %z2, %1\n" \
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append \
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: "+&r" (r), "+A" (*(p)) \
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: "rJ" (n) \
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: "memory"); \
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} else { \
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register unsigned int __rc; \
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\
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__asm__ __volatile__ ( \
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prepend \
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"0: lr" lr_sfx " %0, %2\n" \
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" bne %0, %z3, 1f\n" \
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" sc" sc_cas_sfx " %1, %z4, %2\n" \
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" bnez %1, 0b\n" \
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append \
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"1:\n" \
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: "=&r" (r), "=&r" (__rc), "+A" (*(p)) \
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: "rJ" (co o), "rJ" (n) \
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: "memory"); \
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} \
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})
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#define _arch_cmpxchg(ptr, old, new, sc_sfx, prepend, append) \
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#define _arch_cmpxchg(ptr, old, new, sc_cas_sfx, prepend, append) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(__ptr)) __old = (old); \
···
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switch (sizeof(*__ptr)) { \
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case 1: \
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case 2: \
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__arch_cmpxchg_masked(sc_sfx, prepend, append, \
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__arch_cmpxchg_masked(sc_cas_sfx, prepend, append, \
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__ret, __ptr, __old, __new); \
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break; \
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case 4: \
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__arch_cmpxchg(".w", ".w" sc_sfx, prepend, append, \
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__arch_cmpxchg(".w", ".w" sc_cas_sfx, prepend, append, \
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__ret, __ptr, (long), __old, __new); \
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break; \
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case 8: \
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__arch_cmpxchg(".d", ".d" sc_sfx, prepend, append, \
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__arch_cmpxchg(".d", ".d" sc_cas_sfx, prepend, append, \
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__ret, __ptr, /**/, __old, __new); \
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break; \
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default: \