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riscv: Do not fail to build on byte/halfword operations with Zawrs

riscv does not have lr instructions on byte and halfword but the
qspinlock implementation actually uses such atomics provided by the
Zabha extension, so those sizes are legitimate.

Then instead of failing to build, just fallback to the !Zawrs path.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

authored by

Alexandre Ghiti and committed by
Palmer Dabbelt af042c45 010e12aa

+5
+5
arch/riscv/include/asm/cmpxchg.h
··· 245 245 : : : : no_zawrs); 246 246 247 247 switch (size) { 248 + case 1: 249 + fallthrough; 250 + case 2: 251 + /* RISC-V doesn't have lr instructions on byte and half-word. */ 252 + goto no_zawrs; 248 253 case 4: 249 254 asm volatile( 250 255 " lr.w %0, %1\n"