Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'perf-urgent-2023-10-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf event fixes from Ingo Molnar:
"Misc fixes: work around an AMD microcode bug on certain models, and
fix kexec kernel PMI handlers on AMD systems that get loaded on older
kernels that have an unexpected register state"
* tag 'perf-urgent-2023-10-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/amd: Do not WARN() on every IRQ
perf/x86/amd/core: Fix overflow reset on hotplug
+17
-7
+17
-7
arch/x86/events/amd/core.c
+17
-7
arch/x86/events/amd/core.c
···
534
534
/* Clear enable bits i.e. PerfCntrGlobalCtl.PerfCntrEn */
535
535
wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0);
536
536
537
-
/* Clear overflow bits i.e. PerfCntrGLobalStatus.PerfCntrOvfl */
538
-
wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, amd_pmu_global_cntr_mask);
537
+
/*
538
+
* Clear freeze and overflow bits i.e. PerfCntrGLobalStatus.LbrFreeze
539
+
* and PerfCntrGLobalStatus.PerfCntrOvfl
540
+
*/
541
+
wrmsrl(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
542
+
GLOBAL_STATUS_LBRS_FROZEN | amd_pmu_global_cntr_mask);
539
543
}
540
544
541
545
static int amd_pmu_cpu_prepare(int cpu)
···
574
570
int i, nb_id;
575
571
576
572
cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
573
+
amd_pmu_cpu_reset(cpu);
577
574
578
575
if (!x86_pmu.amd_nb_constraints)
579
576
return;
···
596
591
597
592
cpuc->amd_nb->nb_id = nb_id;
598
593
cpuc->amd_nb->refcnt++;
599
-
600
-
amd_pmu_cpu_reset(cpu);
601
594
}
602
595
603
596
static void amd_pmu_cpu_dead(int cpu)
···
604
601
605
602
kfree(cpuhw->lbr_sel);
606
603
cpuhw->lbr_sel = NULL;
604
+
amd_pmu_cpu_reset(cpu);
607
605
608
606
if (!x86_pmu.amd_nb_constraints)
609
607
return;
···
617
613
618
614
cpuhw->amd_nb = NULL;
619
615
}
620
-
621
-
amd_pmu_cpu_reset(cpu);
622
616
}
623
617
624
618
static inline void amd_pmu_set_global_ctl(u64 ctl)
···
886
884
struct hw_perf_event *hwc;
887
885
struct perf_event *event;
888
886
int handled = 0, idx;
889
-
u64 status, mask;
887
+
u64 reserved, status, mask;
890
888
bool pmu_enabled;
891
889
892
890
/*
···
910
908
amd_pmu_lbr_read();
911
909
status &= ~GLOBAL_STATUS_LBRS_FROZEN;
912
910
}
911
+
912
+
reserved = status & ~amd_pmu_global_cntr_mask;
913
+
if (reserved)
914
+
pr_warn_once("Reserved PerfCntrGlobalStatus bits are set (0x%llx), please consider updating microcode\n",
915
+
reserved);
916
+
917
+
/* Clear any reserved bits set by buggy microcode */
918
+
status &= amd_pmu_global_cntr_mask;
913
919
914
920
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
915
921
if (!test_bit(idx, cpuc->active_mask))