Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next
* clk-samsung:
clk: s2mps11: add support for S2MPG10 PMIC clock
dt-bindings: clock: samsung,s2mps11: add s2mpg10
clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
clk: samsung: exynos990: Add missing USB clock registers to HSI0
clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
clk: samsung: Add clock PLL support for ARTPEC-8 SoC
dt-bindings: clock: Add ARTPEC-8 clock controller
clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
dt-bindings: clock: exynos990: Extend clocks IDs
clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
clk: samsung: pll: convert from round_rate() to determine_rate()
clk: samsung: cpu: convert from round_rate() to determine_rate()
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
dt-bindings: clock: Add CAM_CSI clock macro for FSD
* clk-tegra:
clk: tegra: dfll: Add CVB tables for Tegra114
clk: tegra: Add DFLL DVCO reset control for Tegra114
dt-bindings: arm: tegra: Add ASUS TF101G and SL101
dt-bindings: reset: Add Tegra114 CAR header
dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
* clk-amlogic:
clk: amlogic: fix recent code refactoring
clk: amlogic: c3-peripherals: use helper for basic composite clocks
clk: amlogic: align s4 and c3 pwm clock descriptions
clk: amlogic: add composite clock helpers
clk: amlogic: use the common pclk definition
clk: amlogic: introduce a common pclk definition
clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
clk: amlogic: move PCLK definition to clkc-utils
clk: amlogic: aoclk: use clkc-utils syscon probe
clk: amlogic: use probe helper in mmio based controllers
clk: amlogic: add probe helper for mmio based controllers
clk: amlogic: drop meson-clkcee
clk: amlogic: naming consistency alignment
+6996
-5463
+10
-2
Documentation/devicetree/bindings/arm/tegra.yaml
+10
-2
Documentation/devicetree/bindings/arm/tegra.yaml
···
36
36
- toradex,colibri_t20-iris
37
37
- const: toradex,colibri_t20
38
38
- const: nvidia,tegra20
39
-
- items:
40
-
- const: asus,tf101
39
+
- description: ASUS Transformers T20 Device family
40
+
items:
41
+
- enum:
42
+
- asus,sl101
43
+
- asus,tf101
44
+
- asus,tf101g
41
45
- const: nvidia,tegra20
42
46
- items:
43
47
- const: acer,picasso
···
177
173
- const: google,nyan-big-rev0
178
174
- const: google,nyan-big
179
175
- const: google,nyan
176
+
- const: nvidia,tegra124
177
+
- description: Xiaomi Mi Pad (A0101)
178
+
items:
179
+
- const: xiaomi,mocha
180
180
- const: nvidia,tegra124
181
181
- items:
182
182
- enum:
+213
Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
+213
Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Axis ARTPEC-8 SoC clock controller
8
+
9
+
maintainers:
10
+
- Jesper Nilsson <jesper.nilsson@axis.com>
11
+
12
+
description: |
13
+
ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
14
+
units, generating clocks for different domains. Those CMU units are modeled
15
+
as separate device tree nodes, and might depend on each other.
16
+
The root clock in that root tree is an external clock: OSCCLK (25 MHz).
17
+
This external clock must be defined as a fixed-rate clock in dts.
18
+
19
+
CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
20
+
dividers; all other clocks of function blocks (other CMUs) are usually
21
+
derived from CMU_CMU.
22
+
23
+
Each clock is assigned an identifier and client nodes can use this identifier
24
+
to specify the clock which they consume. All clocks available for usage
25
+
in clock consumer nodes are defined as preprocessor macros in
26
+
'include/dt-bindings/clock/axis,artpec8-clk.h' header.
27
+
28
+
properties:
29
+
compatible:
30
+
enum:
31
+
- axis,artpec8-cmu-cmu
32
+
- axis,artpec8-cmu-bus
33
+
- axis,artpec8-cmu-core
34
+
- axis,artpec8-cmu-cpucl
35
+
- axis,artpec8-cmu-fsys
36
+
- axis,artpec8-cmu-imem
37
+
- axis,artpec8-cmu-peri
38
+
39
+
reg:
40
+
maxItems: 1
41
+
42
+
clocks:
43
+
minItems: 1
44
+
maxItems: 5
45
+
46
+
clock-names:
47
+
minItems: 1
48
+
maxItems: 5
49
+
50
+
"#clock-cells":
51
+
const: 1
52
+
53
+
required:
54
+
- compatible
55
+
- reg
56
+
- clocks
57
+
- clock-names
58
+
- "#clock-cells"
59
+
60
+
allOf:
61
+
- if:
62
+
properties:
63
+
compatible:
64
+
const: axis,artpec8-cmu-cmu
65
+
66
+
then:
67
+
properties:
68
+
clocks:
69
+
items:
70
+
- description: External reference clock (25 MHz)
71
+
72
+
clock-names:
73
+
items:
74
+
- const: fin_pll
75
+
76
+
- if:
77
+
properties:
78
+
compatible:
79
+
const: axis,artpec8-cmu-bus
80
+
81
+
then:
82
+
properties:
83
+
clocks:
84
+
items:
85
+
- description: External reference clock (25 MHz)
86
+
- description: CMU_BUS BUS clock (from CMU_CMU)
87
+
- description: CMU_BUS DLP clock (from CMU_CMU)
88
+
89
+
clock-names:
90
+
items:
91
+
- const: fin_pll
92
+
- const: bus
93
+
- const: dlp
94
+
95
+
- if:
96
+
properties:
97
+
compatible:
98
+
const: axis,artpec8-cmu-core
99
+
100
+
then:
101
+
properties:
102
+
clocks:
103
+
items:
104
+
- description: External reference clock (25 MHz)
105
+
- description: CMU_CORE main clock (from CMU_CMU)
106
+
- description: CMU_CORE DLP clock (from CMU_CMU)
107
+
108
+
clock-names:
109
+
items:
110
+
- const: fin_pll
111
+
- const: main
112
+
- const: dlp
113
+
114
+
- if:
115
+
properties:
116
+
compatible:
117
+
const: axis,artpec8-cmu-cpucl
118
+
119
+
then:
120
+
properties:
121
+
clocks:
122
+
items:
123
+
- description: External reference clock (25 MHz)
124
+
- description: CMU_CPUCL switch clock (from CMU_CMU)
125
+
126
+
clock-names:
127
+
items:
128
+
- const: fin_pll
129
+
- const: switch
130
+
131
+
- if:
132
+
properties:
133
+
compatible:
134
+
const: axis,artpec8-cmu-fsys
135
+
136
+
then:
137
+
properties:
138
+
clocks:
139
+
items:
140
+
- description: External reference clock (25 MHz)
141
+
- description: CMU_FSYS SCAN0 clock (from CMU_CMU)
142
+
- description: CMU_FSYS SCAN1 clock (from CMU_CMU)
143
+
- description: CMU_FSYS BUS clock (from CMU_CMU)
144
+
- description: CMU_FSYS IP clock (from CMU_CMU)
145
+
146
+
clock-names:
147
+
items:
148
+
- const: fin_pll
149
+
- const: scan0
150
+
- const: scan1
151
+
- const: bus
152
+
- const: ip
153
+
154
+
- if:
155
+
properties:
156
+
compatible:
157
+
const: axis,artpec8-cmu-imem
158
+
159
+
then:
160
+
properties:
161
+
clocks:
162
+
items:
163
+
- description: External reference clock (25 MHz)
164
+
- description: CMU_IMEM ACLK clock (from CMU_CMU)
165
+
- description: CMU_IMEM JPEG clock (from CMU_CMU)
166
+
167
+
clock-names:
168
+
items:
169
+
- const: fin_pll
170
+
- const: aclk
171
+
- const: jpeg
172
+
173
+
- if:
174
+
properties:
175
+
compatible:
176
+
const: axis,artpec8-cmu-peri
177
+
178
+
then:
179
+
properties:
180
+
clocks:
181
+
items:
182
+
- description: External reference clock (25 MHz)
183
+
- description: CMU_PERI IP clock (from CMU_CMU)
184
+
- description: CMU_PERI AUDIO clock (from CMU_CMU)
185
+
- description: CMU_PERI DISP clock (from CMU_CMU)
186
+
187
+
clock-names:
188
+
items:
189
+
- const: fin_pll
190
+
- const: ip
191
+
- const: audio
192
+
- const: disp
193
+
194
+
additionalProperties: false
195
+
196
+
examples:
197
+
# Clock controller node for CMU_FSYS
198
+
- |
199
+
#include <dt-bindings/clock/axis,artpec8-clk.h>
200
+
201
+
cmu_fsys: clock-controller@16c10000 {
202
+
compatible = "axis,artpec8-cmu-fsys";
203
+
reg = <0x16c10000 0x4000>;
204
+
#clock-cells = <1>;
205
+
clocks = <&fin_pll>,
206
+
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
207
+
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
208
+
<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
209
+
<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
210
+
clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
211
+
};
212
+
213
+
...
+24
Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
+24
Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
···
30
30
properties:
31
31
compatible:
32
32
enum:
33
+
- samsung,exynos990-cmu-peric1
34
+
- samsung,exynos990-cmu-peric0
33
35
- samsung,exynos990-cmu-hsi0
34
36
- samsung,exynos990-cmu-peris
35
37
- samsung,exynos990-cmu-top
···
58
56
- reg
59
57
60
58
allOf:
59
+
- if:
60
+
properties:
61
+
compatible:
62
+
contains:
63
+
enum:
64
+
- samsung,exynos990-cmu-peric1
65
+
- samsung,exynos990-cmu-peric0
66
+
67
+
then:
68
+
properties:
69
+
clocks:
70
+
items:
71
+
- description: External reference clock (26 MHz)
72
+
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
73
+
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
74
+
75
+
clock-names:
76
+
items:
77
+
- const: oscclk
78
+
- const: bus
79
+
- const: ip
80
+
61
81
- if:
62
82
properties:
63
83
compatible:
+1
Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
+1
Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
-3
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
-3
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
+3
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
+3
Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
+7
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+7
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
···
80
80
support for 64 KiB transactions whereas earlier chips supported no
81
81
more than 4 KiB per transactions.
82
82
const: nvidia,tegra194-i2c
83
+
- description:
84
+
Tegra264 has 17 generic I2C controllers, two of which are in the AON
85
+
(always-on) partition of the SoC. In addition to the features from
86
+
Tegra194, a SW mutex register is added to support use of the same I2C
87
+
instance across multiple firmwares.
88
+
const: nvidia,tegra264-i2c
83
89
84
90
reg:
85
91
maxItems: 1
···
192
186
contains:
193
187
enum:
194
188
- nvidia,tegra194-i2c
189
+
- nvidia,tegra264-i2c
195
190
then:
196
191
required:
197
192
- resets
+8
drivers/clk/clk-s2mps11.c
+8
drivers/clk/clk-s2mps11.c
···
11
11
#include <linux/regmap.h>
12
12
#include <linux/clk-provider.h>
13
13
#include <linux/platform_device.h>
14
+
#include <linux/mfd/samsung/s2mpg10.h>
14
15
#include <linux/mfd/samsung/s2mps11.h>
15
16
#include <linux/mfd/samsung/s2mps13.h>
16
17
#include <linux/mfd/samsung/s2mps14.h>
···
141
140
clk_data->num = S2MPS11_CLKS_NUM;
142
141
143
142
switch (hwid) {
143
+
case S2MPG10:
144
+
s2mps11_reg = S2MPG10_PMIC_RTCBUF;
145
+
break;
144
146
case S2MPS11X:
145
147
s2mps11_reg = S2MPS11_REG_RTC_CTRL;
146
148
break;
···
225
221
}
226
222
227
223
static const struct platform_device_id s2mps11_clk_id[] = {
224
+
{ "s2mpg10-clk", S2MPG10},
228
225
{ "s2mps11-clk", S2MPS11X},
229
226
{ "s2mps13-clk", S2MPS13X},
230
227
{ "s2mps14-clk", S2MPS14X},
···
246
241
*/
247
242
static const struct of_device_id s2mps11_dt_match[] __used = {
248
243
{
244
+
.compatible = "samsung,s2mpg10-clk",
245
+
.data = (void *)S2MPG10,
246
+
}, {
249
247
.compatible = "samsung,s2mps11-clk",
250
248
.data = (void *)S2MPS11X,
251
249
}, {
+5
-8
drivers/clk/meson/Kconfig
+5
-8
drivers/clk/meson/Kconfig
···
36
36
select COMMON_CLK_MESON_REGMAP
37
37
38
38
config COMMON_CLK_MESON_CLKC_UTILS
39
+
select REGMAP
40
+
select MFD_SYSCON
39
41
tristate
40
42
41
43
config COMMON_CLK_MESON_AO_CLKC
···
45
43
select COMMON_CLK_MESON_REGMAP
46
44
select COMMON_CLK_MESON_CLKC_UTILS
47
45
select RESET_CONTROLLER
48
-
49
-
config COMMON_CLK_MESON_EE_CLKC
50
-
tristate
51
-
select COMMON_CLK_MESON_REGMAP
52
-
select COMMON_CLK_MESON_CLKC_UTILS
53
46
54
47
config COMMON_CLK_MESON_CPU_DYNDIV
55
48
tristate
···
70
73
depends on ARM64
71
74
default ARCH_MESON
72
75
select COMMON_CLK_MESON_REGMAP
76
+
select COMMON_CLK_MESON_CLKC_UTILS
73
77
select COMMON_CLK_MESON_DUALDIV
74
78
select COMMON_CLK_MESON_VID_PLL_DIV
75
79
select COMMON_CLK_MESON_MPLL
76
80
select COMMON_CLK_MESON_PLL
77
81
select COMMON_CLK_MESON_AO_CLKC
78
-
select COMMON_CLK_MESON_EE_CLKC
79
82
select MFD_SYSCON
80
83
help
81
84
Support for the clock controller on AmLogic S905 devices, aka gxbb.
···
86
89
depends on ARM64
87
90
default ARCH_MESON
88
91
select COMMON_CLK_MESON_REGMAP
92
+
select COMMON_CLK_MESON_CLKC_UTILS
89
93
select COMMON_CLK_MESON_DUALDIV
90
94
select COMMON_CLK_MESON_MPLL
91
95
select COMMON_CLK_MESON_PLL
92
96
select COMMON_CLK_MESON_AO_CLKC
93
-
select COMMON_CLK_MESON_EE_CLKC
94
97
select MFD_SYSCON
95
98
help
96
99
Support for the clock controller on AmLogic A113D devices, aka axg.
···
164
167
depends on ARM64
165
168
default ARCH_MESON
166
169
select COMMON_CLK_MESON_REGMAP
170
+
select COMMON_CLK_MESON_CLKC_UTILS
167
171
select COMMON_CLK_MESON_DUALDIV
168
172
select COMMON_CLK_MESON_MPLL
169
173
select COMMON_CLK_MESON_PLL
170
174
select COMMON_CLK_MESON_AO_CLKC
171
-
select COMMON_CLK_MESON_EE_CLKC
172
175
select COMMON_CLK_MESON_CPU_DYNDIV
173
176
select COMMON_CLK_MESON_VID_PLL_DIV
174
177
select COMMON_CLK_MESON_VCLK
-1
drivers/clk/meson/Makefile
-1
drivers/clk/meson/Makefile
···
5
5
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
6
6
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
7
7
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
8
-
obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
9
8
obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
10
9
obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
11
10
obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
+491
-508
drivers/clk/meson/a1-peripherals.c
+491
-508
drivers/clk/meson/a1-peripherals.c
···
46
46
#define PSRAM_CLK_CTRL 0xf4
47
47
#define DMC_CLK_CTRL 0xf8
48
48
49
-
static struct clk_regmap xtal_in = {
49
+
static struct clk_regmap a1_xtal_in = {
50
50
.data = &(struct clk_regmap_gate_data){
51
51
.offset = SYS_OSCIN_CTRL,
52
52
.bit_idx = 0,
···
61
61
},
62
62
};
63
63
64
-
static struct clk_regmap fixpll_in = {
64
+
static struct clk_regmap a1_fixpll_in = {
65
65
.data = &(struct clk_regmap_gate_data){
66
66
.offset = SYS_OSCIN_CTRL,
67
67
.bit_idx = 1,
···
76
76
},
77
77
};
78
78
79
-
static struct clk_regmap usb_phy_in = {
79
+
static struct clk_regmap a1_usb_phy_in = {
80
80
.data = &(struct clk_regmap_gate_data){
81
81
.offset = SYS_OSCIN_CTRL,
82
82
.bit_idx = 2,
···
91
91
},
92
92
};
93
93
94
-
static struct clk_regmap usb_ctrl_in = {
94
+
static struct clk_regmap a1_usb_ctrl_in = {
95
95
.data = &(struct clk_regmap_gate_data){
96
96
.offset = SYS_OSCIN_CTRL,
97
97
.bit_idx = 3,
···
106
106
},
107
107
};
108
108
109
-
static struct clk_regmap hifipll_in = {
109
+
static struct clk_regmap a1_hifipll_in = {
110
110
.data = &(struct clk_regmap_gate_data){
111
111
.offset = SYS_OSCIN_CTRL,
112
112
.bit_idx = 4,
···
121
121
},
122
122
};
123
123
124
-
static struct clk_regmap syspll_in = {
124
+
static struct clk_regmap a1_syspll_in = {
125
125
.data = &(struct clk_regmap_gate_data){
126
126
.offset = SYS_OSCIN_CTRL,
127
127
.bit_idx = 5,
···
136
136
},
137
137
};
138
138
139
-
static struct clk_regmap dds_in = {
139
+
static struct clk_regmap a1_dds_in = {
140
140
.data = &(struct clk_regmap_gate_data){
141
141
.offset = SYS_OSCIN_CTRL,
142
142
.bit_idx = 6,
···
151
151
},
152
152
};
153
153
154
-
static struct clk_regmap rtc_32k_in = {
154
+
static struct clk_regmap a1_rtc_32k_in = {
155
155
.data = &(struct clk_regmap_gate_data){
156
156
.offset = RTC_BY_OSCIN_CTRL0,
157
157
.bit_idx = 31,
···
166
166
},
167
167
};
168
168
169
-
static const struct meson_clk_dualdiv_param clk_32k_div_table[] = {
169
+
static const struct meson_clk_dualdiv_param a1_32k_div_table[] = {
170
170
{
171
171
.dual = 1,
172
172
.n1 = 733,
···
177
177
{}
178
178
};
179
179
180
-
static struct clk_regmap rtc_32k_div = {
180
+
static struct clk_regmap a1_rtc_32k_div = {
181
181
.data = &(struct meson_clk_dualdiv_data){
182
182
.n1 = {
183
183
.reg_off = RTC_BY_OSCIN_CTRL0,
···
204
204
.shift = 28,
205
205
.width = 1,
206
206
},
207
-
.table = clk_32k_div_table,
207
+
.table = a1_32k_div_table,
208
208
},
209
209
.hw.init = &(struct clk_init_data){
210
210
.name = "rtc_32k_div",
211
211
.ops = &meson_clk_dualdiv_ops,
212
212
.parent_hws = (const struct clk_hw *[]) {
213
-
&rtc_32k_in.hw
213
+
&a1_rtc_32k_in.hw
214
214
},
215
215
.num_parents = 1,
216
216
},
217
217
};
218
218
219
-
static struct clk_regmap rtc_32k_xtal = {
219
+
static struct clk_regmap a1_rtc_32k_xtal = {
220
220
.data = &(struct clk_regmap_gate_data){
221
221
.offset = RTC_BY_OSCIN_CTRL1,
222
222
.bit_idx = 24,
···
225
225
.name = "rtc_32k_xtal",
226
226
.ops = &clk_regmap_gate_ops,
227
227
.parent_hws = (const struct clk_hw *[]) {
228
-
&rtc_32k_in.hw
228
+
&a1_rtc_32k_in.hw
229
229
},
230
230
.num_parents = 1,
231
231
},
232
232
};
233
233
234
-
static struct clk_regmap rtc_32k_sel = {
234
+
static struct clk_regmap a1_rtc_32k_sel = {
235
235
.data = &(struct clk_regmap_mux_data) {
236
236
.offset = RTC_CTRL,
237
237
.mask = 0x3,
···
242
242
.name = "rtc_32k_sel",
243
243
.ops = &clk_regmap_mux_ops,
244
244
.parent_hws = (const struct clk_hw *[]) {
245
-
&rtc_32k_xtal.hw,
246
-
&rtc_32k_div.hw,
245
+
&a1_rtc_32k_xtal.hw,
246
+
&a1_rtc_32k_div.hw,
247
247
},
248
248
.num_parents = 2,
249
249
.flags = CLK_SET_RATE_PARENT,
250
250
},
251
251
};
252
252
253
-
static struct clk_regmap rtc = {
253
+
static struct clk_regmap a1_rtc = {
254
254
.data = &(struct clk_regmap_gate_data){
255
255
.offset = RTC_BY_OSCIN_CTRL0,
256
256
.bit_idx = 30,
···
259
259
.name = "rtc",
260
260
.ops = &clk_regmap_gate_ops,
261
261
.parent_hws = (const struct clk_hw *[]) {
262
-
&rtc_32k_sel.hw
262
+
&a1_rtc_32k_sel.hw
263
263
},
264
264
.num_parents = 1,
265
265
.flags = CLK_SET_RATE_PARENT,
266
266
},
267
267
};
268
268
269
-
static u32 mux_table_sys[] = { 0, 1, 2, 3, 7 };
270
-
static const struct clk_parent_data sys_parents[] = {
269
+
static u32 a1_sys_parents_val_table[] = { 0, 1, 2, 3, 7 };
270
+
static const struct clk_parent_data a1_sys_parents[] = {
271
271
{ .fw_name = "xtal" },
272
272
{ .fw_name = "fclk_div2" },
273
273
{ .fw_name = "fclk_div3" },
274
274
{ .fw_name = "fclk_div5" },
275
-
{ .hw = &rtc.hw },
275
+
{ .hw = &a1_rtc.hw },
276
276
};
277
277
278
-
static struct clk_regmap sys_b_sel = {
278
+
static struct clk_regmap a1_sys_b_sel = {
279
279
.data = &(struct clk_regmap_mux_data){
280
280
.offset = SYS_CLK_CTRL0,
281
281
.mask = 0x7,
282
282
.shift = 26,
283
-
.table = mux_table_sys,
283
+
.table = a1_sys_parents_val_table,
284
284
},
285
285
.hw.init = &(struct clk_init_data){
286
286
.name = "sys_b_sel",
287
287
.ops = &clk_regmap_mux_ro_ops,
288
-
.parent_data = sys_parents,
289
-
.num_parents = ARRAY_SIZE(sys_parents),
288
+
.parent_data = a1_sys_parents,
289
+
.num_parents = ARRAY_SIZE(a1_sys_parents),
290
290
},
291
291
};
292
292
293
-
static struct clk_regmap sys_b_div = {
293
+
static struct clk_regmap a1_sys_b_div = {
294
294
.data = &(struct clk_regmap_div_data){
295
295
.offset = SYS_CLK_CTRL0,
296
296
.shift = 16,
···
300
300
.name = "sys_b_div",
301
301
.ops = &clk_regmap_divider_ro_ops,
302
302
.parent_hws = (const struct clk_hw *[]) {
303
-
&sys_b_sel.hw
303
+
&a1_sys_b_sel.hw
304
304
},
305
305
.num_parents = 1,
306
306
.flags = CLK_SET_RATE_PARENT,
307
307
},
308
308
};
309
309
310
-
static struct clk_regmap sys_b = {
310
+
static struct clk_regmap a1_sys_b = {
311
311
.data = &(struct clk_regmap_gate_data){
312
312
.offset = SYS_CLK_CTRL0,
313
313
.bit_idx = 29,
···
316
316
.name = "sys_b",
317
317
.ops = &clk_regmap_gate_ro_ops,
318
318
.parent_hws = (const struct clk_hw *[]) {
319
-
&sys_b_div.hw
319
+
&a1_sys_b_div.hw
320
320
},
321
321
.num_parents = 1,
322
322
.flags = CLK_SET_RATE_PARENT,
323
323
},
324
324
};
325
325
326
-
static struct clk_regmap sys_a_sel = {
326
+
static struct clk_regmap a1_sys_a_sel = {
327
327
.data = &(struct clk_regmap_mux_data){
328
328
.offset = SYS_CLK_CTRL0,
329
329
.mask = 0x7,
330
330
.shift = 10,
331
-
.table = mux_table_sys,
331
+
.table = a1_sys_parents_val_table,
332
332
},
333
333
.hw.init = &(struct clk_init_data){
334
334
.name = "sys_a_sel",
335
335
.ops = &clk_regmap_mux_ro_ops,
336
-
.parent_data = sys_parents,
337
-
.num_parents = ARRAY_SIZE(sys_parents),
336
+
.parent_data = a1_sys_parents,
337
+
.num_parents = ARRAY_SIZE(a1_sys_parents),
338
338
},
339
339
};
340
340
341
-
static struct clk_regmap sys_a_div = {
341
+
static struct clk_regmap a1_sys_a_div = {
342
342
.data = &(struct clk_regmap_div_data){
343
343
.offset = SYS_CLK_CTRL0,
344
344
.shift = 0,
···
348
348
.name = "sys_a_div",
349
349
.ops = &clk_regmap_divider_ro_ops,
350
350
.parent_hws = (const struct clk_hw *[]) {
351
-
&sys_a_sel.hw
351
+
&a1_sys_a_sel.hw
352
352
},
353
353
.num_parents = 1,
354
354
.flags = CLK_SET_RATE_PARENT,
355
355
},
356
356
};
357
357
358
-
static struct clk_regmap sys_a = {
358
+
static struct clk_regmap a1_sys_a = {
359
359
.data = &(struct clk_regmap_gate_data){
360
360
.offset = SYS_CLK_CTRL0,
361
361
.bit_idx = 13,
···
364
364
.name = "sys_a",
365
365
.ops = &clk_regmap_gate_ro_ops,
366
366
.parent_hws = (const struct clk_hw *[]) {
367
-
&sys_a_div.hw
367
+
&a1_sys_a_div.hw
368
368
},
369
369
.num_parents = 1,
370
370
.flags = CLK_SET_RATE_PARENT,
371
371
},
372
372
};
373
373
374
-
static struct clk_regmap sys = {
374
+
static struct clk_regmap a1_sys = {
375
375
.data = &(struct clk_regmap_mux_data){
376
376
.offset = SYS_CLK_CTRL0,
377
377
.mask = 0x1,
···
381
381
.name = "sys",
382
382
.ops = &clk_regmap_mux_ro_ops,
383
383
.parent_hws = (const struct clk_hw *[]) {
384
-
&sys_a.hw,
385
-
&sys_b.hw,
384
+
&a1_sys_a.hw,
385
+
&a1_sys_b.hw,
386
386
},
387
387
.num_parents = 2,
388
388
/*
···
398
398
},
399
399
};
400
400
401
-
static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 };
402
-
static const struct clk_parent_data dsp_ab_parent_data[] = {
401
+
static u32 a1_dsp_parents_val_table[] = { 0, 1, 2, 3, 4, 7 };
402
+
static const struct clk_parent_data a1_dsp_parents[] = {
403
403
{ .fw_name = "xtal", },
404
404
{ .fw_name = "fclk_div2", },
405
405
{ .fw_name = "fclk_div3", },
406
406
{ .fw_name = "fclk_div5", },
407
407
{ .fw_name = "hifi_pll", },
408
-
{ .hw = &rtc.hw },
408
+
{ .hw = &a1_rtc.hw },
409
409
};
410
410
411
-
static struct clk_regmap dspa_a_sel = {
411
+
static struct clk_regmap a1_dspa_a_sel = {
412
412
.data = &(struct clk_regmap_mux_data){
413
413
.offset = DSPA_CLK_CTRL0,
414
414
.mask = 0x7,
415
415
.shift = 10,
416
-
.table = mux_table_dsp_ab,
416
+
.table = a1_dsp_parents_val_table,
417
417
},
418
418
.hw.init = &(struct clk_init_data){
419
419
.name = "dspa_a_sel",
420
420
.ops = &clk_regmap_mux_ops,
421
-
.parent_data = dsp_ab_parent_data,
422
-
.num_parents = ARRAY_SIZE(dsp_ab_parent_data),
421
+
.parent_data = a1_dsp_parents,
422
+
.num_parents = ARRAY_SIZE(a1_dsp_parents),
423
423
},
424
424
};
425
425
426
-
static struct clk_regmap dspa_a_div = {
426
+
static struct clk_regmap a1_dspa_a_div = {
427
427
.data = &(struct clk_regmap_div_data){
428
428
.offset = DSPA_CLK_CTRL0,
429
429
.shift = 0,
···
433
433
.name = "dspa_a_div",
434
434
.ops = &clk_regmap_divider_ops,
435
435
.parent_hws = (const struct clk_hw *[]) {
436
-
&dspa_a_sel.hw
436
+
&a1_dspa_a_sel.hw
437
437
},
438
438
.num_parents = 1,
439
439
.flags = CLK_SET_RATE_PARENT,
440
440
},
441
441
};
442
442
443
-
static struct clk_regmap dspa_a = {
443
+
static struct clk_regmap a1_dspa_a = {
444
444
.data = &(struct clk_regmap_gate_data){
445
445
.offset = DSPA_CLK_CTRL0,
446
446
.bit_idx = 13,
···
449
449
.name = "dspa_a",
450
450
.ops = &clk_regmap_gate_ops,
451
451
.parent_hws = (const struct clk_hw *[]) {
452
-
&dspa_a_div.hw
452
+
&a1_dspa_a_div.hw
453
453
},
454
454
.num_parents = 1,
455
455
.flags = CLK_SET_RATE_PARENT,
456
456
},
457
457
};
458
458
459
-
static struct clk_regmap dspa_b_sel = {
459
+
static struct clk_regmap a1_dspa_b_sel = {
460
460
.data = &(struct clk_regmap_mux_data){
461
461
.offset = DSPA_CLK_CTRL0,
462
462
.mask = 0x7,
463
463
.shift = 26,
464
-
.table = mux_table_dsp_ab,
464
+
.table = a1_dsp_parents_val_table,
465
465
},
466
466
.hw.init = &(struct clk_init_data){
467
467
.name = "dspa_b_sel",
468
468
.ops = &clk_regmap_mux_ops,
469
-
.parent_data = dsp_ab_parent_data,
470
-
.num_parents = ARRAY_SIZE(dsp_ab_parent_data),
469
+
.parent_data = a1_dsp_parents,
470
+
.num_parents = ARRAY_SIZE(a1_dsp_parents),
471
471
},
472
472
};
473
473
474
-
static struct clk_regmap dspa_b_div = {
474
+
static struct clk_regmap a1_dspa_b_div = {
475
475
.data = &(struct clk_regmap_div_data){
476
476
.offset = DSPA_CLK_CTRL0,
477
477
.shift = 16,
···
481
481
.name = "dspa_b_div",
482
482
.ops = &clk_regmap_divider_ops,
483
483
.parent_hws = (const struct clk_hw *[]) {
484
-
&dspa_b_sel.hw
484
+
&a1_dspa_b_sel.hw
485
485
},
486
486
.num_parents = 1,
487
487
.flags = CLK_SET_RATE_PARENT,
488
488
},
489
489
};
490
490
491
-
static struct clk_regmap dspa_b = {
491
+
static struct clk_regmap a1_dspa_b = {
492
492
.data = &(struct clk_regmap_gate_data){
493
493
.offset = DSPA_CLK_CTRL0,
494
494
.bit_idx = 29,
···
497
497
.name = "dspa_b",
498
498
.ops = &clk_regmap_gate_ops,
499
499
.parent_hws = (const struct clk_hw *[]) {
500
-
&dspa_b_div.hw
500
+
&a1_dspa_b_div.hw
501
501
},
502
502
.num_parents = 1,
503
503
.flags = CLK_SET_RATE_PARENT,
504
504
},
505
505
};
506
506
507
-
static struct clk_regmap dspa_sel = {
507
+
static struct clk_regmap a1_dspa_sel = {
508
508
.data = &(struct clk_regmap_mux_data){
509
509
.offset = DSPA_CLK_CTRL0,
510
510
.mask = 0x1,
···
514
514
.name = "dspa_sel",
515
515
.ops = &clk_regmap_mux_ops,
516
516
.parent_hws = (const struct clk_hw *[]) {
517
-
&dspa_a.hw,
518
-
&dspa_b.hw,
517
+
&a1_dspa_a.hw,
518
+
&a1_dspa_b.hw,
519
519
},
520
520
.num_parents = 2,
521
521
.flags = CLK_SET_RATE_PARENT,
522
522
},
523
523
};
524
524
525
-
static struct clk_regmap dspa_en = {
525
+
static struct clk_regmap a1_dspa_en = {
526
526
.data = &(struct clk_regmap_gate_data){
527
527
.offset = DSPA_CLK_EN,
528
528
.bit_idx = 1,
···
531
531
.name = "dspa_en",
532
532
.ops = &clk_regmap_gate_ops,
533
533
.parent_hws = (const struct clk_hw *[]) {
534
-
&dspa_sel.hw
534
+
&a1_dspa_sel.hw
535
535
},
536
536
.num_parents = 1,
537
537
.flags = CLK_SET_RATE_PARENT,
538
538
},
539
539
};
540
540
541
-
static struct clk_regmap dspa_en_nic = {
541
+
static struct clk_regmap a1_dspa_en_nic = {
542
542
.data = &(struct clk_regmap_gate_data){
543
543
.offset = DSPA_CLK_EN,
544
544
.bit_idx = 0,
···
547
547
.name = "dspa_en_nic",
548
548
.ops = &clk_regmap_gate_ops,
549
549
.parent_hws = (const struct clk_hw *[]) {
550
-
&dspa_sel.hw
550
+
&a1_dspa_sel.hw
551
551
},
552
552
.num_parents = 1,
553
553
.flags = CLK_SET_RATE_PARENT,
554
554
},
555
555
};
556
556
557
-
static struct clk_regmap dspb_a_sel = {
557
+
static struct clk_regmap a1_dspb_a_sel = {
558
558
.data = &(struct clk_regmap_mux_data){
559
559
.offset = DSPB_CLK_CTRL0,
560
560
.mask = 0x7,
561
561
.shift = 10,
562
-
.table = mux_table_dsp_ab,
562
+
.table = a1_dsp_parents_val_table,
563
563
},
564
564
.hw.init = &(struct clk_init_data){
565
565
.name = "dspb_a_sel",
566
566
.ops = &clk_regmap_mux_ops,
567
-
.parent_data = dsp_ab_parent_data,
568
-
.num_parents = ARRAY_SIZE(dsp_ab_parent_data),
567
+
.parent_data = a1_dsp_parents,
568
+
.num_parents = ARRAY_SIZE(a1_dsp_parents),
569
569
},
570
570
};
571
571
572
-
static struct clk_regmap dspb_a_div = {
572
+
static struct clk_regmap a1_dspb_a_div = {
573
573
.data = &(struct clk_regmap_div_data){
574
574
.offset = DSPB_CLK_CTRL0,
575
575
.shift = 0,
···
579
579
.name = "dspb_a_div",
580
580
.ops = &clk_regmap_divider_ops,
581
581
.parent_hws = (const struct clk_hw *[]) {
582
-
&dspb_a_sel.hw
582
+
&a1_dspb_a_sel.hw
583
583
},
584
584
.num_parents = 1,
585
585
.flags = CLK_SET_RATE_PARENT,
586
586
},
587
587
};
588
588
589
-
static struct clk_regmap dspb_a = {
589
+
static struct clk_regmap a1_dspb_a = {
590
590
.data = &(struct clk_regmap_gate_data){
591
591
.offset = DSPB_CLK_CTRL0,
592
592
.bit_idx = 13,
···
595
595
.name = "dspb_a",
596
596
.ops = &clk_regmap_gate_ops,
597
597
.parent_hws = (const struct clk_hw *[]) {
598
-
&dspb_a_div.hw
598
+
&a1_dspb_a_div.hw
599
599
},
600
600
.num_parents = 1,
601
601
.flags = CLK_SET_RATE_PARENT,
602
602
},
603
603
};
604
604
605
-
static struct clk_regmap dspb_b_sel = {
605
+
static struct clk_regmap a1_dspb_b_sel = {
606
606
.data = &(struct clk_regmap_mux_data){
607
607
.offset = DSPB_CLK_CTRL0,
608
608
.mask = 0x7,
609
609
.shift = 26,
610
-
.table = mux_table_dsp_ab,
610
+
.table = a1_dsp_parents_val_table,
611
611
},
612
612
.hw.init = &(struct clk_init_data){
613
613
.name = "dspb_b_sel",
614
614
.ops = &clk_regmap_mux_ops,
615
-
.parent_data = dsp_ab_parent_data,
616
-
.num_parents = ARRAY_SIZE(dsp_ab_parent_data),
615
+
.parent_data = a1_dsp_parents,
616
+
.num_parents = ARRAY_SIZE(a1_dsp_parents),
617
617
},
618
618
};
619
619
620
-
static struct clk_regmap dspb_b_div = {
620
+
static struct clk_regmap a1_dspb_b_div = {
621
621
.data = &(struct clk_regmap_div_data){
622
622
.offset = DSPB_CLK_CTRL0,
623
623
.shift = 16,
···
627
627
.name = "dspb_b_div",
628
628
.ops = &clk_regmap_divider_ops,
629
629
.parent_hws = (const struct clk_hw *[]) {
630
-
&dspb_b_sel.hw
630
+
&a1_dspb_b_sel.hw
631
631
},
632
632
.num_parents = 1,
633
633
.flags = CLK_SET_RATE_PARENT,
634
634
},
635
635
};
636
636
637
-
static struct clk_regmap dspb_b = {
637
+
static struct clk_regmap a1_dspb_b = {
638
638
.data = &(struct clk_regmap_gate_data){
639
639
.offset = DSPB_CLK_CTRL0,
640
640
.bit_idx = 29,
···
643
643
.name = "dspb_b",
644
644
.ops = &clk_regmap_gate_ops,
645
645
.parent_hws = (const struct clk_hw *[]) {
646
-
&dspb_b_div.hw
646
+
&a1_dspb_b_div.hw
647
647
},
648
648
.num_parents = 1,
649
649
.flags = CLK_SET_RATE_PARENT,
650
650
},
651
651
};
652
652
653
-
static struct clk_regmap dspb_sel = {
653
+
static struct clk_regmap a1_dspb_sel = {
654
654
.data = &(struct clk_regmap_mux_data){
655
655
.offset = DSPB_CLK_CTRL0,
656
656
.mask = 0x1,
···
660
660
.name = "dspb_sel",
661
661
.ops = &clk_regmap_mux_ops,
662
662
.parent_hws = (const struct clk_hw *[]) {
663
-
&dspb_a.hw,
664
-
&dspb_b.hw,
663
+
&a1_dspb_a.hw,
664
+
&a1_dspb_b.hw,
665
665
},
666
666
.num_parents = 2,
667
667
.flags = CLK_SET_RATE_PARENT,
668
668
},
669
669
};
670
670
671
-
static struct clk_regmap dspb_en = {
671
+
static struct clk_regmap a1_dspb_en = {
672
672
.data = &(struct clk_regmap_gate_data){
673
673
.offset = DSPB_CLK_EN,
674
674
.bit_idx = 1,
···
677
677
.name = "dspb_en",
678
678
.ops = &clk_regmap_gate_ops,
679
679
.parent_hws = (const struct clk_hw *[]) {
680
-
&dspb_sel.hw
680
+
&a1_dspb_sel.hw
681
681
},
682
682
.num_parents = 1,
683
683
.flags = CLK_SET_RATE_PARENT,
684
684
},
685
685
};
686
686
687
-
static struct clk_regmap dspb_en_nic = {
687
+
static struct clk_regmap a1_dspb_en_nic = {
688
688
.data = &(struct clk_regmap_gate_data){
689
689
.offset = DSPB_CLK_EN,
690
690
.bit_idx = 0,
···
693
693
.name = "dspb_en_nic",
694
694
.ops = &clk_regmap_gate_ops,
695
695
.parent_hws = (const struct clk_hw *[]) {
696
-
&dspb_sel.hw
696
+
&a1_dspb_sel.hw
697
697
},
698
698
.num_parents = 1,
699
699
.flags = CLK_SET_RATE_PARENT,
700
700
},
701
701
};
702
702
703
-
static struct clk_regmap clk_24m = {
703
+
static struct clk_regmap a1_24m = {
704
704
.data = &(struct clk_regmap_gate_data){
705
705
.offset = CLK12_24_CTRL,
706
706
.bit_idx = 11,
···
715
715
},
716
716
};
717
717
718
-
static struct clk_fixed_factor clk_24m_div2 = {
718
+
static struct clk_fixed_factor a1_24m_div2 = {
719
719
.mult = 1,
720
720
.div = 2,
721
721
.hw.init = &(struct clk_init_data){
722
722
.name = "24m_div2",
723
723
.ops = &clk_fixed_factor_ops,
724
724
.parent_hws = (const struct clk_hw *[]) {
725
-
&clk_24m.hw
725
+
&a1_24m.hw
726
726
},
727
727
.num_parents = 1,
728
728
},
729
729
};
730
730
731
-
static struct clk_regmap clk_12m = {
731
+
static struct clk_regmap a1_12m = {
732
732
.data = &(struct clk_regmap_gate_data){
733
733
.offset = CLK12_24_CTRL,
734
734
.bit_idx = 10,
···
737
737
.name = "12m",
738
738
.ops = &clk_regmap_gate_ops,
739
739
.parent_hws = (const struct clk_hw *[]) {
740
-
&clk_24m_div2.hw
740
+
&a1_24m_div2.hw
741
741
},
742
742
.num_parents = 1,
743
743
},
744
744
};
745
745
746
-
static struct clk_regmap fclk_div2_divn_pre = {
746
+
static struct clk_regmap a1_fclk_div2_divn_pre = {
747
747
.data = &(struct clk_regmap_div_data){
748
748
.offset = CLK12_24_CTRL,
749
749
.shift = 0,
···
759
759
},
760
760
};
761
761
762
-
static struct clk_regmap fclk_div2_divn = {
762
+
static struct clk_regmap a1_fclk_div2_divn = {
763
763
.data = &(struct clk_regmap_gate_data){
764
764
.offset = CLK12_24_CTRL,
765
765
.bit_idx = 12,
···
768
768
.name = "fclk_div2_divn",
769
769
.ops = &clk_regmap_gate_ops,
770
770
.parent_hws = (const struct clk_hw *[]) {
771
-
&fclk_div2_divn_pre.hw
771
+
&a1_fclk_div2_divn_pre.hw
772
772
},
773
773
.num_parents = 1,
774
774
.flags = CLK_SET_RATE_PARENT,
···
779
779
* the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver,
780
780
* the index 4 is the clock measurement source, it's not supported yet
781
781
*/
782
-
static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 };
783
-
static const struct clk_parent_data gen_parent_data[] = {
782
+
static u32 a1_gen_parents_val_table[] = { 0, 1, 3, 5, 6, 7, 8 };
783
+
static const struct clk_parent_data a1_gen_parents[] = {
784
784
{ .fw_name = "xtal", },
785
-
{ .hw = &rtc.hw },
785
+
{ .hw = &a1_rtc.hw },
786
786
{ .fw_name = "hifi_pll", },
787
787
{ .fw_name = "fclk_div2", },
788
788
{ .fw_name = "fclk_div3", },
···
790
790
{ .fw_name = "fclk_div7", },
791
791
};
792
792
793
-
static struct clk_regmap gen_sel = {
793
+
static struct clk_regmap a1_gen_sel = {
794
794
.data = &(struct clk_regmap_mux_data){
795
795
.offset = GEN_CLK_CTRL,
796
796
.mask = 0xf,
797
797
.shift = 12,
798
-
.table = gen_table,
798
+
.table = a1_gen_parents_val_table,
799
799
},
800
800
.hw.init = &(struct clk_init_data){
801
801
.name = "gen_sel",
802
802
.ops = &clk_regmap_mux_ops,
803
-
.parent_data = gen_parent_data,
804
-
.num_parents = ARRAY_SIZE(gen_parent_data),
803
+
.parent_data = a1_gen_parents,
804
+
.num_parents = ARRAY_SIZE(a1_gen_parents),
805
805
/*
806
806
* The GEN clock can be connected to an external pad, so it
807
807
* may be set up directly from the device tree. Additionally,
···
813
813
},
814
814
};
815
815
816
-
static struct clk_regmap gen_div = {
816
+
static struct clk_regmap a1_gen_div = {
817
817
.data = &(struct clk_regmap_div_data){
818
818
.offset = GEN_CLK_CTRL,
819
819
.shift = 0,
···
823
823
.name = "gen_div",
824
824
.ops = &clk_regmap_divider_ops,
825
825
.parent_hws = (const struct clk_hw *[]) {
826
-
&gen_sel.hw
826
+
&a1_gen_sel.hw
827
827
},
828
828
.num_parents = 1,
829
829
.flags = CLK_SET_RATE_PARENT,
830
830
},
831
831
};
832
832
833
-
static struct clk_regmap gen = {
833
+
static struct clk_regmap a1_gen = {
834
834
.data = &(struct clk_regmap_gate_data){
835
835
.offset = GEN_CLK_CTRL,
836
836
.bit_idx = 11,
···
839
839
.name = "gen",
840
840
.ops = &clk_regmap_gate_ops,
841
841
.parent_hws = (const struct clk_hw *[]) {
842
-
&gen_div.hw
842
+
&a1_gen_div.hw
843
843
},
844
844
.num_parents = 1,
845
845
.flags = CLK_SET_RATE_PARENT,
846
846
},
847
847
};
848
848
849
-
static struct clk_regmap saradc_sel = {
849
+
static struct clk_regmap a1_saradc_sel = {
850
850
.data = &(struct clk_regmap_mux_data){
851
851
.offset = SAR_ADC_CLK_CTRL,
852
852
.mask = 0x1,
···
857
857
.ops = &clk_regmap_mux_ops,
858
858
.parent_data = (const struct clk_parent_data []) {
859
859
{ .fw_name = "xtal", },
860
-
{ .hw = &sys.hw, },
860
+
{ .hw = &a1_sys.hw, },
861
861
},
862
862
.num_parents = 2,
863
863
},
864
864
};
865
865
866
-
static struct clk_regmap saradc_div = {
866
+
static struct clk_regmap a1_saradc_div = {
867
867
.data = &(struct clk_regmap_div_data){
868
868
.offset = SAR_ADC_CLK_CTRL,
869
869
.shift = 0,
···
873
873
.name = "saradc_div",
874
874
.ops = &clk_regmap_divider_ops,
875
875
.parent_hws = (const struct clk_hw *[]) {
876
-
&saradc_sel.hw
876
+
&a1_saradc_sel.hw
877
877
},
878
878
.num_parents = 1,
879
879
.flags = CLK_SET_RATE_PARENT,
880
880
},
881
881
};
882
882
883
-
static struct clk_regmap saradc = {
883
+
static struct clk_regmap a1_saradc = {
884
884
.data = &(struct clk_regmap_gate_data){
885
885
.offset = SAR_ADC_CLK_CTRL,
886
886
.bit_idx = 8,
···
889
889
.name = "saradc",
890
890
.ops = &clk_regmap_gate_ops,
891
891
.parent_hws = (const struct clk_hw *[]) {
892
-
&saradc_div.hw
892
+
&a1_saradc_div.hw
893
893
},
894
894
.num_parents = 1,
895
895
.flags = CLK_SET_RATE_PARENT,
896
896
},
897
897
};
898
898
899
-
static const struct clk_parent_data pwm_abcd_parents[] = {
899
+
static const struct clk_parent_data a1_pwm_abcd_parents[] = {
900
900
{ .fw_name = "xtal", },
901
-
{ .hw = &sys.hw },
902
-
{ .hw = &rtc.hw },
901
+
{ .hw = &a1_sys.hw },
902
+
{ .hw = &a1_rtc.hw },
903
903
};
904
904
905
-
static struct clk_regmap pwm_a_sel = {
905
+
static struct clk_regmap a1_pwm_a_sel = {
906
906
.data = &(struct clk_regmap_mux_data){
907
907
.offset = PWM_CLK_AB_CTRL,
908
908
.mask = 0x1,
···
911
911
.hw.init = &(struct clk_init_data){
912
912
.name = "pwm_a_sel",
913
913
.ops = &clk_regmap_mux_ops,
914
-
.parent_data = pwm_abcd_parents,
915
-
.num_parents = ARRAY_SIZE(pwm_abcd_parents),
914
+
.parent_data = a1_pwm_abcd_parents,
915
+
.num_parents = ARRAY_SIZE(a1_pwm_abcd_parents),
916
916
},
917
917
};
918
918
919
-
static struct clk_regmap pwm_a_div = {
919
+
static struct clk_regmap a1_pwm_a_div = {
920
920
.data = &(struct clk_regmap_div_data){
921
921
.offset = PWM_CLK_AB_CTRL,
922
922
.shift = 0,
···
926
926
.name = "pwm_a_div",
927
927
.ops = &clk_regmap_divider_ops,
928
928
.parent_hws = (const struct clk_hw *[]) {
929
-
&pwm_a_sel.hw
929
+
&a1_pwm_a_sel.hw
930
930
},
931
931
.num_parents = 1,
932
932
.flags = CLK_SET_RATE_PARENT,
933
933
},
934
934
};
935
935
936
-
static struct clk_regmap pwm_a = {
936
+
static struct clk_regmap a1_pwm_a = {
937
937
.data = &(struct clk_regmap_gate_data){
938
938
.offset = PWM_CLK_AB_CTRL,
939
939
.bit_idx = 8,
···
942
942
.name = "pwm_a",
943
943
.ops = &clk_regmap_gate_ops,
944
944
.parent_hws = (const struct clk_hw *[]) {
945
-
&pwm_a_div.hw
945
+
&a1_pwm_a_div.hw
946
946
},
947
947
.num_parents = 1,
948
948
.flags = CLK_SET_RATE_PARENT,
949
949
},
950
950
};
951
951
952
-
static struct clk_regmap pwm_b_sel = {
952
+
static struct clk_regmap a1_pwm_b_sel = {
953
953
.data = &(struct clk_regmap_mux_data){
954
954
.offset = PWM_CLK_AB_CTRL,
955
955
.mask = 0x1,
···
958
958
.hw.init = &(struct clk_init_data){
959
959
.name = "pwm_b_sel",
960
960
.ops = &clk_regmap_mux_ops,
961
-
.parent_data = pwm_abcd_parents,
962
-
.num_parents = ARRAY_SIZE(pwm_abcd_parents),
961
+
.parent_data = a1_pwm_abcd_parents,
962
+
.num_parents = ARRAY_SIZE(a1_pwm_abcd_parents),
963
963
},
964
964
};
965
965
966
-
static struct clk_regmap pwm_b_div = {
966
+
static struct clk_regmap a1_pwm_b_div = {
967
967
.data = &(struct clk_regmap_div_data){
968
968
.offset = PWM_CLK_AB_CTRL,
969
969
.shift = 16,
···
973
973
.name = "pwm_b_div",
974
974
.ops = &clk_regmap_divider_ops,
975
975
.parent_hws = (const struct clk_hw *[]) {
976
-
&pwm_b_sel.hw
976
+
&a1_pwm_b_sel.hw
977
977
},
978
978
.num_parents = 1,
979
979
.flags = CLK_SET_RATE_PARENT,
980
980
},
981
981
};
982
982
983
-
static struct clk_regmap pwm_b = {
983
+
static struct clk_regmap a1_pwm_b = {
984
984
.data = &(struct clk_regmap_gate_data){
985
985
.offset = PWM_CLK_AB_CTRL,
986
986
.bit_idx = 24,
···
989
989
.name = "pwm_b",
990
990
.ops = &clk_regmap_gate_ops,
991
991
.parent_hws = (const struct clk_hw *[]) {
992
-
&pwm_b_div.hw
992
+
&a1_pwm_b_div.hw
993
993
},
994
994
.num_parents = 1,
995
995
.flags = CLK_SET_RATE_PARENT,
996
996
},
997
997
};
998
998
999
-
static struct clk_regmap pwm_c_sel = {
999
+
static struct clk_regmap a1_pwm_c_sel = {
1000
1000
.data = &(struct clk_regmap_mux_data){
1001
1001
.offset = PWM_CLK_CD_CTRL,
1002
1002
.mask = 0x1,
···
1005
1005
.hw.init = &(struct clk_init_data){
1006
1006
.name = "pwm_c_sel",
1007
1007
.ops = &clk_regmap_mux_ops,
1008
-
.parent_data = pwm_abcd_parents,
1009
-
.num_parents = ARRAY_SIZE(pwm_abcd_parents),
1008
+
.parent_data = a1_pwm_abcd_parents,
1009
+
.num_parents = ARRAY_SIZE(a1_pwm_abcd_parents),
1010
1010
},
1011
1011
};
1012
1012
1013
-
static struct clk_regmap pwm_c_div = {
1013
+
static struct clk_regmap a1_pwm_c_div = {
1014
1014
.data = &(struct clk_regmap_div_data){
1015
1015
.offset = PWM_CLK_CD_CTRL,
1016
1016
.shift = 0,
···
1020
1020
.name = "pwm_c_div",
1021
1021
.ops = &clk_regmap_divider_ops,
1022
1022
.parent_hws = (const struct clk_hw *[]) {
1023
-
&pwm_c_sel.hw
1023
+
&a1_pwm_c_sel.hw
1024
1024
},
1025
1025
.num_parents = 1,
1026
1026
.flags = CLK_SET_RATE_PARENT,
1027
1027
},
1028
1028
};
1029
1029
1030
-
static struct clk_regmap pwm_c = {
1030
+
static struct clk_regmap a1_pwm_c = {
1031
1031
.data = &(struct clk_regmap_gate_data){
1032
1032
.offset = PWM_CLK_CD_CTRL,
1033
1033
.bit_idx = 8,
···
1036
1036
.name = "pwm_c",
1037
1037
.ops = &clk_regmap_gate_ops,
1038
1038
.parent_hws = (const struct clk_hw *[]) {
1039
-
&pwm_c_div.hw
1039
+
&a1_pwm_c_div.hw
1040
1040
},
1041
1041
.num_parents = 1,
1042
1042
.flags = CLK_SET_RATE_PARENT,
1043
1043
},
1044
1044
};
1045
1045
1046
-
static struct clk_regmap pwm_d_sel = {
1046
+
static struct clk_regmap a1_pwm_d_sel = {
1047
1047
.data = &(struct clk_regmap_mux_data){
1048
1048
.offset = PWM_CLK_CD_CTRL,
1049
1049
.mask = 0x1,
···
1052
1052
.hw.init = &(struct clk_init_data){
1053
1053
.name = "pwm_d_sel",
1054
1054
.ops = &clk_regmap_mux_ops,
1055
-
.parent_data = pwm_abcd_parents,
1056
-
.num_parents = ARRAY_SIZE(pwm_abcd_parents),
1055
+
.parent_data = a1_pwm_abcd_parents,
1056
+
.num_parents = ARRAY_SIZE(a1_pwm_abcd_parents),
1057
1057
},
1058
1058
};
1059
1059
1060
-
static struct clk_regmap pwm_d_div = {
1060
+
static struct clk_regmap a1_pwm_d_div = {
1061
1061
.data = &(struct clk_regmap_div_data){
1062
1062
.offset = PWM_CLK_CD_CTRL,
1063
1063
.shift = 16,
···
1067
1067
.name = "pwm_d_div",
1068
1068
.ops = &clk_regmap_divider_ops,
1069
1069
.parent_hws = (const struct clk_hw *[]) {
1070
-
&pwm_d_sel.hw
1070
+
&a1_pwm_d_sel.hw
1071
1071
},
1072
1072
.num_parents = 1,
1073
1073
.flags = CLK_SET_RATE_PARENT,
1074
1074
},
1075
1075
};
1076
1076
1077
-
static struct clk_regmap pwm_d = {
1077
+
static struct clk_regmap a1_pwm_d = {
1078
1078
.data = &(struct clk_regmap_gate_data){
1079
1079
.offset = PWM_CLK_CD_CTRL,
1080
1080
.bit_idx = 24,
···
1083
1083
.name = "pwm_d",
1084
1084
.ops = &clk_regmap_gate_ops,
1085
1085
.parent_hws = (const struct clk_hw *[]) {
1086
-
&pwm_d_div.hw
1086
+
&a1_pwm_d_div.hw
1087
1087
},
1088
1088
.num_parents = 1,
1089
1089
.flags = CLK_SET_RATE_PARENT,
1090
1090
},
1091
1091
};
1092
1092
1093
-
static const struct clk_parent_data pwm_ef_parents[] = {
1093
+
static const struct clk_parent_data a1_pwm_ef_parents[] = {
1094
1094
{ .fw_name = "xtal", },
1095
-
{ .hw = &sys.hw },
1095
+
{ .hw = &a1_sys.hw },
1096
1096
{ .fw_name = "fclk_div5", },
1097
-
{ .hw = &rtc.hw },
1097
+
{ .hw = &a1_rtc.hw },
1098
1098
};
1099
1099
1100
-
static struct clk_regmap pwm_e_sel = {
1100
+
static struct clk_regmap a1_pwm_e_sel = {
1101
1101
.data = &(struct clk_regmap_mux_data){
1102
1102
.offset = PWM_CLK_EF_CTRL,
1103
1103
.mask = 0x3,
···
1106
1106
.hw.init = &(struct clk_init_data){
1107
1107
.name = "pwm_e_sel",
1108
1108
.ops = &clk_regmap_mux_ops,
1109
-
.parent_data = pwm_ef_parents,
1110
-
.num_parents = ARRAY_SIZE(pwm_ef_parents),
1109
+
.parent_data = a1_pwm_ef_parents,
1110
+
.num_parents = ARRAY_SIZE(a1_pwm_ef_parents),
1111
1111
},
1112
1112
};
1113
1113
1114
-
static struct clk_regmap pwm_e_div = {
1114
+
static struct clk_regmap a1_pwm_e_div = {
1115
1115
.data = &(struct clk_regmap_div_data){
1116
1116
.offset = PWM_CLK_EF_CTRL,
1117
1117
.shift = 0,
···
1121
1121
.name = "pwm_e_div",
1122
1122
.ops = &clk_regmap_divider_ops,
1123
1123
.parent_hws = (const struct clk_hw *[]) {
1124
-
&pwm_e_sel.hw
1124
+
&a1_pwm_e_sel.hw
1125
1125
},
1126
1126
.num_parents = 1,
1127
1127
.flags = CLK_SET_RATE_PARENT,
1128
1128
},
1129
1129
};
1130
1130
1131
-
static struct clk_regmap pwm_e = {
1131
+
static struct clk_regmap a1_pwm_e = {
1132
1132
.data = &(struct clk_regmap_gate_data){
1133
1133
.offset = PWM_CLK_EF_CTRL,
1134
1134
.bit_idx = 8,
···
1137
1137
.name = "pwm_e",
1138
1138
.ops = &clk_regmap_gate_ops,
1139
1139
.parent_hws = (const struct clk_hw *[]) {
1140
-
&pwm_e_div.hw
1140
+
&a1_pwm_e_div.hw
1141
1141
},
1142
1142
.num_parents = 1,
1143
1143
.flags = CLK_SET_RATE_PARENT,
1144
1144
},
1145
1145
};
1146
1146
1147
-
static struct clk_regmap pwm_f_sel = {
1147
+
static struct clk_regmap a1_pwm_f_sel = {
1148
1148
.data = &(struct clk_regmap_mux_data){
1149
1149
.offset = PWM_CLK_EF_CTRL,
1150
1150
.mask = 0x3,
···
1153
1153
.hw.init = &(struct clk_init_data){
1154
1154
.name = "pwm_f_sel",
1155
1155
.ops = &clk_regmap_mux_ops,
1156
-
.parent_data = pwm_ef_parents,
1157
-
.num_parents = ARRAY_SIZE(pwm_ef_parents),
1156
+
.parent_data = a1_pwm_ef_parents,
1157
+
.num_parents = ARRAY_SIZE(a1_pwm_ef_parents),
1158
1158
},
1159
1159
};
1160
1160
1161
-
static struct clk_regmap pwm_f_div = {
1161
+
static struct clk_regmap a1_pwm_f_div = {
1162
1162
.data = &(struct clk_regmap_div_data){
1163
1163
.offset = PWM_CLK_EF_CTRL,
1164
1164
.shift = 16,
···
1168
1168
.name = "pwm_f_div",
1169
1169
.ops = &clk_regmap_divider_ops,
1170
1170
.parent_hws = (const struct clk_hw *[]) {
1171
-
&pwm_f_sel.hw
1171
+
&a1_pwm_f_sel.hw
1172
1172
},
1173
1173
.num_parents = 1,
1174
1174
.flags = CLK_SET_RATE_PARENT,
1175
1175
},
1176
1176
};
1177
1177
1178
-
static struct clk_regmap pwm_f = {
1178
+
static struct clk_regmap a1_pwm_f = {
1179
1179
.data = &(struct clk_regmap_gate_data){
1180
1180
.offset = PWM_CLK_EF_CTRL,
1181
1181
.bit_idx = 24,
···
1184
1184
.name = "pwm_f",
1185
1185
.ops = &clk_regmap_gate_ops,
1186
1186
.parent_hws = (const struct clk_hw *[]) {
1187
-
&pwm_f_div.hw
1187
+
&a1_pwm_f_div.hw
1188
1188
},
1189
1189
.num_parents = 1,
1190
1190
.flags = CLK_SET_RATE_PARENT,
···
1200
1200
* --------------------|/
1201
1201
* 24M
1202
1202
*/
1203
-
static const struct clk_parent_data spicc_spifc_parents[] = {
1203
+
static const struct clk_parent_data a1_spi_parents[] = {
1204
1204
{ .fw_name = "fclk_div2"},
1205
1205
{ .fw_name = "fclk_div3"},
1206
1206
{ .fw_name = "fclk_div5"},
1207
1207
{ .fw_name = "hifi_pll" },
1208
1208
};
1209
1209
1210
-
static struct clk_regmap spicc_sel = {
1210
+
static struct clk_regmap a1_spicc_sel = {
1211
1211
.data = &(struct clk_regmap_mux_data){
1212
1212
.offset = SPICC_CLK_CTRL,
1213
1213
.mask = 0x3,
···
1216
1216
.hw.init = &(struct clk_init_data){
1217
1217
.name = "spicc_sel",
1218
1218
.ops = &clk_regmap_mux_ops,
1219
-
.parent_data = spicc_spifc_parents,
1220
-
.num_parents = ARRAY_SIZE(spicc_spifc_parents),
1219
+
.parent_data = a1_spi_parents,
1220
+
.num_parents = ARRAY_SIZE(a1_spi_parents),
1221
1221
},
1222
1222
};
1223
1223
1224
-
static struct clk_regmap spicc_div = {
1224
+
static struct clk_regmap a1_spicc_div = {
1225
1225
.data = &(struct clk_regmap_div_data){
1226
1226
.offset = SPICC_CLK_CTRL,
1227
1227
.shift = 0,
···
1231
1231
.name = "spicc_div",
1232
1232
.ops = &clk_regmap_divider_ops,
1233
1233
.parent_hws = (const struct clk_hw *[]) {
1234
-
&spicc_sel.hw
1234
+
&a1_spicc_sel.hw
1235
1235
},
1236
1236
.num_parents = 1,
1237
1237
.flags = CLK_SET_RATE_PARENT,
1238
1238
},
1239
1239
};
1240
1240
1241
-
static struct clk_regmap spicc_sel2 = {
1241
+
static struct clk_regmap a1_spicc_sel2 = {
1242
1242
.data = &(struct clk_regmap_mux_data){
1243
1243
.offset = SPICC_CLK_CTRL,
1244
1244
.mask = 0x1,
···
1248
1248
.name = "spicc_sel2",
1249
1249
.ops = &clk_regmap_mux_ops,
1250
1250
.parent_data = (const struct clk_parent_data []) {
1251
-
{ .hw = &spicc_div.hw },
1251
+
{ .hw = &a1_spicc_div.hw },
1252
1252
{ .fw_name = "xtal", },
1253
1253
},
1254
1254
.num_parents = 2,
···
1256
1256
},
1257
1257
};
1258
1258
1259
-
static struct clk_regmap spicc = {
1259
+
static struct clk_regmap a1_spicc = {
1260
1260
.data = &(struct clk_regmap_gate_data){
1261
1261
.offset = SPICC_CLK_CTRL,
1262
1262
.bit_idx = 8,
···
1265
1265
.name = "spicc",
1266
1266
.ops = &clk_regmap_gate_ops,
1267
1267
.parent_hws = (const struct clk_hw *[]) {
1268
-
&spicc_sel2.hw
1268
+
&a1_spicc_sel2.hw
1269
1269
},
1270
1270
.num_parents = 1,
1271
1271
.flags = CLK_SET_RATE_PARENT,
1272
1272
},
1273
1273
};
1274
1274
1275
-
static struct clk_regmap ts_div = {
1275
+
static struct clk_regmap a1_ts_div = {
1276
1276
.data = &(struct clk_regmap_div_data){
1277
1277
.offset = TS_CLK_CTRL,
1278
1278
.shift = 0,
···
1288
1288
},
1289
1289
};
1290
1290
1291
-
static struct clk_regmap ts = {
1291
+
static struct clk_regmap a1_ts = {
1292
1292
.data = &(struct clk_regmap_gate_data){
1293
1293
.offset = TS_CLK_CTRL,
1294
1294
.bit_idx = 8,
···
1297
1297
.name = "ts",
1298
1298
.ops = &clk_regmap_gate_ops,
1299
1299
.parent_hws = (const struct clk_hw *[]) {
1300
-
&ts_div.hw
1300
+
&a1_ts_div.hw
1301
1301
},
1302
1302
.num_parents = 1,
1303
1303
.flags = CLK_SET_RATE_PARENT,
1304
1304
},
1305
1305
};
1306
1306
1307
-
static struct clk_regmap spifc_sel = {
1307
+
static struct clk_regmap a1_spifc_sel = {
1308
1308
.data = &(struct clk_regmap_mux_data){
1309
1309
.offset = SPIFC_CLK_CTRL,
1310
1310
.mask = 0x3,
···
1313
1313
.hw.init = &(struct clk_init_data){
1314
1314
.name = "spifc_sel",
1315
1315
.ops = &clk_regmap_mux_ops,
1316
-
.parent_data = spicc_spifc_parents,
1317
-
.num_parents = ARRAY_SIZE(spicc_spifc_parents),
1316
+
.parent_data = a1_spi_parents,
1317
+
.num_parents = ARRAY_SIZE(a1_spi_parents),
1318
1318
},
1319
1319
};
1320
1320
1321
-
static struct clk_regmap spifc_div = {
1321
+
static struct clk_regmap a1_spifc_div = {
1322
1322
.data = &(struct clk_regmap_div_data){
1323
1323
.offset = SPIFC_CLK_CTRL,
1324
1324
.shift = 0,
···
1328
1328
.name = "spifc_div",
1329
1329
.ops = &clk_regmap_divider_ops,
1330
1330
.parent_hws = (const struct clk_hw *[]) {
1331
-
&spifc_sel.hw
1331
+
&a1_spifc_sel.hw
1332
1332
},
1333
1333
.num_parents = 1,
1334
1334
.flags = CLK_SET_RATE_PARENT,
1335
1335
},
1336
1336
};
1337
1337
1338
-
static struct clk_regmap spifc_sel2 = {
1338
+
static struct clk_regmap a1_spifc_sel2 = {
1339
1339
.data = &(struct clk_regmap_mux_data){
1340
1340
.offset = SPIFC_CLK_CTRL,
1341
1341
.mask = 0x1,
···
1345
1345
.name = "spifc_sel2",
1346
1346
.ops = &clk_regmap_mux_ops,
1347
1347
.parent_data = (const struct clk_parent_data []) {
1348
-
{ .hw = &spifc_div.hw },
1348
+
{ .hw = &a1_spifc_div.hw },
1349
1349
{ .fw_name = "xtal", },
1350
1350
},
1351
1351
.num_parents = 2,
···
1353
1353
},
1354
1354
};
1355
1355
1356
-
static struct clk_regmap spifc = {
1356
+
static struct clk_regmap a1_spifc = {
1357
1357
.data = &(struct clk_regmap_gate_data){
1358
1358
.offset = SPIFC_CLK_CTRL,
1359
1359
.bit_idx = 8,
···
1362
1362
.name = "spifc",
1363
1363
.ops = &clk_regmap_gate_ops,
1364
1364
.parent_hws = (const struct clk_hw *[]) {
1365
-
&spifc_sel2.hw
1365
+
&a1_spifc_sel2.hw
1366
1366
},
1367
1367
.num_parents = 1,
1368
1368
.flags = CLK_SET_RATE_PARENT,
1369
1369
},
1370
1370
};
1371
1371
1372
-
static const struct clk_parent_data usb_bus_parents[] = {
1372
+
static const struct clk_parent_data a1_usb_bus_parents[] = {
1373
1373
{ .fw_name = "xtal", },
1374
-
{ .hw = &sys.hw },
1374
+
{ .hw = &a1_sys.hw },
1375
1375
{ .fw_name = "fclk_div3", },
1376
1376
{ .fw_name = "fclk_div5", },
1377
1377
};
1378
1378
1379
-
static struct clk_regmap usb_bus_sel = {
1379
+
static struct clk_regmap a1_usb_bus_sel = {
1380
1380
.data = &(struct clk_regmap_mux_data){
1381
1381
.offset = USB_BUSCLK_CTRL,
1382
1382
.mask = 0x3,
···
1385
1385
.hw.init = &(struct clk_init_data){
1386
1386
.name = "usb_bus_sel",
1387
1387
.ops = &clk_regmap_mux_ops,
1388
-
.parent_data = usb_bus_parents,
1389
-
.num_parents = ARRAY_SIZE(usb_bus_parents),
1388
+
.parent_data = a1_usb_bus_parents,
1389
+
.num_parents = ARRAY_SIZE(a1_usb_bus_parents),
1390
1390
.flags = CLK_SET_RATE_PARENT,
1391
1391
},
1392
1392
};
1393
1393
1394
-
static struct clk_regmap usb_bus_div = {
1394
+
static struct clk_regmap a1_usb_bus_div = {
1395
1395
.data = &(struct clk_regmap_div_data){
1396
1396
.offset = USB_BUSCLK_CTRL,
1397
1397
.shift = 0,
···
1401
1401
.name = "usb_bus_div",
1402
1402
.ops = &clk_regmap_divider_ops,
1403
1403
.parent_hws = (const struct clk_hw *[]) {
1404
-
&usb_bus_sel.hw
1404
+
&a1_usb_bus_sel.hw
1405
1405
},
1406
1406
.num_parents = 1,
1407
1407
.flags = CLK_SET_RATE_PARENT,
1408
1408
},
1409
1409
};
1410
1410
1411
-
static struct clk_regmap usb_bus = {
1411
+
static struct clk_regmap a1_usb_bus = {
1412
1412
.data = &(struct clk_regmap_gate_data){
1413
1413
.offset = USB_BUSCLK_CTRL,
1414
1414
.bit_idx = 8,
···
1417
1417
.name = "usb_bus",
1418
1418
.ops = &clk_regmap_gate_ops,
1419
1419
.parent_hws = (const struct clk_hw *[]) {
1420
-
&usb_bus_div.hw
1420
+
&a1_usb_bus_div.hw
1421
1421
},
1422
1422
.num_parents = 1,
1423
1423
.flags = CLK_SET_RATE_PARENT,
1424
1424
},
1425
1425
};
1426
1426
1427
-
static const struct clk_parent_data sd_emmc_psram_dmc_parents[] = {
1427
+
static const struct clk_parent_data a1_sd_emmc_parents[] = {
1428
1428
{ .fw_name = "fclk_div2", },
1429
1429
{ .fw_name = "fclk_div3", },
1430
1430
{ .fw_name = "fclk_div5", },
1431
1431
{ .fw_name = "hifi_pll", },
1432
1432
};
1433
1433
1434
-
static struct clk_regmap sd_emmc_sel = {
1434
+
static struct clk_regmap a1_sd_emmc_sel = {
1435
1435
.data = &(struct clk_regmap_mux_data){
1436
1436
.offset = SD_EMMC_CLK_CTRL,
1437
1437
.mask = 0x3,
···
1440
1440
.hw.init = &(struct clk_init_data){
1441
1441
.name = "sd_emmc_sel",
1442
1442
.ops = &clk_regmap_mux_ops,
1443
-
.parent_data = sd_emmc_psram_dmc_parents,
1444
-
.num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
1443
+
.parent_data = a1_sd_emmc_parents,
1444
+
.num_parents = ARRAY_SIZE(a1_sd_emmc_parents),
1445
1445
},
1446
1446
};
1447
1447
1448
-
static struct clk_regmap sd_emmc_div = {
1448
+
static struct clk_regmap a1_sd_emmc_div = {
1449
1449
.data = &(struct clk_regmap_div_data){
1450
1450
.offset = SD_EMMC_CLK_CTRL,
1451
1451
.shift = 0,
···
1455
1455
.name = "sd_emmc_div",
1456
1456
.ops = &clk_regmap_divider_ops,
1457
1457
.parent_hws = (const struct clk_hw *[]) {
1458
-
&sd_emmc_sel.hw
1458
+
&a1_sd_emmc_sel.hw
1459
1459
},
1460
1460
.num_parents = 1,
1461
1461
.flags = CLK_SET_RATE_PARENT,
1462
1462
},
1463
1463
};
1464
1464
1465
-
static struct clk_regmap sd_emmc_sel2 = {
1465
+
static struct clk_regmap a1_sd_emmc_sel2 = {
1466
1466
.data = &(struct clk_regmap_mux_data){
1467
1467
.offset = SD_EMMC_CLK_CTRL,
1468
1468
.mask = 0x1,
···
1472
1472
.name = "sd_emmc_sel2",
1473
1473
.ops = &clk_regmap_mux_ops,
1474
1474
.parent_data = (const struct clk_parent_data []) {
1475
-
{ .hw = &sd_emmc_div.hw },
1475
+
{ .hw = &a1_sd_emmc_div.hw },
1476
1476
{ .fw_name = "xtal", },
1477
1477
},
1478
1478
.num_parents = 2,
···
1480
1480
},
1481
1481
};
1482
1482
1483
-
static struct clk_regmap sd_emmc = {
1483
+
static struct clk_regmap a1_sd_emmc = {
1484
1484
.data = &(struct clk_regmap_gate_data){
1485
1485
.offset = SD_EMMC_CLK_CTRL,
1486
1486
.bit_idx = 8,
···
1489
1489
.name = "sd_emmc",
1490
1490
.ops = &clk_regmap_gate_ops,
1491
1491
.parent_hws = (const struct clk_hw *[]) {
1492
-
&sd_emmc_sel2.hw
1492
+
&a1_sd_emmc_sel2.hw
1493
1493
},
1494
1494
.num_parents = 1,
1495
1495
.flags = CLK_SET_RATE_PARENT,
1496
1496
},
1497
1497
};
1498
1498
1499
-
static struct clk_regmap psram_sel = {
1499
+
static struct clk_regmap a1_psram_sel = {
1500
1500
.data = &(struct clk_regmap_mux_data){
1501
1501
.offset = PSRAM_CLK_CTRL,
1502
1502
.mask = 0x3,
···
1505
1505
.hw.init = &(struct clk_init_data){
1506
1506
.name = "psram_sel",
1507
1507
.ops = &clk_regmap_mux_ops,
1508
-
.parent_data = sd_emmc_psram_dmc_parents,
1509
-
.num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
1508
+
.parent_data = a1_sd_emmc_parents,
1509
+
.num_parents = ARRAY_SIZE(a1_sd_emmc_parents),
1510
1510
},
1511
1511
};
1512
1512
1513
-
static struct clk_regmap psram_div = {
1513
+
static struct clk_regmap a1_psram_div = {
1514
1514
.data = &(struct clk_regmap_div_data){
1515
1515
.offset = PSRAM_CLK_CTRL,
1516
1516
.shift = 0,
···
1520
1520
.name = "psram_div",
1521
1521
.ops = &clk_regmap_divider_ops,
1522
1522
.parent_hws = (const struct clk_hw *[]) {
1523
-
&psram_sel.hw
1523
+
&a1_psram_sel.hw
1524
1524
},
1525
1525
.num_parents = 1,
1526
1526
.flags = CLK_SET_RATE_PARENT,
1527
1527
},
1528
1528
};
1529
1529
1530
-
static struct clk_regmap psram_sel2 = {
1530
+
static struct clk_regmap a1_psram_sel2 = {
1531
1531
.data = &(struct clk_regmap_mux_data){
1532
1532
.offset = PSRAM_CLK_CTRL,
1533
1533
.mask = 0x1,
···
1537
1537
.name = "psram_sel2",
1538
1538
.ops = &clk_regmap_mux_ops,
1539
1539
.parent_data = (const struct clk_parent_data []) {
1540
-
{ .hw = &psram_div.hw },
1540
+
{ .hw = &a1_psram_div.hw },
1541
1541
{ .fw_name = "xtal", },
1542
1542
},
1543
1543
.num_parents = 2,
···
1545
1545
},
1546
1546
};
1547
1547
1548
-
static struct clk_regmap psram = {
1548
+
static struct clk_regmap a1_psram = {
1549
1549
.data = &(struct clk_regmap_gate_data){
1550
1550
.offset = PSRAM_CLK_CTRL,
1551
1551
.bit_idx = 8,
···
1554
1554
.name = "psram",
1555
1555
.ops = &clk_regmap_gate_ops,
1556
1556
.parent_hws = (const struct clk_hw *[]) {
1557
-
&psram_sel2.hw
1557
+
&a1_psram_sel2.hw
1558
1558
},
1559
1559
.num_parents = 1,
1560
1560
.flags = CLK_SET_RATE_PARENT,
1561
1561
},
1562
1562
};
1563
1563
1564
-
static struct clk_regmap dmc_sel = {
1564
+
static struct clk_regmap a1_dmc_sel = {
1565
1565
.data = &(struct clk_regmap_mux_data){
1566
1566
.offset = DMC_CLK_CTRL,
1567
1567
.mask = 0x3,
···
1570
1570
.hw.init = &(struct clk_init_data){
1571
1571
.name = "dmc_sel",
1572
1572
.ops = &clk_regmap_mux_ops,
1573
-
.parent_data = sd_emmc_psram_dmc_parents,
1574
-
.num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents),
1573
+
.parent_data = a1_sd_emmc_parents,
1574
+
.num_parents = ARRAY_SIZE(a1_sd_emmc_parents),
1575
1575
},
1576
1576
};
1577
1577
1578
-
static struct clk_regmap dmc_div = {
1578
+
static struct clk_regmap a1_dmc_div = {
1579
1579
.data = &(struct clk_regmap_div_data){
1580
1580
.offset = DMC_CLK_CTRL,
1581
1581
.shift = 0,
···
1585
1585
.name = "dmc_div",
1586
1586
.ops = &clk_regmap_divider_ops,
1587
1587
.parent_hws = (const struct clk_hw *[]) {
1588
-
&dmc_sel.hw
1588
+
&a1_dmc_sel.hw
1589
1589
},
1590
1590
.num_parents = 1,
1591
1591
.flags = CLK_SET_RATE_PARENT,
1592
1592
},
1593
1593
};
1594
1594
1595
-
static struct clk_regmap dmc_sel2 = {
1595
+
static struct clk_regmap a1_dmc_sel2 = {
1596
1596
.data = &(struct clk_regmap_mux_data){
1597
1597
.offset = DMC_CLK_CTRL,
1598
1598
.mask = 0x1,
···
1602
1602
.name = "dmc_sel2",
1603
1603
.ops = &clk_regmap_mux_ops,
1604
1604
.parent_data = (const struct clk_parent_data []) {
1605
-
{ .hw = &dmc_div.hw },
1605
+
{ .hw = &a1_dmc_div.hw },
1606
1606
{ .fw_name = "xtal", },
1607
1607
},
1608
1608
.num_parents = 2,
···
1610
1610
},
1611
1611
};
1612
1612
1613
-
static struct clk_regmap dmc = {
1613
+
static struct clk_regmap a1_dmc = {
1614
1614
.data = &(struct clk_regmap_gate_data){
1615
1615
.offset = DMC_CLK_CTRL,
1616
1616
.bit_idx = 8,
···
1619
1619
.name = "dmc",
1620
1620
.ops = &clk_regmap_gate_ro_ops,
1621
1621
.parent_hws = (const struct clk_hw *[]) {
1622
-
&dmc_sel2.hw
1622
+
&a1_dmc_sel2.hw
1623
1623
},
1624
1624
.num_parents = 1,
1625
1625
.flags = CLK_SET_RATE_PARENT,
1626
1626
},
1627
1627
};
1628
1628
1629
-
static struct clk_regmap ceca_32k_in = {
1629
+
static struct clk_regmap a1_ceca_32k_in = {
1630
1630
.data = &(struct clk_regmap_gate_data){
1631
1631
.offset = CECA_CLK_CTRL0,
1632
1632
.bit_idx = 31,
···
1641
1641
},
1642
1642
};
1643
1643
1644
-
static struct clk_regmap ceca_32k_div = {
1644
+
static struct clk_regmap a1_ceca_32k_div = {
1645
1645
.data = &(struct meson_clk_dualdiv_data){
1646
1646
.n1 = {
1647
1647
.reg_off = CECA_CLK_CTRL0,
···
1668
1668
.shift = 28,
1669
1669
.width = 1,
1670
1670
},
1671
-
.table = clk_32k_div_table,
1671
+
.table = a1_32k_div_table,
1672
1672
},
1673
1673
.hw.init = &(struct clk_init_data){
1674
1674
.name = "ceca_32k_div",
1675
1675
.ops = &meson_clk_dualdiv_ops,
1676
1676
.parent_hws = (const struct clk_hw *[]) {
1677
-
&ceca_32k_in.hw
1677
+
&a1_ceca_32k_in.hw
1678
1678
},
1679
1679
.num_parents = 1,
1680
1680
},
1681
1681
};
1682
1682
1683
-
static struct clk_regmap ceca_32k_sel_pre = {
1683
+
static struct clk_regmap a1_ceca_32k_sel_pre = {
1684
1684
.data = &(struct clk_regmap_mux_data) {
1685
1685
.offset = CECA_CLK_CTRL1,
1686
1686
.mask = 0x1,
···
1691
1691
.name = "ceca_32k_sel_pre",
1692
1692
.ops = &clk_regmap_mux_ops,
1693
1693
.parent_hws = (const struct clk_hw *[]) {
1694
-
&ceca_32k_div.hw,
1695
-
&ceca_32k_in.hw,
1694
+
&a1_ceca_32k_div.hw,
1695
+
&a1_ceca_32k_in.hw,
1696
1696
},
1697
1697
.num_parents = 2,
1698
1698
.flags = CLK_SET_RATE_PARENT,
1699
1699
},
1700
1700
};
1701
1701
1702
-
static struct clk_regmap ceca_32k_sel = {
1702
+
static struct clk_regmap a1_ceca_32k_sel = {
1703
1703
.data = &(struct clk_regmap_mux_data) {
1704
1704
.offset = CECA_CLK_CTRL1,
1705
1705
.mask = 0x1,
···
1710
1710
.name = "ceca_32k_sel",
1711
1711
.ops = &clk_regmap_mux_ops,
1712
1712
.parent_hws = (const struct clk_hw *[]) {
1713
-
&ceca_32k_sel_pre.hw,
1714
-
&rtc.hw,
1713
+
&a1_ceca_32k_sel_pre.hw,
1714
+
&a1_rtc.hw,
1715
1715
},
1716
1716
.num_parents = 2,
1717
1717
},
1718
1718
};
1719
1719
1720
-
static struct clk_regmap ceca_32k_out = {
1720
+
static struct clk_regmap a1_ceca_32k_out = {
1721
1721
.data = &(struct clk_regmap_gate_data){
1722
1722
.offset = CECA_CLK_CTRL0,
1723
1723
.bit_idx = 30,
···
1726
1726
.name = "ceca_32k_out",
1727
1727
.ops = &clk_regmap_gate_ops,
1728
1728
.parent_hws = (const struct clk_hw *[]) {
1729
-
&ceca_32k_sel.hw
1729
+
&a1_ceca_32k_sel.hw
1730
1730
},
1731
1731
.num_parents = 1,
1732
1732
.flags = CLK_SET_RATE_PARENT,
1733
1733
},
1734
1734
};
1735
1735
1736
-
static struct clk_regmap cecb_32k_in = {
1736
+
static struct clk_regmap a1_cecb_32k_in = {
1737
1737
.data = &(struct clk_regmap_gate_data){
1738
1738
.offset = CECB_CLK_CTRL0,
1739
1739
.bit_idx = 31,
···
1748
1748
},
1749
1749
};
1750
1750
1751
-
static struct clk_regmap cecb_32k_div = {
1751
+
static struct clk_regmap a1_cecb_32k_div = {
1752
1752
.data = &(struct meson_clk_dualdiv_data){
1753
1753
.n1 = {
1754
1754
.reg_off = CECB_CLK_CTRL0,
···
1775
1775
.shift = 28,
1776
1776
.width = 1,
1777
1777
},
1778
-
.table = clk_32k_div_table,
1778
+
.table = a1_32k_div_table,
1779
1779
},
1780
1780
.hw.init = &(struct clk_init_data){
1781
1781
.name = "cecb_32k_div",
1782
1782
.ops = &meson_clk_dualdiv_ops,
1783
1783
.parent_hws = (const struct clk_hw *[]) {
1784
-
&cecb_32k_in.hw
1784
+
&a1_cecb_32k_in.hw
1785
1785
},
1786
1786
.num_parents = 1,
1787
1787
},
1788
1788
};
1789
1789
1790
-
static struct clk_regmap cecb_32k_sel_pre = {
1790
+
static struct clk_regmap a1_cecb_32k_sel_pre = {
1791
1791
.data = &(struct clk_regmap_mux_data) {
1792
1792
.offset = CECB_CLK_CTRL1,
1793
1793
.mask = 0x1,
···
1798
1798
.name = "cecb_32k_sel_pre",
1799
1799
.ops = &clk_regmap_mux_ops,
1800
1800
.parent_hws = (const struct clk_hw *[]) {
1801
-
&cecb_32k_div.hw,
1802
-
&cecb_32k_in.hw,
1801
+
&a1_cecb_32k_div.hw,
1802
+
&a1_cecb_32k_in.hw,
1803
1803
},
1804
1804
.num_parents = 2,
1805
1805
.flags = CLK_SET_RATE_PARENT,
1806
1806
},
1807
1807
};
1808
1808
1809
-
static struct clk_regmap cecb_32k_sel = {
1809
+
static struct clk_regmap a1_cecb_32k_sel = {
1810
1810
.data = &(struct clk_regmap_mux_data) {
1811
1811
.offset = CECB_CLK_CTRL1,
1812
1812
.mask = 0x1,
···
1817
1817
.name = "cecb_32k_sel",
1818
1818
.ops = &clk_regmap_mux_ops,
1819
1819
.parent_hws = (const struct clk_hw *[]) {
1820
-
&cecb_32k_sel_pre.hw,
1821
-
&rtc.hw,
1820
+
&a1_cecb_32k_sel_pre.hw,
1821
+
&a1_rtc.hw,
1822
1822
},
1823
1823
.num_parents = 2,
1824
1824
},
1825
1825
};
1826
1826
1827
-
static struct clk_regmap cecb_32k_out = {
1827
+
static struct clk_regmap a1_cecb_32k_out = {
1828
1828
.data = &(struct clk_regmap_gate_data){
1829
1829
.offset = CECB_CLK_CTRL0,
1830
1830
.bit_idx = 30,
···
1833
1833
.name = "cecb_32k_out",
1834
1834
.ops = &clk_regmap_gate_ops,
1835
1835
.parent_hws = (const struct clk_hw *[]) {
1836
-
&cecb_32k_sel.hw
1836
+
&a1_cecb_32k_sel.hw
1837
1837
},
1838
1838
.num_parents = 1,
1839
1839
.flags = CLK_SET_RATE_PARENT,
1840
1840
},
1841
1841
};
1842
1842
1843
-
#define MESON_GATE(_name, _reg, _bit) \
1844
-
MESON_PCLK(_name, _reg, _bit, &sys.hw)
1843
+
static const struct clk_parent_data a1_pclk_parents = { .hw = &a1_sys.hw };
1845
1844
1846
-
static MESON_GATE(clktree, SYS_CLK_EN0, 0);
1847
-
static MESON_GATE(reset_ctrl, SYS_CLK_EN0, 1);
1848
-
static MESON_GATE(analog_ctrl, SYS_CLK_EN0, 2);
1849
-
static MESON_GATE(pwr_ctrl, SYS_CLK_EN0, 3);
1850
-
static MESON_GATE(pad_ctrl, SYS_CLK_EN0, 4);
1851
-
static MESON_GATE(sys_ctrl, SYS_CLK_EN0, 5);
1852
-
static MESON_GATE(temp_sensor, SYS_CLK_EN0, 6);
1853
-
static MESON_GATE(am2axi_dev, SYS_CLK_EN0, 7);
1854
-
static MESON_GATE(spicc_b, SYS_CLK_EN0, 8);
1855
-
static MESON_GATE(spicc_a, SYS_CLK_EN0, 9);
1856
-
static MESON_GATE(msr, SYS_CLK_EN0, 10);
1857
-
static MESON_GATE(audio, SYS_CLK_EN0, 11);
1858
-
static MESON_GATE(jtag_ctrl, SYS_CLK_EN0, 12);
1859
-
static MESON_GATE(saradc_en, SYS_CLK_EN0, 13);
1860
-
static MESON_GATE(pwm_ef, SYS_CLK_EN0, 14);
1861
-
static MESON_GATE(pwm_cd, SYS_CLK_EN0, 15);
1862
-
static MESON_GATE(pwm_ab, SYS_CLK_EN0, 16);
1863
-
static MESON_GATE(cec, SYS_CLK_EN0, 17);
1864
-
static MESON_GATE(i2c_s, SYS_CLK_EN0, 18);
1865
-
static MESON_GATE(ir_ctrl, SYS_CLK_EN0, 19);
1866
-
static MESON_GATE(i2c_m_d, SYS_CLK_EN0, 20);
1867
-
static MESON_GATE(i2c_m_c, SYS_CLK_EN0, 21);
1868
-
static MESON_GATE(i2c_m_b, SYS_CLK_EN0, 22);
1869
-
static MESON_GATE(i2c_m_a, SYS_CLK_EN0, 23);
1870
-
static MESON_GATE(acodec, SYS_CLK_EN0, 24);
1871
-
static MESON_GATE(otp, SYS_CLK_EN0, 25);
1872
-
static MESON_GATE(sd_emmc_a, SYS_CLK_EN0, 26);
1873
-
static MESON_GATE(usb_phy, SYS_CLK_EN0, 27);
1874
-
static MESON_GATE(usb_ctrl, SYS_CLK_EN0, 28);
1875
-
static MESON_GATE(sys_dspb, SYS_CLK_EN0, 29);
1876
-
static MESON_GATE(sys_dspa, SYS_CLK_EN0, 30);
1877
-
static MESON_GATE(dma, SYS_CLK_EN0, 31);
1878
-
static MESON_GATE(irq_ctrl, SYS_CLK_EN1, 0);
1879
-
static MESON_GATE(nic, SYS_CLK_EN1, 1);
1880
-
static MESON_GATE(gic, SYS_CLK_EN1, 2);
1881
-
static MESON_GATE(uart_c, SYS_CLK_EN1, 3);
1882
-
static MESON_GATE(uart_b, SYS_CLK_EN1, 4);
1883
-
static MESON_GATE(uart_a, SYS_CLK_EN1, 5);
1884
-
static MESON_GATE(sys_psram, SYS_CLK_EN1, 6);
1885
-
static MESON_GATE(rsa, SYS_CLK_EN1, 8);
1886
-
static MESON_GATE(coresight, SYS_CLK_EN1, 9);
1887
-
static MESON_GATE(am2axi_vad, AXI_CLK_EN, 0);
1888
-
static MESON_GATE(audio_vad, AXI_CLK_EN, 1);
1889
-
static MESON_GATE(axi_dmc, AXI_CLK_EN, 3);
1890
-
static MESON_GATE(axi_psram, AXI_CLK_EN, 4);
1891
-
static MESON_GATE(ramb, AXI_CLK_EN, 5);
1892
-
static MESON_GATE(rama, AXI_CLK_EN, 6);
1893
-
static MESON_GATE(axi_spifc, AXI_CLK_EN, 7);
1894
-
static MESON_GATE(axi_nic, AXI_CLK_EN, 8);
1895
-
static MESON_GATE(axi_dma, AXI_CLK_EN, 9);
1896
-
static MESON_GATE(cpu_ctrl, AXI_CLK_EN, 10);
1897
-
static MESON_GATE(rom, AXI_CLK_EN, 11);
1898
-
static MESON_GATE(prod_i2c, AXI_CLK_EN, 12);
1845
+
#define A1_PCLK(_name, _reg, _bit, _flags) \
1846
+
MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags)
1847
+
1848
+
/*
1849
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
1850
+
* Users are encouraged to test without it and submit changes to:
1851
+
* - remove the flag if not necessary
1852
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
1853
+
* if appropriate.
1854
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
1855
+
* for a particular clock.
1856
+
*/
1857
+
static A1_PCLK(clktree, SYS_CLK_EN0, 0, CLK_IGNORE_UNUSED);
1858
+
static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1, CLK_IGNORE_UNUSED);
1859
+
static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2, CLK_IGNORE_UNUSED);
1860
+
static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3, CLK_IGNORE_UNUSED);
1861
+
static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4, CLK_IGNORE_UNUSED);
1862
+
static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5, CLK_IGNORE_UNUSED);
1863
+
static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6, CLK_IGNORE_UNUSED);
1864
+
static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7, CLK_IGNORE_UNUSED);
1865
+
static A1_PCLK(spicc_b, SYS_CLK_EN0, 8, CLK_IGNORE_UNUSED);
1866
+
static A1_PCLK(spicc_a, SYS_CLK_EN0, 9, CLK_IGNORE_UNUSED);
1867
+
static A1_PCLK(msr, SYS_CLK_EN0, 10, CLK_IGNORE_UNUSED);
1868
+
static A1_PCLK(audio, SYS_CLK_EN0, 11, CLK_IGNORE_UNUSED);
1869
+
static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12, CLK_IGNORE_UNUSED);
1870
+
static A1_PCLK(saradc_en, SYS_CLK_EN0, 13, CLK_IGNORE_UNUSED);
1871
+
static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14, CLK_IGNORE_UNUSED);
1872
+
static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15, CLK_IGNORE_UNUSED);
1873
+
static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16, CLK_IGNORE_UNUSED);
1874
+
static A1_PCLK(cec, SYS_CLK_EN0, 17, CLK_IGNORE_UNUSED);
1875
+
static A1_PCLK(i2c_s, SYS_CLK_EN0, 18, CLK_IGNORE_UNUSED);
1876
+
static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19, CLK_IGNORE_UNUSED);
1877
+
static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20, CLK_IGNORE_UNUSED);
1878
+
static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21, CLK_IGNORE_UNUSED);
1879
+
static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22, CLK_IGNORE_UNUSED);
1880
+
static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23, CLK_IGNORE_UNUSED);
1881
+
static A1_PCLK(acodec, SYS_CLK_EN0, 24, CLK_IGNORE_UNUSED);
1882
+
static A1_PCLK(otp, SYS_CLK_EN0, 25, CLK_IGNORE_UNUSED);
1883
+
static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26, CLK_IGNORE_UNUSED);
1884
+
static A1_PCLK(usb_phy, SYS_CLK_EN0, 27, CLK_IGNORE_UNUSED);
1885
+
static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28, CLK_IGNORE_UNUSED);
1886
+
static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29, CLK_IGNORE_UNUSED);
1887
+
static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30, CLK_IGNORE_UNUSED);
1888
+
static A1_PCLK(dma, SYS_CLK_EN0, 31, CLK_IGNORE_UNUSED);
1889
+
1890
+
static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0, CLK_IGNORE_UNUSED);
1891
+
static A1_PCLK(nic, SYS_CLK_EN1, 1, CLK_IGNORE_UNUSED);
1892
+
static A1_PCLK(gic, SYS_CLK_EN1, 2, CLK_IGNORE_UNUSED);
1893
+
static A1_PCLK(uart_c, SYS_CLK_EN1, 3, CLK_IGNORE_UNUSED);
1894
+
static A1_PCLK(uart_b, SYS_CLK_EN1, 4, CLK_IGNORE_UNUSED);
1895
+
static A1_PCLK(uart_a, SYS_CLK_EN1, 5, CLK_IGNORE_UNUSED);
1896
+
static A1_PCLK(sys_psram, SYS_CLK_EN1, 6, CLK_IGNORE_UNUSED);
1897
+
static A1_PCLK(rsa, SYS_CLK_EN1, 8, CLK_IGNORE_UNUSED);
1898
+
static A1_PCLK(coresight, SYS_CLK_EN1, 9, CLK_IGNORE_UNUSED);
1899
+
1900
+
static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0, CLK_IGNORE_UNUSED);
1901
+
static A1_PCLK(audio_vad, AXI_CLK_EN, 1, CLK_IGNORE_UNUSED);
1902
+
static A1_PCLK(axi_dmc, AXI_CLK_EN, 3, CLK_IGNORE_UNUSED);
1903
+
static A1_PCLK(axi_psram, AXI_CLK_EN, 4, CLK_IGNORE_UNUSED);
1904
+
static A1_PCLK(ramb, AXI_CLK_EN, 5, CLK_IGNORE_UNUSED);
1905
+
static A1_PCLK(rama, AXI_CLK_EN, 6, CLK_IGNORE_UNUSED);
1906
+
static A1_PCLK(axi_spifc, AXI_CLK_EN, 7, CLK_IGNORE_UNUSED);
1907
+
static A1_PCLK(axi_nic, AXI_CLK_EN, 8, CLK_IGNORE_UNUSED);
1908
+
static A1_PCLK(axi_dma, AXI_CLK_EN, 9, CLK_IGNORE_UNUSED);
1909
+
static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10, CLK_IGNORE_UNUSED);
1910
+
static A1_PCLK(rom, AXI_CLK_EN, 11, CLK_IGNORE_UNUSED);
1911
+
static A1_PCLK(prod_i2c, AXI_CLK_EN, 12, CLK_IGNORE_UNUSED);
1899
1912
1900
1913
/* Array of all clocks registered by this provider */
1901
-
static struct clk_hw *a1_periphs_hw_clks[] = {
1902
-
[CLKID_XTAL_IN] = &xtal_in.hw,
1903
-
[CLKID_FIXPLL_IN] = &fixpll_in.hw,
1904
-
[CLKID_USB_PHY_IN] = &usb_phy_in.hw,
1905
-
[CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
1906
-
[CLKID_HIFIPLL_IN] = &hifipll_in.hw,
1907
-
[CLKID_SYSPLL_IN] = &syspll_in.hw,
1908
-
[CLKID_DDS_IN] = &dds_in.hw,
1909
-
[CLKID_SYS] = &sys.hw,
1910
-
[CLKID_CLKTREE] = &clktree.hw,
1911
-
[CLKID_RESET_CTRL] = &reset_ctrl.hw,
1912
-
[CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
1913
-
[CLKID_PWR_CTRL] = &pwr_ctrl.hw,
1914
-
[CLKID_PAD_CTRL] = &pad_ctrl.hw,
1915
-
[CLKID_SYS_CTRL] = &sys_ctrl.hw,
1916
-
[CLKID_TEMP_SENSOR] = &temp_sensor.hw,
1917
-
[CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
1918
-
[CLKID_SPICC_B] = &spicc_b.hw,
1919
-
[CLKID_SPICC_A] = &spicc_a.hw,
1920
-
[CLKID_MSR] = &msr.hw,
1921
-
[CLKID_AUDIO] = &audio.hw,
1922
-
[CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
1923
-
[CLKID_SARADC_EN] = &saradc_en.hw,
1924
-
[CLKID_PWM_EF] = &pwm_ef.hw,
1925
-
[CLKID_PWM_CD] = &pwm_cd.hw,
1926
-
[CLKID_PWM_AB] = &pwm_ab.hw,
1927
-
[CLKID_CEC] = &cec.hw,
1928
-
[CLKID_I2C_S] = &i2c_s.hw,
1929
-
[CLKID_IR_CTRL] = &ir_ctrl.hw,
1930
-
[CLKID_I2C_M_D] = &i2c_m_d.hw,
1931
-
[CLKID_I2C_M_C] = &i2c_m_c.hw,
1932
-
[CLKID_I2C_M_B] = &i2c_m_b.hw,
1933
-
[CLKID_I2C_M_A] = &i2c_m_a.hw,
1934
-
[CLKID_ACODEC] = &acodec.hw,
1935
-
[CLKID_OTP] = &otp.hw,
1936
-
[CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
1937
-
[CLKID_USB_PHY] = &usb_phy.hw,
1938
-
[CLKID_USB_CTRL] = &usb_ctrl.hw,
1939
-
[CLKID_SYS_DSPB] = &sys_dspb.hw,
1940
-
[CLKID_SYS_DSPA] = &sys_dspa.hw,
1941
-
[CLKID_DMA] = &dma.hw,
1942
-
[CLKID_IRQ_CTRL] = &irq_ctrl.hw,
1943
-
[CLKID_NIC] = &nic.hw,
1944
-
[CLKID_GIC] = &gic.hw,
1945
-
[CLKID_UART_C] = &uart_c.hw,
1946
-
[CLKID_UART_B] = &uart_b.hw,
1947
-
[CLKID_UART_A] = &uart_a.hw,
1948
-
[CLKID_SYS_PSRAM] = &sys_psram.hw,
1949
-
[CLKID_RSA] = &rsa.hw,
1950
-
[CLKID_CORESIGHT] = &coresight.hw,
1951
-
[CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
1952
-
[CLKID_AUDIO_VAD] = &audio_vad.hw,
1953
-
[CLKID_AXI_DMC] = &axi_dmc.hw,
1954
-
[CLKID_AXI_PSRAM] = &axi_psram.hw,
1955
-
[CLKID_RAMB] = &ramb.hw,
1956
-
[CLKID_RAMA] = &rama.hw,
1957
-
[CLKID_AXI_SPIFC] = &axi_spifc.hw,
1958
-
[CLKID_AXI_NIC] = &axi_nic.hw,
1959
-
[CLKID_AXI_DMA] = &axi_dma.hw,
1960
-
[CLKID_CPU_CTRL] = &cpu_ctrl.hw,
1961
-
[CLKID_ROM] = &rom.hw,
1962
-
[CLKID_PROC_I2C] = &prod_i2c.hw,
1963
-
[CLKID_DSPA_SEL] = &dspa_sel.hw,
1964
-
[CLKID_DSPB_SEL] = &dspb_sel.hw,
1965
-
[CLKID_DSPA_EN] = &dspa_en.hw,
1966
-
[CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
1967
-
[CLKID_DSPB_EN] = &dspb_en.hw,
1968
-
[CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
1969
-
[CLKID_RTC] = &rtc.hw,
1970
-
[CLKID_CECA_32K] = &ceca_32k_out.hw,
1971
-
[CLKID_CECB_32K] = &cecb_32k_out.hw,
1972
-
[CLKID_24M] = &clk_24m.hw,
1973
-
[CLKID_12M] = &clk_12m.hw,
1974
-
[CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
1975
-
[CLKID_GEN] = &gen.hw,
1976
-
[CLKID_SARADC_SEL] = &saradc_sel.hw,
1977
-
[CLKID_SARADC] = &saradc.hw,
1978
-
[CLKID_PWM_A] = &pwm_a.hw,
1979
-
[CLKID_PWM_B] = &pwm_b.hw,
1980
-
[CLKID_PWM_C] = &pwm_c.hw,
1981
-
[CLKID_PWM_D] = &pwm_d.hw,
1982
-
[CLKID_PWM_E] = &pwm_e.hw,
1983
-
[CLKID_PWM_F] = &pwm_f.hw,
1984
-
[CLKID_SPICC] = &spicc.hw,
1985
-
[CLKID_TS] = &ts.hw,
1986
-
[CLKID_SPIFC] = &spifc.hw,
1987
-
[CLKID_USB_BUS] = &usb_bus.hw,
1988
-
[CLKID_SD_EMMC] = &sd_emmc.hw,
1989
-
[CLKID_PSRAM] = &psram.hw,
1990
-
[CLKID_DMC] = &dmc.hw,
1991
-
[CLKID_SYS_A_SEL] = &sys_a_sel.hw,
1992
-
[CLKID_SYS_A_DIV] = &sys_a_div.hw,
1993
-
[CLKID_SYS_A] = &sys_a.hw,
1994
-
[CLKID_SYS_B_SEL] = &sys_b_sel.hw,
1995
-
[CLKID_SYS_B_DIV] = &sys_b_div.hw,
1996
-
[CLKID_SYS_B] = &sys_b.hw,
1997
-
[CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
1998
-
[CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
1999
-
[CLKID_DSPA_A] = &dspa_a.hw,
2000
-
[CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
2001
-
[CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
2002
-
[CLKID_DSPA_B] = &dspa_b.hw,
2003
-
[CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
2004
-
[CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
2005
-
[CLKID_DSPB_A] = &dspb_a.hw,
2006
-
[CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
2007
-
[CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
2008
-
[CLKID_DSPB_B] = &dspb_b.hw,
2009
-
[CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
2010
-
[CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
2011
-
[CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
2012
-
[CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
2013
-
[CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
2014
-
[CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
2015
-
[CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
2016
-
[CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
2017
-
[CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
2018
-
[CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
2019
-
[CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
2020
-
[CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
2021
-
[CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
2022
-
[CLKID_24M_DIV2] = &clk_24m_div2.hw,
2023
-
[CLKID_GEN_SEL] = &gen_sel.hw,
2024
-
[CLKID_GEN_DIV] = &gen_div.hw,
2025
-
[CLKID_SARADC_DIV] = &saradc_div.hw,
2026
-
[CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
2027
-
[CLKID_PWM_A_DIV] = &pwm_a_div.hw,
2028
-
[CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
2029
-
[CLKID_PWM_B_DIV] = &pwm_b_div.hw,
2030
-
[CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
2031
-
[CLKID_PWM_C_DIV] = &pwm_c_div.hw,
2032
-
[CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
2033
-
[CLKID_PWM_D_DIV] = &pwm_d_div.hw,
2034
-
[CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
2035
-
[CLKID_PWM_E_DIV] = &pwm_e_div.hw,
2036
-
[CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
2037
-
[CLKID_PWM_F_DIV] = &pwm_f_div.hw,
2038
-
[CLKID_SPICC_SEL] = &spicc_sel.hw,
2039
-
[CLKID_SPICC_DIV] = &spicc_div.hw,
2040
-
[CLKID_SPICC_SEL2] = &spicc_sel2.hw,
2041
-
[CLKID_TS_DIV] = &ts_div.hw,
2042
-
[CLKID_SPIFC_SEL] = &spifc_sel.hw,
2043
-
[CLKID_SPIFC_DIV] = &spifc_div.hw,
2044
-
[CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
2045
-
[CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
2046
-
[CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
2047
-
[CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
2048
-
[CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
2049
-
[CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
2050
-
[CLKID_PSRAM_SEL] = &psram_sel.hw,
2051
-
[CLKID_PSRAM_DIV] = &psram_div.hw,
2052
-
[CLKID_PSRAM_SEL2] = &psram_sel2.hw,
2053
-
[CLKID_DMC_SEL] = &dmc_sel.hw,
2054
-
[CLKID_DMC_DIV] = &dmc_div.hw,
2055
-
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
1914
+
static struct clk_hw *a1_peripherals_hw_clks[] = {
1915
+
[CLKID_XTAL_IN] = &a1_xtal_in.hw,
1916
+
[CLKID_FIXPLL_IN] = &a1_fixpll_in.hw,
1917
+
[CLKID_USB_PHY_IN] = &a1_usb_phy_in.hw,
1918
+
[CLKID_USB_CTRL_IN] = &a1_usb_ctrl_in.hw,
1919
+
[CLKID_HIFIPLL_IN] = &a1_hifipll_in.hw,
1920
+
[CLKID_SYSPLL_IN] = &a1_syspll_in.hw,
1921
+
[CLKID_DDS_IN] = &a1_dds_in.hw,
1922
+
[CLKID_SYS] = &a1_sys.hw,
1923
+
[CLKID_CLKTREE] = &a1_clktree.hw,
1924
+
[CLKID_RESET_CTRL] = &a1_reset_ctrl.hw,
1925
+
[CLKID_ANALOG_CTRL] = &a1_analog_ctrl.hw,
1926
+
[CLKID_PWR_CTRL] = &a1_pwr_ctrl.hw,
1927
+
[CLKID_PAD_CTRL] = &a1_pad_ctrl.hw,
1928
+
[CLKID_SYS_CTRL] = &a1_sys_ctrl.hw,
1929
+
[CLKID_TEMP_SENSOR] = &a1_temp_sensor.hw,
1930
+
[CLKID_AM2AXI_DIV] = &a1_am2axi_dev.hw,
1931
+
[CLKID_SPICC_B] = &a1_spicc_b.hw,
1932
+
[CLKID_SPICC_A] = &a1_spicc_a.hw,
1933
+
[CLKID_MSR] = &a1_msr.hw,
1934
+
[CLKID_AUDIO] = &a1_audio.hw,
1935
+
[CLKID_JTAG_CTRL] = &a1_jtag_ctrl.hw,
1936
+
[CLKID_SARADC_EN] = &a1_saradc_en.hw,
1937
+
[CLKID_PWM_EF] = &a1_pwm_ef.hw,
1938
+
[CLKID_PWM_CD] = &a1_pwm_cd.hw,
1939
+
[CLKID_PWM_AB] = &a1_pwm_ab.hw,
1940
+
[CLKID_CEC] = &a1_cec.hw,
1941
+
[CLKID_I2C_S] = &a1_i2c_s.hw,
1942
+
[CLKID_IR_CTRL] = &a1_ir_ctrl.hw,
1943
+
[CLKID_I2C_M_D] = &a1_i2c_m_d.hw,
1944
+
[CLKID_I2C_M_C] = &a1_i2c_m_c.hw,
1945
+
[CLKID_I2C_M_B] = &a1_i2c_m_b.hw,
1946
+
[CLKID_I2C_M_A] = &a1_i2c_m_a.hw,
1947
+
[CLKID_ACODEC] = &a1_acodec.hw,
1948
+
[CLKID_OTP] = &a1_otp.hw,
1949
+
[CLKID_SD_EMMC_A] = &a1_sd_emmc_a.hw,
1950
+
[CLKID_USB_PHY] = &a1_usb_phy.hw,
1951
+
[CLKID_USB_CTRL] = &a1_usb_ctrl.hw,
1952
+
[CLKID_SYS_DSPB] = &a1_sys_dspb.hw,
1953
+
[CLKID_SYS_DSPA] = &a1_sys_dspa.hw,
1954
+
[CLKID_DMA] = &a1_dma.hw,
1955
+
[CLKID_IRQ_CTRL] = &a1_irq_ctrl.hw,
1956
+
[CLKID_NIC] = &a1_nic.hw,
1957
+
[CLKID_GIC] = &a1_gic.hw,
1958
+
[CLKID_UART_C] = &a1_uart_c.hw,
1959
+
[CLKID_UART_B] = &a1_uart_b.hw,
1960
+
[CLKID_UART_A] = &a1_uart_a.hw,
1961
+
[CLKID_SYS_PSRAM] = &a1_sys_psram.hw,
1962
+
[CLKID_RSA] = &a1_rsa.hw,
1963
+
[CLKID_CORESIGHT] = &a1_coresight.hw,
1964
+
[CLKID_AM2AXI_VAD] = &a1_am2axi_vad.hw,
1965
+
[CLKID_AUDIO_VAD] = &a1_audio_vad.hw,
1966
+
[CLKID_AXI_DMC] = &a1_axi_dmc.hw,
1967
+
[CLKID_AXI_PSRAM] = &a1_axi_psram.hw,
1968
+
[CLKID_RAMB] = &a1_ramb.hw,
1969
+
[CLKID_RAMA] = &a1_rama.hw,
1970
+
[CLKID_AXI_SPIFC] = &a1_axi_spifc.hw,
1971
+
[CLKID_AXI_NIC] = &a1_axi_nic.hw,
1972
+
[CLKID_AXI_DMA] = &a1_axi_dma.hw,
1973
+
[CLKID_CPU_CTRL] = &a1_cpu_ctrl.hw,
1974
+
[CLKID_ROM] = &a1_rom.hw,
1975
+
[CLKID_PROC_I2C] = &a1_prod_i2c.hw,
1976
+
[CLKID_DSPA_SEL] = &a1_dspa_sel.hw,
1977
+
[CLKID_DSPB_SEL] = &a1_dspb_sel.hw,
1978
+
[CLKID_DSPA_EN] = &a1_dspa_en.hw,
1979
+
[CLKID_DSPA_EN_NIC] = &a1_dspa_en_nic.hw,
1980
+
[CLKID_DSPB_EN] = &a1_dspb_en.hw,
1981
+
[CLKID_DSPB_EN_NIC] = &a1_dspb_en_nic.hw,
1982
+
[CLKID_RTC] = &a1_rtc.hw,
1983
+
[CLKID_CECA_32K] = &a1_ceca_32k_out.hw,
1984
+
[CLKID_CECB_32K] = &a1_cecb_32k_out.hw,
1985
+
[CLKID_24M] = &a1_24m.hw,
1986
+
[CLKID_12M] = &a1_12m.hw,
1987
+
[CLKID_FCLK_DIV2_DIVN] = &a1_fclk_div2_divn.hw,
1988
+
[CLKID_GEN] = &a1_gen.hw,
1989
+
[CLKID_SARADC_SEL] = &a1_saradc_sel.hw,
1990
+
[CLKID_SARADC] = &a1_saradc.hw,
1991
+
[CLKID_PWM_A] = &a1_pwm_a.hw,
1992
+
[CLKID_PWM_B] = &a1_pwm_b.hw,
1993
+
[CLKID_PWM_C] = &a1_pwm_c.hw,
1994
+
[CLKID_PWM_D] = &a1_pwm_d.hw,
1995
+
[CLKID_PWM_E] = &a1_pwm_e.hw,
1996
+
[CLKID_PWM_F] = &a1_pwm_f.hw,
1997
+
[CLKID_SPICC] = &a1_spicc.hw,
1998
+
[CLKID_TS] = &a1_ts.hw,
1999
+
[CLKID_SPIFC] = &a1_spifc.hw,
2000
+
[CLKID_USB_BUS] = &a1_usb_bus.hw,
2001
+
[CLKID_SD_EMMC] = &a1_sd_emmc.hw,
2002
+
[CLKID_PSRAM] = &a1_psram.hw,
2003
+
[CLKID_DMC] = &a1_dmc.hw,
2004
+
[CLKID_SYS_A_SEL] = &a1_sys_a_sel.hw,
2005
+
[CLKID_SYS_A_DIV] = &a1_sys_a_div.hw,
2006
+
[CLKID_SYS_A] = &a1_sys_a.hw,
2007
+
[CLKID_SYS_B_SEL] = &a1_sys_b_sel.hw,
2008
+
[CLKID_SYS_B_DIV] = &a1_sys_b_div.hw,
2009
+
[CLKID_SYS_B] = &a1_sys_b.hw,
2010
+
[CLKID_DSPA_A_SEL] = &a1_dspa_a_sel.hw,
2011
+
[CLKID_DSPA_A_DIV] = &a1_dspa_a_div.hw,
2012
+
[CLKID_DSPA_A] = &a1_dspa_a.hw,
2013
+
[CLKID_DSPA_B_SEL] = &a1_dspa_b_sel.hw,
2014
+
[CLKID_DSPA_B_DIV] = &a1_dspa_b_div.hw,
2015
+
[CLKID_DSPA_B] = &a1_dspa_b.hw,
2016
+
[CLKID_DSPB_A_SEL] = &a1_dspb_a_sel.hw,
2017
+
[CLKID_DSPB_A_DIV] = &a1_dspb_a_div.hw,
2018
+
[CLKID_DSPB_A] = &a1_dspb_a.hw,
2019
+
[CLKID_DSPB_B_SEL] = &a1_dspb_b_sel.hw,
2020
+
[CLKID_DSPB_B_DIV] = &a1_dspb_b_div.hw,
2021
+
[CLKID_DSPB_B] = &a1_dspb_b.hw,
2022
+
[CLKID_RTC_32K_IN] = &a1_rtc_32k_in.hw,
2023
+
[CLKID_RTC_32K_DIV] = &a1_rtc_32k_div.hw,
2024
+
[CLKID_RTC_32K_XTAL] = &a1_rtc_32k_xtal.hw,
2025
+
[CLKID_RTC_32K_SEL] = &a1_rtc_32k_sel.hw,
2026
+
[CLKID_CECB_32K_IN] = &a1_cecb_32k_in.hw,
2027
+
[CLKID_CECB_32K_DIV] = &a1_cecb_32k_div.hw,
2028
+
[CLKID_CECB_32K_SEL_PRE] = &a1_cecb_32k_sel_pre.hw,
2029
+
[CLKID_CECB_32K_SEL] = &a1_cecb_32k_sel.hw,
2030
+
[CLKID_CECA_32K_IN] = &a1_ceca_32k_in.hw,
2031
+
[CLKID_CECA_32K_DIV] = &a1_ceca_32k_div.hw,
2032
+
[CLKID_CECA_32K_SEL_PRE] = &a1_ceca_32k_sel_pre.hw,
2033
+
[CLKID_CECA_32K_SEL] = &a1_ceca_32k_sel.hw,
2034
+
[CLKID_DIV2_PRE] = &a1_fclk_div2_divn_pre.hw,
2035
+
[CLKID_24M_DIV2] = &a1_24m_div2.hw,
2036
+
[CLKID_GEN_SEL] = &a1_gen_sel.hw,
2037
+
[CLKID_GEN_DIV] = &a1_gen_div.hw,
2038
+
[CLKID_SARADC_DIV] = &a1_saradc_div.hw,
2039
+
[CLKID_PWM_A_SEL] = &a1_pwm_a_sel.hw,
2040
+
[CLKID_PWM_A_DIV] = &a1_pwm_a_div.hw,
2041
+
[CLKID_PWM_B_SEL] = &a1_pwm_b_sel.hw,
2042
+
[CLKID_PWM_B_DIV] = &a1_pwm_b_div.hw,
2043
+
[CLKID_PWM_C_SEL] = &a1_pwm_c_sel.hw,
2044
+
[CLKID_PWM_C_DIV] = &a1_pwm_c_div.hw,
2045
+
[CLKID_PWM_D_SEL] = &a1_pwm_d_sel.hw,
2046
+
[CLKID_PWM_D_DIV] = &a1_pwm_d_div.hw,
2047
+
[CLKID_PWM_E_SEL] = &a1_pwm_e_sel.hw,
2048
+
[CLKID_PWM_E_DIV] = &a1_pwm_e_div.hw,
2049
+
[CLKID_PWM_F_SEL] = &a1_pwm_f_sel.hw,
2050
+
[CLKID_PWM_F_DIV] = &a1_pwm_f_div.hw,
2051
+
[CLKID_SPICC_SEL] = &a1_spicc_sel.hw,
2052
+
[CLKID_SPICC_DIV] = &a1_spicc_div.hw,
2053
+
[CLKID_SPICC_SEL2] = &a1_spicc_sel2.hw,
2054
+
[CLKID_TS_DIV] = &a1_ts_div.hw,
2055
+
[CLKID_SPIFC_SEL] = &a1_spifc_sel.hw,
2056
+
[CLKID_SPIFC_DIV] = &a1_spifc_div.hw,
2057
+
[CLKID_SPIFC_SEL2] = &a1_spifc_sel2.hw,
2058
+
[CLKID_USB_BUS_SEL] = &a1_usb_bus_sel.hw,
2059
+
[CLKID_USB_BUS_DIV] = &a1_usb_bus_div.hw,
2060
+
[CLKID_SD_EMMC_SEL] = &a1_sd_emmc_sel.hw,
2061
+
[CLKID_SD_EMMC_DIV] = &a1_sd_emmc_div.hw,
2062
+
[CLKID_SD_EMMC_SEL2] = &a1_sd_emmc_sel2.hw,
2063
+
[CLKID_PSRAM_SEL] = &a1_psram_sel.hw,
2064
+
[CLKID_PSRAM_DIV] = &a1_psram_div.hw,
2065
+
[CLKID_PSRAM_SEL2] = &a1_psram_sel2.hw,
2066
+
[CLKID_DMC_SEL] = &a1_dmc_sel.hw,
2067
+
[CLKID_DMC_DIV] = &a1_dmc_div.hw,
2068
+
[CLKID_DMC_SEL2] = &a1_dmc_sel2.hw,
2056
2069
};
2057
2070
2058
-
static const struct regmap_config a1_periphs_regmap_cfg = {
2059
-
.reg_bits = 32,
2060
-
.val_bits = 32,
2061
-
.reg_stride = 4,
2062
-
.max_register = DMC_CLK_CTRL,
2063
-
};
2064
-
2065
-
static struct meson_clk_hw_data a1_periphs_clks = {
2066
-
.hws = a1_periphs_hw_clks,
2067
-
.num = ARRAY_SIZE(a1_periphs_hw_clks),
2068
-
};
2069
-
2070
-
static int meson_a1_periphs_probe(struct platform_device *pdev)
2071
-
{
2072
-
struct device *dev = &pdev->dev;
2073
-
void __iomem *base;
2074
-
struct regmap *map;
2075
-
int clkid, err;
2076
-
2077
-
base = devm_platform_ioremap_resource(pdev, 0);
2078
-
if (IS_ERR(base))
2079
-
return dev_err_probe(dev, PTR_ERR(base),
2080
-
"can't ioremap resource\n");
2081
-
2082
-
map = devm_regmap_init_mmio(dev, base, &a1_periphs_regmap_cfg);
2083
-
if (IS_ERR(map))
2084
-
return dev_err_probe(dev, PTR_ERR(map),
2085
-
"can't init regmap mmio region\n");
2086
-
2087
-
for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) {
2088
-
err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]);
2089
-
if (err)
2090
-
return dev_err_probe(dev, err,
2091
-
"clock[%d] registration failed\n",
2092
-
clkid);
2093
-
}
2094
-
2095
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks);
2096
-
}
2097
-
2098
-
static const struct of_device_id a1_periphs_clkc_match_table[] = {
2099
-
{ .compatible = "amlogic,a1-peripherals-clkc", },
2100
-
{}
2101
-
};
2102
-
MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table);
2103
-
2104
-
static struct platform_driver a1_periphs_clkc_driver = {
2105
-
.probe = meson_a1_periphs_probe,
2106
-
.driver = {
2107
-
.name = "a1-peripherals-clkc",
2108
-
.of_match_table = a1_periphs_clkc_match_table,
2071
+
static const struct meson_clkc_data a1_peripherals_clkc_data = {
2072
+
.hw_clks = {
2073
+
.hws = a1_peripherals_hw_clks,
2074
+
.num = ARRAY_SIZE(a1_peripherals_hw_clks),
2109
2075
},
2110
2076
};
2111
-
module_platform_driver(a1_periphs_clkc_driver);
2077
+
2078
+
static const struct of_device_id a1_peripherals_clkc_match_table[] = {
2079
+
{
2080
+
.compatible = "amlogic,a1-peripherals-clkc",
2081
+
.data = &a1_peripherals_clkc_data,
2082
+
},
2083
+
{}
2084
+
};
2085
+
MODULE_DEVICE_TABLE(of, a1_peripherals_clkc_match_table);
2086
+
2087
+
static struct platform_driver a1_peripherals_clkc_driver = {
2088
+
.probe = meson_clkc_mmio_probe,
2089
+
.driver = {
2090
+
.name = "a1-peripherals-clkc",
2091
+
.of_match_table = a1_peripherals_clkc_match_table,
2092
+
},
2093
+
};
2094
+
module_platform_driver(a1_peripherals_clkc_driver);
2112
2095
2113
2096
MODULE_DESCRIPTION("Amlogic A1 Peripherals Clock Controller driver");
2114
2097
MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
+46
-78
drivers/clk/meson/a1-pll.c
+46
-78
drivers/clk/meson/a1-pll.c
···
26
26
27
27
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
28
28
29
-
static struct clk_regmap fixed_pll_dco = {
29
+
static struct clk_regmap a1_fixed_pll_dco = {
30
30
.data = &(struct meson_clk_pll_data){
31
31
.en = {
32
32
.reg_off = ANACTRL_FIXPLL_CTRL0,
···
69
69
},
70
70
};
71
71
72
-
static struct clk_regmap fixed_pll = {
72
+
static struct clk_regmap a1_fixed_pll = {
73
73
.data = &(struct clk_regmap_gate_data){
74
74
.offset = ANACTRL_FIXPLL_CTRL0,
75
75
.bit_idx = 20,
···
78
78
.name = "fixed_pll",
79
79
.ops = &clk_regmap_gate_ops,
80
80
.parent_hws = (const struct clk_hw *[]) {
81
-
&fixed_pll_dco.hw
81
+
&a1_fixed_pll_dco.hw
82
82
},
83
83
.num_parents = 1,
84
84
},
85
85
};
86
86
87
-
static const struct pll_mult_range hifi_pll_mult_range = {
87
+
static const struct pll_mult_range a1_hifi_pll_range = {
88
88
.min = 32,
89
89
.max = 64,
90
90
};
91
91
92
-
static const struct reg_sequence hifi_init_regs[] = {
92
+
static const struct reg_sequence a1_hifi_pll_init_regs[] = {
93
93
{ .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x01800000 },
94
94
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00001100 },
95
95
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x100a1100 },
···
97
97
{ .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x01f18000 },
98
98
};
99
99
100
-
static struct clk_regmap hifi_pll = {
100
+
static struct clk_regmap a1_hifi_pll = {
101
101
.data = &(struct meson_clk_pll_data){
102
102
.en = {
103
103
.reg_off = ANACTRL_HIFIPLL_CTRL0,
···
134
134
.shift = 6,
135
135
.width = 1,
136
136
},
137
-
.range = &hifi_pll_mult_range,
138
-
.init_regs = hifi_init_regs,
139
-
.init_count = ARRAY_SIZE(hifi_init_regs),
137
+
.range = &a1_hifi_pll_range,
138
+
.init_regs = a1_hifi_pll_init_regs,
139
+
.init_count = ARRAY_SIZE(a1_hifi_pll_init_regs),
140
140
},
141
141
.hw.init = &(struct clk_init_data){
142
142
.name = "hifi_pll",
···
148
148
},
149
149
};
150
150
151
-
static struct clk_fixed_factor fclk_div2_div = {
151
+
static struct clk_fixed_factor a1_fclk_div2_div = {
152
152
.mult = 1,
153
153
.div = 2,
154
154
.hw.init = &(struct clk_init_data){
155
155
.name = "fclk_div2_div",
156
156
.ops = &clk_fixed_factor_ops,
157
157
.parent_hws = (const struct clk_hw *[]) {
158
-
&fixed_pll.hw
158
+
&a1_fixed_pll.hw
159
159
},
160
160
.num_parents = 1,
161
161
},
162
162
};
163
163
164
-
static struct clk_regmap fclk_div2 = {
164
+
static struct clk_regmap a1_fclk_div2 = {
165
165
.data = &(struct clk_regmap_gate_data){
166
166
.offset = ANACTRL_FIXPLL_CTRL0,
167
167
.bit_idx = 21,
···
170
170
.name = "fclk_div2",
171
171
.ops = &clk_regmap_gate_ops,
172
172
.parent_hws = (const struct clk_hw *[]) {
173
-
&fclk_div2_div.hw
173
+
&a1_fclk_div2_div.hw
174
174
},
175
175
.num_parents = 1,
176
176
/*
···
186
186
},
187
187
};
188
188
189
-
static struct clk_fixed_factor fclk_div3_div = {
189
+
static struct clk_fixed_factor a1_fclk_div3_div = {
190
190
.mult = 1,
191
191
.div = 3,
192
192
.hw.init = &(struct clk_init_data){
193
193
.name = "fclk_div3_div",
194
194
.ops = &clk_fixed_factor_ops,
195
195
.parent_hws = (const struct clk_hw *[]) {
196
-
&fixed_pll.hw
196
+
&a1_fixed_pll.hw
197
197
},
198
198
.num_parents = 1,
199
199
},
200
200
};
201
201
202
-
static struct clk_regmap fclk_div3 = {
202
+
static struct clk_regmap a1_fclk_div3 = {
203
203
.data = &(struct clk_regmap_gate_data){
204
204
.offset = ANACTRL_FIXPLL_CTRL0,
205
205
.bit_idx = 22,
···
208
208
.name = "fclk_div3",
209
209
.ops = &clk_regmap_gate_ops,
210
210
.parent_hws = (const struct clk_hw *[]) {
211
-
&fclk_div3_div.hw
211
+
&a1_fclk_div3_div.hw
212
212
},
213
213
.num_parents = 1,
214
214
/*
···
219
219
},
220
220
};
221
221
222
-
static struct clk_fixed_factor fclk_div5_div = {
222
+
static struct clk_fixed_factor a1_fclk_div5_div = {
223
223
.mult = 1,
224
224
.div = 5,
225
225
.hw.init = &(struct clk_init_data){
226
226
.name = "fclk_div5_div",
227
227
.ops = &clk_fixed_factor_ops,
228
228
.parent_hws = (const struct clk_hw *[]) {
229
-
&fixed_pll.hw
229
+
&a1_fixed_pll.hw
230
230
},
231
231
.num_parents = 1,
232
232
},
233
233
};
234
234
235
-
static struct clk_regmap fclk_div5 = {
235
+
static struct clk_regmap a1_fclk_div5 = {
236
236
.data = &(struct clk_regmap_gate_data){
237
237
.offset = ANACTRL_FIXPLL_CTRL0,
238
238
.bit_idx = 23,
···
241
241
.name = "fclk_div5",
242
242
.ops = &clk_regmap_gate_ops,
243
243
.parent_hws = (const struct clk_hw *[]) {
244
-
&fclk_div5_div.hw
244
+
&a1_fclk_div5_div.hw
245
245
},
246
246
.num_parents = 1,
247
247
/*
···
252
252
},
253
253
};
254
254
255
-
static struct clk_fixed_factor fclk_div7_div = {
255
+
static struct clk_fixed_factor a1_fclk_div7_div = {
256
256
.mult = 1,
257
257
.div = 7,
258
258
.hw.init = &(struct clk_init_data){
259
259
.name = "fclk_div7_div",
260
260
.ops = &clk_fixed_factor_ops,
261
261
.parent_hws = (const struct clk_hw *[]) {
262
-
&fixed_pll.hw
262
+
&a1_fixed_pll.hw
263
263
},
264
264
.num_parents = 1,
265
265
},
266
266
};
267
267
268
-
static struct clk_regmap fclk_div7 = {
268
+
static struct clk_regmap a1_fclk_div7 = {
269
269
.data = &(struct clk_regmap_gate_data){
270
270
.offset = ANACTRL_FIXPLL_CTRL0,
271
271
.bit_idx = 24,
···
274
274
.name = "fclk_div7",
275
275
.ops = &clk_regmap_gate_ops,
276
276
.parent_hws = (const struct clk_hw *[]) {
277
-
&fclk_div7_div.hw
277
+
&a1_fclk_div7_div.hw
278
278
},
279
279
.num_parents = 1,
280
280
},
···
282
282
283
283
/* Array of all clocks registered by this provider */
284
284
static struct clk_hw *a1_pll_hw_clks[] = {
285
-
[CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
286
-
[CLKID_FIXED_PLL] = &fixed_pll.hw,
287
-
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
288
-
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
289
-
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
290
-
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
291
-
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
292
-
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
293
-
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
294
-
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
295
-
[CLKID_HIFI_PLL] = &hifi_pll.hw,
285
+
[CLKID_FIXED_PLL_DCO] = &a1_fixed_pll_dco.hw,
286
+
[CLKID_FIXED_PLL] = &a1_fixed_pll.hw,
287
+
[CLKID_FCLK_DIV2_DIV] = &a1_fclk_div2_div.hw,
288
+
[CLKID_FCLK_DIV3_DIV] = &a1_fclk_div3_div.hw,
289
+
[CLKID_FCLK_DIV5_DIV] = &a1_fclk_div5_div.hw,
290
+
[CLKID_FCLK_DIV7_DIV] = &a1_fclk_div7_div.hw,
291
+
[CLKID_FCLK_DIV2] = &a1_fclk_div2.hw,
292
+
[CLKID_FCLK_DIV3] = &a1_fclk_div3.hw,
293
+
[CLKID_FCLK_DIV5] = &a1_fclk_div5.hw,
294
+
[CLKID_FCLK_DIV7] = &a1_fclk_div7.hw,
295
+
[CLKID_HIFI_PLL] = &a1_hifi_pll.hw,
296
296
};
297
297
298
-
static const struct regmap_config a1_pll_regmap_cfg = {
299
-
.reg_bits = 32,
300
-
.val_bits = 32,
301
-
.reg_stride = 4,
302
-
.max_register = ANACTRL_HIFIPLL_STS,
298
+
static const struct meson_clkc_data a1_pll_clkc_data = {
299
+
.hw_clks = {
300
+
.hws = a1_pll_hw_clks,
301
+
.num = ARRAY_SIZE(a1_pll_hw_clks),
302
+
},
303
303
};
304
-
305
-
static struct meson_clk_hw_data a1_pll_clks = {
306
-
.hws = a1_pll_hw_clks,
307
-
.num = ARRAY_SIZE(a1_pll_hw_clks),
308
-
};
309
-
310
-
static int meson_a1_pll_probe(struct platform_device *pdev)
311
-
{
312
-
struct device *dev = &pdev->dev;
313
-
void __iomem *base;
314
-
struct regmap *map;
315
-
int clkid, err;
316
-
317
-
base = devm_platform_ioremap_resource(pdev, 0);
318
-
if (IS_ERR(base))
319
-
return dev_err_probe(dev, PTR_ERR(base),
320
-
"can't ioremap resource\n");
321
-
322
-
map = devm_regmap_init_mmio(dev, base, &a1_pll_regmap_cfg);
323
-
if (IS_ERR(map))
324
-
return dev_err_probe(dev, PTR_ERR(map),
325
-
"can't init regmap mmio region\n");
326
-
327
-
/* Register clocks */
328
-
for (clkid = 0; clkid < a1_pll_clks.num; clkid++) {
329
-
err = devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]);
330
-
if (err)
331
-
return dev_err_probe(dev, err,
332
-
"clock[%d] registration failed\n",
333
-
clkid);
334
-
}
335
-
336
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
337
-
&a1_pll_clks);
338
-
}
339
304
340
305
static const struct of_device_id a1_pll_clkc_match_table[] = {
341
-
{ .compatible = "amlogic,a1-pll-clkc", },
306
+
{
307
+
.compatible = "amlogic,a1-pll-clkc",
308
+
.data = &a1_pll_clkc_data,
309
+
},
342
310
{}
343
311
};
344
312
MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table);
345
313
346
314
static struct platform_driver a1_pll_clkc_driver = {
347
-
.probe = meson_a1_pll_probe,
315
+
.probe = meson_clkc_mmio_probe,
348
316
.driver = {
349
317
.name = "a1-pll-clkc",
350
318
.of_match_table = a1_pll_clkc_match_table,
+75
-78
drivers/clk/meson/axg-aoclk.c
+75
-78
drivers/clk/meson/axg-aoclk.c
···
34
34
#define AO_RTC_ALT_CLK_CNTL0 0x94
35
35
#define AO_RTC_ALT_CLK_CNTL1 0x98
36
36
37
-
#define AXG_AO_GATE(_name, _bit) \
38
-
static struct clk_regmap axg_aoclk_##_name = { \
39
-
.data = &(struct clk_regmap_gate_data) { \
40
-
.offset = (AO_RTI_GEN_CNTL_REG0), \
41
-
.bit_idx = (_bit), \
42
-
}, \
43
-
.hw.init = &(struct clk_init_data) { \
44
-
.name = "axg_ao_" #_name, \
45
-
.ops = &clk_regmap_gate_ops, \
46
-
.parent_data = &(const struct clk_parent_data) { \
47
-
.fw_name = "mpeg-clk", \
48
-
}, \
49
-
.num_parents = 1, \
50
-
.flags = CLK_IGNORE_UNUSED, \
51
-
}, \
52
-
}
37
+
static const struct clk_parent_data axg_ao_pclk_parents = { .fw_name = "mpeg-clk" };
53
38
54
-
AXG_AO_GATE(remote, 0);
55
-
AXG_AO_GATE(i2c_master, 1);
56
-
AXG_AO_GATE(i2c_slave, 2);
57
-
AXG_AO_GATE(uart1, 3);
58
-
AXG_AO_GATE(uart2, 5);
59
-
AXG_AO_GATE(ir_blaster, 6);
60
-
AXG_AO_GATE(saradc, 7);
39
+
#define AXG_AO_GATE(_name, _bit, _flags) \
40
+
MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
41
+
&axg_ao_pclk_parents, _flags)
61
42
62
-
static struct clk_regmap axg_aoclk_cts_oscin = {
43
+
static AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED);
44
+
static AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED);
45
+
static AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED);
46
+
static AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED);
47
+
static AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED);
48
+
static AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED);
49
+
static AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED);
50
+
51
+
static struct clk_regmap axg_ao_cts_oscin = {
63
52
.data = &(struct clk_regmap_gate_data){
64
53
.offset = AO_RTI_PWR_CNTL_REG0,
65
54
.bit_idx = 14,
···
63
74
},
64
75
};
65
76
66
-
static struct clk_regmap axg_aoclk_32k_pre = {
77
+
static struct clk_regmap axg_ao_32k_pre = {
67
78
.data = &(struct clk_regmap_gate_data){
68
79
.offset = AO_RTC_ALT_CLK_CNTL0,
69
80
.bit_idx = 31,
···
72
83
.name = "axg_ao_32k_pre",
73
84
.ops = &clk_regmap_gate_ops,
74
85
.parent_hws = (const struct clk_hw *[]) {
75
-
&axg_aoclk_cts_oscin.hw
86
+
&axg_ao_cts_oscin.hw
76
87
},
77
88
.num_parents = 1,
78
89
},
···
88
99
}, {}
89
100
};
90
101
91
-
static struct clk_regmap axg_aoclk_32k_div = {
102
+
static struct clk_regmap axg_ao_32k_div = {
92
103
.data = &(struct meson_clk_dualdiv_data){
93
104
.n1 = {
94
105
.reg_off = AO_RTC_ALT_CLK_CNTL0,
···
121
132
.name = "axg_ao_32k_div",
122
133
.ops = &meson_clk_dualdiv_ops,
123
134
.parent_hws = (const struct clk_hw *[]) {
124
-
&axg_aoclk_32k_pre.hw
135
+
&axg_ao_32k_pre.hw
125
136
},
126
137
.num_parents = 1,
127
138
},
128
139
};
129
140
130
-
static struct clk_regmap axg_aoclk_32k_sel = {
141
+
static struct clk_regmap axg_ao_32k_sel = {
131
142
.data = &(struct clk_regmap_mux_data) {
132
143
.offset = AO_RTC_ALT_CLK_CNTL1,
133
144
.mask = 0x1,
···
138
149
.name = "axg_ao_32k_sel",
139
150
.ops = &clk_regmap_mux_ops,
140
151
.parent_hws = (const struct clk_hw *[]) {
141
-
&axg_aoclk_32k_div.hw,
142
-
&axg_aoclk_32k_pre.hw,
152
+
&axg_ao_32k_div.hw,
153
+
&axg_ao_32k_pre.hw,
143
154
},
144
155
.num_parents = 2,
145
156
.flags = CLK_SET_RATE_PARENT,
146
157
},
147
158
};
148
159
149
-
static struct clk_regmap axg_aoclk_32k = {
160
+
static struct clk_regmap axg_ao_32k = {
150
161
.data = &(struct clk_regmap_gate_data){
151
162
.offset = AO_RTC_ALT_CLK_CNTL0,
152
163
.bit_idx = 30,
···
155
166
.name = "axg_ao_32k",
156
167
.ops = &clk_regmap_gate_ops,
157
168
.parent_hws = (const struct clk_hw *[]) {
158
-
&axg_aoclk_32k_sel.hw
169
+
&axg_ao_32k_sel.hw
159
170
},
160
171
.num_parents = 1,
161
172
.flags = CLK_SET_RATE_PARENT,
162
173
},
163
174
};
164
175
165
-
static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
176
+
static struct clk_regmap axg_ao_cts_rtc_oscin = {
166
177
.data = &(struct clk_regmap_mux_data) {
167
178
.offset = AO_RTI_PWR_CNTL_REG0,
168
179
.mask = 0x1,
···
173
184
.name = "axg_ao_cts_rtc_oscin",
174
185
.ops = &clk_regmap_mux_ops,
175
186
.parent_data = (const struct clk_parent_data []) {
176
-
{ .hw = &axg_aoclk_32k.hw },
187
+
{ .hw = &axg_ao_32k.hw },
177
188
{ .fw_name = "ext_32k-0", },
178
189
},
179
190
.num_parents = 2,
···
181
192
},
182
193
};
183
194
184
-
static struct clk_regmap axg_aoclk_clk81 = {
195
+
static struct clk_regmap axg_ao_clk81 = {
185
196
.data = &(struct clk_regmap_mux_data) {
186
197
.offset = AO_RTI_PWR_CNTL_REG0,
187
198
.mask = 0x1,
···
189
200
.flags = CLK_MUX_ROUND_CLOSEST,
190
201
},
191
202
.hw.init = &(struct clk_init_data){
203
+
/*
204
+
* NOTE: this is one of the infamous clock the pwm driver
205
+
* can request directly by its global name. It's wrong but
206
+
* there is not much we can do about it until the support
207
+
* for the old pwm bindings is dropped
208
+
*/
192
209
.name = "axg_ao_clk81",
193
210
.ops = &clk_regmap_mux_ro_ops,
194
211
.parent_data = (const struct clk_parent_data []) {
195
212
{ .fw_name = "mpeg-clk", },
196
-
{ .hw = &axg_aoclk_cts_rtc_oscin.hw },
213
+
{ .hw = &axg_ao_cts_rtc_oscin.hw },
197
214
},
198
215
.num_parents = 2,
199
216
.flags = CLK_SET_RATE_PARENT,
200
217
},
201
218
};
202
219
203
-
static struct clk_regmap axg_aoclk_saradc_mux = {
220
+
static struct clk_regmap axg_ao_saradc_mux = {
204
221
.data = &(struct clk_regmap_mux_data) {
205
222
.offset = AO_SAR_CLK,
206
223
.mask = 0x3,
207
224
.shift = 9,
208
225
},
209
226
.hw.init = &(struct clk_init_data){
210
-
.name = "axg_ao_saradc_mux",
227
+
.name = "ao_saradc_mux",
211
228
.ops = &clk_regmap_mux_ops,
212
229
.parent_data = (const struct clk_parent_data []) {
213
230
{ .fw_name = "xtal", },
214
-
{ .hw = &axg_aoclk_clk81.hw },
231
+
{ .hw = &axg_ao_clk81.hw },
215
232
},
216
233
.num_parents = 2,
217
234
},
218
235
};
219
236
220
-
static struct clk_regmap axg_aoclk_saradc_div = {
237
+
static struct clk_regmap axg_ao_saradc_div = {
221
238
.data = &(struct clk_regmap_div_data) {
222
239
.offset = AO_SAR_CLK,
223
240
.shift = 0,
224
241
.width = 8,
225
242
},
226
243
.hw.init = &(struct clk_init_data){
227
-
.name = "axg_ao_saradc_div",
244
+
.name = "ao_saradc_div",
228
245
.ops = &clk_regmap_divider_ops,
229
246
.parent_hws = (const struct clk_hw *[]) {
230
-
&axg_aoclk_saradc_mux.hw
247
+
&axg_ao_saradc_mux.hw
231
248
},
232
249
.num_parents = 1,
233
250
.flags = CLK_SET_RATE_PARENT,
234
251
},
235
252
};
236
253
237
-
static struct clk_regmap axg_aoclk_saradc_gate = {
254
+
static struct clk_regmap axg_ao_saradc_gate = {
238
255
.data = &(struct clk_regmap_gate_data) {
239
256
.offset = AO_SAR_CLK,
240
257
.bit_idx = 8,
241
258
},
242
259
.hw.init = &(struct clk_init_data){
243
-
.name = "axg_ao_saradc_gate",
260
+
.name = "ao_saradc_gate",
244
261
.ops = &clk_regmap_gate_ops,
245
262
.parent_hws = (const struct clk_hw *[]) {
246
-
&axg_aoclk_saradc_div.hw
263
+
&axg_ao_saradc_div.hw
247
264
},
248
265
.num_parents = 1,
249
266
.flags = CLK_SET_RATE_PARENT,
250
267
},
251
268
};
252
269
253
-
static const unsigned int axg_aoclk_reset[] = {
270
+
static const unsigned int axg_ao_reset[] = {
254
271
[RESET_AO_REMOTE] = 16,
255
272
[RESET_AO_I2C_MASTER] = 18,
256
273
[RESET_AO_I2C_SLAVE] = 19,
···
265
270
[RESET_AO_IR_BLASTER] = 23,
266
271
};
267
272
268
-
static struct clk_hw *axg_aoclk_hw_clks[] = {
269
-
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
270
-
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
271
-
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
272
-
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
273
-
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
274
-
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
275
-
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
276
-
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
277
-
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
278
-
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
279
-
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
280
-
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
281
-
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
282
-
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
283
-
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
284
-
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
285
-
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
273
+
static struct clk_hw *axg_ao_hw_clks[] = {
274
+
[CLKID_AO_REMOTE] = &axg_ao_remote.hw,
275
+
[CLKID_AO_I2C_MASTER] = &axg_ao_i2c_master.hw,
276
+
[CLKID_AO_I2C_SLAVE] = &axg_ao_i2c_slave.hw,
277
+
[CLKID_AO_UART1] = &axg_ao_uart1.hw,
278
+
[CLKID_AO_UART2] = &axg_ao_uart2.hw,
279
+
[CLKID_AO_IR_BLASTER] = &axg_ao_ir_blaster.hw,
280
+
[CLKID_AO_SAR_ADC] = &axg_ao_saradc.hw,
281
+
[CLKID_AO_CLK81] = &axg_ao_clk81.hw,
282
+
[CLKID_AO_SAR_ADC_SEL] = &axg_ao_saradc_mux.hw,
283
+
[CLKID_AO_SAR_ADC_DIV] = &axg_ao_saradc_div.hw,
284
+
[CLKID_AO_SAR_ADC_CLK] = &axg_ao_saradc_gate.hw,
285
+
[CLKID_AO_CTS_OSCIN] = &axg_ao_cts_oscin.hw,
286
+
[CLKID_AO_32K_PRE] = &axg_ao_32k_pre.hw,
287
+
[CLKID_AO_32K_DIV] = &axg_ao_32k_div.hw,
288
+
[CLKID_AO_32K_SEL] = &axg_ao_32k_sel.hw,
289
+
[CLKID_AO_32K] = &axg_ao_32k.hw,
290
+
[CLKID_AO_CTS_RTC_OSCIN] = &axg_ao_cts_rtc_oscin.hw,
286
291
};
287
292
288
-
static const struct meson_aoclk_data axg_aoclkc_data = {
293
+
static const struct meson_aoclk_data axg_ao_clkc_data = {
289
294
.reset_reg = AO_RTI_GEN_CNTL_REG0,
290
-
.num_reset = ARRAY_SIZE(axg_aoclk_reset),
291
-
.reset = axg_aoclk_reset,
292
-
.hw_clks = {
293
-
.hws = axg_aoclk_hw_clks,
294
-
.num = ARRAY_SIZE(axg_aoclk_hw_clks),
295
+
.num_reset = ARRAY_SIZE(axg_ao_reset),
296
+
.reset = axg_ao_reset,
297
+
.clkc_data = {
298
+
.hw_clks = {
299
+
.hws = axg_ao_hw_clks,
300
+
.num = ARRAY_SIZE(axg_ao_hw_clks),
301
+
},
295
302
},
296
303
};
297
304
298
-
static const struct of_device_id axg_aoclkc_match_table[] = {
305
+
static const struct of_device_id axg_ao_clkc_match_table[] = {
299
306
{
300
307
.compatible = "amlogic,meson-axg-aoclkc",
301
-
.data = &axg_aoclkc_data,
308
+
.data = &axg_ao_clkc_data.clkc_data,
302
309
},
303
310
{ }
304
311
};
305
-
MODULE_DEVICE_TABLE(of, axg_aoclkc_match_table);
312
+
MODULE_DEVICE_TABLE(of, axg_ao_clkc_match_table);
306
313
307
-
static struct platform_driver axg_aoclkc_driver = {
314
+
static struct platform_driver axg_ao_clkc_driver = {
308
315
.probe = meson_aoclkc_probe,
309
316
.driver = {
310
-
.name = "axg-aoclkc",
311
-
.of_match_table = axg_aoclkc_match_table,
317
+
.name = "axg-ao-clkc",
318
+
.of_match_table = axg_ao_clkc_match_table,
312
319
},
313
320
};
314
-
module_platform_driver(axg_aoclkc_driver);
321
+
module_platform_driver(axg_ao_clkc_driver);
315
322
316
323
MODULE_DESCRIPTION("Amlogic AXG Always-ON Clock Controller driver");
317
324
MODULE_LICENSE("GPL");
+121
-110
drivers/clk/meson/axg.c
+121
-110
drivers/clk/meson/axg.c
···
18
18
#include "clk-regmap.h"
19
19
#include "clk-pll.h"
20
20
#include "clk-mpll.h"
21
-
#include "meson-eeclk.h"
21
+
#include "meson-clkc-utils.h"
22
22
23
23
#include <dt-bindings/clock/axg-clkc.h>
24
24
···
333
333
},
334
334
};
335
335
336
-
static const struct reg_sequence axg_hifi_init_regs[] = {
336
+
static const struct reg_sequence axg_hifi_pll_init_regs[] = {
337
337
{ .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
338
338
{ .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
339
339
{ .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
···
374
374
.width = 1,
375
375
},
376
376
.table = axg_gp0_pll_params_table,
377
-
.init_regs = axg_hifi_init_regs,
378
-
.init_count = ARRAY_SIZE(axg_hifi_init_regs),
377
+
.init_regs = axg_hifi_pll_init_regs,
378
+
.init_count = ARRAY_SIZE(axg_hifi_pll_init_regs),
379
379
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
380
380
},
381
381
.hw.init = &(struct clk_init_data){
···
780
780
{ /* sentinel */ },
781
781
};
782
782
783
-
static const struct reg_sequence axg_pcie_init_regs[] = {
783
+
static const struct reg_sequence axg_pcie_pll_init_regs[] = {
784
784
{ .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
785
785
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
786
786
{ .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
···
823
823
.width = 1,
824
824
},
825
825
.table = axg_pcie_pll_params_table,
826
-
.init_regs = axg_pcie_init_regs,
827
-
.init_count = ARRAY_SIZE(axg_pcie_init_regs),
826
+
.init_regs = axg_pcie_pll_init_regs,
827
+
.init_count = ARRAY_SIZE(axg_pcie_pll_init_regs),
828
828
},
829
829
.hw.init = &(struct clk_init_data){
830
830
.name = "pcie_pll_dco",
···
935
935
},
936
936
};
937
937
938
-
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
939
-
static const struct clk_parent_data clk81_parent_data[] = {
938
+
/* clk81 is often referred as "mpeg_clk" */
939
+
static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
940
+
static const struct clk_parent_data clk81_parents[] = {
940
941
{ .fw_name = "xtal", },
941
942
{ .hw = &axg_fclk_div7.hw },
942
943
{ .hw = &axg_mpll1.hw },
···
947
946
{ .hw = &axg_fclk_div5.hw },
948
947
};
949
948
950
-
static struct clk_regmap axg_mpeg_clk_sel = {
949
+
static struct clk_regmap axg_clk81_sel = {
951
950
.data = &(struct clk_regmap_mux_data){
952
951
.offset = HHI_MPEG_CLK_CNTL,
953
952
.mask = 0x7,
954
953
.shift = 12,
955
-
.table = mux_table_clk81,
954
+
.table = clk81_parents_val_table,
956
955
},
957
956
.hw.init = &(struct clk_init_data){
958
-
.name = "mpeg_clk_sel",
957
+
.name = "clk81_sel",
959
958
.ops = &clk_regmap_mux_ro_ops,
960
-
.parent_data = clk81_parent_data,
961
-
.num_parents = ARRAY_SIZE(clk81_parent_data),
959
+
.parent_data = clk81_parents,
960
+
.num_parents = ARRAY_SIZE(clk81_parents),
962
961
},
963
962
};
964
963
965
-
static struct clk_regmap axg_mpeg_clk_div = {
964
+
static struct clk_regmap axg_clk81_div = {
966
965
.data = &(struct clk_regmap_div_data){
967
966
.offset = HHI_MPEG_CLK_CNTL,
968
967
.shift = 0,
969
968
.width = 7,
970
969
},
971
970
.hw.init = &(struct clk_init_data){
972
-
.name = "mpeg_clk_div",
971
+
.name = "clk81_div",
973
972
.ops = &clk_regmap_divider_ops,
974
973
.parent_hws = (const struct clk_hw *[]) {
975
-
&axg_mpeg_clk_sel.hw
974
+
&axg_clk81_sel.hw
976
975
},
977
976
.num_parents = 1,
978
977
.flags = CLK_SET_RATE_PARENT,
···
988
987
.name = "clk81",
989
988
.ops = &clk_regmap_gate_ops,
990
989
.parent_hws = (const struct clk_hw *[]) {
991
-
&axg_mpeg_clk_div.hw
990
+
&axg_clk81_div.hw
992
991
},
993
992
.num_parents = 1,
994
993
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
995
994
},
996
995
};
997
996
998
-
static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
997
+
static const struct clk_parent_data axg_sd_emmc_clk0_parents[] = {
999
998
{ .fw_name = "xtal", },
1000
999
{ .hw = &axg_fclk_div2.hw },
1001
1000
{ .hw = &axg_fclk_div3.hw },
···
1019
1018
.hw.init = &(struct clk_init_data) {
1020
1019
.name = "sd_emmc_b_clk0_sel",
1021
1020
.ops = &clk_regmap_mux_ops,
1022
-
.parent_data = axg_sd_emmc_clk0_parent_data,
1023
-
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
1021
+
.parent_data = axg_sd_emmc_clk0_parents,
1022
+
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents),
1024
1023
.flags = CLK_SET_RATE_PARENT,
1025
1024
},
1026
1025
};
···
1069
1068
.hw.init = &(struct clk_init_data) {
1070
1069
.name = "sd_emmc_c_clk0_sel",
1071
1070
.ops = &clk_regmap_mux_ops,
1072
-
.parent_data = axg_sd_emmc_clk0_parent_data,
1073
-
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
1071
+
.parent_data = axg_sd_emmc_clk0_parents,
1072
+
.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents),
1074
1073
.flags = CLK_SET_RATE_PARENT,
1075
1074
},
1076
1075
};
···
1111
1110
1112
1111
/* VPU Clock */
1113
1112
1114
-
static const struct clk_hw *axg_vpu_parent_hws[] = {
1113
+
static const struct clk_hw *axg_vpu_parents[] = {
1115
1114
&axg_fclk_div4.hw,
1116
1115
&axg_fclk_div3.hw,
1117
1116
&axg_fclk_div5.hw,
···
1127
1126
.hw.init = &(struct clk_init_data){
1128
1127
.name = "vpu_0_sel",
1129
1128
.ops = &clk_regmap_mux_ops,
1130
-
.parent_hws = axg_vpu_parent_hws,
1131
-
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1129
+
.parent_hws = axg_vpu_parents,
1130
+
.num_parents = ARRAY_SIZE(axg_vpu_parents),
1132
1131
/* We need a specific parent for VPU clock source, let it be set in DT */
1133
1132
.flags = CLK_SET_RATE_NO_REPARENT,
1134
1133
},
···
1176
1175
.hw.init = &(struct clk_init_data){
1177
1176
.name = "vpu_1_sel",
1178
1177
.ops = &clk_regmap_mux_ops,
1179
-
.parent_hws = axg_vpu_parent_hws,
1180
-
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1178
+
.parent_hws = axg_vpu_parents,
1179
+
.num_parents = ARRAY_SIZE(axg_vpu_parents),
1181
1180
/* We need a specific parent for VPU clock source, let it be set in DT */
1182
1181
.flags = CLK_SET_RATE_NO_REPARENT,
1183
1182
},
···
1245
1244
.hw.init = &(struct clk_init_data){
1246
1245
.name = "vapb_0_sel",
1247
1246
.ops = &clk_regmap_mux_ops,
1248
-
.parent_hws = axg_vpu_parent_hws,
1249
-
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1247
+
.parent_hws = axg_vpu_parents,
1248
+
.num_parents = ARRAY_SIZE(axg_vpu_parents),
1250
1249
.flags = CLK_SET_RATE_NO_REPARENT,
1251
1250
},
1252
1251
};
···
1293
1292
.hw.init = &(struct clk_init_data){
1294
1293
.name = "vapb_1_sel",
1295
1294
.ops = &clk_regmap_mux_ops,
1296
-
.parent_hws = axg_vpu_parent_hws,
1297
-
.num_parents = ARRAY_SIZE(axg_vpu_parent_hws),
1295
+
.parent_hws = axg_vpu_parents,
1296
+
.num_parents = ARRAY_SIZE(axg_vpu_parents),
1298
1297
.flags = CLK_SET_RATE_NO_REPARENT,
1299
1298
},
1300
1299
};
···
1366
1365
1367
1366
/* Video Clocks */
1368
1367
1369
-
static const struct clk_hw *axg_vclk_parent_hws[] = {
1368
+
static const struct clk_hw *axg_vclk_parents[] = {
1370
1369
&axg_gp0_pll.hw,
1371
1370
&axg_fclk_div4.hw,
1372
1371
&axg_fclk_div3.hw,
···
1385
1384
.hw.init = &(struct clk_init_data){
1386
1385
.name = "vclk_sel",
1387
1386
.ops = &clk_regmap_mux_ops,
1388
-
.parent_hws = axg_vclk_parent_hws,
1389
-
.num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1387
+
.parent_hws = axg_vclk_parents,
1388
+
.num_parents = ARRAY_SIZE(axg_vclk_parents),
1390
1389
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1391
1390
},
1392
1391
};
···
1400
1399
.hw.init = &(struct clk_init_data){
1401
1400
.name = "vclk2_sel",
1402
1401
.ops = &clk_regmap_mux_ops,
1403
-
.parent_hws = axg_vclk_parent_hws,
1404
-
.num_parents = ARRAY_SIZE(axg_vclk_parent_hws),
1402
+
.parent_hws = axg_vclk_parents,
1403
+
.num_parents = ARRAY_SIZE(axg_vclk_parents),
1405
1404
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1406
1405
},
1407
1406
};
···
1740
1739
},
1741
1740
};
1742
1741
1743
-
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1744
-
static const struct clk_hw *axg_cts_parent_hws[] = {
1742
+
static u32 axg_cts_encl_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1743
+
static const struct clk_hw *axg_cts_encl_parents[] = {
1745
1744
&axg_vclk_div1.hw,
1746
1745
&axg_vclk_div2.hw,
1747
1746
&axg_vclk_div4.hw,
···
1759
1758
.offset = HHI_VIID_CLK_DIV,
1760
1759
.mask = 0xf,
1761
1760
.shift = 12,
1762
-
.table = mux_table_cts_sel,
1761
+
.table = axg_cts_encl_parents_val_table,
1763
1762
},
1764
1763
.hw.init = &(struct clk_init_data){
1765
1764
.name = "cts_encl_sel",
1766
1765
.ops = &clk_regmap_mux_ops,
1767
-
.parent_hws = axg_cts_parent_hws,
1768
-
.num_parents = ARRAY_SIZE(axg_cts_parent_hws),
1766
+
.parent_hws = axg_cts_encl_parents,
1767
+
.num_parents = ARRAY_SIZE(axg_cts_encl_parents),
1769
1768
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1770
1769
},
1771
1770
};
···
1788
1787
1789
1788
/* MIPI DSI Host Clock */
1790
1789
1791
-
static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
1792
-
static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
1790
+
static u32 axg_vdin_meas_parents_val_table[] = { 0, 1, 2, 3, 6, 7 };
1791
+
static const struct clk_parent_data axg_vdin_meas_parents[] = {
1793
1792
{ .fw_name = "xtal", },
1794
1793
{ .hw = &axg_fclk_div4.hw },
1795
1794
{ .hw = &axg_fclk_div3.hw },
···
1804
1803
.mask = 0x7,
1805
1804
.shift = 21,
1806
1805
.flags = CLK_MUX_ROUND_CLOSEST,
1807
-
.table = mux_table_axg_vdin_meas,
1806
+
.table = axg_vdin_meas_parents_val_table,
1808
1807
},
1809
1808
.hw.init = &(struct clk_init_data){
1810
1809
.name = "vdin_meas_sel",
1811
1810
.ops = &clk_regmap_mux_ops,
1812
-
.parent_data = axg_vdin_meas_parent_data,
1813
-
.num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
1811
+
.parent_data = axg_vdin_meas_parents,
1812
+
.num_parents = ARRAY_SIZE(axg_vdin_meas_parents),
1814
1813
.flags = CLK_SET_RATE_PARENT,
1815
1814
},
1816
1815
};
···
1846
1845
},
1847
1846
};
1848
1847
1849
-
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
1850
-
9, 10, 11, 13, 14, };
1851
-
static const struct clk_parent_data gen_clk_parent_data[] = {
1848
+
static u32 gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, };
1849
+
static const struct clk_parent_data gen_clk_parents[] = {
1852
1850
{ .fw_name = "xtal", },
1853
1851
{ .hw = &axg_hifi_pll.hw },
1854
1852
{ .hw = &axg_mpll0.hw },
···
1866
1866
.offset = HHI_GEN_CLK_CNTL,
1867
1867
.mask = 0xf,
1868
1868
.shift = 12,
1869
-
.table = mux_table_gen_clk,
1869
+
.table = gen_clk_parents_val_table,
1870
1870
},
1871
1871
.hw.init = &(struct clk_init_data){
1872
1872
.name = "gen_clk_sel",
···
1877
1877
* hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
1878
1878
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1879
1879
*/
1880
-
.parent_data = gen_clk_parent_data,
1881
-
.num_parents = ARRAY_SIZE(gen_clk_parent_data),
1880
+
.parent_data = gen_clk_parents,
1881
+
.num_parents = ARRAY_SIZE(gen_clk_parents),
1882
1882
},
1883
1883
};
1884
1884
···
1915
1915
},
1916
1916
};
1917
1917
1918
-
#define MESON_GATE(_name, _reg, _bit) \
1919
-
MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
1918
+
static const struct clk_parent_data axg_pclk_parents = { .hw = &axg_clk81.hw };
1920
1919
1921
-
/* Everything Else (EE) domain gates */
1922
-
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1923
-
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1924
-
static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1925
-
static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1926
-
static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1927
-
static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1928
-
static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1929
-
static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1930
-
static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1931
-
static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1932
-
static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1933
-
static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1934
-
static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1935
-
static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1936
-
static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1937
-
static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1938
-
static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1939
-
static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1940
-
static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1941
-
static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1920
+
#define AXG_PCLK(_name, _reg, _bit, _flags) \
1921
+
MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags)
1942
1922
1943
-
static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1944
-
static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1945
-
static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1946
-
static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1947
-
static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1948
-
static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1949
-
static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1950
-
static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1951
-
static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1952
-
static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1953
-
static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1923
+
/*
1924
+
* Everything Else (EE) domain gates
1925
+
*
1926
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
1927
+
* Users are encouraged to test without it and submit changes to:
1928
+
* - remove the flag if not necessary
1929
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
1930
+
* if appropriate.
1931
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
1932
+
* for a particular clock.
1933
+
*/
1934
+
static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED);
1935
+
static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED);
1936
+
static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSED);
1937
+
static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED);
1938
+
static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED);
1939
+
static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED);
1940
+
static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED);
1941
+
static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED);
1942
+
static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED);
1943
+
static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED);
1944
+
static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED);
1945
+
static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED);
1946
+
static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED);
1947
+
static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED);
1948
+
static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED);
1949
+
static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED);
1950
+
static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED);
1951
+
static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED);
1952
+
static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27, CLK_IGNORE_UNUSED);
1953
+
static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED);
1954
1954
1955
-
static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1956
-
static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1957
-
static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1958
-
static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1959
-
static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1960
-
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1961
-
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1962
-
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1955
+
static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED);
1956
+
static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED);
1957
+
static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED);
1958
+
static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED);
1959
+
static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED);
1960
+
static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED);
1961
+
static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED);
1962
+
static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED);
1963
+
static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED);
1964
+
static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED);
1965
+
static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED);
1966
+
1967
+
static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED);
1968
+
static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED);
1969
+
static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED);
1970
+
static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED);
1971
+
static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED);
1972
+
static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED);
1973
+
static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED);
1974
+
static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED);
1963
1975
1964
1976
/* Always On (AO) domain gates */
1965
1977
1966
-
static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1967
-
static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1968
-
static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1969
-
static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1970
-
static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1978
+
static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED);
1979
+
static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED);
1980
+
static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED);
1981
+
static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED);
1982
+
static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED);
1971
1983
1972
1984
/* Array of all clocks provided by this provider */
1973
1985
···
1992
1980
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1993
1981
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1994
1982
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1995
-
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1996
-
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1983
+
[CLKID_MPEG_SEL] = &axg_clk81_sel.hw,
1984
+
[CLKID_MPEG_DIV] = &axg_clk81_div.hw,
1997
1985
[CLKID_CLK81] = &axg_clk81.hw,
1998
1986
[CLKID_MPLL0] = &axg_mpll0.hw,
1999
1987
[CLKID_MPLL1] = &axg_mpll1.hw,
···
2122
2110
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
2123
2111
};
2124
2112
2125
-
static const struct meson_eeclkc_data axg_clkc_data = {
2113
+
static const struct meson_clkc_data axg_clkc_data = {
2126
2114
.hw_clks = {
2127
2115
.hws = axg_hw_clks,
2128
2116
.num = ARRAY_SIZE(axg_hw_clks),
2129
2117
},
2130
2118
};
2131
2119
2132
-
2133
-
static const struct of_device_id clkc_match_table[] = {
2120
+
static const struct of_device_id axg_clkc_match_table[] = {
2134
2121
{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2135
2122
{}
2136
2123
};
2137
-
MODULE_DEVICE_TABLE(of, clkc_match_table);
2124
+
MODULE_DEVICE_TABLE(of, axg_clkc_match_table);
2138
2125
2139
-
static struct platform_driver axg_driver = {
2140
-
.probe = meson_eeclkc_probe,
2126
+
static struct platform_driver axg_clkc_driver = {
2127
+
.probe = meson_clkc_syscon_probe,
2141
2128
.driver = {
2142
2129
.name = "axg-clkc",
2143
-
.of_match_table = clkc_match_table,
2130
+
.of_match_table = axg_clkc_match_table,
2144
2131
},
2145
2132
};
2146
-
module_platform_driver(axg_driver);
2133
+
module_platform_driver(axg_clkc_driver);
2147
2134
2148
2135
MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver");
2149
2136
MODULE_LICENSE("GPL");
+485
-1516
drivers/clk/meson/c3-peripherals.c
+485
-1516
drivers/clk/meson/c3-peripherals.c
···
48
48
#define SPIFC_CLK_CTRL 0x1a0
49
49
#define NNA_CLK_CTRL 0x220
50
50
51
-
static struct clk_regmap rtc_xtal_clkin = {
51
+
#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
52
+
MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
53
+
54
+
#define C3_COMP_DIV(_name, _reg, _shift, _width) \
55
+
MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
56
+
57
+
#define C3_COMP_GATE(_name, _reg, _bit) \
58
+
MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
59
+
60
+
static struct clk_regmap c3_rtc_xtal_clkin = {
52
61
.data = &(struct clk_regmap_gate_data) {
53
62
.offset = RTC_BY_OSCIN_CTRL0,
54
63
.bit_idx = 31,
···
72
63
},
73
64
};
74
65
75
-
static const struct meson_clk_dualdiv_param rtc_32k_div_table[] = {
66
+
static const struct meson_clk_dualdiv_param c3_rtc_32k_div_table[] = {
76
67
{ 733, 732, 8, 11, 1 },
77
68
{ /* sentinel */ }
78
69
};
79
70
80
-
static struct clk_regmap rtc_32k_div = {
71
+
static struct clk_regmap c3_rtc_32k_div = {
81
72
.data = &(struct meson_clk_dualdiv_data) {
82
73
.n1 = {
83
74
.reg_off = RTC_BY_OSCIN_CTRL0,
···
104
95
.shift = 28,
105
96
.width = 1,
106
97
},
107
-
.table = rtc_32k_div_table,
98
+
.table = c3_rtc_32k_div_table,
108
99
},
109
100
.hw.init = &(struct clk_init_data) {
110
101
.name = "rtc_32k_div",
111
102
.ops = &meson_clk_dualdiv_ops,
112
103
.parent_hws = (const struct clk_hw *[]) {
113
-
&rtc_xtal_clkin.hw
104
+
&c3_rtc_xtal_clkin.hw
114
105
},
115
106
.num_parents = 1,
116
107
},
117
108
};
118
109
119
-
static const struct clk_parent_data rtc_32k_mux_parent_data[] = {
120
-
{ .hw = &rtc_32k_div.hw },
121
-
{ .hw = &rtc_xtal_clkin.hw }
110
+
static const struct clk_parent_data c3_rtc_32k_parents[] = {
111
+
{ .hw = &c3_rtc_32k_div.hw },
112
+
{ .hw = &c3_rtc_xtal_clkin.hw }
122
113
};
123
114
124
-
static struct clk_regmap rtc_32k_mux = {
115
+
static struct clk_regmap c3_rtc_32k_sel = {
125
116
.data = &(struct clk_regmap_mux_data) {
126
117
.offset = RTC_BY_OSCIN_CTRL1,
127
118
.mask = 0x1,
128
119
.shift = 24,
129
120
},
130
121
.hw.init = &(struct clk_init_data) {
131
-
.name = "rtc_32k_mux",
122
+
.name = "rtc_32k_sel",
132
123
.ops = &clk_regmap_mux_ops,
133
-
.parent_data = rtc_32k_mux_parent_data,
134
-
.num_parents = ARRAY_SIZE(rtc_32k_mux_parent_data),
124
+
.parent_data = c3_rtc_32k_parents,
125
+
.num_parents = ARRAY_SIZE(c3_rtc_32k_parents),
135
126
.flags = CLK_SET_RATE_PARENT,
136
127
},
137
128
};
138
129
139
-
static struct clk_regmap rtc_32k = {
130
+
static struct clk_regmap c3_rtc_32k = {
140
131
.data = &(struct clk_regmap_gate_data) {
141
132
.offset = RTC_BY_OSCIN_CTRL0,
142
133
.bit_idx = 30,
···
145
136
.name = "rtc_32k",
146
137
.ops = &clk_regmap_gate_ops,
147
138
.parent_hws = (const struct clk_hw *[]) {
148
-
&rtc_32k_mux.hw
139
+
&c3_rtc_32k_sel.hw
149
140
},
150
141
.num_parents = 1,
151
142
.flags = CLK_SET_RATE_PARENT,
152
143
},
153
144
};
154
145
155
-
static const struct clk_parent_data rtc_clk_mux_parent_data[] = {
146
+
static const struct clk_parent_data c3_rtc_clk_parents[] = {
156
147
{ .fw_name = "oscin" },
157
-
{ .hw = &rtc_32k.hw },
148
+
{ .hw = &c3_rtc_32k.hw },
158
149
{ .fw_name = "pad_osc" }
159
150
};
160
151
161
-
static struct clk_regmap rtc_clk = {
152
+
static struct clk_regmap c3_rtc_clk = {
162
153
.data = &(struct clk_regmap_mux_data) {
163
154
.offset = RTC_CTRL,
164
155
.mask = 0x3,
···
167
158
.hw.init = &(struct clk_init_data) {
168
159
.name = "rtc_clk",
169
160
.ops = &clk_regmap_mux_ops,
170
-
.parent_data = rtc_clk_mux_parent_data,
171
-
.num_parents = ARRAY_SIZE(rtc_clk_mux_parent_data),
161
+
.parent_data = c3_rtc_clk_parents,
162
+
.num_parents = ARRAY_SIZE(c3_rtc_clk_parents),
172
163
.flags = CLK_SET_RATE_PARENT,
173
164
},
174
165
};
175
166
176
-
#define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \
177
-
struct clk_regmap _name = { \
178
-
.data = &(struct clk_regmap_gate_data){ \
179
-
.offset = (_reg), \
180
-
.bit_idx = (_bit), \
181
-
}, \
182
-
.hw.init = &(struct clk_init_data) { \
183
-
.name = #_name, \
184
-
.ops = _ops, \
185
-
.parent_data = &(const struct clk_parent_data) { \
186
-
.fw_name = #_fw_name, \
187
-
}, \
188
-
.num_parents = 1, \
189
-
.flags = (_flags), \
190
-
}, \
191
-
}
167
+
static const struct clk_parent_data c3_sys_pclk_parents = { .fw_name = "sysclk" };
192
168
193
-
#define C3_SYS_GATE(_name, _reg, _bit, _flags) \
194
-
C3_CLK_GATE(_name, _reg, _bit, sysclk, \
195
-
&clk_regmap_gate_ops, _flags)
169
+
#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \
170
+
MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags)
196
171
197
-
#define C3_SYS_GATE_RO(_name, _reg, _bit) \
198
-
C3_CLK_GATE(_name, _reg, _bit, sysclk, \
199
-
&clk_regmap_gate_ro_ops, 0)
172
+
#define C3_SYS_PCLK_RO(_name, _reg, _bit) \
173
+
MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0)
200
174
201
-
static C3_SYS_GATE(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
202
-
static C3_SYS_GATE(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
203
-
static C3_SYS_GATE(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);
204
-
static C3_SYS_GATE(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);
205
-
static C3_SYS_GATE(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);
175
+
static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
176
+
static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
177
+
static C3_SYS_PCLK(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);
178
+
static C3_SYS_PCLK(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);
179
+
static C3_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);
206
180
207
181
/*
208
182
* NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that
209
183
* access the AXI bus.
210
184
*/
211
-
static C3_SYS_GATE(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);
185
+
static C3_SYS_PCLK(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);
212
186
213
187
/*
214
188
* FIXME: sys_mmc_pclk provides the clock for the DDR PHY, DDR will only be
215
189
* initialized in bl2, and this clock should not be touched in linux.
216
190
*/
217
-
static C3_SYS_GATE_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8);
191
+
static C3_SYS_PCLK_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8);
218
192
219
193
/*
220
194
* NOTE: sys_cpu_ctrl provides the clock for CPU controller. After clock is
221
195
* disabled, cpu_clk and other key CPU-related configurations cannot take effect.
222
196
*/
223
-
static C3_SYS_GATE(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL);
224
-
static C3_SYS_GATE(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);
225
-
static C3_SYS_GATE(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);
197
+
static C3_SYS_PCLK(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL);
198
+
static C3_SYS_PCLK(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);
199
+
static C3_SYS_PCLK(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);
226
200
227
201
/*
228
202
* NOTE: sys_irq_ctrl provides the clock for IRQ controller. The IRQ controller
···
213
221
* AOCPU. If the clock is disabled, interrupt-related functions will occurs an
214
222
* exception.
215
223
*/
216
-
static C3_SYS_GATE(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL);
217
-
static C3_SYS_GATE(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);
218
-
static C3_SYS_GATE(sys_rom, SYS_CLK_EN0_REG0, 16, 0);
219
-
static C3_SYS_GATE(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0);
220
-
static C3_SYS_GATE(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);
221
-
static C3_SYS_GATE(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);
222
-
static C3_SYS_GATE(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0);
223
-
static C3_SYS_GATE(sys_startup, SYS_CLK_EN0_REG0, 21, 0);
224
-
static C3_SYS_GATE(sys_secure, SYS_CLK_EN0_REG0, 22, 0);
225
-
static C3_SYS_GATE(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);
226
-
static C3_SYS_GATE(sys_nna, SYS_CLK_EN0_REG0, 25, 0);
227
-
static C3_SYS_GATE(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);
224
+
static C3_SYS_PCLK(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL);
225
+
static C3_SYS_PCLK(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);
226
+
static C3_SYS_PCLK(sys_rom, SYS_CLK_EN0_REG0, 16, 0);
227
+
static C3_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0);
228
+
static C3_SYS_PCLK(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);
229
+
static C3_SYS_PCLK(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);
230
+
static C3_SYS_PCLK(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0);
231
+
static C3_SYS_PCLK(sys_startup, SYS_CLK_EN0_REG0, 21, 0);
232
+
static C3_SYS_PCLK(sys_secure, SYS_CLK_EN0_REG0, 22, 0);
233
+
static C3_SYS_PCLK(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);
234
+
static C3_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 25, 0);
235
+
static C3_SYS_PCLK(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);
228
236
229
237
/*
230
238
* FIXME: sys_gic provides the clock for GIC(Generic Interrupt Controller).
···
232
240
* used by our GIC is the public driver in kernel, and there is no management
233
241
* clock in the driver.
234
242
*/
235
-
static C3_SYS_GATE(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL);
236
-
static C3_SYS_GATE(sys_rama, SYS_CLK_EN0_REG0, 28, 0);
243
+
static C3_SYS_PCLK(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL);
244
+
static C3_SYS_PCLK(sys_rama, SYS_CLK_EN0_REG0, 28, 0);
237
245
238
246
/*
239
247
* NOTE: sys_big_nic provides the clock to the control bus of the NIC(Network
···
241
249
* SPIFC, CAPU, JTAG, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) in the
242
250
* system. After clock is disabled, The NIC cannot work.
243
251
*/
244
-
static C3_SYS_GATE(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL);
245
-
static C3_SYS_GATE(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);
246
-
static C3_SYS_GATE(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0);
247
-
static C3_SYS_GATE(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0);
248
-
static C3_SYS_GATE(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0);
249
-
static C3_SYS_GATE(sys_usb, SYS_CLK_EN0_REG1, 2, 0);
250
-
static C3_SYS_GATE(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);
251
-
static C3_SYS_GATE(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);
252
-
static C3_SYS_GATE(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);
253
-
static C3_SYS_GATE(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);
254
-
static C3_SYS_GATE(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);
255
-
static C3_SYS_GATE(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);
256
-
static C3_SYS_GATE(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);
257
-
static C3_SYS_GATE(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);
258
-
static C3_SYS_GATE(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);
259
-
static C3_SYS_GATE(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);
260
-
static C3_SYS_GATE(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);
261
-
static C3_SYS_GATE(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);
262
-
static C3_SYS_GATE(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);
263
-
static C3_SYS_GATE(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);
264
-
static C3_SYS_GATE(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);
265
-
static C3_SYS_GATE(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);
266
-
static C3_SYS_GATE(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);
267
-
static C3_SYS_GATE(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0);
268
-
static C3_SYS_GATE(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);
269
-
static C3_SYS_GATE(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0);
270
-
static C3_SYS_GATE(sys_isp, SYS_CLK_EN0_REG1, 23, 0);
271
-
static C3_SYS_GATE(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0);
272
-
static C3_SYS_GATE(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0);
273
-
static C3_SYS_GATE(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0);
274
-
static C3_SYS_GATE(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0);
275
-
static C3_SYS_GATE(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0);
276
-
static C3_SYS_GATE(sys_acodec, SYS_CLK_EN0_REG1, 29, 0);
277
-
static C3_SYS_GATE(sys_dwap, SYS_CLK_EN0_REG1, 30, 0);
278
-
static C3_SYS_GATE(sys_dos, SYS_CLK_EN0_REG1, 31, 0);
279
-
static C3_SYS_GATE(sys_cve, SYS_CLK_EN0_REG2, 0, 0);
280
-
static C3_SYS_GATE(sys_vout, SYS_CLK_EN0_REG2, 1, 0);
281
-
static C3_SYS_GATE(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);
282
-
static C3_SYS_GATE(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);
283
-
static C3_SYS_GATE(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);
252
+
static C3_SYS_PCLK(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL);
253
+
static C3_SYS_PCLK(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);
254
+
static C3_SYS_PCLK(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0);
255
+
static C3_SYS_PCLK(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0);
256
+
static C3_SYS_PCLK(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0);
257
+
static C3_SYS_PCLK(sys_usb, SYS_CLK_EN0_REG1, 2, 0);
258
+
static C3_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);
259
+
static C3_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);
260
+
static C3_SYS_PCLK(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);
261
+
static C3_SYS_PCLK(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);
262
+
static C3_SYS_PCLK(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);
263
+
static C3_SYS_PCLK(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);
264
+
static C3_SYS_PCLK(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);
265
+
static C3_SYS_PCLK(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);
266
+
static C3_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);
267
+
static C3_SYS_PCLK(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);
268
+
static C3_SYS_PCLK(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);
269
+
static C3_SYS_PCLK(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);
270
+
static C3_SYS_PCLK(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);
271
+
static C3_SYS_PCLK(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);
272
+
static C3_SYS_PCLK(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);
273
+
static C3_SYS_PCLK(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);
274
+
static C3_SYS_PCLK(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);
275
+
static C3_SYS_PCLK(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0);
276
+
static C3_SYS_PCLK(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);
277
+
static C3_SYS_PCLK(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0);
278
+
static C3_SYS_PCLK(sys_isp, SYS_CLK_EN0_REG1, 23, 0);
279
+
static C3_SYS_PCLK(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0);
280
+
static C3_SYS_PCLK(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0);
281
+
static C3_SYS_PCLK(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0);
282
+
static C3_SYS_PCLK(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0);
283
+
static C3_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0);
284
+
static C3_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG1, 29, 0);
285
+
static C3_SYS_PCLK(sys_dwap, SYS_CLK_EN0_REG1, 30, 0);
286
+
static C3_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG1, 31, 0);
287
+
static C3_SYS_PCLK(sys_cve, SYS_CLK_EN0_REG2, 0, 0);
288
+
static C3_SYS_PCLK(sys_vout, SYS_CLK_EN0_REG2, 1, 0);
289
+
static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);
290
+
static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);
291
+
static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);
284
292
285
-
#define C3_AXI_GATE(_name, _reg, _bit, _flags) \
286
-
C3_CLK_GATE(_name, _reg, _bit, axiclk, \
287
-
&clk_regmap_gate_ops, _flags)
293
+
static const struct clk_parent_data c3_axi_pclk_parents = { .fw_name = "axiclk" };
294
+
295
+
#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \
296
+
MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags)
288
297
289
298
/*
290
299
* NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. After
291
300
* clock is disabled, The NIC cannot work.
292
301
*/
293
-
static C3_AXI_GATE(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL);
294
-
static C3_AXI_GATE(axi_isp_nic, AXI_CLK_EN0, 3, 0);
295
-
static C3_AXI_GATE(axi_cve_nic, AXI_CLK_EN0, 4, 0);
296
-
static C3_AXI_GATE(axi_ramb, AXI_CLK_EN0, 5, 0);
297
-
static C3_AXI_GATE(axi_rama, AXI_CLK_EN0, 6, 0);
302
+
static C3_AXI_PCLK(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL);
303
+
static C3_AXI_PCLK(axi_isp_nic, AXI_CLK_EN0, 3, 0);
304
+
static C3_AXI_PCLK(axi_cve_nic, AXI_CLK_EN0, 4, 0);
305
+
static C3_AXI_PCLK(axi_ramb, AXI_CLK_EN0, 5, 0);
306
+
static C3_AXI_PCLK(axi_rama, AXI_CLK_EN0, 6, 0);
298
307
299
308
/*
300
309
* NOTE: axi_cpu_dmc provides the clock to the AXI bus where the CPU accesses
301
310
* the DDR. After clock is disabled, The CPU will not have access to the DDR.
302
311
*/
303
-
static C3_AXI_GATE(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL);
304
-
static C3_AXI_GATE(axi_nic, AXI_CLK_EN0, 8, 0);
305
-
static C3_AXI_GATE(axi_dma, AXI_CLK_EN0, 9, 0);
312
+
static C3_AXI_PCLK(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL);
313
+
static C3_AXI_PCLK(axi_nic, AXI_CLK_EN0, 8, 0);
314
+
static C3_AXI_PCLK(axi_dma, AXI_CLK_EN0, 9, 0);
306
315
307
316
/*
308
317
* NOTE: axi_mux_nic provides the clock to the NIC's AXI bus for NN(Neural
309
318
* Network) and other devices(CPU, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC)
310
319
* to access RAM space.
311
320
*/
312
-
static C3_AXI_GATE(axi_mux_nic, AXI_CLK_EN0, 10, 0);
313
-
static C3_AXI_GATE(axi_cve, AXI_CLK_EN0, 12, 0);
321
+
static C3_AXI_PCLK(axi_mux_nic, AXI_CLK_EN0, 10, 0);
322
+
static C3_AXI_PCLK(axi_cve, AXI_CLK_EN0, 12, 0);
314
323
315
324
/*
316
325
* NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO,
317
326
* sec_top, USB, Audio, ETH, SPICC) to access the AXI bus of the DDR.
318
327
*/
319
-
static C3_AXI_GATE(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);
320
-
static C3_AXI_GATE(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);
321
-
static C3_AXI_GATE(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);
328
+
static C3_AXI_PCLK(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);
329
+
static C3_AXI_PCLK(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);
330
+
static C3_AXI_PCLK(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);
322
331
323
332
/*
324
333
* clk_12_24m model
···
328
335
* xtal---->| gate |---->| div |------------>| pad |
329
336
* |------| |-----| |-----|
330
337
*/
331
-
static struct clk_regmap clk_12_24m_in = {
338
+
static struct clk_regmap c3_clk_12_24m_in = {
332
339
.data = &(struct clk_regmap_gate_data) {
333
340
.offset = CLK12_24_CTRL,
334
341
.bit_idx = 11,
···
343
350
},
344
351
};
345
352
346
-
static struct clk_regmap clk_12_24m = {
353
+
static struct clk_regmap c3_clk_12_24m = {
347
354
.data = &(struct clk_regmap_div_data) {
348
355
.offset = CLK12_24_CTRL,
349
356
.shift = 10,
···
353
360
.name = "clk_12_24m",
354
361
.ops = &clk_regmap_divider_ops,
355
362
.parent_hws = (const struct clk_hw *[]) {
356
-
&clk_12_24m_in.hw
363
+
&c3_clk_12_24m_in.hw
357
364
},
358
365
.num_parents = 1,
359
366
},
360
367
};
361
368
362
369
/* Fix me: set value 0 will div by 2 like value 1 */
363
-
static struct clk_regmap fclk_25m_div = {
370
+
static struct clk_regmap c3_fclk_25m_div = {
364
371
.data = &(struct clk_regmap_div_data) {
365
372
.offset = CLK12_24_CTRL,
366
373
.shift = 0,
···
376
383
},
377
384
};
378
385
379
-
static struct clk_regmap fclk_25m = {
386
+
static struct clk_regmap c3_fclk_25m = {
380
387
.data = &(struct clk_regmap_gate_data) {
381
388
.offset = CLK12_24_CTRL,
382
389
.bit_idx = 12,
···
385
392
.name = "fclk_25m",
386
393
.ops = &clk_regmap_gate_ops,
387
394
.parent_hws = (const struct clk_hw *[]) {
388
-
&fclk_25m_div.hw
395
+
&c3_fclk_25m_div.hw
389
396
},
390
397
.num_parents = 1,
391
398
.flags = CLK_SET_RATE_PARENT,
···
397
404
* is manged by clock measures module. Their hardware are out of clock tree.
398
405
* Channel 4 8 9 10 11 13 14 15 16 18 are not connected.
399
406
*/
400
-
static u32 gen_parent_table[] = { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, 23, 24};
401
-
402
-
static const struct clk_parent_data gen_parent_data[] = {
407
+
static u32 c3_gen_parents_val_table[] = { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, 23, 24};
408
+
static const struct clk_parent_data c3_gen_parents[] = {
403
409
{ .fw_name = "oscin" },
404
-
{ .hw = &rtc_clk.hw },
410
+
{ .hw = &c3_rtc_clk.hw },
405
411
{ .fw_name = "sysplldiv16" },
406
412
{ .fw_name = "gp0" },
407
413
{ .fw_name = "gp1" },
···
414
422
{ .fw_name = "fdiv7" }
415
423
};
416
424
417
-
static struct clk_regmap gen_sel = {
425
+
static struct clk_regmap c3_gen_sel = {
418
426
.data = &(struct clk_regmap_mux_data) {
419
427
.offset = GEN_CLK_CTRL,
420
428
.mask = 0x1f,
421
429
.shift = 12,
422
-
.table = gen_parent_table,
430
+
.table = c3_gen_parents_val_table,
423
431
},
424
432
.hw.init = &(struct clk_init_data) {
425
433
.name = "gen_sel",
426
434
.ops = &clk_regmap_mux_ops,
427
-
.parent_data = gen_parent_data,
428
-
.num_parents = ARRAY_SIZE(gen_parent_data),
435
+
.parent_data = c3_gen_parents,
436
+
.num_parents = ARRAY_SIZE(c3_gen_parents),
429
437
},
430
438
};
431
439
432
-
static struct clk_regmap gen_div = {
440
+
static struct clk_regmap c3_gen_div = {
433
441
.data = &(struct clk_regmap_div_data) {
434
442
.offset = GEN_CLK_CTRL,
435
443
.shift = 0,
···
439
447
.name = "gen_div",
440
448
.ops = &clk_regmap_divider_ops,
441
449
.parent_hws = (const struct clk_hw *[]) {
442
-
&gen_sel.hw
450
+
&c3_gen_sel.hw
443
451
},
444
452
.num_parents = 1,
445
453
.flags = CLK_SET_RATE_PARENT,
446
454
},
447
455
};
448
456
449
-
static struct clk_regmap gen = {
457
+
static struct clk_regmap c3_gen = {
450
458
.data = &(struct clk_regmap_gate_data) {
451
459
.offset = GEN_CLK_CTRL,
452
460
.bit_idx = 11,
···
455
463
.name = "gen",
456
464
.ops = &clk_regmap_gate_ops,
457
465
.parent_hws = (const struct clk_hw *[]) {
458
-
&gen_div.hw
466
+
&c3_gen_div.hw
459
467
},
460
468
.num_parents = 1,
461
469
.flags = CLK_SET_RATE_PARENT,
462
470
},
463
471
};
464
472
465
-
static const struct clk_parent_data saradc_parent_data[] = {
473
+
static const struct clk_parent_data c3_saradc_parents[] = {
466
474
{ .fw_name = "oscin" },
467
475
{ .fw_name = "sysclk" }
468
476
};
469
477
470
-
static struct clk_regmap saradc_sel = {
471
-
.data = &(struct clk_regmap_mux_data) {
472
-
.offset = SAR_CLK_CTRL0,
473
-
.mask = 0x1,
474
-
.shift = 9,
475
-
},
476
-
.hw.init = &(struct clk_init_data) {
477
-
.name = "saradc_sel",
478
-
.ops = &clk_regmap_mux_ops,
479
-
.parent_data = saradc_parent_data,
480
-
.num_parents = ARRAY_SIZE(saradc_parent_data),
481
-
},
482
-
};
478
+
static C3_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, c3_saradc_parents);
479
+
static C3_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
480
+
static C3_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
483
481
484
-
static struct clk_regmap saradc_div = {
485
-
.data = &(struct clk_regmap_div_data) {
486
-
.offset = SAR_CLK_CTRL0,
487
-
.shift = 0,
488
-
.width = 8,
489
-
},
490
-
.hw.init = &(struct clk_init_data) {
491
-
.name = "saradc_div",
492
-
.ops = &clk_regmap_divider_ops,
493
-
.parent_hws = (const struct clk_hw *[]) {
494
-
&saradc_sel.hw
495
-
},
496
-
.num_parents = 1,
497
-
.flags = CLK_SET_RATE_PARENT,
498
-
},
499
-
};
500
-
501
-
static struct clk_regmap saradc = {
502
-
.data = &(struct clk_regmap_gate_data) {
503
-
.offset = SAR_CLK_CTRL0,
504
-
.bit_idx = 8,
505
-
},
506
-
.hw.init = &(struct clk_init_data) {
507
-
.name = "saradc",
508
-
.ops = &clk_regmap_gate_ops,
509
-
.parent_hws = (const struct clk_hw *[]) {
510
-
&saradc_div.hw
511
-
},
512
-
.num_parents = 1,
513
-
.flags = CLK_SET_RATE_PARENT,
514
-
},
515
-
};
516
-
517
-
static const struct clk_parent_data pwm_parent_data[] = {
482
+
static const struct clk_parent_data c3_pwm_parents[] = {
518
483
{ .fw_name = "oscin" },
519
484
{ .fw_name = "gp1" },
520
485
{ .fw_name = "fdiv4" },
521
486
{ .fw_name = "fdiv3" }
522
487
};
523
488
524
-
#define AML_PWM_CLK_MUX(_name, _reg, _shift) { \
525
-
.data = &(struct clk_regmap_mux_data) { \
526
-
.offset = _reg, \
527
-
.mask = 0x3, \
528
-
.shift = _shift, \
529
-
}, \
530
-
.hw.init = &(struct clk_init_data) { \
531
-
.name = #_name "_sel", \
532
-
.ops = &clk_regmap_mux_ops, \
533
-
.parent_data = pwm_parent_data, \
534
-
.num_parents = ARRAY_SIZE(pwm_parent_data), \
535
-
}, \
536
-
}
489
+
static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents);
490
+
static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
491
+
static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
537
492
538
-
#define AML_PWM_CLK_DIV(_name, _reg, _shift) { \
539
-
.data = &(struct clk_regmap_div_data) { \
540
-
.offset = _reg, \
541
-
.shift = _shift, \
542
-
.width = 8, \
543
-
}, \
544
-
.hw.init = &(struct clk_init_data) { \
545
-
.name = #_name "_div", \
546
-
.ops = &clk_regmap_divider_ops, \
547
-
.parent_names = (const char *[]) { #_name "_sel" },\
548
-
.num_parents = 1, \
549
-
.flags = CLK_SET_RATE_PARENT, \
550
-
}, \
551
-
}
493
+
static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents);
494
+
static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
495
+
static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
552
496
553
-
#define AML_PWM_CLK_GATE(_name, _reg, _bit) { \
554
-
.data = &(struct clk_regmap_gate_data) { \
555
-
.offset = _reg, \
556
-
.bit_idx = _bit, \
557
-
}, \
558
-
.hw.init = &(struct clk_init_data) { \
559
-
.name = #_name, \
560
-
.ops = &clk_regmap_gate_ops, \
561
-
.parent_names = (const char *[]) { #_name "_div" },\
562
-
.num_parents = 1, \
563
-
.flags = CLK_SET_RATE_PARENT, \
564
-
}, \
565
-
}
497
+
static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents);
498
+
static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
499
+
static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
566
500
567
-
static struct clk_regmap pwm_a_sel =
568
-
AML_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9);
569
-
static struct clk_regmap pwm_a_div =
570
-
AML_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0);
571
-
static struct clk_regmap pwm_a =
572
-
AML_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
501
+
static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents);
502
+
static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
503
+
static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
573
504
574
-
static struct clk_regmap pwm_b_sel =
575
-
AML_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25);
576
-
static struct clk_regmap pwm_b_div =
577
-
AML_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16);
578
-
static struct clk_regmap pwm_b =
579
-
AML_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
505
+
static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents);
506
+
static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
507
+
static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
580
508
581
-
static struct clk_regmap pwm_c_sel =
582
-
AML_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9);
583
-
static struct clk_regmap pwm_c_div =
584
-
AML_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0);
585
-
static struct clk_regmap pwm_c =
586
-
AML_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
509
+
static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents);
510
+
static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
511
+
static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
587
512
588
-
static struct clk_regmap pwm_d_sel =
589
-
AML_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25);
590
-
static struct clk_regmap pwm_d_div =
591
-
AML_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16);
592
-
static struct clk_regmap pwm_d =
593
-
AML_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
513
+
static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents);
514
+
static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8);
515
+
static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
594
516
595
-
static struct clk_regmap pwm_e_sel =
596
-
AML_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9);
597
-
static struct clk_regmap pwm_e_div =
598
-
AML_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0);
599
-
static struct clk_regmap pwm_e =
600
-
AML_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
517
+
static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents);
518
+
static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8);
519
+
static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
601
520
602
-
static struct clk_regmap pwm_f_sel =
603
-
AML_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25);
604
-
static struct clk_regmap pwm_f_div =
605
-
AML_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16);
606
-
static struct clk_regmap pwm_f =
607
-
AML_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
521
+
static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents);
522
+
static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8);
523
+
static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
608
524
609
-
static struct clk_regmap pwm_g_sel =
610
-
AML_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9);
611
-
static struct clk_regmap pwm_g_div =
612
-
AML_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0);
613
-
static struct clk_regmap pwm_g =
614
-
AML_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
525
+
static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents);
526
+
static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8);
527
+
static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
615
528
616
-
static struct clk_regmap pwm_h_sel =
617
-
AML_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25);
618
-
static struct clk_regmap pwm_h_div =
619
-
AML_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16);
620
-
static struct clk_regmap pwm_h =
621
-
AML_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
529
+
static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents);
530
+
static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8);
531
+
static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
622
532
623
-
static struct clk_regmap pwm_i_sel =
624
-
AML_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9);
625
-
static struct clk_regmap pwm_i_div =
626
-
AML_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0);
627
-
static struct clk_regmap pwm_i =
628
-
AML_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
533
+
static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents);
534
+
static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8);
535
+
static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
629
536
630
-
static struct clk_regmap pwm_j_sel =
631
-
AML_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25);
632
-
static struct clk_regmap pwm_j_div =
633
-
AML_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16);
634
-
static struct clk_regmap pwm_j =
635
-
AML_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
537
+
static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents);
538
+
static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8);
539
+
static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
636
540
637
-
static struct clk_regmap pwm_k_sel =
638
-
AML_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9);
639
-
static struct clk_regmap pwm_k_div =
640
-
AML_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0);
641
-
static struct clk_regmap pwm_k =
642
-
AML_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
541
+
static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents);
542
+
static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8);
543
+
static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
643
544
644
-
static struct clk_regmap pwm_l_sel =
645
-
AML_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25);
646
-
static struct clk_regmap pwm_l_div =
647
-
AML_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16);
648
-
static struct clk_regmap pwm_l =
649
-
AML_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
650
-
651
-
static struct clk_regmap pwm_m_sel =
652
-
AML_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9);
653
-
static struct clk_regmap pwm_m_div =
654
-
AML_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0);
655
-
static struct clk_regmap pwm_m =
656
-
AML_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
657
-
658
-
static struct clk_regmap pwm_n_sel =
659
-
AML_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25);
660
-
static struct clk_regmap pwm_n_div =
661
-
AML_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16);
662
-
static struct clk_regmap pwm_n =
663
-
AML_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
664
-
665
-
static const struct clk_parent_data spicc_parent_data[] = {
545
+
static const struct clk_parent_data c3_spicc_parents[] = {
666
546
{ .fw_name = "oscin" },
667
547
{ .fw_name = "sysclk" },
668
548
{ .fw_name = "fdiv4" },
···
545
681
{ .fw_name = "gp1" }
546
682
};
547
683
548
-
static struct clk_regmap spicc_a_sel = {
549
-
.data = &(struct clk_regmap_mux_data) {
550
-
.offset = SPICC_CLK_CTRL,
551
-
.mask = 0x7,
552
-
.shift = 7,
553
-
},
554
-
.hw.init = &(struct clk_init_data) {
555
-
.name = "spicc_a_sel",
556
-
.ops = &clk_regmap_mux_ops,
557
-
.parent_data = spicc_parent_data,
558
-
.num_parents = ARRAY_SIZE(spicc_parent_data),
559
-
},
560
-
};
684
+
static C3_COMP_SEL(spicc_a, SPICC_CLK_CTRL, 7, 0x7, c3_spicc_parents);
685
+
static C3_COMP_DIV(spicc_a, SPICC_CLK_CTRL, 0, 6);
686
+
static C3_COMP_GATE(spicc_a, SPICC_CLK_CTRL, 6);
561
687
562
-
static struct clk_regmap spicc_a_div = {
563
-
.data = &(struct clk_regmap_div_data) {
564
-
.offset = SPICC_CLK_CTRL,
565
-
.shift = 0,
566
-
.width = 6,
567
-
},
568
-
.hw.init = &(struct clk_init_data) {
569
-
.name = "spicc_a_div",
570
-
.ops = &clk_regmap_divider_ops,
571
-
.parent_hws = (const struct clk_hw *[]) {
572
-
&spicc_a_sel.hw
573
-
},
574
-
.num_parents = 1,
575
-
.flags = CLK_SET_RATE_PARENT,
576
-
},
577
-
};
688
+
static C3_COMP_SEL(spicc_b, SPICC_CLK_CTRL, 23, 0x7, c3_spicc_parents);
689
+
static C3_COMP_DIV(spicc_b, SPICC_CLK_CTRL, 16, 6);
690
+
static C3_COMP_GATE(spicc_b, SPICC_CLK_CTRL, 22);
578
691
579
-
static struct clk_regmap spicc_a = {
580
-
.data = &(struct clk_regmap_gate_data) {
581
-
.offset = SPICC_CLK_CTRL,
582
-
.bit_idx = 6,
583
-
},
584
-
.hw.init = &(struct clk_init_data) {
585
-
.name = "spicc_a",
586
-
.ops = &clk_regmap_gate_ops,
587
-
.parent_hws = (const struct clk_hw *[]) {
588
-
&spicc_a_div.hw
589
-
},
590
-
.num_parents = 1,
591
-
.flags = CLK_SET_RATE_PARENT,
592
-
},
593
-
};
594
-
595
-
static struct clk_regmap spicc_b_sel = {
596
-
.data = &(struct clk_regmap_mux_data) {
597
-
.offset = SPICC_CLK_CTRL,
598
-
.mask = 0x7,
599
-
.shift = 23,
600
-
},
601
-
.hw.init = &(struct clk_init_data) {
602
-
.name = "spicc_b_sel",
603
-
.ops = &clk_regmap_mux_ops,
604
-
.parent_data = spicc_parent_data,
605
-
.num_parents = ARRAY_SIZE(spicc_parent_data),
606
-
},
607
-
};
608
-
609
-
static struct clk_regmap spicc_b_div = {
610
-
.data = &(struct clk_regmap_div_data) {
611
-
.offset = SPICC_CLK_CTRL,
612
-
.shift = 16,
613
-
.width = 6,
614
-
},
615
-
.hw.init = &(struct clk_init_data) {
616
-
.name = "spicc_b_div",
617
-
.ops = &clk_regmap_divider_ops,
618
-
.parent_hws = (const struct clk_hw *[]) {
619
-
&spicc_b_sel.hw
620
-
},
621
-
.num_parents = 1,
622
-
.flags = CLK_SET_RATE_PARENT,
623
-
},
624
-
};
625
-
626
-
static struct clk_regmap spicc_b = {
627
-
.data = &(struct clk_regmap_gate_data) {
628
-
.offset = SPICC_CLK_CTRL,
629
-
.bit_idx = 22,
630
-
},
631
-
.hw.init = &(struct clk_init_data) {
632
-
.name = "spicc_b",
633
-
.ops = &clk_regmap_gate_ops,
634
-
.parent_hws = (const struct clk_hw *[]) {
635
-
&spicc_b_div.hw
636
-
},
637
-
.num_parents = 1,
638
-
.flags = CLK_SET_RATE_PARENT,
639
-
},
640
-
};
641
-
642
-
static const struct clk_parent_data spifc_parent_data[] = {
692
+
static const struct clk_parent_data c3_spifc_parents[] = {
643
693
{ .fw_name = "gp0" },
644
694
{ .fw_name = "fdiv2" },
645
695
{ .fw_name = "fdiv3" },
···
564
786
{ .fw_name = "fdiv7" }
565
787
};
566
788
567
-
static struct clk_regmap spifc_sel = {
568
-
.data = &(struct clk_regmap_mux_data) {
569
-
.offset = SPIFC_CLK_CTRL,
570
-
.mask = 0x7,
571
-
.shift = 9,
572
-
},
573
-
.hw.init = &(struct clk_init_data) {
574
-
.name = "spifc_sel",
575
-
.ops = &clk_regmap_mux_ops,
576
-
.parent_data = spifc_parent_data,
577
-
.num_parents = ARRAY_SIZE(spifc_parent_data),
578
-
},
579
-
};
789
+
static C3_COMP_SEL(spifc, SPIFC_CLK_CTRL, 9, 0x7, c3_spifc_parents);
790
+
static C3_COMP_DIV(spifc, SPIFC_CLK_CTRL, 0, 7);
791
+
static C3_COMP_GATE(spifc, SPIFC_CLK_CTRL, 8);
580
792
581
-
static struct clk_regmap spifc_div = {
582
-
.data = &(struct clk_regmap_div_data) {
583
-
.offset = SPIFC_CLK_CTRL,
584
-
.shift = 0,
585
-
.width = 7,
586
-
},
587
-
.hw.init = &(struct clk_init_data) {
588
-
.name = "spifc_div",
589
-
.ops = &clk_regmap_divider_ops,
590
-
.parent_hws = (const struct clk_hw *[]) {
591
-
&spifc_sel.hw
592
-
},
593
-
.num_parents = 1,
594
-
.flags = CLK_SET_RATE_PARENT,
595
-
},
596
-
};
597
-
598
-
static struct clk_regmap spifc = {
599
-
.data = &(struct clk_regmap_gate_data) {
600
-
.offset = SPIFC_CLK_CTRL,
601
-
.bit_idx = 8,
602
-
},
603
-
.hw.init = &(struct clk_init_data) {
604
-
.name = "spifc",
605
-
.ops = &clk_regmap_gate_ops,
606
-
.parent_hws = (const struct clk_hw *[]) {
607
-
&spifc_div.hw
608
-
},
609
-
.num_parents = 1,
610
-
.flags = CLK_SET_RATE_PARENT,
611
-
},
612
-
};
613
-
614
-
static const struct clk_parent_data emmc_parent_data[] = {
793
+
static const struct clk_parent_data c3_sd_emmc_parents[] = {
615
794
{ .fw_name = "oscin" },
616
795
{ .fw_name = "fdiv2" },
617
796
{ .fw_name = "fdiv3" },
···
579
844
{ .fw_name = "gp0" }
580
845
};
581
846
582
-
static struct clk_regmap sd_emmc_a_sel = {
583
-
.data = &(struct clk_regmap_mux_data) {
584
-
.offset = SD_EMMC_CLK_CTRL,
585
-
.mask = 0x7,
586
-
.shift = 9,
587
-
},
588
-
.hw.init = &(struct clk_init_data) {
589
-
.name = "sd_emmc_a_sel",
590
-
.ops = &clk_regmap_mux_ops,
591
-
.parent_data = emmc_parent_data,
592
-
.num_parents = ARRAY_SIZE(emmc_parent_data),
593
-
},
594
-
};
847
+
static C3_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents);
848
+
static C3_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
849
+
static C3_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7);
595
850
596
-
static struct clk_regmap sd_emmc_a_div = {
597
-
.data = &(struct clk_regmap_div_data) {
598
-
.offset = SD_EMMC_CLK_CTRL,
599
-
.shift = 0,
600
-
.width = 7,
601
-
},
602
-
.hw.init = &(struct clk_init_data) {
603
-
.name = "sd_emmc_a_div",
604
-
.ops = &clk_regmap_divider_ops,
605
-
.parent_hws = (const struct clk_hw *[]) {
606
-
&sd_emmc_a_sel.hw
607
-
},
608
-
.num_parents = 1,
609
-
.flags = CLK_SET_RATE_PARENT,
610
-
},
611
-
};
851
+
static C3_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, c3_sd_emmc_parents);
852
+
static C3_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7);
853
+
static C3_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23);
612
854
613
-
static struct clk_regmap sd_emmc_a = {
614
-
.data = &(struct clk_regmap_gate_data) {
615
-
.offset = SD_EMMC_CLK_CTRL,
616
-
.bit_idx = 7,
617
-
},
618
-
.hw.init = &(struct clk_init_data) {
619
-
.name = "sd_emmc_a",
620
-
.ops = &clk_regmap_gate_ops,
621
-
.parent_hws = (const struct clk_hw *[]) {
622
-
&sd_emmc_a_div.hw
623
-
},
624
-
.num_parents = 1,
625
-
.flags = CLK_SET_RATE_PARENT,
626
-
},
627
-
};
855
+
static C3_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents);
856
+
static C3_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
857
+
static C3_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
628
858
629
-
static struct clk_regmap sd_emmc_b_sel = {
630
-
.data = &(struct clk_regmap_mux_data) {
631
-
.offset = SD_EMMC_CLK_CTRL,
632
-
.mask = 0x7,
633
-
.shift = 25,
634
-
},
635
-
.hw.init = &(struct clk_init_data) {
636
-
.name = "sd_emmc_b_sel",
637
-
.ops = &clk_regmap_mux_ops,
638
-
.parent_data = emmc_parent_data,
639
-
.num_parents = ARRAY_SIZE(emmc_parent_data),
640
-
},
641
-
};
642
-
643
-
static struct clk_regmap sd_emmc_b_div = {
644
-
.data = &(struct clk_regmap_div_data) {
645
-
.offset = SD_EMMC_CLK_CTRL,
646
-
.shift = 16,
647
-
.width = 7,
648
-
},
649
-
.hw.init = &(struct clk_init_data) {
650
-
.name = "sd_emmc_b_div",
651
-
.ops = &clk_regmap_divider_ops,
652
-
.parent_hws = (const struct clk_hw *[]) {
653
-
&sd_emmc_b_sel.hw
654
-
},
655
-
.num_parents = 1,
656
-
.flags = CLK_SET_RATE_PARENT,
657
-
},
658
-
};
659
-
660
-
static struct clk_regmap sd_emmc_b = {
661
-
.data = &(struct clk_regmap_gate_data) {
662
-
.offset = SD_EMMC_CLK_CTRL,
663
-
.bit_idx = 23,
664
-
},
665
-
.hw.init = &(struct clk_init_data) {
666
-
.name = "sd_emmc_b",
667
-
.ops = &clk_regmap_gate_ops,
668
-
.parent_hws = (const struct clk_hw *[]) {
669
-
&sd_emmc_b_div.hw
670
-
},
671
-
.num_parents = 1,
672
-
.flags = CLK_SET_RATE_PARENT,
673
-
},
674
-
};
675
-
676
-
static struct clk_regmap sd_emmc_c_sel = {
677
-
.data = &(struct clk_regmap_mux_data) {
678
-
.offset = NAND_CLK_CTRL,
679
-
.mask = 0x7,
680
-
.shift = 9,
681
-
},
682
-
.hw.init = &(struct clk_init_data) {
683
-
.name = "sd_emmc_c_sel",
684
-
.ops = &clk_regmap_mux_ops,
685
-
.parent_data = emmc_parent_data,
686
-
.num_parents = ARRAY_SIZE(emmc_parent_data),
687
-
},
688
-
};
689
-
690
-
static struct clk_regmap sd_emmc_c_div = {
691
-
.data = &(struct clk_regmap_div_data) {
692
-
.offset = NAND_CLK_CTRL,
693
-
.shift = 0,
694
-
.width = 7,
695
-
},
696
-
.hw.init = &(struct clk_init_data) {
697
-
.name = "sd_emmc_c_div",
698
-
.ops = &clk_regmap_divider_ops,
699
-
.parent_hws = (const struct clk_hw *[]) {
700
-
&sd_emmc_c_sel.hw
701
-
},
702
-
.num_parents = 1,
703
-
.flags = CLK_SET_RATE_PARENT,
704
-
},
705
-
};
706
-
707
-
static struct clk_regmap sd_emmc_c = {
708
-
.data = &(struct clk_regmap_gate_data) {
709
-
.offset = NAND_CLK_CTRL,
710
-
.bit_idx = 7,
711
-
},
712
-
.hw.init = &(struct clk_init_data) {
713
-
.name = "sd_emmc_c",
714
-
.ops = &clk_regmap_gate_ops,
715
-
.parent_hws = (const struct clk_hw *[]) {
716
-
&sd_emmc_c_div.hw
717
-
},
718
-
.num_parents = 1,
719
-
.flags = CLK_SET_RATE_PARENT,
720
-
},
721
-
};
722
-
723
-
static struct clk_regmap ts_div = {
859
+
static struct clk_regmap c3_ts_div = {
724
860
.data = &(struct clk_regmap_div_data) {
725
861
.offset = TS_CLK_CTRL,
726
862
.shift = 0,
···
607
1001
},
608
1002
};
609
1003
610
-
static struct clk_regmap ts = {
1004
+
static struct clk_regmap c3_ts = {
611
1005
.data = &(struct clk_regmap_gate_data) {
612
1006
.offset = TS_CLK_CTRL,
613
1007
.bit_idx = 8,
···
616
1010
.name = "ts",
617
1011
.ops = &clk_regmap_gate_ops,
618
1012
.parent_hws = (const struct clk_hw *[]) {
619
-
&ts_div.hw
1013
+
&c3_ts_div.hw
620
1014
},
621
1015
.num_parents = 1,
622
1016
.flags = CLK_SET_RATE_PARENT,
623
1017
},
624
1018
};
625
1019
626
-
static const struct clk_parent_data eth_parent = {
1020
+
static const struct clk_parent_data c3_eth_parents = {
627
1021
.fw_name = "fdiv2",
628
1022
};
629
1023
630
-
static struct clk_fixed_factor eth_125m_div = {
1024
+
static struct clk_fixed_factor c3_eth_125m_div = {
631
1025
.mult = 1,
632
1026
.div = 8,
633
1027
.hw.init = &(struct clk_init_data) {
634
1028
.name = "eth_125m_div",
635
1029
.ops = &clk_fixed_factor_ops,
636
-
.parent_data = ð_parent,
1030
+
.parent_data = &c3_eth_parents,
637
1031
.num_parents = 1,
638
1032
},
639
1033
};
640
1034
641
-
static struct clk_regmap eth_125m = {
1035
+
static struct clk_regmap c3_eth_125m = {
642
1036
.data = &(struct clk_regmap_gate_data) {
643
1037
.offset = ETH_CLK_CTRL,
644
1038
.bit_idx = 7,
···
647
1041
.name = "eth_125m",
648
1042
.ops = &clk_regmap_gate_ops,
649
1043
.parent_hws = (const struct clk_hw *[]) {
650
-
ð_125m_div.hw
1044
+
&c3_eth_125m_div.hw
651
1045
},
652
1046
.num_parents = 1,
653
1047
.flags = CLK_SET_RATE_PARENT,
654
1048
},
655
1049
};
656
1050
657
-
static struct clk_regmap eth_rmii_div = {
1051
+
static struct clk_regmap c3_eth_rmii_div = {
658
1052
.data = &(struct clk_regmap_div_data) {
659
1053
.offset = ETH_CLK_CTRL,
660
1054
.shift = 0,
···
663
1057
.hw.init = &(struct clk_init_data) {
664
1058
.name = "eth_rmii_div",
665
1059
.ops = &clk_regmap_divider_ops,
666
-
.parent_data = ð_parent,
1060
+
.parent_data = &c3_eth_parents,
667
1061
.num_parents = 1,
668
1062
},
669
1063
};
670
1064
671
-
static struct clk_regmap eth_rmii = {
1065
+
static struct clk_regmap c3_eth_rmii = {
672
1066
.data = &(struct clk_regmap_gate_data) {
673
1067
.offset = ETH_CLK_CTRL,
674
1068
.bit_idx = 8,
···
677
1071
.name = "eth_rmii",
678
1072
.ops = &clk_regmap_gate_ops,
679
1073
.parent_hws = (const struct clk_hw *[]) {
680
-
ð_rmii_div.hw
1074
+
&c3_eth_rmii_div.hw
681
1075
},
682
1076
.num_parents = 1,
683
1077
.flags = CLK_SET_RATE_PARENT,
684
1078
},
685
1079
};
686
1080
687
-
static const struct clk_parent_data mipi_dsi_meas_parent_data[] = {
1081
+
static const struct clk_parent_data c3_mipi_dsi_meas_parents[] = {
688
1082
{ .fw_name = "oscin" },
689
1083
{ .fw_name = "fdiv4" },
690
1084
{ .fw_name = "fdiv3" },
···
695
1089
{ .fw_name = "fdiv7" }
696
1090
};
697
1091
698
-
static struct clk_regmap mipi_dsi_meas_sel = {
699
-
.data = &(struct clk_regmap_mux_data) {
700
-
.offset = VDIN_MEAS_CLK_CTRL,
701
-
.mask = 0x7,
702
-
.shift = 21,
703
-
},
704
-
.hw.init = &(struct clk_init_data) {
705
-
.name = "mipi_dsi_meas_sel",
706
-
.ops = &clk_regmap_mux_ops,
707
-
.parent_data = mipi_dsi_meas_parent_data,
708
-
.num_parents = ARRAY_SIZE(mipi_dsi_meas_parent_data),
709
-
},
710
-
};
1092
+
static C3_COMP_SEL(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 21, 0x7, c3_mipi_dsi_meas_parents);
1093
+
static C3_COMP_DIV(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 12, 7);
1094
+
static C3_COMP_GATE(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 20);
711
1095
712
-
static struct clk_regmap mipi_dsi_meas_div = {
713
-
.data = &(struct clk_regmap_div_data) {
714
-
.offset = VDIN_MEAS_CLK_CTRL,
715
-
.shift = 12,
716
-
.width = 7,
717
-
},
718
-
.hw.init = &(struct clk_init_data) {
719
-
.name = "mipi_dsi_meas_div",
720
-
.ops = &clk_regmap_divider_ops,
721
-
.parent_hws = (const struct clk_hw *[]) {
722
-
&mipi_dsi_meas_sel.hw
723
-
},
724
-
.num_parents = 1,
725
-
.flags = CLK_SET_RATE_PARENT,
726
-
},
727
-
};
728
-
729
-
static struct clk_regmap mipi_dsi_meas = {
730
-
.data = &(struct clk_regmap_gate_data) {
731
-
.offset = VDIN_MEAS_CLK_CTRL,
732
-
.bit_idx = 20,
733
-
},
734
-
.hw.init = &(struct clk_init_data) {
735
-
.name = "mipi_dsi_meas",
736
-
.ops = &clk_regmap_gate_ops,
737
-
.parent_hws = (const struct clk_hw *[]) {
738
-
&mipi_dsi_meas_div.hw
739
-
},
740
-
.num_parents = 1,
741
-
.flags = CLK_SET_RATE_PARENT,
742
-
},
743
-
};
744
-
745
-
static const struct clk_parent_data dsi_phy_parent_data[] = {
1096
+
static const struct clk_parent_data c3_dsi_phy_parents[] = {
746
1097
{ .fw_name = "gp1" },
747
1098
{ .fw_name = "gp0" },
748
1099
{ .fw_name = "hifi" },
···
710
1147
{ .fw_name = "fdiv7" }
711
1148
};
712
1149
713
-
static struct clk_regmap dsi_phy_sel = {
714
-
.data = &(struct clk_regmap_mux_data) {
715
-
.offset = MIPIDSI_PHY_CLK_CTRL,
716
-
.mask = 0x7,
717
-
.shift = 12,
718
-
},
719
-
.hw.init = &(struct clk_init_data) {
720
-
.name = "dsi_phy_sel",
721
-
.ops = &clk_regmap_mux_ops,
722
-
.parent_data = dsi_phy_parent_data,
723
-
.num_parents = ARRAY_SIZE(dsi_phy_parent_data),
724
-
},
725
-
};
1150
+
static C3_COMP_SEL(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 12, 0x7, c3_dsi_phy_parents);
1151
+
static C3_COMP_DIV(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 0, 7);
1152
+
static C3_COMP_GATE(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 8);
726
1153
727
-
static struct clk_regmap dsi_phy_div = {
728
-
.data = &(struct clk_regmap_div_data) {
729
-
.offset = MIPIDSI_PHY_CLK_CTRL,
730
-
.shift = 0,
731
-
.width = 7,
732
-
},
733
-
.hw.init = &(struct clk_init_data) {
734
-
.name = "dsi_phy_div",
735
-
.ops = &clk_regmap_divider_ops,
736
-
.parent_hws = (const struct clk_hw *[]) {
737
-
&dsi_phy_sel.hw
738
-
},
739
-
.num_parents = 1,
740
-
.flags = CLK_SET_RATE_PARENT,
741
-
},
742
-
};
743
-
744
-
static struct clk_regmap dsi_phy = {
745
-
.data = &(struct clk_regmap_gate_data) {
746
-
.offset = MIPIDSI_PHY_CLK_CTRL,
747
-
.bit_idx = 8,
748
-
},
749
-
.hw.init = &(struct clk_init_data) {
750
-
.name = "dsi_phy",
751
-
.ops = &clk_regmap_gate_ops,
752
-
.parent_hws = (const struct clk_hw *[]) {
753
-
&dsi_phy_div.hw
754
-
},
755
-
.num_parents = 1,
756
-
.flags = CLK_SET_RATE_PARENT,
757
-
},
758
-
};
759
-
760
-
static const struct clk_parent_data vout_mclk_parent_data[] = {
1154
+
static const struct clk_parent_data c3_vout_mclk_parents[] = {
761
1155
{ .fw_name = "fdiv2p5" },
762
1156
{ .fw_name = "fdiv3" },
763
1157
{ .fw_name = "fdiv4" },
···
725
1205
{ .fw_name = "fdiv7" }
726
1206
};
727
1207
728
-
static struct clk_regmap vout_mclk_sel = {
729
-
.data = &(struct clk_regmap_mux_data) {
730
-
.offset = VOUTENC_CLK_CTRL,
731
-
.mask = 0x7,
732
-
.shift = 9,
733
-
},
734
-
.hw.init = &(struct clk_init_data) {
735
-
.name = "vout_mclk_sel",
736
-
.ops = &clk_regmap_mux_ops,
737
-
.parent_data = vout_mclk_parent_data,
738
-
.num_parents = ARRAY_SIZE(vout_mclk_parent_data),
739
-
},
740
-
};
1208
+
static C3_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, c3_vout_mclk_parents);
1209
+
static C3_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7);
1210
+
static C3_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8);
741
1211
742
-
static struct clk_regmap vout_mclk_div = {
743
-
.data = &(struct clk_regmap_div_data) {
744
-
.offset = VOUTENC_CLK_CTRL,
745
-
.shift = 0,
746
-
.width = 7,
747
-
},
748
-
.hw.init = &(struct clk_init_data) {
749
-
.name = "vout_mclk_div",
750
-
.ops = &clk_regmap_divider_ops,
751
-
.parent_hws = (const struct clk_hw *[]) {
752
-
&vout_mclk_sel.hw
753
-
},
754
-
.num_parents = 1,
755
-
.flags = CLK_SET_RATE_PARENT,
756
-
},
757
-
};
758
-
759
-
static struct clk_regmap vout_mclk = {
760
-
.data = &(struct clk_regmap_gate_data) {
761
-
.offset = VOUTENC_CLK_CTRL,
762
-
.bit_idx = 8,
763
-
},
764
-
.hw.init = &(struct clk_init_data) {
765
-
.name = "vout_mclk",
766
-
.ops = &clk_regmap_gate_ops,
767
-
.parent_hws = (const struct clk_hw *[]) {
768
-
&vout_mclk_div.hw
769
-
},
770
-
.num_parents = 1,
771
-
.flags = CLK_SET_RATE_PARENT,
772
-
},
773
-
};
774
-
775
-
static const struct clk_parent_data vout_enc_parent_data[] = {
1212
+
static const struct clk_parent_data c3_vout_enc_parents[] = {
776
1213
{ .fw_name = "gp1" },
777
1214
{ .fw_name = "fdiv3" },
778
1215
{ .fw_name = "fdiv4" },
···
740
1263
{ .fw_name = "fdiv7" }
741
1264
};
742
1265
743
-
static struct clk_regmap vout_enc_sel = {
744
-
.data = &(struct clk_regmap_mux_data) {
745
-
.offset = VOUTENC_CLK_CTRL,
746
-
.mask = 0x7,
747
-
.shift = 25,
748
-
},
749
-
.hw.init = &(struct clk_init_data) {
750
-
.name = "vout_enc_sel",
751
-
.ops = &clk_regmap_mux_ops,
752
-
.parent_data = vout_enc_parent_data,
753
-
.num_parents = ARRAY_SIZE(vout_enc_parent_data),
754
-
},
755
-
};
1266
+
static C3_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, c3_vout_enc_parents);
1267
+
static C3_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7);
1268
+
static C3_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24);
756
1269
757
-
static struct clk_regmap vout_enc_div = {
758
-
.data = &(struct clk_regmap_div_data) {
759
-
.offset = VOUTENC_CLK_CTRL,
760
-
.shift = 16,
761
-
.width = 7,
762
-
},
763
-
.hw.init = &(struct clk_init_data) {
764
-
.name = "vout_enc_div",
765
-
.ops = &clk_regmap_divider_ops,
766
-
.parent_hws = (const struct clk_hw *[]) {
767
-
&vout_enc_sel.hw
768
-
},
769
-
.num_parents = 1,
770
-
.flags = CLK_SET_RATE_PARENT,
771
-
},
772
-
};
773
-
774
-
static struct clk_regmap vout_enc = {
775
-
.data = &(struct clk_regmap_gate_data) {
776
-
.offset = VOUTENC_CLK_CTRL,
777
-
.bit_idx = 24,
778
-
},
779
-
.hw.init = &(struct clk_init_data) {
780
-
.name = "vout_enc",
781
-
.ops = &clk_regmap_gate_ops,
782
-
.parent_hws = (const struct clk_hw *[]) {
783
-
&vout_enc_div.hw
784
-
},
785
-
.num_parents = 1,
786
-
.flags = CLK_SET_RATE_PARENT,
787
-
},
788
-
};
789
-
790
-
static const struct clk_parent_data hcodec_pre_parent_data[] = {
1270
+
static const struct clk_parent_data c3_hcodec_pre_parents[] = {
791
1271
{ .fw_name = "fdiv2p5" },
792
1272
{ .fw_name = "fdiv3" },
793
1273
{ .fw_name = "fdiv4" },
···
755
1321
{ .fw_name = "oscin" }
756
1322
};
757
1323
758
-
static struct clk_regmap hcodec_0_sel = {
759
-
.data = &(struct clk_regmap_mux_data) {
760
-
.offset = VDEC_CLK_CTRL,
761
-
.mask = 0x7,
762
-
.shift = 9,
763
-
},
764
-
.hw.init = &(struct clk_init_data) {
765
-
.name = "hcodec_0_sel",
766
-
.ops = &clk_regmap_mux_ops,
767
-
.parent_data = hcodec_pre_parent_data,
768
-
.num_parents = ARRAY_SIZE(hcodec_pre_parent_data),
769
-
},
1324
+
static C3_COMP_SEL(hcodec_0, VDEC_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents);
1325
+
static C3_COMP_DIV(hcodec_0, VDEC_CLK_CTRL, 0, 7);
1326
+
static C3_COMP_GATE(hcodec_0, VDEC_CLK_CTRL, 8);
1327
+
1328
+
static C3_COMP_SEL(hcodec_1, VDEC3_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents);
1329
+
static C3_COMP_DIV(hcodec_1, VDEC3_CLK_CTRL, 0, 7);
1330
+
static C3_COMP_GATE(hcodec_1, VDEC3_CLK_CTRL, 8);
1331
+
1332
+
static const struct clk_parent_data c3_hcodec_parents[] = {
1333
+
{ .hw = &c3_hcodec_0.hw },
1334
+
{ .hw = &c3_hcodec_1.hw }
770
1335
};
771
1336
772
-
static struct clk_regmap hcodec_0_div = {
773
-
.data = &(struct clk_regmap_div_data) {
774
-
.offset = VDEC_CLK_CTRL,
775
-
.shift = 0,
776
-
.width = 7,
777
-
},
778
-
.hw.init = &(struct clk_init_data) {
779
-
.name = "hcodec_0_div",
780
-
.ops = &clk_regmap_divider_ops,
781
-
.parent_hws = (const struct clk_hw *[]) {
782
-
&hcodec_0_sel.hw
783
-
},
784
-
.num_parents = 1,
785
-
.flags = CLK_SET_RATE_PARENT,
786
-
},
787
-
};
788
-
789
-
static struct clk_regmap hcodec_0 = {
790
-
.data = &(struct clk_regmap_gate_data) {
791
-
.offset = VDEC_CLK_CTRL,
792
-
.bit_idx = 8,
793
-
},
794
-
.hw.init = &(struct clk_init_data) {
795
-
.name = "hcodec_0",
796
-
.ops = &clk_regmap_gate_ops,
797
-
.parent_hws = (const struct clk_hw *[]) {
798
-
&hcodec_0_div.hw
799
-
},
800
-
.num_parents = 1,
801
-
.flags = CLK_SET_RATE_PARENT,
802
-
},
803
-
};
804
-
805
-
static struct clk_regmap hcodec_1_sel = {
806
-
.data = &(struct clk_regmap_mux_data) {
807
-
.offset = VDEC3_CLK_CTRL,
808
-
.mask = 0x7,
809
-
.shift = 9,
810
-
},
811
-
.hw.init = &(struct clk_init_data) {
812
-
.name = "hcodec_1_sel",
813
-
.ops = &clk_regmap_mux_ops,
814
-
.parent_data = hcodec_pre_parent_data,
815
-
.num_parents = ARRAY_SIZE(hcodec_pre_parent_data),
816
-
},
817
-
};
818
-
819
-
static struct clk_regmap hcodec_1_div = {
820
-
.data = &(struct clk_regmap_div_data) {
821
-
.offset = VDEC3_CLK_CTRL,
822
-
.shift = 0,
823
-
.width = 7,
824
-
},
825
-
.hw.init = &(struct clk_init_data) {
826
-
.name = "hcodec_1_div",
827
-
.ops = &clk_regmap_divider_ops,
828
-
.parent_hws = (const struct clk_hw *[]) {
829
-
&hcodec_1_sel.hw
830
-
},
831
-
.num_parents = 1,
832
-
.flags = CLK_SET_RATE_PARENT,
833
-
},
834
-
};
835
-
836
-
static struct clk_regmap hcodec_1 = {
837
-
.data = &(struct clk_regmap_gate_data) {
838
-
.offset = VDEC3_CLK_CTRL,
839
-
.bit_idx = 8,
840
-
},
841
-
.hw.init = &(struct clk_init_data) {
842
-
.name = "hcodec_1",
843
-
.ops = &clk_regmap_gate_ops,
844
-
.parent_hws = (const struct clk_hw *[]) {
845
-
&hcodec_1_div.hw
846
-
},
847
-
.num_parents = 1,
848
-
.flags = CLK_SET_RATE_PARENT,
849
-
},
850
-
};
851
-
852
-
static const struct clk_parent_data hcodec_parent_data[] = {
853
-
{ .hw = &hcodec_0.hw },
854
-
{ .hw = &hcodec_1.hw }
855
-
};
856
-
857
-
static struct clk_regmap hcodec = {
1337
+
static struct clk_regmap c3_hcodec = {
858
1338
.data = &(struct clk_regmap_mux_data) {
859
1339
.offset = VDEC3_CLK_CTRL,
860
1340
.mask = 0x1,
···
777
1429
.hw.init = &(struct clk_init_data) {
778
1430
.name = "hcodec",
779
1431
.ops = &clk_regmap_mux_ops,
780
-
.parent_data = hcodec_parent_data,
781
-
.num_parents = ARRAY_SIZE(hcodec_parent_data),
1432
+
.parent_data = c3_hcodec_parents,
1433
+
.num_parents = ARRAY_SIZE(c3_hcodec_parents),
782
1434
.flags = CLK_SET_RATE_PARENT,
783
1435
},
784
1436
};
785
1437
786
-
static const struct clk_parent_data vc9000e_parent_data[] = {
1438
+
static const struct clk_parent_data c3_vc9000e_parents[] = {
787
1439
{ .fw_name = "oscin" },
788
1440
{ .fw_name = "fdiv4" },
789
1441
{ .fw_name = "fdiv3" },
···
794
1446
{ .fw_name = "gp0" }
795
1447
};
796
1448
797
-
static struct clk_regmap vc9000e_aclk_sel = {
798
-
.data = &(struct clk_regmap_mux_data) {
799
-
.offset = VC9000E_CLK_CTRL,
800
-
.mask = 0x7,
801
-
.shift = 9,
802
-
},
803
-
.hw.init = &(struct clk_init_data) {
804
-
.name = "vc9000e_aclk_sel",
805
-
.ops = &clk_regmap_mux_ops,
806
-
.parent_data = vc9000e_parent_data,
807
-
.num_parents = ARRAY_SIZE(vc9000e_parent_data),
808
-
},
809
-
};
1449
+
static C3_COMP_SEL(vc9000e_aclk, VC9000E_CLK_CTRL, 9, 0x7, c3_vc9000e_parents);
1450
+
static C3_COMP_DIV(vc9000e_aclk, VC9000E_CLK_CTRL, 0, 7);
1451
+
static C3_COMP_GATE(vc9000e_aclk, VC9000E_CLK_CTRL, 8);
810
1452
811
-
static struct clk_regmap vc9000e_aclk_div = {
812
-
.data = &(struct clk_regmap_div_data) {
813
-
.offset = VC9000E_CLK_CTRL,
814
-
.shift = 0,
815
-
.width = 7,
816
-
},
817
-
.hw.init = &(struct clk_init_data) {
818
-
.name = "vc9000e_aclk_div",
819
-
.ops = &clk_regmap_divider_ops,
820
-
.parent_hws = (const struct clk_hw *[]) {
821
-
&vc9000e_aclk_sel.hw
822
-
},
823
-
.num_parents = 1,
824
-
.flags = CLK_SET_RATE_PARENT,
825
-
},
826
-
};
1453
+
static C3_COMP_SEL(vc9000e_core, VC9000E_CLK_CTRL, 25, 0x7, c3_vc9000e_parents);
1454
+
static C3_COMP_DIV(vc9000e_core, VC9000E_CLK_CTRL, 16, 7);
1455
+
static C3_COMP_GATE(vc9000e_core, VC9000E_CLK_CTRL, 24);
827
1456
828
-
static struct clk_regmap vc9000e_aclk = {
829
-
.data = &(struct clk_regmap_gate_data) {
830
-
.offset = VC9000E_CLK_CTRL,
831
-
.bit_idx = 8,
832
-
},
833
-
.hw.init = &(struct clk_init_data) {
834
-
.name = "vc9000e_aclk",
835
-
.ops = &clk_regmap_gate_ops,
836
-
.parent_hws = (const struct clk_hw *[]) {
837
-
&vc9000e_aclk_div.hw
838
-
},
839
-
.num_parents = 1,
840
-
.flags = CLK_SET_RATE_PARENT,
841
-
},
842
-
};
843
-
844
-
static struct clk_regmap vc9000e_core_sel = {
845
-
.data = &(struct clk_regmap_mux_data) {
846
-
.offset = VC9000E_CLK_CTRL,
847
-
.mask = 0x7,
848
-
.shift = 25,
849
-
},
850
-
.hw.init = &(struct clk_init_data) {
851
-
.name = "vc9000e_core_sel",
852
-
.ops = &clk_regmap_mux_ops,
853
-
.parent_data = vc9000e_parent_data,
854
-
.num_parents = ARRAY_SIZE(vc9000e_parent_data),
855
-
},
856
-
};
857
-
858
-
static struct clk_regmap vc9000e_core_div = {
859
-
.data = &(struct clk_regmap_div_data) {
860
-
.offset = VC9000E_CLK_CTRL,
861
-
.shift = 16,
862
-
.width = 7,
863
-
},
864
-
.hw.init = &(struct clk_init_data) {
865
-
.name = "vc9000e_core_div",
866
-
.ops = &clk_regmap_divider_ops,
867
-
.parent_hws = (const struct clk_hw *[]) {
868
-
&vc9000e_core_sel.hw
869
-
},
870
-
.num_parents = 1,
871
-
.flags = CLK_SET_RATE_PARENT,
872
-
},
873
-
};
874
-
875
-
static struct clk_regmap vc9000e_core = {
876
-
.data = &(struct clk_regmap_gate_data) {
877
-
.offset = VC9000E_CLK_CTRL,
878
-
.bit_idx = 24,
879
-
},
880
-
.hw.init = &(struct clk_init_data) {
881
-
.name = "vc9000e_core",
882
-
.ops = &clk_regmap_gate_ops,
883
-
.parent_hws = (const struct clk_hw *[]) {
884
-
&vc9000e_core_div.hw
885
-
},
886
-
.num_parents = 1,
887
-
.flags = CLK_SET_RATE_PARENT,
888
-
},
889
-
};
890
-
891
-
static const struct clk_parent_data csi_phy_parent_data[] = {
1457
+
static const struct clk_parent_data c3_csi_phy_parents[] = {
892
1458
{ .fw_name = "fdiv2p5" },
893
1459
{ .fw_name = "fdiv3" },
894
1460
{ .fw_name = "fdiv4" },
···
813
1551
{ .fw_name = "oscin" }
814
1552
};
815
1553
816
-
static struct clk_regmap csi_phy0_sel = {
817
-
.data = &(struct clk_regmap_mux_data) {
818
-
.offset = ISP0_CLK_CTRL,
819
-
.mask = 0x7,
820
-
.shift = 25,
821
-
},
822
-
.hw.init = &(struct clk_init_data) {
823
-
.name = "csi_phy0_sel",
824
-
.ops = &clk_regmap_mux_ops,
825
-
.parent_data = csi_phy_parent_data,
826
-
.num_parents = ARRAY_SIZE(csi_phy_parent_data),
827
-
},
828
-
};
1554
+
static C3_COMP_SEL(csi_phy0, ISP0_CLK_CTRL, 25, 0x7, c3_csi_phy_parents);
1555
+
static C3_COMP_DIV(csi_phy0, ISP0_CLK_CTRL, 16, 7);
1556
+
static C3_COMP_GATE(csi_phy0, ISP0_CLK_CTRL, 24);
829
1557
830
-
static struct clk_regmap csi_phy0_div = {
831
-
.data = &(struct clk_regmap_div_data) {
832
-
.offset = ISP0_CLK_CTRL,
833
-
.shift = 16,
834
-
.width = 7,
835
-
},
836
-
.hw.init = &(struct clk_init_data) {
837
-
.name = "csi_phy0_div",
838
-
.ops = &clk_regmap_divider_ops,
839
-
.parent_hws = (const struct clk_hw *[]) {
840
-
&csi_phy0_sel.hw
841
-
},
842
-
.num_parents = 1,
843
-
.flags = CLK_SET_RATE_PARENT,
844
-
},
845
-
};
846
-
847
-
static struct clk_regmap csi_phy0 = {
848
-
.data = &(struct clk_regmap_gate_data) {
849
-
.offset = ISP0_CLK_CTRL,
850
-
.bit_idx = 24,
851
-
},
852
-
.hw.init = &(struct clk_init_data) {
853
-
.name = "csi_phy0",
854
-
.ops = &clk_regmap_gate_ops,
855
-
.parent_hws = (const struct clk_hw *[]) {
856
-
&csi_phy0_div.hw
857
-
},
858
-
.num_parents = 1,
859
-
.flags = CLK_SET_RATE_PARENT,
860
-
},
861
-
};
862
-
863
-
static const struct clk_parent_data dewarpa_parent_data[] = {
1558
+
static const struct clk_parent_data c3_dewarpa_parents[] = {
864
1559
{ .fw_name = "fdiv2p5" },
865
1560
{ .fw_name = "fdiv3" },
866
1561
{ .fw_name = "fdiv4" },
···
828
1609
{ .fw_name = "fdiv7" }
829
1610
};
830
1611
831
-
static struct clk_regmap dewarpa_sel = {
832
-
.data = &(struct clk_regmap_mux_data) {
833
-
.offset = DEWARPA_CLK_CTRL,
834
-
.mask = 0x7,
835
-
.shift = 9,
836
-
},
837
-
.hw.init = &(struct clk_init_data) {
838
-
.name = "dewarpa_sel",
839
-
.ops = &clk_regmap_mux_ops,
840
-
.parent_data = dewarpa_parent_data,
841
-
.num_parents = ARRAY_SIZE(dewarpa_parent_data),
842
-
},
843
-
};
1612
+
static C3_COMP_SEL(dewarpa, DEWARPA_CLK_CTRL, 9, 0x7, c3_dewarpa_parents);
1613
+
static C3_COMP_DIV(dewarpa, DEWARPA_CLK_CTRL, 0, 7);
1614
+
static C3_COMP_GATE(dewarpa, DEWARPA_CLK_CTRL, 8);
844
1615
845
-
static struct clk_regmap dewarpa_div = {
846
-
.data = &(struct clk_regmap_div_data) {
847
-
.offset = DEWARPA_CLK_CTRL,
848
-
.shift = 0,
849
-
.width = 7,
850
-
},
851
-
.hw.init = &(struct clk_init_data) {
852
-
.name = "dewarpa_div",
853
-
.ops = &clk_regmap_divider_ops,
854
-
.parent_hws = (const struct clk_hw *[]) {
855
-
&dewarpa_sel.hw
856
-
},
857
-
.num_parents = 1,
858
-
.flags = CLK_SET_RATE_PARENT,
859
-
},
860
-
};
861
-
862
-
static struct clk_regmap dewarpa = {
863
-
.data = &(struct clk_regmap_gate_data) {
864
-
.offset = DEWARPA_CLK_CTRL,
865
-
.bit_idx = 8,
866
-
},
867
-
.hw.init = &(struct clk_init_data) {
868
-
.name = "dewarpa",
869
-
.ops = &clk_regmap_gate_ops,
870
-
.parent_hws = (const struct clk_hw *[]) {
871
-
&dewarpa_div.hw
872
-
},
873
-
.num_parents = 1,
874
-
.flags = CLK_SET_RATE_PARENT,
875
-
},
876
-
};
877
-
878
-
static const struct clk_parent_data isp_parent_data[] = {
1616
+
static const struct clk_parent_data c3_isp_parents[] = {
879
1617
{ .fw_name = "fdiv2p5" },
880
1618
{ .fw_name = "fdiv3" },
881
1619
{ .fw_name = "fdiv4" },
···
843
1667
{ .fw_name = "oscin" }
844
1668
};
845
1669
846
-
static struct clk_regmap isp0_sel = {
847
-
.data = &(struct clk_regmap_mux_data) {
848
-
.offset = ISP0_CLK_CTRL,
849
-
.mask = 0x7,
850
-
.shift = 9,
851
-
},
852
-
.hw.init = &(struct clk_init_data) {
853
-
.name = "isp0_sel",
854
-
.ops = &clk_regmap_mux_ops,
855
-
.parent_data = isp_parent_data,
856
-
.num_parents = ARRAY_SIZE(isp_parent_data),
857
-
},
858
-
};
1670
+
static C3_COMP_SEL(isp0, ISP0_CLK_CTRL, 9, 0x7, c3_isp_parents);
1671
+
static C3_COMP_DIV(isp0, ISP0_CLK_CTRL, 0, 7);
1672
+
static C3_COMP_GATE(isp0, ISP0_CLK_CTRL, 8);
859
1673
860
-
static struct clk_regmap isp0_div = {
861
-
.data = &(struct clk_regmap_div_data) {
862
-
.offset = ISP0_CLK_CTRL,
863
-
.shift = 0,
864
-
.width = 7,
865
-
},
866
-
.hw.init = &(struct clk_init_data) {
867
-
.name = "isp0_div",
868
-
.ops = &clk_regmap_divider_ops,
869
-
.parent_hws = (const struct clk_hw *[]) {
870
-
&isp0_sel.hw
871
-
},
872
-
.num_parents = 1,
873
-
.flags = CLK_SET_RATE_PARENT,
874
-
},
875
-
};
876
-
877
-
static struct clk_regmap isp0 = {
878
-
.data = &(struct clk_regmap_gate_data) {
879
-
.offset = ISP0_CLK_CTRL,
880
-
.bit_idx = 8,
881
-
},
882
-
.hw.init = &(struct clk_init_data) {
883
-
.name = "isp0",
884
-
.ops = &clk_regmap_gate_ops,
885
-
.parent_hws = (const struct clk_hw *[]) {
886
-
&isp0_div.hw
887
-
},
888
-
.num_parents = 1,
889
-
.flags = CLK_SET_RATE_PARENT,
890
-
},
891
-
};
892
-
893
-
static const struct clk_parent_data nna_core_parent_data[] = {
1674
+
static const struct clk_parent_data c3_nna_core_parents[] = {
894
1675
{ .fw_name = "oscin" },
895
1676
{ .fw_name = "fdiv2p5" },
896
1677
{ .fw_name = "fdiv4" },
···
858
1725
{ .fw_name = "hifi" }
859
1726
};
860
1727
861
-
static struct clk_regmap nna_core_sel = {
862
-
.data = &(struct clk_regmap_mux_data) {
863
-
.offset = NNA_CLK_CTRL,
864
-
.mask = 0x7,
865
-
.shift = 9,
866
-
},
867
-
.hw.init = &(struct clk_init_data) {
868
-
.name = "nna_core_sel",
869
-
.ops = &clk_regmap_mux_ops,
870
-
.parent_data = nna_core_parent_data,
871
-
.num_parents = ARRAY_SIZE(nna_core_parent_data),
872
-
},
873
-
};
1728
+
static C3_COMP_SEL(nna_core, NNA_CLK_CTRL, 9, 0x7, c3_nna_core_parents);
1729
+
static C3_COMP_DIV(nna_core, NNA_CLK_CTRL, 0, 7);
1730
+
static C3_COMP_GATE(nna_core, NNA_CLK_CTRL, 8);
874
1731
875
-
static struct clk_regmap nna_core_div = {
876
-
.data = &(struct clk_regmap_div_data) {
877
-
.offset = NNA_CLK_CTRL,
878
-
.shift = 0,
879
-
.width = 7,
880
-
},
881
-
.hw.init = &(struct clk_init_data) {
882
-
.name = "nna_core_div",
883
-
.ops = &clk_regmap_divider_ops,
884
-
.parent_hws = (const struct clk_hw *[]) {
885
-
&nna_core_sel.hw
886
-
},
887
-
.num_parents = 1,
888
-
.flags = CLK_SET_RATE_PARENT,
889
-
},
890
-
};
891
-
892
-
static struct clk_regmap nna_core = {
893
-
.data = &(struct clk_regmap_gate_data) {
894
-
.offset = NNA_CLK_CTRL,
895
-
.bit_idx = 8,
896
-
},
897
-
.hw.init = &(struct clk_init_data) {
898
-
.name = "nna_core",
899
-
.ops = &clk_regmap_gate_ops,
900
-
.parent_hws = (const struct clk_hw *[]) {
901
-
&nna_core_div.hw
902
-
},
903
-
.num_parents = 1,
904
-
.flags = CLK_SET_RATE_PARENT,
905
-
},
906
-
};
907
-
908
-
static const struct clk_parent_data ge2d_parent_data[] = {
1732
+
static const struct clk_parent_data c3_ge2d_parents[] = {
909
1733
{ .fw_name = "oscin" },
910
1734
{ .fw_name = "fdiv2p5" },
911
1735
{ .fw_name = "fdiv3" },
···
870
1780
{ .fw_name = "hifi" },
871
1781
{ .fw_name = "fdiv5" },
872
1782
{ .fw_name = "gp0" },
873
-
{ .hw = &rtc_clk.hw }
1783
+
{ .hw = &c3_rtc_clk.hw }
874
1784
};
875
1785
876
-
static struct clk_regmap ge2d_sel = {
877
-
.data = &(struct clk_regmap_mux_data) {
878
-
.offset = GE2D_CLK_CTRL,
879
-
.mask = 0x7,
880
-
.shift = 9,
881
-
},
882
-
.hw.init = &(struct clk_init_data) {
883
-
.name = "ge2d_sel",
884
-
.ops = &clk_regmap_mux_ops,
885
-
.parent_data = ge2d_parent_data,
886
-
.num_parents = ARRAY_SIZE(ge2d_parent_data),
887
-
},
888
-
};
1786
+
static C3_COMP_SEL(ge2d, GE2D_CLK_CTRL, 9, 0x7, c3_ge2d_parents);
1787
+
static C3_COMP_DIV(ge2d, GE2D_CLK_CTRL, 0, 7);
1788
+
static C3_COMP_GATE(ge2d, GE2D_CLK_CTRL, 8);
889
1789
890
-
static struct clk_regmap ge2d_div = {
891
-
.data = &(struct clk_regmap_div_data) {
892
-
.offset = GE2D_CLK_CTRL,
893
-
.shift = 0,
894
-
.width = 7,
895
-
},
896
-
.hw.init = &(struct clk_init_data) {
897
-
.name = "ge2d_div",
898
-
.ops = &clk_regmap_divider_ops,
899
-
.parent_hws = (const struct clk_hw *[]) {
900
-
&ge2d_sel.hw
901
-
},
902
-
.num_parents = 1,
903
-
.flags = CLK_SET_RATE_PARENT,
904
-
},
905
-
};
906
-
907
-
static struct clk_regmap ge2d = {
908
-
.data = &(struct clk_regmap_gate_data) {
909
-
.offset = GE2D_CLK_CTRL,
910
-
.bit_idx = 8,
911
-
},
912
-
.hw.init = &(struct clk_init_data) {
913
-
.name = "ge2d",
914
-
.ops = &clk_regmap_gate_ops,
915
-
.parent_hws = (const struct clk_hw *[]) {
916
-
&ge2d_div.hw
917
-
},
918
-
.num_parents = 1,
919
-
.flags = CLK_SET_RATE_PARENT,
920
-
},
921
-
};
922
-
923
-
static const struct clk_parent_data vapb_parent_data[] = {
1790
+
static const struct clk_parent_data c3_vapb_parents[] = {
924
1791
{ .fw_name = "fdiv2p5" },
925
1792
{ .fw_name = "fdiv3" },
926
1793
{ .fw_name = "fdiv4" },
···
888
1841
{ .fw_name = "oscin" },
889
1842
};
890
1843
891
-
static struct clk_regmap vapb_sel = {
892
-
.data = &(struct clk_regmap_mux_data) {
893
-
.offset = VAPB_CLK_CTRL,
894
-
.mask = 0x7,
895
-
.shift = 9,
896
-
},
897
-
.hw.init = &(struct clk_init_data) {
898
-
.name = "vapb_sel",
899
-
.ops = &clk_regmap_mux_ops,
900
-
.parent_data = vapb_parent_data,
901
-
.num_parents = ARRAY_SIZE(vapb_parent_data),
902
-
},
1844
+
static C3_COMP_SEL(vapb, VAPB_CLK_CTRL, 9, 0x7, c3_vapb_parents);
1845
+
static C3_COMP_DIV(vapb, VAPB_CLK_CTRL, 0, 7);
1846
+
static C3_COMP_GATE(vapb, VAPB_CLK_CTRL, 8);
1847
+
1848
+
static struct clk_hw *c3_peripherals_hw_clks[] = {
1849
+
[CLKID_RTC_XTAL_CLKIN] = &c3_rtc_xtal_clkin.hw,
1850
+
[CLKID_RTC_32K_DIV] = &c3_rtc_32k_div.hw,
1851
+
[CLKID_RTC_32K_MUX] = &c3_rtc_32k_sel.hw,
1852
+
[CLKID_RTC_32K] = &c3_rtc_32k.hw,
1853
+
[CLKID_RTC_CLK] = &c3_rtc_clk.hw,
1854
+
[CLKID_SYS_RESET_CTRL] = &c3_sys_reset_ctrl.hw,
1855
+
[CLKID_SYS_PWR_CTRL] = &c3_sys_pwr_ctrl.hw,
1856
+
[CLKID_SYS_PAD_CTRL] = &c3_sys_pad_ctrl.hw,
1857
+
[CLKID_SYS_CTRL] = &c3_sys_ctrl.hw,
1858
+
[CLKID_SYS_TS_PLL] = &c3_sys_ts_pll.hw,
1859
+
[CLKID_SYS_DEV_ARB] = &c3_sys_dev_arb.hw,
1860
+
[CLKID_SYS_MMC_PCLK] = &c3_sys_mmc_pclk.hw,
1861
+
[CLKID_SYS_CPU_CTRL] = &c3_sys_cpu_ctrl.hw,
1862
+
[CLKID_SYS_JTAG_CTRL] = &c3_sys_jtag_ctrl.hw,
1863
+
[CLKID_SYS_IR_CTRL] = &c3_sys_ir_ctrl.hw,
1864
+
[CLKID_SYS_IRQ_CTRL] = &c3_sys_irq_ctrl.hw,
1865
+
[CLKID_SYS_MSR_CLK] = &c3_sys_msr_clk.hw,
1866
+
[CLKID_SYS_ROM] = &c3_sys_rom.hw,
1867
+
[CLKID_SYS_UART_F] = &c3_sys_uart_f.hw,
1868
+
[CLKID_SYS_CPU_ARB] = &c3_sys_cpu_apb.hw,
1869
+
[CLKID_SYS_RSA] = &c3_sys_rsa.hw,
1870
+
[CLKID_SYS_SAR_ADC] = &c3_sys_sar_adc.hw,
1871
+
[CLKID_SYS_STARTUP] = &c3_sys_startup.hw,
1872
+
[CLKID_SYS_SECURE] = &c3_sys_secure.hw,
1873
+
[CLKID_SYS_SPIFC] = &c3_sys_spifc.hw,
1874
+
[CLKID_SYS_NNA] = &c3_sys_nna.hw,
1875
+
[CLKID_SYS_ETH_MAC] = &c3_sys_eth_mac.hw,
1876
+
[CLKID_SYS_GIC] = &c3_sys_gic.hw,
1877
+
[CLKID_SYS_RAMA] = &c3_sys_rama.hw,
1878
+
[CLKID_SYS_BIG_NIC] = &c3_sys_big_nic.hw,
1879
+
[CLKID_SYS_RAMB] = &c3_sys_ramb.hw,
1880
+
[CLKID_SYS_AUDIO_PCLK] = &c3_sys_audio_pclk.hw,
1881
+
[CLKID_SYS_PWM_KL] = &c3_sys_pwm_kl.hw,
1882
+
[CLKID_SYS_PWM_IJ] = &c3_sys_pwm_ij.hw,
1883
+
[CLKID_SYS_USB] = &c3_sys_usb.hw,
1884
+
[CLKID_SYS_SD_EMMC_A] = &c3_sys_sd_emmc_a.hw,
1885
+
[CLKID_SYS_SD_EMMC_C] = &c3_sys_sd_emmc_c.hw,
1886
+
[CLKID_SYS_PWM_AB] = &c3_sys_pwm_ab.hw,
1887
+
[CLKID_SYS_PWM_CD] = &c3_sys_pwm_cd.hw,
1888
+
[CLKID_SYS_PWM_EF] = &c3_sys_pwm_ef.hw,
1889
+
[CLKID_SYS_PWM_GH] = &c3_sys_pwm_gh.hw,
1890
+
[CLKID_SYS_SPICC_1] = &c3_sys_spicc_1.hw,
1891
+
[CLKID_SYS_SPICC_0] = &c3_sys_spicc_0.hw,
1892
+
[CLKID_SYS_UART_A] = &c3_sys_uart_a.hw,
1893
+
[CLKID_SYS_UART_B] = &c3_sys_uart_b.hw,
1894
+
[CLKID_SYS_UART_C] = &c3_sys_uart_c.hw,
1895
+
[CLKID_SYS_UART_D] = &c3_sys_uart_d.hw,
1896
+
[CLKID_SYS_UART_E] = &c3_sys_uart_e.hw,
1897
+
[CLKID_SYS_I2C_M_A] = &c3_sys_i2c_m_a.hw,
1898
+
[CLKID_SYS_I2C_M_B] = &c3_sys_i2c_m_b.hw,
1899
+
[CLKID_SYS_I2C_M_C] = &c3_sys_i2c_m_c.hw,
1900
+
[CLKID_SYS_I2C_M_D] = &c3_sys_i2c_m_d.hw,
1901
+
[CLKID_SYS_I2S_S_A] = &c3_sys_i2c_s_a.hw,
1902
+
[CLKID_SYS_RTC] = &c3_sys_rtc.hw,
1903
+
[CLKID_SYS_GE2D] = &c3_sys_ge2d.hw,
1904
+
[CLKID_SYS_ISP] = &c3_sys_isp.hw,
1905
+
[CLKID_SYS_GPV_ISP_NIC] = &c3_sys_gpv_isp_nic.hw,
1906
+
[CLKID_SYS_GPV_CVE_NIC] = &c3_sys_gpv_cve_nic.hw,
1907
+
[CLKID_SYS_MIPI_DSI_HOST] = &c3_sys_mipi_dsi_host.hw,
1908
+
[CLKID_SYS_MIPI_DSI_PHY] = &c3_sys_mipi_dsi_phy.hw,
1909
+
[CLKID_SYS_ETH_PHY] = &c3_sys_eth_phy.hw,
1910
+
[CLKID_SYS_ACODEC] = &c3_sys_acodec.hw,
1911
+
[CLKID_SYS_DWAP] = &c3_sys_dwap.hw,
1912
+
[CLKID_SYS_DOS] = &c3_sys_dos.hw,
1913
+
[CLKID_SYS_CVE] = &c3_sys_cve.hw,
1914
+
[CLKID_SYS_VOUT] = &c3_sys_vout.hw,
1915
+
[CLKID_SYS_VC9000E] = &c3_sys_vc9000e.hw,
1916
+
[CLKID_SYS_PWM_MN] = &c3_sys_pwm_mn.hw,
1917
+
[CLKID_SYS_SD_EMMC_B] = &c3_sys_sd_emmc_b.hw,
1918
+
[CLKID_AXI_SYS_NIC] = &c3_axi_sys_nic.hw,
1919
+
[CLKID_AXI_ISP_NIC] = &c3_axi_isp_nic.hw,
1920
+
[CLKID_AXI_CVE_NIC] = &c3_axi_cve_nic.hw,
1921
+
[CLKID_AXI_RAMB] = &c3_axi_ramb.hw,
1922
+
[CLKID_AXI_RAMA] = &c3_axi_rama.hw,
1923
+
[CLKID_AXI_CPU_DMC] = &c3_axi_cpu_dmc.hw,
1924
+
[CLKID_AXI_NIC] = &c3_axi_nic.hw,
1925
+
[CLKID_AXI_DMA] = &c3_axi_dma.hw,
1926
+
[CLKID_AXI_MUX_NIC] = &c3_axi_mux_nic.hw,
1927
+
[CLKID_AXI_CVE] = &c3_axi_cve.hw,
1928
+
[CLKID_AXI_DEV1_DMC] = &c3_axi_dev1_dmc.hw,
1929
+
[CLKID_AXI_DEV0_DMC] = &c3_axi_dev0_dmc.hw,
1930
+
[CLKID_AXI_DSP_DMC] = &c3_axi_dsp_dmc.hw,
1931
+
[CLKID_12_24M_IN] = &c3_clk_12_24m_in.hw,
1932
+
[CLKID_12M_24M] = &c3_clk_12_24m.hw,
1933
+
[CLKID_FCLK_25M_DIV] = &c3_fclk_25m_div.hw,
1934
+
[CLKID_FCLK_25M] = &c3_fclk_25m.hw,
1935
+
[CLKID_GEN_SEL] = &c3_gen_sel.hw,
1936
+
[CLKID_GEN_DIV] = &c3_gen_div.hw,
1937
+
[CLKID_GEN] = &c3_gen.hw,
1938
+
[CLKID_SARADC_SEL] = &c3_saradc_sel.hw,
1939
+
[CLKID_SARADC_DIV] = &c3_saradc_div.hw,
1940
+
[CLKID_SARADC] = &c3_saradc.hw,
1941
+
[CLKID_PWM_A_SEL] = &c3_pwm_a_sel.hw,
1942
+
[CLKID_PWM_A_DIV] = &c3_pwm_a_div.hw,
1943
+
[CLKID_PWM_A] = &c3_pwm_a.hw,
1944
+
[CLKID_PWM_B_SEL] = &c3_pwm_b_sel.hw,
1945
+
[CLKID_PWM_B_DIV] = &c3_pwm_b_div.hw,
1946
+
[CLKID_PWM_B] = &c3_pwm_b.hw,
1947
+
[CLKID_PWM_C_SEL] = &c3_pwm_c_sel.hw,
1948
+
[CLKID_PWM_C_DIV] = &c3_pwm_c_div.hw,
1949
+
[CLKID_PWM_C] = &c3_pwm_c.hw,
1950
+
[CLKID_PWM_D_SEL] = &c3_pwm_d_sel.hw,
1951
+
[CLKID_PWM_D_DIV] = &c3_pwm_d_div.hw,
1952
+
[CLKID_PWM_D] = &c3_pwm_d.hw,
1953
+
[CLKID_PWM_E_SEL] = &c3_pwm_e_sel.hw,
1954
+
[CLKID_PWM_E_DIV] = &c3_pwm_e_div.hw,
1955
+
[CLKID_PWM_E] = &c3_pwm_e.hw,
1956
+
[CLKID_PWM_F_SEL] = &c3_pwm_f_sel.hw,
1957
+
[CLKID_PWM_F_DIV] = &c3_pwm_f_div.hw,
1958
+
[CLKID_PWM_F] = &c3_pwm_f.hw,
1959
+
[CLKID_PWM_G_SEL] = &c3_pwm_g_sel.hw,
1960
+
[CLKID_PWM_G_DIV] = &c3_pwm_g_div.hw,
1961
+
[CLKID_PWM_G] = &c3_pwm_g.hw,
1962
+
[CLKID_PWM_H_SEL] = &c3_pwm_h_sel.hw,
1963
+
[CLKID_PWM_H_DIV] = &c3_pwm_h_div.hw,
1964
+
[CLKID_PWM_H] = &c3_pwm_h.hw,
1965
+
[CLKID_PWM_I_SEL] = &c3_pwm_i_sel.hw,
1966
+
[CLKID_PWM_I_DIV] = &c3_pwm_i_div.hw,
1967
+
[CLKID_PWM_I] = &c3_pwm_i.hw,
1968
+
[CLKID_PWM_J_SEL] = &c3_pwm_j_sel.hw,
1969
+
[CLKID_PWM_J_DIV] = &c3_pwm_j_div.hw,
1970
+
[CLKID_PWM_J] = &c3_pwm_j.hw,
1971
+
[CLKID_PWM_K_SEL] = &c3_pwm_k_sel.hw,
1972
+
[CLKID_PWM_K_DIV] = &c3_pwm_k_div.hw,
1973
+
[CLKID_PWM_K] = &c3_pwm_k.hw,
1974
+
[CLKID_PWM_L_SEL] = &c3_pwm_l_sel.hw,
1975
+
[CLKID_PWM_L_DIV] = &c3_pwm_l_div.hw,
1976
+
[CLKID_PWM_L] = &c3_pwm_l.hw,
1977
+
[CLKID_PWM_M_SEL] = &c3_pwm_m_sel.hw,
1978
+
[CLKID_PWM_M_DIV] = &c3_pwm_m_div.hw,
1979
+
[CLKID_PWM_M] = &c3_pwm_m.hw,
1980
+
[CLKID_PWM_N_SEL] = &c3_pwm_n_sel.hw,
1981
+
[CLKID_PWM_N_DIV] = &c3_pwm_n_div.hw,
1982
+
[CLKID_PWM_N] = &c3_pwm_n.hw,
1983
+
[CLKID_SPICC_A_SEL] = &c3_spicc_a_sel.hw,
1984
+
[CLKID_SPICC_A_DIV] = &c3_spicc_a_div.hw,
1985
+
[CLKID_SPICC_A] = &c3_spicc_a.hw,
1986
+
[CLKID_SPICC_B_SEL] = &c3_spicc_b_sel.hw,
1987
+
[CLKID_SPICC_B_DIV] = &c3_spicc_b_div.hw,
1988
+
[CLKID_SPICC_B] = &c3_spicc_b.hw,
1989
+
[CLKID_SPIFC_SEL] = &c3_spifc_sel.hw,
1990
+
[CLKID_SPIFC_DIV] = &c3_spifc_div.hw,
1991
+
[CLKID_SPIFC] = &c3_spifc.hw,
1992
+
[CLKID_SD_EMMC_A_SEL] = &c3_sd_emmc_a_sel.hw,
1993
+
[CLKID_SD_EMMC_A_DIV] = &c3_sd_emmc_a_div.hw,
1994
+
[CLKID_SD_EMMC_A] = &c3_sd_emmc_a.hw,
1995
+
[CLKID_SD_EMMC_B_SEL] = &c3_sd_emmc_b_sel.hw,
1996
+
[CLKID_SD_EMMC_B_DIV] = &c3_sd_emmc_b_div.hw,
1997
+
[CLKID_SD_EMMC_B] = &c3_sd_emmc_b.hw,
1998
+
[CLKID_SD_EMMC_C_SEL] = &c3_sd_emmc_c_sel.hw,
1999
+
[CLKID_SD_EMMC_C_DIV] = &c3_sd_emmc_c_div.hw,
2000
+
[CLKID_SD_EMMC_C] = &c3_sd_emmc_c.hw,
2001
+
[CLKID_TS_DIV] = &c3_ts_div.hw,
2002
+
[CLKID_TS] = &c3_ts.hw,
2003
+
[CLKID_ETH_125M_DIV] = &c3_eth_125m_div.hw,
2004
+
[CLKID_ETH_125M] = &c3_eth_125m.hw,
2005
+
[CLKID_ETH_RMII_DIV] = &c3_eth_rmii_div.hw,
2006
+
[CLKID_ETH_RMII] = &c3_eth_rmii.hw,
2007
+
[CLKID_MIPI_DSI_MEAS_SEL] = &c3_mipi_dsi_meas_sel.hw,
2008
+
[CLKID_MIPI_DSI_MEAS_DIV] = &c3_mipi_dsi_meas_div.hw,
2009
+
[CLKID_MIPI_DSI_MEAS] = &c3_mipi_dsi_meas.hw,
2010
+
[CLKID_DSI_PHY_SEL] = &c3_dsi_phy_sel.hw,
2011
+
[CLKID_DSI_PHY_DIV] = &c3_dsi_phy_div.hw,
2012
+
[CLKID_DSI_PHY] = &c3_dsi_phy.hw,
2013
+
[CLKID_VOUT_MCLK_SEL] = &c3_vout_mclk_sel.hw,
2014
+
[CLKID_VOUT_MCLK_DIV] = &c3_vout_mclk_div.hw,
2015
+
[CLKID_VOUT_MCLK] = &c3_vout_mclk.hw,
2016
+
[CLKID_VOUT_ENC_SEL] = &c3_vout_enc_sel.hw,
2017
+
[CLKID_VOUT_ENC_DIV] = &c3_vout_enc_div.hw,
2018
+
[CLKID_VOUT_ENC] = &c3_vout_enc.hw,
2019
+
[CLKID_HCODEC_0_SEL] = &c3_hcodec_0_sel.hw,
2020
+
[CLKID_HCODEC_0_DIV] = &c3_hcodec_0_div.hw,
2021
+
[CLKID_HCODEC_0] = &c3_hcodec_0.hw,
2022
+
[CLKID_HCODEC_1_SEL] = &c3_hcodec_1_sel.hw,
2023
+
[CLKID_HCODEC_1_DIV] = &c3_hcodec_1_div.hw,
2024
+
[CLKID_HCODEC_1] = &c3_hcodec_1.hw,
2025
+
[CLKID_HCODEC] = &c3_hcodec.hw,
2026
+
[CLKID_VC9000E_ACLK_SEL] = &c3_vc9000e_aclk_sel.hw,
2027
+
[CLKID_VC9000E_ACLK_DIV] = &c3_vc9000e_aclk_div.hw,
2028
+
[CLKID_VC9000E_ACLK] = &c3_vc9000e_aclk.hw,
2029
+
[CLKID_VC9000E_CORE_SEL] = &c3_vc9000e_core_sel.hw,
2030
+
[CLKID_VC9000E_CORE_DIV] = &c3_vc9000e_core_div.hw,
2031
+
[CLKID_VC9000E_CORE] = &c3_vc9000e_core.hw,
2032
+
[CLKID_CSI_PHY0_SEL] = &c3_csi_phy0_sel.hw,
2033
+
[CLKID_CSI_PHY0_DIV] = &c3_csi_phy0_div.hw,
2034
+
[CLKID_CSI_PHY0] = &c3_csi_phy0.hw,
2035
+
[CLKID_DEWARPA_SEL] = &c3_dewarpa_sel.hw,
2036
+
[CLKID_DEWARPA_DIV] = &c3_dewarpa_div.hw,
2037
+
[CLKID_DEWARPA] = &c3_dewarpa.hw,
2038
+
[CLKID_ISP0_SEL] = &c3_isp0_sel.hw,
2039
+
[CLKID_ISP0_DIV] = &c3_isp0_div.hw,
2040
+
[CLKID_ISP0] = &c3_isp0.hw,
2041
+
[CLKID_NNA_CORE_SEL] = &c3_nna_core_sel.hw,
2042
+
[CLKID_NNA_CORE_DIV] = &c3_nna_core_div.hw,
2043
+
[CLKID_NNA_CORE] = &c3_nna_core.hw,
2044
+
[CLKID_GE2D_SEL] = &c3_ge2d_sel.hw,
2045
+
[CLKID_GE2D_DIV] = &c3_ge2d_div.hw,
2046
+
[CLKID_GE2D] = &c3_ge2d.hw,
2047
+
[CLKID_VAPB_SEL] = &c3_vapb_sel.hw,
2048
+
[CLKID_VAPB_DIV] = &c3_vapb_div.hw,
2049
+
[CLKID_VAPB] = &c3_vapb.hw,
903
2050
};
904
2051
905
-
static struct clk_regmap vapb_div = {
906
-
.data = &(struct clk_regmap_div_data) {
907
-
.offset = VAPB_CLK_CTRL,
908
-
.shift = 0,
909
-
.width = 7,
910
-
},
911
-
.hw.init = &(struct clk_init_data) {
912
-
.name = "vapb_div",
913
-
.ops = &clk_regmap_divider_ops,
914
-
.parent_hws = (const struct clk_hw *[]) {
915
-
&vapb_sel.hw
916
-
},
917
-
.num_parents = 1,
918
-
.flags = CLK_SET_RATE_PARENT,
2052
+
static const struct meson_clkc_data c3_peripherals_clkc_data = {
2053
+
.hw_clks = {
2054
+
.hws = c3_peripherals_hw_clks,
2055
+
.num = ARRAY_SIZE(c3_peripherals_hw_clks),
919
2056
},
920
2057
};
921
-
922
-
static struct clk_regmap vapb = {
923
-
.data = &(struct clk_regmap_gate_data) {
924
-
.offset = VAPB_CLK_CTRL,
925
-
.bit_idx = 8,
926
-
},
927
-
.hw.init = &(struct clk_init_data) {
928
-
.name = "vapb",
929
-
.ops = &clk_regmap_gate_ops,
930
-
.parent_hws = (const struct clk_hw *[]) {
931
-
&vapb_div.hw
932
-
},
933
-
.num_parents = 1,
934
-
.flags = CLK_SET_RATE_PARENT,
935
-
},
936
-
};
937
-
938
-
static struct clk_hw *c3_periphs_hw_clks[] = {
939
-
[CLKID_RTC_XTAL_CLKIN] = &rtc_xtal_clkin.hw,
940
-
[CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
941
-
[CLKID_RTC_32K_MUX] = &rtc_32k_mux.hw,
942
-
[CLKID_RTC_32K] = &rtc_32k.hw,
943
-
[CLKID_RTC_CLK] = &rtc_clk.hw,
944
-
[CLKID_SYS_RESET_CTRL] = &sys_reset_ctrl.hw,
945
-
[CLKID_SYS_PWR_CTRL] = &sys_pwr_ctrl.hw,
946
-
[CLKID_SYS_PAD_CTRL] = &sys_pad_ctrl.hw,
947
-
[CLKID_SYS_CTRL] = &sys_ctrl.hw,
948
-
[CLKID_SYS_TS_PLL] = &sys_ts_pll.hw,
949
-
[CLKID_SYS_DEV_ARB] = &sys_dev_arb.hw,
950
-
[CLKID_SYS_MMC_PCLK] = &sys_mmc_pclk.hw,
951
-
[CLKID_SYS_CPU_CTRL] = &sys_cpu_ctrl.hw,
952
-
[CLKID_SYS_JTAG_CTRL] = &sys_jtag_ctrl.hw,
953
-
[CLKID_SYS_IR_CTRL] = &sys_ir_ctrl.hw,
954
-
[CLKID_SYS_IRQ_CTRL] = &sys_irq_ctrl.hw,
955
-
[CLKID_SYS_MSR_CLK] = &sys_msr_clk.hw,
956
-
[CLKID_SYS_ROM] = &sys_rom.hw,
957
-
[CLKID_SYS_UART_F] = &sys_uart_f.hw,
958
-
[CLKID_SYS_CPU_ARB] = &sys_cpu_apb.hw,
959
-
[CLKID_SYS_RSA] = &sys_rsa.hw,
960
-
[CLKID_SYS_SAR_ADC] = &sys_sar_adc.hw,
961
-
[CLKID_SYS_STARTUP] = &sys_startup.hw,
962
-
[CLKID_SYS_SECURE] = &sys_secure.hw,
963
-
[CLKID_SYS_SPIFC] = &sys_spifc.hw,
964
-
[CLKID_SYS_NNA] = &sys_nna.hw,
965
-
[CLKID_SYS_ETH_MAC] = &sys_eth_mac.hw,
966
-
[CLKID_SYS_GIC] = &sys_gic.hw,
967
-
[CLKID_SYS_RAMA] = &sys_rama.hw,
968
-
[CLKID_SYS_BIG_NIC] = &sys_big_nic.hw,
969
-
[CLKID_SYS_RAMB] = &sys_ramb.hw,
970
-
[CLKID_SYS_AUDIO_PCLK] = &sys_audio_pclk.hw,
971
-
[CLKID_SYS_PWM_KL] = &sys_pwm_kl.hw,
972
-
[CLKID_SYS_PWM_IJ] = &sys_pwm_ij.hw,
973
-
[CLKID_SYS_USB] = &sys_usb.hw,
974
-
[CLKID_SYS_SD_EMMC_A] = &sys_sd_emmc_a.hw,
975
-
[CLKID_SYS_SD_EMMC_C] = &sys_sd_emmc_c.hw,
976
-
[CLKID_SYS_PWM_AB] = &sys_pwm_ab.hw,
977
-
[CLKID_SYS_PWM_CD] = &sys_pwm_cd.hw,
978
-
[CLKID_SYS_PWM_EF] = &sys_pwm_ef.hw,
979
-
[CLKID_SYS_PWM_GH] = &sys_pwm_gh.hw,
980
-
[CLKID_SYS_SPICC_1] = &sys_spicc_1.hw,
981
-
[CLKID_SYS_SPICC_0] = &sys_spicc_0.hw,
982
-
[CLKID_SYS_UART_A] = &sys_uart_a.hw,
983
-
[CLKID_SYS_UART_B] = &sys_uart_b.hw,
984
-
[CLKID_SYS_UART_C] = &sys_uart_c.hw,
985
-
[CLKID_SYS_UART_D] = &sys_uart_d.hw,
986
-
[CLKID_SYS_UART_E] = &sys_uart_e.hw,
987
-
[CLKID_SYS_I2C_M_A] = &sys_i2c_m_a.hw,
988
-
[CLKID_SYS_I2C_M_B] = &sys_i2c_m_b.hw,
989
-
[CLKID_SYS_I2C_M_C] = &sys_i2c_m_c.hw,
990
-
[CLKID_SYS_I2C_M_D] = &sys_i2c_m_d.hw,
991
-
[CLKID_SYS_I2S_S_A] = &sys_i2c_s_a.hw,
992
-
[CLKID_SYS_RTC] = &sys_rtc.hw,
993
-
[CLKID_SYS_GE2D] = &sys_ge2d.hw,
994
-
[CLKID_SYS_ISP] = &sys_isp.hw,
995
-
[CLKID_SYS_GPV_ISP_NIC] = &sys_gpv_isp_nic.hw,
996
-
[CLKID_SYS_GPV_CVE_NIC] = &sys_gpv_cve_nic.hw,
997
-
[CLKID_SYS_MIPI_DSI_HOST] = &sys_mipi_dsi_host.hw,
998
-
[CLKID_SYS_MIPI_DSI_PHY] = &sys_mipi_dsi_phy.hw,
999
-
[CLKID_SYS_ETH_PHY] = &sys_eth_phy.hw,
1000
-
[CLKID_SYS_ACODEC] = &sys_acodec.hw,
1001
-
[CLKID_SYS_DWAP] = &sys_dwap.hw,
1002
-
[CLKID_SYS_DOS] = &sys_dos.hw,
1003
-
[CLKID_SYS_CVE] = &sys_cve.hw,
1004
-
[CLKID_SYS_VOUT] = &sys_vout.hw,
1005
-
[CLKID_SYS_VC9000E] = &sys_vc9000e.hw,
1006
-
[CLKID_SYS_PWM_MN] = &sys_pwm_mn.hw,
1007
-
[CLKID_SYS_SD_EMMC_B] = &sys_sd_emmc_b.hw,
1008
-
[CLKID_AXI_SYS_NIC] = &axi_sys_nic.hw,
1009
-
[CLKID_AXI_ISP_NIC] = &axi_isp_nic.hw,
1010
-
[CLKID_AXI_CVE_NIC] = &axi_cve_nic.hw,
1011
-
[CLKID_AXI_RAMB] = &axi_ramb.hw,
1012
-
[CLKID_AXI_RAMA] = &axi_rama.hw,
1013
-
[CLKID_AXI_CPU_DMC] = &axi_cpu_dmc.hw,
1014
-
[CLKID_AXI_NIC] = &axi_nic.hw,
1015
-
[CLKID_AXI_DMA] = &axi_dma.hw,
1016
-
[CLKID_AXI_MUX_NIC] = &axi_mux_nic.hw,
1017
-
[CLKID_AXI_CVE] = &axi_cve.hw,
1018
-
[CLKID_AXI_DEV1_DMC] = &axi_dev1_dmc.hw,
1019
-
[CLKID_AXI_DEV0_DMC] = &axi_dev0_dmc.hw,
1020
-
[CLKID_AXI_DSP_DMC] = &axi_dsp_dmc.hw,
1021
-
[CLKID_12_24M_IN] = &clk_12_24m_in.hw,
1022
-
[CLKID_12M_24M] = &clk_12_24m.hw,
1023
-
[CLKID_FCLK_25M_DIV] = &fclk_25m_div.hw,
1024
-
[CLKID_FCLK_25M] = &fclk_25m.hw,
1025
-
[CLKID_GEN_SEL] = &gen_sel.hw,
1026
-
[CLKID_GEN_DIV] = &gen_div.hw,
1027
-
[CLKID_GEN] = &gen.hw,
1028
-
[CLKID_SARADC_SEL] = &saradc_sel.hw,
1029
-
[CLKID_SARADC_DIV] = &saradc_div.hw,
1030
-
[CLKID_SARADC] = &saradc.hw,
1031
-
[CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
1032
-
[CLKID_PWM_A_DIV] = &pwm_a_div.hw,
1033
-
[CLKID_PWM_A] = &pwm_a.hw,
1034
-
[CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
1035
-
[CLKID_PWM_B_DIV] = &pwm_b_div.hw,
1036
-
[CLKID_PWM_B] = &pwm_b.hw,
1037
-
[CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
1038
-
[CLKID_PWM_C_DIV] = &pwm_c_div.hw,
1039
-
[CLKID_PWM_C] = &pwm_c.hw,
1040
-
[CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
1041
-
[CLKID_PWM_D_DIV] = &pwm_d_div.hw,
1042
-
[CLKID_PWM_D] = &pwm_d.hw,
1043
-
[CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
1044
-
[CLKID_PWM_E_DIV] = &pwm_e_div.hw,
1045
-
[CLKID_PWM_E] = &pwm_e.hw,
1046
-
[CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
1047
-
[CLKID_PWM_F_DIV] = &pwm_f_div.hw,
1048
-
[CLKID_PWM_F] = &pwm_f.hw,
1049
-
[CLKID_PWM_G_SEL] = &pwm_g_sel.hw,
1050
-
[CLKID_PWM_G_DIV] = &pwm_g_div.hw,
1051
-
[CLKID_PWM_G] = &pwm_g.hw,
1052
-
[CLKID_PWM_H_SEL] = &pwm_h_sel.hw,
1053
-
[CLKID_PWM_H_DIV] = &pwm_h_div.hw,
1054
-
[CLKID_PWM_H] = &pwm_h.hw,
1055
-
[CLKID_PWM_I_SEL] = &pwm_i_sel.hw,
1056
-
[CLKID_PWM_I_DIV] = &pwm_i_div.hw,
1057
-
[CLKID_PWM_I] = &pwm_i.hw,
1058
-
[CLKID_PWM_J_SEL] = &pwm_j_sel.hw,
1059
-
[CLKID_PWM_J_DIV] = &pwm_j_div.hw,
1060
-
[CLKID_PWM_J] = &pwm_j.hw,
1061
-
[CLKID_PWM_K_SEL] = &pwm_k_sel.hw,
1062
-
[CLKID_PWM_K_DIV] = &pwm_k_div.hw,
1063
-
[CLKID_PWM_K] = &pwm_k.hw,
1064
-
[CLKID_PWM_L_SEL] = &pwm_l_sel.hw,
1065
-
[CLKID_PWM_L_DIV] = &pwm_l_div.hw,
1066
-
[CLKID_PWM_L] = &pwm_l.hw,
1067
-
[CLKID_PWM_M_SEL] = &pwm_m_sel.hw,
1068
-
[CLKID_PWM_M_DIV] = &pwm_m_div.hw,
1069
-
[CLKID_PWM_M] = &pwm_m.hw,
1070
-
[CLKID_PWM_N_SEL] = &pwm_n_sel.hw,
1071
-
[CLKID_PWM_N_DIV] = &pwm_n_div.hw,
1072
-
[CLKID_PWM_N] = &pwm_n.hw,
1073
-
[CLKID_SPICC_A_SEL] = &spicc_a_sel.hw,
1074
-
[CLKID_SPICC_A_DIV] = &spicc_a_div.hw,
1075
-
[CLKID_SPICC_A] = &spicc_a.hw,
1076
-
[CLKID_SPICC_B_SEL] = &spicc_b_sel.hw,
1077
-
[CLKID_SPICC_B_DIV] = &spicc_b_div.hw,
1078
-
[CLKID_SPICC_B] = &spicc_b.hw,
1079
-
[CLKID_SPIFC_SEL] = &spifc_sel.hw,
1080
-
[CLKID_SPIFC_DIV] = &spifc_div.hw,
1081
-
[CLKID_SPIFC] = &spifc.hw,
1082
-
[CLKID_SD_EMMC_A_SEL] = &sd_emmc_a_sel.hw,
1083
-
[CLKID_SD_EMMC_A_DIV] = &sd_emmc_a_div.hw,
1084
-
[CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
1085
-
[CLKID_SD_EMMC_B_SEL] = &sd_emmc_b_sel.hw,
1086
-
[CLKID_SD_EMMC_B_DIV] = &sd_emmc_b_div.hw,
1087
-
[CLKID_SD_EMMC_B] = &sd_emmc_b.hw,
1088
-
[CLKID_SD_EMMC_C_SEL] = &sd_emmc_c_sel.hw,
1089
-
[CLKID_SD_EMMC_C_DIV] = &sd_emmc_c_div.hw,
1090
-
[CLKID_SD_EMMC_C] = &sd_emmc_c.hw,
1091
-
[CLKID_TS_DIV] = &ts_div.hw,
1092
-
[CLKID_TS] = &ts.hw,
1093
-
[CLKID_ETH_125M_DIV] = ð_125m_div.hw,
1094
-
[CLKID_ETH_125M] = ð_125m.hw,
1095
-
[CLKID_ETH_RMII_DIV] = ð_rmii_div.hw,
1096
-
[CLKID_ETH_RMII] = ð_rmii.hw,
1097
-
[CLKID_MIPI_DSI_MEAS_SEL] = &mipi_dsi_meas_sel.hw,
1098
-
[CLKID_MIPI_DSI_MEAS_DIV] = &mipi_dsi_meas_div.hw,
1099
-
[CLKID_MIPI_DSI_MEAS] = &mipi_dsi_meas.hw,
1100
-
[CLKID_DSI_PHY_SEL] = &dsi_phy_sel.hw,
1101
-
[CLKID_DSI_PHY_DIV] = &dsi_phy_div.hw,
1102
-
[CLKID_DSI_PHY] = &dsi_phy.hw,
1103
-
[CLKID_VOUT_MCLK_SEL] = &vout_mclk_sel.hw,
1104
-
[CLKID_VOUT_MCLK_DIV] = &vout_mclk_div.hw,
1105
-
[CLKID_VOUT_MCLK] = &vout_mclk.hw,
1106
-
[CLKID_VOUT_ENC_SEL] = &vout_enc_sel.hw,
1107
-
[CLKID_VOUT_ENC_DIV] = &vout_enc_div.hw,
1108
-
[CLKID_VOUT_ENC] = &vout_enc.hw,
1109
-
[CLKID_HCODEC_0_SEL] = &hcodec_0_sel.hw,
1110
-
[CLKID_HCODEC_0_DIV] = &hcodec_0_div.hw,
1111
-
[CLKID_HCODEC_0] = &hcodec_0.hw,
1112
-
[CLKID_HCODEC_1_SEL] = &hcodec_1_sel.hw,
1113
-
[CLKID_HCODEC_1_DIV] = &hcodec_1_div.hw,
1114
-
[CLKID_HCODEC_1] = &hcodec_1.hw,
1115
-
[CLKID_HCODEC] = &hcodec.hw,
1116
-
[CLKID_VC9000E_ACLK_SEL] = &vc9000e_aclk_sel.hw,
1117
-
[CLKID_VC9000E_ACLK_DIV] = &vc9000e_aclk_div.hw,
1118
-
[CLKID_VC9000E_ACLK] = &vc9000e_aclk.hw,
1119
-
[CLKID_VC9000E_CORE_SEL] = &vc9000e_core_sel.hw,
1120
-
[CLKID_VC9000E_CORE_DIV] = &vc9000e_core_div.hw,
1121
-
[CLKID_VC9000E_CORE] = &vc9000e_core.hw,
1122
-
[CLKID_CSI_PHY0_SEL] = &csi_phy0_sel.hw,
1123
-
[CLKID_CSI_PHY0_DIV] = &csi_phy0_div.hw,
1124
-
[CLKID_CSI_PHY0] = &csi_phy0.hw,
1125
-
[CLKID_DEWARPA_SEL] = &dewarpa_sel.hw,
1126
-
[CLKID_DEWARPA_DIV] = &dewarpa_div.hw,
1127
-
[CLKID_DEWARPA] = &dewarpa.hw,
1128
-
[CLKID_ISP0_SEL] = &isp0_sel.hw,
1129
-
[CLKID_ISP0_DIV] = &isp0_div.hw,
1130
-
[CLKID_ISP0] = &isp0.hw,
1131
-
[CLKID_NNA_CORE_SEL] = &nna_core_sel.hw,
1132
-
[CLKID_NNA_CORE_DIV] = &nna_core_div.hw,
1133
-
[CLKID_NNA_CORE] = &nna_core.hw,
1134
-
[CLKID_GE2D_SEL] = &ge2d_sel.hw,
1135
-
[CLKID_GE2D_DIV] = &ge2d_div.hw,
1136
-
[CLKID_GE2D] = &ge2d.hw,
1137
-
[CLKID_VAPB_SEL] = &vapb_sel.hw,
1138
-
[CLKID_VAPB_DIV] = &vapb_div.hw,
1139
-
[CLKID_VAPB] = &vapb.hw,
1140
-
};
1141
-
1142
-
static const struct regmap_config clkc_regmap_config = {
1143
-
.reg_bits = 32,
1144
-
.val_bits = 32,
1145
-
.reg_stride = 4,
1146
-
.max_register = NNA_CLK_CTRL,
1147
-
};
1148
-
1149
-
static struct meson_clk_hw_data c3_periphs_clks = {
1150
-
.hws = c3_periphs_hw_clks,
1151
-
.num = ARRAY_SIZE(c3_periphs_hw_clks),
1152
-
};
1153
-
1154
-
static int c3_peripherals_probe(struct platform_device *pdev)
1155
-
{
1156
-
struct device *dev = &pdev->dev;
1157
-
struct regmap *regmap;
1158
-
void __iomem *base;
1159
-
int clkid, ret;
1160
-
1161
-
base = devm_platform_ioremap_resource(pdev, 0);
1162
-
if (IS_ERR(base))
1163
-
return PTR_ERR(base);
1164
-
1165
-
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
1166
-
if (IS_ERR(regmap))
1167
-
return PTR_ERR(regmap);
1168
-
1169
-
for (clkid = 0; clkid < c3_periphs_clks.num; clkid++) {
1170
-
/* array might be sparse */
1171
-
if (!c3_periphs_clks.hws[clkid])
1172
-
continue;
1173
-
1174
-
ret = devm_clk_hw_register(dev, c3_periphs_clks.hws[clkid]);
1175
-
if (ret) {
1176
-
dev_err(dev, "Clock registration failed\n");
1177
-
return ret;
1178
-
}
1179
-
}
1180
-
1181
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
1182
-
&c3_periphs_clks);
1183
-
}
1184
2058
1185
2059
static const struct of_device_id c3_peripherals_clkc_match_table[] = {
1186
2060
{
1187
2061
.compatible = "amlogic,c3-peripherals-clkc",
2062
+
.data = &c3_peripherals_clkc_data,
1188
2063
},
1189
2064
{ /* sentinel */ }
1190
2065
};
1191
2066
1192
2067
MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table);
1193
2068
1194
-
static struct platform_driver c3_peripherals_driver = {
1195
-
.probe = c3_peripherals_probe,
2069
+
static struct platform_driver c3_peripherals_clkc_driver = {
2070
+
.probe = meson_clkc_mmio_probe,
1196
2071
.driver = {
1197
2072
.name = "c3-peripherals-clkc",
1198
2073
.of_match_table = c3_peripherals_clkc_match_table,
1199
2074
},
1200
2075
};
1201
-
module_platform_driver(c3_peripherals_driver);
2076
+
module_platform_driver(c3_peripherals_clkc_driver);
1202
2077
1203
2078
MODULE_DESCRIPTION("Amlogic C3 Peripherals Clock Controller driver");
1204
2079
MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
+102
-137
drivers/clk/meson/c3-pll.c
+102
-137
drivers/clk/meson/c3-pll.c
···
34
34
#define ANACTRL_MPLL_CTRL3 0x18c
35
35
#define ANACTRL_MPLL_CTRL4 0x190
36
36
37
-
static struct clk_regmap fclk_50m_en = {
37
+
static struct clk_regmap c3_fclk_50m_en = {
38
38
.data = &(struct clk_regmap_gate_data) {
39
39
.offset = ANACTRL_FIXPLL_CTRL4,
40
40
.bit_idx = 0,
···
49
49
},
50
50
};
51
51
52
-
static struct clk_fixed_factor fclk_50m = {
52
+
static struct clk_fixed_factor c3_fclk_50m = {
53
53
.mult = 1,
54
54
.div = 40,
55
55
.hw.init = &(struct clk_init_data) {
56
56
.name = "fclk_50m",
57
57
.ops = &clk_fixed_factor_ops,
58
58
.parent_hws = (const struct clk_hw *[]) {
59
-
&fclk_50m_en.hw
59
+
&c3_fclk_50m_en.hw
60
60
},
61
61
.num_parents = 1,
62
62
},
63
63
};
64
64
65
-
static struct clk_fixed_factor fclk_div2_div = {
65
+
static struct clk_fixed_factor c3_fclk_div2_div = {
66
66
.mult = 1,
67
67
.div = 2,
68
68
.hw.init = &(struct clk_init_data) {
···
75
75
},
76
76
};
77
77
78
-
static struct clk_regmap fclk_div2 = {
78
+
static struct clk_regmap c3_fclk_div2 = {
79
79
.data = &(struct clk_regmap_gate_data) {
80
80
.offset = ANACTRL_FIXPLL_CTRL4,
81
81
.bit_idx = 24,
···
84
84
.name = "fclk_div2",
85
85
.ops = &clk_regmap_gate_ro_ops,
86
86
.parent_hws = (const struct clk_hw *[]) {
87
-
&fclk_div2_div.hw
87
+
&c3_fclk_div2_div.hw
88
88
},
89
89
.num_parents = 1,
90
90
},
91
91
};
92
92
93
-
static struct clk_fixed_factor fclk_div2p5_div = {
93
+
static struct clk_fixed_factor c3_fclk_div2p5_div = {
94
94
.mult = 2,
95
95
.div = 5,
96
96
.hw.init = &(struct clk_init_data) {
···
103
103
},
104
104
};
105
105
106
-
static struct clk_regmap fclk_div2p5 = {
106
+
static struct clk_regmap c3_fclk_div2p5 = {
107
107
.data = &(struct clk_regmap_gate_data) {
108
108
.offset = ANACTRL_FIXPLL_CTRL4,
109
109
.bit_idx = 4,
···
112
112
.name = "fclk_div2p5",
113
113
.ops = &clk_regmap_gate_ro_ops,
114
114
.parent_hws = (const struct clk_hw *[]) {
115
-
&fclk_div2p5_div.hw
115
+
&c3_fclk_div2p5_div.hw
116
116
},
117
117
.num_parents = 1,
118
118
},
119
119
};
120
120
121
-
static struct clk_fixed_factor fclk_div3_div = {
121
+
static struct clk_fixed_factor c3_fclk_div3_div = {
122
122
.mult = 1,
123
123
.div = 3,
124
124
.hw.init = &(struct clk_init_data) {
···
131
131
},
132
132
};
133
133
134
-
static struct clk_regmap fclk_div3 = {
134
+
static struct clk_regmap c3_fclk_div3 = {
135
135
.data = &(struct clk_regmap_gate_data) {
136
136
.offset = ANACTRL_FIXPLL_CTRL4,
137
137
.bit_idx = 20,
···
140
140
.name = "fclk_div3",
141
141
.ops = &clk_regmap_gate_ro_ops,
142
142
.parent_hws = (const struct clk_hw *[]) {
143
-
&fclk_div3_div.hw
143
+
&c3_fclk_div3_div.hw
144
144
},
145
145
.num_parents = 1,
146
146
},
147
147
};
148
148
149
-
static struct clk_fixed_factor fclk_div4_div = {
149
+
static struct clk_fixed_factor c3_fclk_div4_div = {
150
150
.mult = 1,
151
151
.div = 4,
152
152
.hw.init = &(struct clk_init_data) {
···
159
159
},
160
160
};
161
161
162
-
static struct clk_regmap fclk_div4 = {
162
+
static struct clk_regmap c3_fclk_div4 = {
163
163
.data = &(struct clk_regmap_gate_data) {
164
164
.offset = ANACTRL_FIXPLL_CTRL4,
165
165
.bit_idx = 21,
···
168
168
.name = "fclk_div4",
169
169
.ops = &clk_regmap_gate_ro_ops,
170
170
.parent_hws = (const struct clk_hw *[]) {
171
-
&fclk_div4_div.hw
171
+
&c3_fclk_div4_div.hw
172
172
},
173
173
.num_parents = 1,
174
174
},
175
175
};
176
176
177
-
static struct clk_fixed_factor fclk_div5_div = {
177
+
static struct clk_fixed_factor c3_fclk_div5_div = {
178
178
.mult = 1,
179
179
.div = 5,
180
180
.hw.init = &(struct clk_init_data) {
···
187
187
},
188
188
};
189
189
190
-
static struct clk_regmap fclk_div5 = {
190
+
static struct clk_regmap c3_fclk_div5 = {
191
191
.data = &(struct clk_regmap_gate_data) {
192
192
.offset = ANACTRL_FIXPLL_CTRL4,
193
193
.bit_idx = 22,
···
196
196
.name = "fclk_div5",
197
197
.ops = &clk_regmap_gate_ro_ops,
198
198
.parent_hws = (const struct clk_hw *[]) {
199
-
&fclk_div5_div.hw
199
+
&c3_fclk_div5_div.hw
200
200
},
201
201
.num_parents = 1,
202
202
},
203
203
};
204
204
205
-
static struct clk_fixed_factor fclk_div7_div = {
205
+
static struct clk_fixed_factor c3_fclk_div7_div = {
206
206
.mult = 1,
207
207
.div = 7,
208
208
.hw.init = &(struct clk_init_data) {
···
215
215
},
216
216
};
217
217
218
-
static struct clk_regmap fclk_div7 = {
218
+
static struct clk_regmap c3_fclk_div7 = {
219
219
.data = &(struct clk_regmap_gate_data) {
220
220
.offset = ANACTRL_FIXPLL_CTRL4,
221
221
.bit_idx = 23,
···
224
224
.name = "fclk_div7",
225
225
.ops = &clk_regmap_gate_ro_ops,
226
226
.parent_hws = (const struct clk_hw *[]) {
227
-
&fclk_div7_div.hw
227
+
&c3_fclk_div7_div.hw
228
228
},
229
229
.num_parents = 1,
230
230
},
231
231
};
232
232
233
-
static const struct reg_sequence c3_gp0_init_regs[] = {
233
+
static const struct reg_sequence c3_gp0_pll_init_regs[] = {
234
234
{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x0 },
235
235
{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
236
236
{ .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
···
243
243
.max = 250,
244
244
};
245
245
246
-
static struct clk_regmap gp0_pll_dco = {
246
+
static struct clk_regmap c3_gp0_pll_dco = {
247
247
.data = &(struct meson_clk_pll_data) {
248
248
.en = {
249
249
.reg_off = ANACTRL_GP0PLL_CTRL0,
···
276
276
.width = 1,
277
277
},
278
278
.range = &c3_gp0_pll_mult_range,
279
-
.init_regs = c3_gp0_init_regs,
280
-
.init_count = ARRAY_SIZE(c3_gp0_init_regs),
279
+
.init_regs = c3_gp0_pll_init_regs,
280
+
.init_count = ARRAY_SIZE(c3_gp0_pll_init_regs),
281
281
},
282
282
.hw.init = &(struct clk_init_data) {
283
283
.name = "gp0_pll_dco",
···
300
300
{ /* sentinel */ }
301
301
};
302
302
303
-
static struct clk_regmap gp0_pll = {
303
+
static struct clk_regmap c3_gp0_pll = {
304
304
.data = &(struct clk_regmap_div_data) {
305
305
.offset = ANACTRL_GP0PLL_CTRL0,
306
306
.shift = 16,
···
311
311
.name = "gp0_pll",
312
312
.ops = &clk_regmap_divider_ops,
313
313
.parent_hws = (const struct clk_hw *[]) {
314
-
&gp0_pll_dco.hw
314
+
&c3_gp0_pll_dco.hw
315
315
},
316
316
.num_parents = 1,
317
317
.flags = CLK_SET_RATE_PARENT,
318
318
},
319
319
};
320
320
321
-
static const struct reg_sequence c3_hifi_init_regs[] = {
321
+
static const struct reg_sequence c3_hifi_pll_init_regs[] = {
322
322
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x0 },
323
323
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
324
324
{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
···
326
326
{ .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 },
327
327
};
328
328
329
-
static struct clk_regmap hifi_pll_dco = {
329
+
static struct clk_regmap c3_hifi_pll_dco = {
330
330
.data = &(struct meson_clk_pll_data) {
331
331
.en = {
332
332
.reg_off = ANACTRL_HIFIPLL_CTRL0,
···
359
359
.width = 1,
360
360
},
361
361
.range = &c3_gp0_pll_mult_range,
362
-
.init_regs = c3_hifi_init_regs,
363
-
.init_count = ARRAY_SIZE(c3_hifi_init_regs),
362
+
.init_regs = c3_hifi_pll_init_regs,
363
+
.init_count = ARRAY_SIZE(c3_hifi_pll_init_regs),
364
364
.frac_max = 100000,
365
365
},
366
366
.hw.init = &(struct clk_init_data) {
···
373
373
},
374
374
};
375
375
376
-
static struct clk_regmap hifi_pll = {
376
+
static struct clk_regmap c3_hifi_pll = {
377
377
.data = &(struct clk_regmap_div_data) {
378
378
.offset = ANACTRL_HIFIPLL_CTRL0,
379
379
.shift = 16,
···
384
384
.name = "hifi_pll",
385
385
.ops = &clk_regmap_divider_ops,
386
386
.parent_hws = (const struct clk_hw *[]) {
387
-
&hifi_pll_dco.hw
387
+
&c3_hifi_pll_dco.hw
388
388
},
389
389
.num_parents = 1,
390
390
.flags = CLK_SET_RATE_PARENT,
391
391
},
392
392
};
393
393
394
-
static const struct reg_sequence c3_mclk_init_regs[] = {
394
+
static const struct reg_sequence c3_mclk_pll_init_regs[] = {
395
395
{ .reg = ANACTRL_MPLL_CTRL1, .def = 0x1420500f },
396
396
{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x00023041 },
397
397
{ .reg = ANACTRL_MPLL_CTRL3, .def = 0x18180000 },
···
403
403
.max = 133,
404
404
};
405
405
406
-
static struct clk_regmap mclk_pll_dco = {
406
+
static struct clk_regmap c3_mclk_pll_dco = {
407
407
.data = &(struct meson_clk_pll_data) {
408
408
.en = {
409
409
.reg_off = ANACTRL_MPLL_CTRL0,
···
431
431
.width = 1,
432
432
},
433
433
.range = &c3_mclk_pll_mult_range,
434
-
.init_regs = c3_mclk_init_regs,
435
-
.init_count = ARRAY_SIZE(c3_mclk_init_regs),
434
+
.init_regs = c3_mclk_pll_init_regs,
435
+
.init_count = ARRAY_SIZE(c3_mclk_pll_init_regs),
436
436
},
437
437
.hw.init = &(struct clk_init_data) {
438
438
.name = "mclk_pll_dco",
···
444
444
},
445
445
};
446
446
447
-
static const struct clk_div_table c3_mpll_od_table[] = {
447
+
static const struct clk_div_table c3_mpll_pll_od_table[] = {
448
448
{ 0, 1 },
449
449
{ 1, 2 },
450
450
{ 2, 4 },
···
453
453
{ /* sentinel */ }
454
454
};
455
455
456
-
static struct clk_regmap mclk_pll_od = {
456
+
static struct clk_regmap c3_mclk_pll_od = {
457
457
.data = &(struct clk_regmap_div_data) {
458
458
.offset = ANACTRL_MPLL_CTRL0,
459
459
.shift = 12,
460
460
.width = 3,
461
-
.table = c3_mpll_od_table,
461
+
.table = c3_mpll_pll_od_table,
462
462
},
463
463
.hw.init = &(struct clk_init_data) {
464
464
.name = "mclk_pll_od",
465
465
.ops = &clk_regmap_divider_ops,
466
466
.parent_hws = (const struct clk_hw *[]) {
467
-
&mclk_pll_dco.hw },
467
+
&c3_mclk_pll_dco.hw },
468
468
.num_parents = 1,
469
469
.flags = CLK_SET_RATE_PARENT,
470
470
},
471
471
};
472
472
473
473
/* both value 0 and 1 gives divide the input rate by one */
474
-
static struct clk_regmap mclk_pll = {
474
+
static struct clk_regmap c3_mclk_pll = {
475
475
.data = &(struct clk_regmap_div_data) {
476
476
.offset = ANACTRL_MPLL_CTRL4,
477
477
.shift = 16,
···
482
482
.name = "mclk_pll",
483
483
.ops = &clk_regmap_divider_ops,
484
484
.parent_hws = (const struct clk_hw *[]) {
485
-
&mclk_pll_od.hw
485
+
&c3_mclk_pll_od.hw
486
486
},
487
487
.num_parents = 1,
488
488
.flags = CLK_SET_RATE_PARENT,
489
489
},
490
490
};
491
491
492
-
static const struct clk_parent_data mclk_parent[] = {
493
-
{ .hw = &mclk_pll.hw },
492
+
static const struct clk_parent_data c3_mclk_parents[] = {
493
+
{ .hw = &c3_mclk_pll.hw },
494
494
{ .fw_name = "mclk" },
495
-
{ .hw = &fclk_50m.hw }
495
+
{ .hw = &c3_fclk_50m.hw }
496
496
};
497
497
498
-
static struct clk_regmap mclk0_sel = {
498
+
static struct clk_regmap c3_mclk0_sel = {
499
499
.data = &(struct clk_regmap_mux_data) {
500
500
.offset = ANACTRL_MPLL_CTRL4,
501
501
.mask = 0x3,
···
504
504
.hw.init = &(struct clk_init_data) {
505
505
.name = "mclk0_sel",
506
506
.ops = &clk_regmap_mux_ops,
507
-
.parent_data = mclk_parent,
508
-
.num_parents = ARRAY_SIZE(mclk_parent),
507
+
.parent_data = c3_mclk_parents,
508
+
.num_parents = ARRAY_SIZE(c3_mclk_parents),
509
509
},
510
510
};
511
511
512
-
static struct clk_regmap mclk0_div_en = {
512
+
static struct clk_regmap c3_mclk0_div_en = {
513
513
.data = &(struct clk_regmap_gate_data) {
514
514
.offset = ANACTRL_MPLL_CTRL4,
515
515
.bit_idx = 1,
···
518
518
.name = "mclk0_div_en",
519
519
.ops = &clk_regmap_gate_ops,
520
520
.parent_hws = (const struct clk_hw *[]) {
521
-
&mclk0_sel.hw
521
+
&c3_mclk0_sel.hw
522
522
},
523
523
.num_parents = 1,
524
524
.flags = CLK_SET_RATE_PARENT,
525
525
},
526
526
};
527
527
528
-
static struct clk_regmap mclk0_div = {
528
+
static struct clk_regmap c3_mclk0_div = {
529
529
.data = &(struct clk_regmap_div_data) {
530
530
.offset = ANACTRL_MPLL_CTRL4,
531
531
.shift = 2,
···
535
535
.name = "mclk0_div",
536
536
.ops = &clk_regmap_divider_ops,
537
537
.parent_hws = (const struct clk_hw *[]) {
538
-
&mclk0_div_en.hw
538
+
&c3_mclk0_div_en.hw
539
539
},
540
540
.num_parents = 1,
541
541
.flags = CLK_SET_RATE_PARENT,
542
542
},
543
543
};
544
544
545
-
static struct clk_regmap mclk0 = {
545
+
static struct clk_regmap c3_mclk0 = {
546
546
.data = &(struct clk_regmap_gate_data) {
547
547
.offset = ANACTRL_MPLL_CTRL4,
548
548
.bit_idx = 0,
···
551
551
.name = "mclk0",
552
552
.ops = &clk_regmap_gate_ops,
553
553
.parent_hws = (const struct clk_hw *[]) {
554
-
&mclk0_div.hw
554
+
&c3_mclk0_div.hw
555
555
},
556
556
.num_parents = 1,
557
557
.flags = CLK_SET_RATE_PARENT,
558
558
},
559
559
};
560
560
561
-
static struct clk_regmap mclk1_sel = {
561
+
static struct clk_regmap c3_mclk1_sel = {
562
562
.data = &(struct clk_regmap_mux_data) {
563
563
.offset = ANACTRL_MPLL_CTRL4,
564
564
.mask = 0x3,
···
567
567
.hw.init = &(struct clk_init_data) {
568
568
.name = "mclk1_sel",
569
569
.ops = &clk_regmap_mux_ops,
570
-
.parent_data = mclk_parent,
571
-
.num_parents = ARRAY_SIZE(mclk_parent),
570
+
.parent_data = c3_mclk_parents,
571
+
.num_parents = ARRAY_SIZE(c3_mclk_parents),
572
572
},
573
573
};
574
574
575
-
static struct clk_regmap mclk1_div_en = {
575
+
static struct clk_regmap c3_mclk1_div_en = {
576
576
.data = &(struct clk_regmap_gate_data) {
577
577
.offset = ANACTRL_MPLL_CTRL4,
578
578
.bit_idx = 9,
···
581
581
.name = "mclk1_div_en",
582
582
.ops = &clk_regmap_gate_ops,
583
583
.parent_hws = (const struct clk_hw *[]) {
584
-
&mclk1_sel.hw
584
+
&c3_mclk1_sel.hw
585
585
},
586
586
.num_parents = 1,
587
587
.flags = CLK_SET_RATE_PARENT,
588
588
},
589
589
};
590
590
591
-
static struct clk_regmap mclk1_div = {
591
+
static struct clk_regmap c3_mclk1_div = {
592
592
.data = &(struct clk_regmap_div_data) {
593
593
.offset = ANACTRL_MPLL_CTRL4,
594
594
.shift = 10,
···
598
598
.name = "mclk1_div",
599
599
.ops = &clk_regmap_divider_ops,
600
600
.parent_hws = (const struct clk_hw *[]) {
601
-
&mclk1_div_en.hw
601
+
&c3_mclk1_div_en.hw
602
602
},
603
603
.num_parents = 1,
604
604
.flags = CLK_SET_RATE_PARENT,
605
605
},
606
606
};
607
607
608
-
static struct clk_regmap mclk1 = {
608
+
static struct clk_regmap c3_mclk1 = {
609
609
.data = &(struct clk_regmap_gate_data) {
610
610
.offset = ANACTRL_MPLL_CTRL4,
611
611
.bit_idx = 8,
···
614
614
.name = "mclk1",
615
615
.ops = &clk_regmap_gate_ops,
616
616
.parent_hws = (const struct clk_hw *[]) {
617
-
&mclk1_div.hw
617
+
&c3_mclk1_div.hw
618
618
},
619
619
.num_parents = 1,
620
620
.flags = CLK_SET_RATE_PARENT,
···
622
622
};
623
623
624
624
static struct clk_hw *c3_pll_hw_clks[] = {
625
-
[CLKID_FCLK_50M_EN] = &fclk_50m_en.hw,
626
-
[CLKID_FCLK_50M] = &fclk_50m.hw,
627
-
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
628
-
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
629
-
[CLKID_FCLK_DIV2P5_DIV] = &fclk_div2p5_div.hw,
630
-
[CLKID_FCLK_DIV2P5] = &fclk_div2p5.hw,
631
-
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
632
-
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
633
-
[CLKID_FCLK_DIV4_DIV] = &fclk_div4_div.hw,
634
-
[CLKID_FCLK_DIV4] = &fclk_div4.hw,
635
-
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
636
-
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
637
-
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
638
-
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
639
-
[CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw,
640
-
[CLKID_GP0_PLL] = &gp0_pll.hw,
641
-
[CLKID_HIFI_PLL_DCO] = &hifi_pll_dco.hw,
642
-
[CLKID_HIFI_PLL] = &hifi_pll.hw,
643
-
[CLKID_MCLK_PLL_DCO] = &mclk_pll_dco.hw,
644
-
[CLKID_MCLK_PLL_OD] = &mclk_pll_od.hw,
645
-
[CLKID_MCLK_PLL] = &mclk_pll.hw,
646
-
[CLKID_MCLK0_SEL] = &mclk0_sel.hw,
647
-
[CLKID_MCLK0_SEL_EN] = &mclk0_div_en.hw,
648
-
[CLKID_MCLK0_DIV] = &mclk0_div.hw,
649
-
[CLKID_MCLK0] = &mclk0.hw,
650
-
[CLKID_MCLK1_SEL] = &mclk1_sel.hw,
651
-
[CLKID_MCLK1_SEL_EN] = &mclk1_div_en.hw,
652
-
[CLKID_MCLK1_DIV] = &mclk1_div.hw,
653
-
[CLKID_MCLK1] = &mclk1.hw
625
+
[CLKID_FCLK_50M_EN] = &c3_fclk_50m_en.hw,
626
+
[CLKID_FCLK_50M] = &c3_fclk_50m.hw,
627
+
[CLKID_FCLK_DIV2_DIV] = &c3_fclk_div2_div.hw,
628
+
[CLKID_FCLK_DIV2] = &c3_fclk_div2.hw,
629
+
[CLKID_FCLK_DIV2P5_DIV] = &c3_fclk_div2p5_div.hw,
630
+
[CLKID_FCLK_DIV2P5] = &c3_fclk_div2p5.hw,
631
+
[CLKID_FCLK_DIV3_DIV] = &c3_fclk_div3_div.hw,
632
+
[CLKID_FCLK_DIV3] = &c3_fclk_div3.hw,
633
+
[CLKID_FCLK_DIV4_DIV] = &c3_fclk_div4_div.hw,
634
+
[CLKID_FCLK_DIV4] = &c3_fclk_div4.hw,
635
+
[CLKID_FCLK_DIV5_DIV] = &c3_fclk_div5_div.hw,
636
+
[CLKID_FCLK_DIV5] = &c3_fclk_div5.hw,
637
+
[CLKID_FCLK_DIV7_DIV] = &c3_fclk_div7_div.hw,
638
+
[CLKID_FCLK_DIV7] = &c3_fclk_div7.hw,
639
+
[CLKID_GP0_PLL_DCO] = &c3_gp0_pll_dco.hw,
640
+
[CLKID_GP0_PLL] = &c3_gp0_pll.hw,
641
+
[CLKID_HIFI_PLL_DCO] = &c3_hifi_pll_dco.hw,
642
+
[CLKID_HIFI_PLL] = &c3_hifi_pll.hw,
643
+
[CLKID_MCLK_PLL_DCO] = &c3_mclk_pll_dco.hw,
644
+
[CLKID_MCLK_PLL_OD] = &c3_mclk_pll_od.hw,
645
+
[CLKID_MCLK_PLL] = &c3_mclk_pll.hw,
646
+
[CLKID_MCLK0_SEL] = &c3_mclk0_sel.hw,
647
+
[CLKID_MCLK0_SEL_EN] = &c3_mclk0_div_en.hw,
648
+
[CLKID_MCLK0_DIV] = &c3_mclk0_div.hw,
649
+
[CLKID_MCLK0] = &c3_mclk0.hw,
650
+
[CLKID_MCLK1_SEL] = &c3_mclk1_sel.hw,
651
+
[CLKID_MCLK1_SEL_EN] = &c3_mclk1_div_en.hw,
652
+
[CLKID_MCLK1_DIV] = &c3_mclk1_div.hw,
653
+
[CLKID_MCLK1] = &c3_mclk1.hw
654
654
};
655
655
656
-
static const struct regmap_config clkc_regmap_config = {
657
-
.reg_bits = 32,
658
-
.val_bits = 32,
659
-
.reg_stride = 4,
660
-
.max_register = ANACTRL_MPLL_CTRL4,
656
+
static const struct meson_clkc_data c3_pll_clkc_data = {
657
+
.hw_clks = {
658
+
.hws = c3_pll_hw_clks,
659
+
.num = ARRAY_SIZE(c3_pll_hw_clks),
660
+
},
661
661
};
662
-
663
-
static struct meson_clk_hw_data c3_pll_clks = {
664
-
.hws = c3_pll_hw_clks,
665
-
.num = ARRAY_SIZE(c3_pll_hw_clks),
666
-
};
667
-
668
-
static int c3_pll_probe(struct platform_device *pdev)
669
-
{
670
-
struct device *dev = &pdev->dev;
671
-
struct regmap *regmap;
672
-
void __iomem *base;
673
-
int clkid, ret;
674
-
675
-
base = devm_platform_ioremap_resource(pdev, 0);
676
-
if (IS_ERR(base))
677
-
return PTR_ERR(base);
678
-
679
-
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
680
-
if (IS_ERR(regmap))
681
-
return PTR_ERR(regmap);
682
-
683
-
for (clkid = 0; clkid < c3_pll_clks.num; clkid++) {
684
-
/* array might be sparse */
685
-
if (!c3_pll_clks.hws[clkid])
686
-
continue;
687
-
688
-
ret = devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]);
689
-
if (ret) {
690
-
dev_err(dev, "Clock registration failed\n");
691
-
return ret;
692
-
}
693
-
}
694
-
695
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
696
-
&c3_pll_clks);
697
-
}
698
662
699
663
static const struct of_device_id c3_pll_clkc_match_table[] = {
700
664
{
701
665
.compatible = "amlogic,c3-pll-clkc",
666
+
.data = &c3_pll_clkc_data,
702
667
},
703
668
{}
704
669
};
705
670
MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table);
706
671
707
-
static struct platform_driver c3_pll_driver = {
708
-
.probe = c3_pll_probe,
672
+
static struct platform_driver c3_pll_clkc_driver = {
673
+
.probe = meson_clkc_mmio_probe,
709
674
.driver = {
710
675
.name = "c3-pll-clkc",
711
676
.of_match_table = c3_pll_clkc_match_table,
712
677
},
713
678
};
714
-
module_platform_driver(c3_pll_driver);
679
+
module_platform_driver(c3_pll_clkc_driver);
715
680
716
681
MODULE_DESCRIPTION("Amlogic C3 PLL Clock Controller driver");
717
682
MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
-20
drivers/clk/meson/clk-regmap.h
-20
drivers/clk/meson/clk-regmap.h
···
118
118
extern const struct clk_ops clk_regmap_mux_ops;
119
119
extern const struct clk_ops clk_regmap_mux_ro_ops;
120
120
121
-
#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \
122
-
struct clk_regmap _name = { \
123
-
.data = &(struct clk_regmap_gate_data){ \
124
-
.offset = (_reg), \
125
-
.bit_idx = (_bit), \
126
-
}, \
127
-
.hw.init = &(struct clk_init_data) { \
128
-
.name = #_name, \
129
-
.ops = _ops, \
130
-
.parent_hws = (const struct clk_hw *[]) { _pname }, \
131
-
.num_parents = 1, \
132
-
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
133
-
}, \
134
-
}
135
-
136
-
#define MESON_PCLK(_name, _reg, _bit, _pname) \
137
-
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
138
-
139
-
#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \
140
-
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
141
121
#endif /* __CLK_REGMAP_H */
+119
-119
drivers/clk/meson/g12a-aoclk.c
+119
-119
drivers/clk/meson/g12a-aoclk.c
···
37
37
#define AO_RTC_ALT_CLK_CNTL0 0x94
38
38
#define AO_RTC_ALT_CLK_CNTL1 0x98
39
39
40
+
static const struct clk_parent_data g12a_ao_pclk_parents = { .fw_name = "mpeg-clk" };
41
+
42
+
#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \
43
+
MESON_PCLK(g12a_ao_##_name, _reg, _bit, &g12a_ao_pclk_parents, _flags)
44
+
40
45
/*
41
-
* Like every other peripheral clock gate in Amlogic Clock drivers,
42
-
* we are using CLK_IGNORE_UNUSED here, so we keep the state of the
43
-
* bootloader. The goal is to remove this flag at some point.
44
-
* Actually removing it will require some extensive test to be done safely.
46
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
47
+
* Users are encouraged to test without it and submit changes to:
48
+
* - remove the flag if not necessary
49
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
50
+
* if appropriate.
51
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
52
+
* for a particular clock.
45
53
*/
46
-
#define AXG_AO_GATE(_name, _reg, _bit) \
47
-
static struct clk_regmap g12a_aoclk_##_name = { \
48
-
.data = &(struct clk_regmap_gate_data) { \
49
-
.offset = (_reg), \
50
-
.bit_idx = (_bit), \
51
-
}, \
52
-
.hw.init = &(struct clk_init_data) { \
53
-
.name = "g12a_ao_" #_name, \
54
-
.ops = &clk_regmap_gate_ops, \
55
-
.parent_data = &(const struct clk_parent_data) { \
56
-
.fw_name = "mpeg-clk", \
57
-
}, \
58
-
.num_parents = 1, \
59
-
.flags = CLK_IGNORE_UNUSED, \
60
-
}, \
61
-
}
54
+
static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED);
55
+
static G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED);
56
+
static G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED);
57
+
static G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED);
58
+
static G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED);
59
+
static G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED);
60
+
static G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED);
61
+
static G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED);
62
+
static G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED);
62
63
63
-
AXG_AO_GATE(ahb, AO_CLK_GATE0, 0);
64
-
AXG_AO_GATE(ir_in, AO_CLK_GATE0, 1);
65
-
AXG_AO_GATE(i2c_m0, AO_CLK_GATE0, 2);
66
-
AXG_AO_GATE(i2c_s0, AO_CLK_GATE0, 3);
67
-
AXG_AO_GATE(uart, AO_CLK_GATE0, 4);
68
-
AXG_AO_GATE(prod_i2c, AO_CLK_GATE0, 5);
69
-
AXG_AO_GATE(uart2, AO_CLK_GATE0, 6);
70
-
AXG_AO_GATE(ir_out, AO_CLK_GATE0, 7);
71
-
AXG_AO_GATE(saradc, AO_CLK_GATE0, 8);
72
-
AXG_AO_GATE(mailbox, AO_CLK_GATE0_SP, 0);
73
-
AXG_AO_GATE(m3, AO_CLK_GATE0_SP, 1);
74
-
AXG_AO_GATE(ahb_sram, AO_CLK_GATE0_SP, 2);
75
-
AXG_AO_GATE(rti, AO_CLK_GATE0_SP, 3);
76
-
AXG_AO_GATE(m4_fclk, AO_CLK_GATE0_SP, 4);
77
-
AXG_AO_GATE(m4_hclk, AO_CLK_GATE0_SP, 5);
64
+
static G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED);
65
+
static G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED);
66
+
static G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED);
67
+
static G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED);
68
+
static G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED);
69
+
static G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED);
78
70
79
-
static struct clk_regmap g12a_aoclk_cts_oscin = {
71
+
static struct clk_regmap g12a_ao_cts_oscin = {
80
72
.data = &(struct clk_regmap_gate_data){
81
73
.offset = AO_RTI_PWR_CNTL_REG0,
82
74
.bit_idx = 14,
···
95
103
96
104
/* 32k_by_oscin clock */
97
105
98
-
static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
106
+
static struct clk_regmap g12a_ao_32k_by_oscin_pre = {
99
107
.data = &(struct clk_regmap_gate_data){
100
108
.offset = AO_RTC_ALT_CLK_CNTL0,
101
109
.bit_idx = 31,
102
110
},
103
111
.hw.init = &(struct clk_init_data){
104
-
.name = "g12a_ao_32k_by_oscin_pre",
112
+
.name = "ao_32k_by_oscin_pre",
105
113
.ops = &clk_regmap_gate_ops,
106
114
.parent_hws = (const struct clk_hw *[]) {
107
-
&g12a_aoclk_cts_oscin.hw
115
+
&g12a_ao_cts_oscin.hw
108
116
},
109
117
.num_parents = 1,
110
118
},
111
119
};
112
120
113
-
static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
121
+
static struct clk_regmap g12a_ao_32k_by_oscin_div = {
114
122
.data = &(struct meson_clk_dualdiv_data){
115
123
.n1 = {
116
124
.reg_off = AO_RTC_ALT_CLK_CNTL0,
···
140
148
.table = g12a_32k_div_table,
141
149
},
142
150
.hw.init = &(struct clk_init_data){
143
-
.name = "g12a_ao_32k_by_oscin_div",
151
+
.name = "ao_32k_by_oscin_div",
144
152
.ops = &meson_clk_dualdiv_ops,
145
153
.parent_hws = (const struct clk_hw *[]) {
146
-
&g12a_aoclk_32k_by_oscin_pre.hw
154
+
&g12a_ao_32k_by_oscin_pre.hw
147
155
},
148
156
.num_parents = 1,
149
157
},
150
158
};
151
159
152
-
static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
160
+
static struct clk_regmap g12a_ao_32k_by_oscin_sel = {
153
161
.data = &(struct clk_regmap_mux_data) {
154
162
.offset = AO_RTC_ALT_CLK_CNTL1,
155
163
.mask = 0x1,
···
157
165
.flags = CLK_MUX_ROUND_CLOSEST,
158
166
},
159
167
.hw.init = &(struct clk_init_data){
160
-
.name = "g12a_ao_32k_by_oscin_sel",
168
+
.name = "ao_32k_by_oscin_sel",
161
169
.ops = &clk_regmap_mux_ops,
162
170
.parent_hws = (const struct clk_hw *[]) {
163
-
&g12a_aoclk_32k_by_oscin_div.hw,
164
-
&g12a_aoclk_32k_by_oscin_pre.hw,
171
+
&g12a_ao_32k_by_oscin_div.hw,
172
+
&g12a_ao_32k_by_oscin_pre.hw,
165
173
},
166
174
.num_parents = 2,
167
175
.flags = CLK_SET_RATE_PARENT,
168
176
},
169
177
};
170
178
171
-
static struct clk_regmap g12a_aoclk_32k_by_oscin = {
179
+
static struct clk_regmap g12a_ao_32k_by_oscin = {
172
180
.data = &(struct clk_regmap_gate_data){
173
181
.offset = AO_RTC_ALT_CLK_CNTL0,
174
182
.bit_idx = 30,
175
183
},
176
184
.hw.init = &(struct clk_init_data){
177
-
.name = "g12a_ao_32k_by_oscin",
185
+
.name = "ao_32k_by_oscin",
178
186
.ops = &clk_regmap_gate_ops,
179
187
.parent_hws = (const struct clk_hw *[]) {
180
-
&g12a_aoclk_32k_by_oscin_sel.hw
188
+
&g12a_ao_32k_by_oscin_sel.hw
181
189
},
182
190
.num_parents = 1,
183
191
.flags = CLK_SET_RATE_PARENT,
···
186
194
187
195
/* cec clock */
188
196
189
-
static struct clk_regmap g12a_aoclk_cec_pre = {
197
+
static struct clk_regmap g12a_ao_cec_pre = {
190
198
.data = &(struct clk_regmap_gate_data){
191
199
.offset = AO_CEC_CLK_CNTL_REG0,
192
200
.bit_idx = 31,
193
201
},
194
202
.hw.init = &(struct clk_init_data){
195
-
.name = "g12a_ao_cec_pre",
203
+
.name = "ao_cec_pre",
196
204
.ops = &clk_regmap_gate_ops,
197
205
.parent_hws = (const struct clk_hw *[]) {
198
-
&g12a_aoclk_cts_oscin.hw
206
+
&g12a_ao_cts_oscin.hw
199
207
},
200
208
.num_parents = 1,
201
209
},
202
210
};
203
211
204
-
static struct clk_regmap g12a_aoclk_cec_div = {
212
+
static struct clk_regmap g12a_ao_cec_div = {
205
213
.data = &(struct meson_clk_dualdiv_data){
206
214
.n1 = {
207
215
.reg_off = AO_CEC_CLK_CNTL_REG0,
···
231
239
.table = g12a_32k_div_table,
232
240
},
233
241
.hw.init = &(struct clk_init_data){
234
-
.name = "g12a_ao_cec_div",
242
+
.name = "ao_cec_div",
235
243
.ops = &meson_clk_dualdiv_ops,
236
244
.parent_hws = (const struct clk_hw *[]) {
237
-
&g12a_aoclk_cec_pre.hw
245
+
&g12a_ao_cec_pre.hw
238
246
},
239
247
.num_parents = 1,
240
248
},
241
249
};
242
250
243
-
static struct clk_regmap g12a_aoclk_cec_sel = {
251
+
static struct clk_regmap g12a_ao_cec_sel = {
244
252
.data = &(struct clk_regmap_mux_data) {
245
253
.offset = AO_CEC_CLK_CNTL_REG1,
246
254
.mask = 0x1,
···
248
256
.flags = CLK_MUX_ROUND_CLOSEST,
249
257
},
250
258
.hw.init = &(struct clk_init_data){
251
-
.name = "g12a_ao_cec_sel",
259
+
.name = "ao_cec_sel",
252
260
.ops = &clk_regmap_mux_ops,
253
261
.parent_hws = (const struct clk_hw *[]) {
254
-
&g12a_aoclk_cec_div.hw,
255
-
&g12a_aoclk_cec_pre.hw,
262
+
&g12a_ao_cec_div.hw,
263
+
&g12a_ao_cec_pre.hw,
256
264
},
257
265
.num_parents = 2,
258
266
.flags = CLK_SET_RATE_PARENT,
259
267
},
260
268
};
261
269
262
-
static struct clk_regmap g12a_aoclk_cec = {
270
+
static struct clk_regmap g12a_ao_cec = {
263
271
.data = &(struct clk_regmap_gate_data){
264
272
.offset = AO_CEC_CLK_CNTL_REG0,
265
273
.bit_idx = 30,
266
274
},
267
275
.hw.init = &(struct clk_init_data){
268
-
.name = "g12a_ao_cec",
276
+
.name = "ao_cec",
269
277
.ops = &clk_regmap_gate_ops,
270
278
.parent_hws = (const struct clk_hw *[]) {
271
-
&g12a_aoclk_cec_sel.hw
279
+
&g12a_ao_cec_sel.hw
272
280
},
273
281
.num_parents = 1,
274
282
.flags = CLK_SET_RATE_PARENT,
275
283
},
276
284
};
277
285
278
-
static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
286
+
static struct clk_regmap g12a_ao_cts_rtc_oscin = {
279
287
.data = &(struct clk_regmap_mux_data) {
280
288
.offset = AO_RTI_PWR_CNTL_REG0,
281
289
.mask = 0x1,
···
283
291
.flags = CLK_MUX_ROUND_CLOSEST,
284
292
},
285
293
.hw.init = &(struct clk_init_data){
286
-
.name = "g12a_ao_cts_rtc_oscin",
294
+
.name = "ao_cts_rtc_oscin",
287
295
.ops = &clk_regmap_mux_ops,
288
296
.parent_data = (const struct clk_parent_data []) {
289
-
{ .hw = &g12a_aoclk_32k_by_oscin.hw },
297
+
{ .hw = &g12a_ao_32k_by_oscin.hw },
290
298
{ .fw_name = "ext-32k-0", },
291
299
},
292
300
.num_parents = 2,
···
294
302
},
295
303
};
296
304
297
-
static struct clk_regmap g12a_aoclk_clk81 = {
305
+
static struct clk_regmap g12a_ao_clk81 = {
298
306
.data = &(struct clk_regmap_mux_data) {
299
307
.offset = AO_RTI_PWR_CNTL_REG0,
300
308
.mask = 0x1,
···
302
310
.flags = CLK_MUX_ROUND_CLOSEST,
303
311
},
304
312
.hw.init = &(struct clk_init_data){
313
+
/*
314
+
* NOTE: this is one of the infamous clock the pwm driver
315
+
* can request directly by its global name. It's wrong but
316
+
* there is not much we can do about it until the support
317
+
* for the old pwm bindings is dropped
318
+
*/
305
319
.name = "g12a_ao_clk81",
306
320
.ops = &clk_regmap_mux_ro_ops,
307
321
.parent_data = (const struct clk_parent_data []) {
308
322
{ .fw_name = "mpeg-clk", },
309
-
{ .hw = &g12a_aoclk_cts_rtc_oscin.hw },
323
+
{ .hw = &g12a_ao_cts_rtc_oscin.hw },
310
324
},
311
325
.num_parents = 2,
312
326
.flags = CLK_SET_RATE_PARENT,
313
327
},
314
328
};
315
329
316
-
static struct clk_regmap g12a_aoclk_saradc_mux = {
330
+
static struct clk_regmap g12a_ao_saradc_mux = {
317
331
.data = &(struct clk_regmap_mux_data) {
318
332
.offset = AO_SAR_CLK,
319
333
.mask = 0x3,
320
334
.shift = 9,
321
335
},
322
336
.hw.init = &(struct clk_init_data){
323
-
.name = "g12a_ao_saradc_mux",
337
+
.name = "ao_saradc_mux",
324
338
.ops = &clk_regmap_mux_ops,
325
339
.parent_data = (const struct clk_parent_data []) {
326
340
{ .fw_name = "xtal", },
327
-
{ .hw = &g12a_aoclk_clk81.hw },
341
+
{ .hw = &g12a_ao_clk81.hw },
328
342
},
329
343
.num_parents = 2,
330
344
},
331
345
};
332
346
333
-
static struct clk_regmap g12a_aoclk_saradc_div = {
347
+
static struct clk_regmap g12a_ao_saradc_div = {
334
348
.data = &(struct clk_regmap_div_data) {
335
349
.offset = AO_SAR_CLK,
336
350
.shift = 0,
337
351
.width = 8,
338
352
},
339
353
.hw.init = &(struct clk_init_data){
340
-
.name = "g12a_ao_saradc_div",
354
+
.name = "ao_saradc_div",
341
355
.ops = &clk_regmap_divider_ops,
342
356
.parent_hws = (const struct clk_hw *[]) {
343
-
&g12a_aoclk_saradc_mux.hw
357
+
&g12a_ao_saradc_mux.hw
344
358
},
345
359
.num_parents = 1,
346
360
.flags = CLK_SET_RATE_PARENT,
347
361
},
348
362
};
349
363
350
-
static struct clk_regmap g12a_aoclk_saradc_gate = {
364
+
static struct clk_regmap g12a_ao_saradc_gate = {
351
365
.data = &(struct clk_regmap_gate_data) {
352
366
.offset = AO_SAR_CLK,
353
367
.bit_idx = 8,
354
368
},
355
369
.hw.init = &(struct clk_init_data){
356
-
.name = "g12a_ao_saradc_gate",
370
+
.name = "ao_saradc_gate",
357
371
.ops = &clk_regmap_gate_ops,
358
372
.parent_hws = (const struct clk_hw *[]) {
359
-
&g12a_aoclk_saradc_div.hw
373
+
&g12a_ao_saradc_div.hw
360
374
},
361
375
.num_parents = 1,
362
376
.flags = CLK_SET_RATE_PARENT,
363
377
},
364
378
};
365
379
366
-
static const unsigned int g12a_aoclk_reset[] = {
380
+
static const unsigned int g12a_ao_reset[] = {
367
381
[RESET_AO_IR_IN] = 16,
368
382
[RESET_AO_UART] = 17,
369
383
[RESET_AO_I2C_M] = 18,
···
379
381
[RESET_AO_IR_OUT] = 23,
380
382
};
381
383
382
-
static struct clk_hw *g12a_aoclk_hw_clks[] = {
383
-
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
384
-
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
385
-
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
386
-
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
387
-
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
388
-
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
389
-
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
390
-
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
391
-
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
392
-
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
393
-
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
394
-
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
395
-
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
396
-
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
397
-
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
398
-
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
399
-
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
400
-
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
401
-
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
402
-
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
403
-
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
404
-
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
405
-
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
406
-
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
407
-
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
408
-
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
409
-
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
410
-
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
411
-
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
384
+
static struct clk_hw *g12a_ao_hw_clks[] = {
385
+
[CLKID_AO_AHB] = &g12a_ao_ahb.hw,
386
+
[CLKID_AO_IR_IN] = &g12a_ao_ir_in.hw,
387
+
[CLKID_AO_I2C_M0] = &g12a_ao_i2c_m0.hw,
388
+
[CLKID_AO_I2C_S0] = &g12a_ao_i2c_s0.hw,
389
+
[CLKID_AO_UART] = &g12a_ao_uart.hw,
390
+
[CLKID_AO_PROD_I2C] = &g12a_ao_prod_i2c.hw,
391
+
[CLKID_AO_UART2] = &g12a_ao_uart2.hw,
392
+
[CLKID_AO_IR_OUT] = &g12a_ao_ir_out.hw,
393
+
[CLKID_AO_SAR_ADC] = &g12a_ao_saradc.hw,
394
+
[CLKID_AO_MAILBOX] = &g12a_ao_mailbox.hw,
395
+
[CLKID_AO_M3] = &g12a_ao_m3.hw,
396
+
[CLKID_AO_AHB_SRAM] = &g12a_ao_ahb_sram.hw,
397
+
[CLKID_AO_RTI] = &g12a_ao_rti.hw,
398
+
[CLKID_AO_M4_FCLK] = &g12a_ao_m4_fclk.hw,
399
+
[CLKID_AO_M4_HCLK] = &g12a_ao_m4_hclk.hw,
400
+
[CLKID_AO_CLK81] = &g12a_ao_clk81.hw,
401
+
[CLKID_AO_SAR_ADC_SEL] = &g12a_ao_saradc_mux.hw,
402
+
[CLKID_AO_SAR_ADC_DIV] = &g12a_ao_saradc_div.hw,
403
+
[CLKID_AO_SAR_ADC_CLK] = &g12a_ao_saradc_gate.hw,
404
+
[CLKID_AO_CTS_OSCIN] = &g12a_ao_cts_oscin.hw,
405
+
[CLKID_AO_32K_PRE] = &g12a_ao_32k_by_oscin_pre.hw,
406
+
[CLKID_AO_32K_DIV] = &g12a_ao_32k_by_oscin_div.hw,
407
+
[CLKID_AO_32K_SEL] = &g12a_ao_32k_by_oscin_sel.hw,
408
+
[CLKID_AO_32K] = &g12a_ao_32k_by_oscin.hw,
409
+
[CLKID_AO_CEC_PRE] = &g12a_ao_cec_pre.hw,
410
+
[CLKID_AO_CEC_DIV] = &g12a_ao_cec_div.hw,
411
+
[CLKID_AO_CEC_SEL] = &g12a_ao_cec_sel.hw,
412
+
[CLKID_AO_CEC] = &g12a_ao_cec.hw,
413
+
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_ao_cts_rtc_oscin.hw,
412
414
};
413
415
414
-
static const struct meson_aoclk_data g12a_aoclkc_data = {
416
+
static const struct meson_aoclk_data g12a_ao_clkc_data = {
415
417
.reset_reg = AO_RTI_GEN_CNTL_REG0,
416
-
.num_reset = ARRAY_SIZE(g12a_aoclk_reset),
417
-
.reset = g12a_aoclk_reset,
418
-
.hw_clks = {
419
-
.hws = g12a_aoclk_hw_clks,
420
-
.num = ARRAY_SIZE(g12a_aoclk_hw_clks),
418
+
.num_reset = ARRAY_SIZE(g12a_ao_reset),
419
+
.reset = g12a_ao_reset,
420
+
.clkc_data = {
421
+
.hw_clks = {
422
+
.hws = g12a_ao_hw_clks,
423
+
.num = ARRAY_SIZE(g12a_ao_hw_clks),
424
+
},
421
425
},
422
426
};
423
427
424
-
static const struct of_device_id g12a_aoclkc_match_table[] = {
428
+
static const struct of_device_id g12a_ao_clkc_match_table[] = {
425
429
{
426
430
.compatible = "amlogic,meson-g12a-aoclkc",
427
-
.data = &g12a_aoclkc_data,
431
+
.data = &g12a_ao_clkc_data.clkc_data,
428
432
},
429
433
{ }
430
434
};
431
-
MODULE_DEVICE_TABLE(of, g12a_aoclkc_match_table);
435
+
MODULE_DEVICE_TABLE(of, g12a_ao_clkc_match_table);
432
436
433
-
static struct platform_driver g12a_aoclkc_driver = {
437
+
static struct platform_driver g12a_ao_clkc_driver = {
434
438
.probe = meson_aoclkc_probe,
435
439
.driver = {
436
440
.name = "g12a-aoclkc",
437
-
.of_match_table = g12a_aoclkc_match_table,
441
+
.of_match_table = g12a_ao_clkc_match_table,
438
442
},
439
443
};
440
-
module_platform_driver(g12a_aoclkc_driver);
444
+
module_platform_driver(g12a_ao_clkc_driver);
441
445
442
446
MODULE_DESCRIPTION("Amlogic G12A Always-ON Clock Controller driver");
443
447
MODULE_LICENSE("GPL");
+1020
-1032
drivers/clk/meson/g12a.c
+1020
-1032
drivers/clk/meson/g12a.c
···
23
23
#include "clk-cpu-dyndiv.h"
24
24
#include "vid-pll-div.h"
25
25
#include "vclk.h"
26
-
#include "meson-eeclk.h"
26
+
#include "meson-clkc-utils.h"
27
27
28
28
#include <dt-bindings/clock/g12a-clkc.h>
29
29
···
386
386
},
387
387
};
388
388
389
+
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
390
+
.min = 125,
391
+
.max = 255,
392
+
};
393
+
394
+
/*
395
+
* Internal gp0 pll emulation configuration parameters
396
+
*/
397
+
static const struct reg_sequence g12a_gp0_pll_init_regs[] = {
398
+
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
399
+
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
400
+
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
401
+
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
402
+
{ .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
403
+
{ .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
404
+
};
405
+
406
+
static struct clk_regmap g12a_gp0_pll_dco = {
407
+
.data = &(struct meson_clk_pll_data){
408
+
.en = {
409
+
.reg_off = HHI_GP0_PLL_CNTL0,
410
+
.shift = 28,
411
+
.width = 1,
412
+
},
413
+
.m = {
414
+
.reg_off = HHI_GP0_PLL_CNTL0,
415
+
.shift = 0,
416
+
.width = 8,
417
+
},
418
+
.n = {
419
+
.reg_off = HHI_GP0_PLL_CNTL0,
420
+
.shift = 10,
421
+
.width = 5,
422
+
},
423
+
.frac = {
424
+
.reg_off = HHI_GP0_PLL_CNTL1,
425
+
.shift = 0,
426
+
.width = 17,
427
+
},
428
+
.l = {
429
+
.reg_off = HHI_GP0_PLL_CNTL0,
430
+
.shift = 31,
431
+
.width = 1,
432
+
},
433
+
.rst = {
434
+
.reg_off = HHI_GP0_PLL_CNTL0,
435
+
.shift = 29,
436
+
.width = 1,
437
+
},
438
+
.range = &g12a_gp0_pll_mult_range,
439
+
.init_regs = g12a_gp0_pll_init_regs,
440
+
.init_count = ARRAY_SIZE(g12a_gp0_pll_init_regs),
441
+
},
442
+
.hw.init = &(struct clk_init_data){
443
+
.name = "gp0_pll_dco",
444
+
.ops = &meson_clk_pll_ops,
445
+
.parent_data = &(const struct clk_parent_data) {
446
+
.fw_name = "xtal",
447
+
},
448
+
.num_parents = 1,
449
+
},
450
+
};
451
+
452
+
static struct clk_regmap g12a_gp0_pll = {
453
+
.data = &(struct clk_regmap_div_data){
454
+
.offset = HHI_GP0_PLL_CNTL0,
455
+
.shift = 16,
456
+
.width = 3,
457
+
.flags = (CLK_DIVIDER_POWER_OF_TWO |
458
+
CLK_DIVIDER_ROUND_CLOSEST),
459
+
},
460
+
.hw.init = &(struct clk_init_data){
461
+
.name = "gp0_pll",
462
+
.ops = &clk_regmap_divider_ops,
463
+
.parent_hws = (const struct clk_hw *[]) {
464
+
&g12a_gp0_pll_dco.hw
465
+
},
466
+
.num_parents = 1,
467
+
.flags = CLK_SET_RATE_PARENT,
468
+
},
469
+
};
470
+
471
+
static struct clk_regmap sm1_gp1_pll_dco = {
472
+
.data = &(struct meson_clk_pll_data){
473
+
.en = {
474
+
.reg_off = HHI_GP1_PLL_CNTL0,
475
+
.shift = 28,
476
+
.width = 1,
477
+
},
478
+
.m = {
479
+
.reg_off = HHI_GP1_PLL_CNTL0,
480
+
.shift = 0,
481
+
.width = 8,
482
+
},
483
+
.n = {
484
+
.reg_off = HHI_GP1_PLL_CNTL0,
485
+
.shift = 10,
486
+
.width = 5,
487
+
},
488
+
.frac = {
489
+
.reg_off = HHI_GP1_PLL_CNTL1,
490
+
.shift = 0,
491
+
.width = 17,
492
+
},
493
+
.l = {
494
+
.reg_off = HHI_GP1_PLL_CNTL0,
495
+
.shift = 31,
496
+
.width = 1,
497
+
},
498
+
.rst = {
499
+
.reg_off = HHI_GP1_PLL_CNTL0,
500
+
.shift = 29,
501
+
.width = 1,
502
+
},
503
+
},
504
+
.hw.init = &(struct clk_init_data){
505
+
.name = "gp1_pll_dco",
506
+
.ops = &meson_clk_pll_ro_ops,
507
+
.parent_data = &(const struct clk_parent_data) {
508
+
.fw_name = "xtal",
509
+
},
510
+
.num_parents = 1,
511
+
/* This clock feeds the DSU, avoid disabling it */
512
+
.flags = CLK_IS_CRITICAL,
513
+
},
514
+
};
515
+
516
+
static struct clk_regmap sm1_gp1_pll = {
517
+
.data = &(struct clk_regmap_div_data){
518
+
.offset = HHI_GP1_PLL_CNTL0,
519
+
.shift = 16,
520
+
.width = 3,
521
+
.flags = (CLK_DIVIDER_POWER_OF_TWO |
522
+
CLK_DIVIDER_ROUND_CLOSEST),
523
+
},
524
+
.hw.init = &(struct clk_init_data){
525
+
.name = "gp1_pll",
526
+
.ops = &clk_regmap_divider_ro_ops,
527
+
.parent_hws = (const struct clk_hw *[]) {
528
+
&sm1_gp1_pll_dco.hw
529
+
},
530
+
.num_parents = 1,
531
+
},
532
+
};
533
+
534
+
/*
535
+
* Internal hifi pll emulation configuration parameters
536
+
*/
537
+
static const struct reg_sequence g12a_hifi_pll_init_regs[] = {
538
+
{ .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
539
+
{ .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
540
+
{ .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
541
+
{ .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
542
+
{ .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
543
+
{ .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
544
+
};
545
+
546
+
static struct clk_regmap g12a_hifi_pll_dco = {
547
+
.data = &(struct meson_clk_pll_data){
548
+
.en = {
549
+
.reg_off = HHI_HIFI_PLL_CNTL0,
550
+
.shift = 28,
551
+
.width = 1,
552
+
},
553
+
.m = {
554
+
.reg_off = HHI_HIFI_PLL_CNTL0,
555
+
.shift = 0,
556
+
.width = 8,
557
+
},
558
+
.n = {
559
+
.reg_off = HHI_HIFI_PLL_CNTL0,
560
+
.shift = 10,
561
+
.width = 5,
562
+
},
563
+
.frac = {
564
+
.reg_off = HHI_HIFI_PLL_CNTL1,
565
+
.shift = 0,
566
+
.width = 17,
567
+
},
568
+
.l = {
569
+
.reg_off = HHI_HIFI_PLL_CNTL0,
570
+
.shift = 31,
571
+
.width = 1,
572
+
},
573
+
.rst = {
574
+
.reg_off = HHI_HIFI_PLL_CNTL0,
575
+
.shift = 29,
576
+
.width = 1,
577
+
},
578
+
.range = &g12a_gp0_pll_mult_range,
579
+
.init_regs = g12a_hifi_pll_init_regs,
580
+
.init_count = ARRAY_SIZE(g12a_hifi_pll_init_regs),
581
+
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
582
+
},
583
+
.hw.init = &(struct clk_init_data){
584
+
.name = "hifi_pll_dco",
585
+
.ops = &meson_clk_pll_ops,
586
+
.parent_data = &(const struct clk_parent_data) {
587
+
.fw_name = "xtal",
588
+
},
589
+
.num_parents = 1,
590
+
},
591
+
};
592
+
593
+
static struct clk_regmap g12a_hifi_pll = {
594
+
.data = &(struct clk_regmap_div_data){
595
+
.offset = HHI_HIFI_PLL_CNTL0,
596
+
.shift = 16,
597
+
.width = 2,
598
+
.flags = (CLK_DIVIDER_POWER_OF_TWO |
599
+
CLK_DIVIDER_ROUND_CLOSEST),
600
+
},
601
+
.hw.init = &(struct clk_init_data){
602
+
.name = "hifi_pll",
603
+
.ops = &clk_regmap_divider_ops,
604
+
.parent_hws = (const struct clk_hw *[]) {
605
+
&g12a_hifi_pll_dco.hw
606
+
},
607
+
.num_parents = 1,
608
+
.flags = CLK_SET_RATE_PARENT,
609
+
},
610
+
};
611
+
612
+
/*
613
+
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
614
+
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
615
+
* a strict register sequence to enable the PLL.
616
+
*/
617
+
static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
618
+
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
619
+
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
620
+
{ .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
621
+
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
622
+
{ .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
623
+
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
624
+
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
625
+
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
626
+
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
627
+
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
628
+
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
629
+
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
630
+
};
631
+
632
+
/* Keep a single entry table for recalc/round_rate() ops */
633
+
static const struct pll_params_table g12a_pcie_pll_table[] = {
634
+
PLL_PARAMS(150, 1),
635
+
{0, 0},
636
+
};
637
+
638
+
static struct clk_regmap g12a_pcie_pll_dco = {
639
+
.data = &(struct meson_clk_pll_data){
640
+
.en = {
641
+
.reg_off = HHI_PCIE_PLL_CNTL0,
642
+
.shift = 28,
643
+
.width = 1,
644
+
},
645
+
.m = {
646
+
.reg_off = HHI_PCIE_PLL_CNTL0,
647
+
.shift = 0,
648
+
.width = 8,
649
+
},
650
+
.n = {
651
+
.reg_off = HHI_PCIE_PLL_CNTL0,
652
+
.shift = 10,
653
+
.width = 5,
654
+
},
655
+
.frac = {
656
+
.reg_off = HHI_PCIE_PLL_CNTL1,
657
+
.shift = 0,
658
+
.width = 12,
659
+
},
660
+
.l = {
661
+
.reg_off = HHI_PCIE_PLL_CNTL0,
662
+
.shift = 31,
663
+
.width = 1,
664
+
},
665
+
.rst = {
666
+
.reg_off = HHI_PCIE_PLL_CNTL0,
667
+
.shift = 29,
668
+
.width = 1,
669
+
},
670
+
.table = g12a_pcie_pll_table,
671
+
.init_regs = g12a_pcie_pll_init_regs,
672
+
.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
673
+
},
674
+
.hw.init = &(struct clk_init_data){
675
+
.name = "pcie_pll_dco",
676
+
.ops = &meson_clk_pcie_pll_ops,
677
+
.parent_data = &(const struct clk_parent_data) {
678
+
.fw_name = "xtal",
679
+
},
680
+
.num_parents = 1,
681
+
},
682
+
};
683
+
684
+
static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
685
+
.mult = 1,
686
+
.div = 2,
687
+
.hw.init = &(struct clk_init_data){
688
+
.name = "pcie_pll_dco_div2",
689
+
.ops = &clk_fixed_factor_ops,
690
+
.parent_hws = (const struct clk_hw *[]) {
691
+
&g12a_pcie_pll_dco.hw
692
+
},
693
+
.num_parents = 1,
694
+
.flags = CLK_SET_RATE_PARENT,
695
+
},
696
+
};
697
+
698
+
static struct clk_regmap g12a_pcie_pll_od = {
699
+
.data = &(struct clk_regmap_div_data){
700
+
.offset = HHI_PCIE_PLL_CNTL0,
701
+
.shift = 16,
702
+
.width = 5,
703
+
.flags = CLK_DIVIDER_ROUND_CLOSEST |
704
+
CLK_DIVIDER_ONE_BASED |
705
+
CLK_DIVIDER_ALLOW_ZERO,
706
+
},
707
+
.hw.init = &(struct clk_init_data){
708
+
.name = "pcie_pll_od",
709
+
.ops = &clk_regmap_divider_ops,
710
+
.parent_hws = (const struct clk_hw *[]) {
711
+
&g12a_pcie_pll_dco_div2.hw
712
+
},
713
+
.num_parents = 1,
714
+
.flags = CLK_SET_RATE_PARENT,
715
+
},
716
+
};
717
+
718
+
static struct clk_fixed_factor g12a_pcie_pll = {
719
+
.mult = 1,
720
+
.div = 2,
721
+
.hw.init = &(struct clk_init_data){
722
+
.name = "pcie_pll_pll",
723
+
.ops = &clk_fixed_factor_ops,
724
+
.parent_hws = (const struct clk_hw *[]) {
725
+
&g12a_pcie_pll_od.hw
726
+
},
727
+
.num_parents = 1,
728
+
.flags = CLK_SET_RATE_PARENT,
729
+
},
730
+
};
731
+
732
+
static struct clk_regmap g12a_hdmi_pll_dco = {
733
+
.data = &(struct meson_clk_pll_data){
734
+
.en = {
735
+
.reg_off = HHI_HDMI_PLL_CNTL0,
736
+
.shift = 28,
737
+
.width = 1,
738
+
},
739
+
.m = {
740
+
.reg_off = HHI_HDMI_PLL_CNTL0,
741
+
.shift = 0,
742
+
.width = 8,
743
+
},
744
+
.n = {
745
+
.reg_off = HHI_HDMI_PLL_CNTL0,
746
+
.shift = 10,
747
+
.width = 5,
748
+
},
749
+
.frac = {
750
+
.reg_off = HHI_HDMI_PLL_CNTL1,
751
+
.shift = 0,
752
+
.width = 16,
753
+
},
754
+
.l = {
755
+
.reg_off = HHI_HDMI_PLL_CNTL0,
756
+
.shift = 30,
757
+
.width = 1,
758
+
},
759
+
.rst = {
760
+
.reg_off = HHI_HDMI_PLL_CNTL0,
761
+
.shift = 29,
762
+
.width = 1,
763
+
},
764
+
},
765
+
.hw.init = &(struct clk_init_data){
766
+
.name = "hdmi_pll_dco",
767
+
.ops = &meson_clk_pll_ro_ops,
768
+
.parent_data = &(const struct clk_parent_data) {
769
+
.fw_name = "xtal",
770
+
},
771
+
.num_parents = 1,
772
+
/*
773
+
* Display directly handle hdmi pll registers ATM, we need
774
+
* NOCACHE to keep our view of the clock as accurate as possible
775
+
*/
776
+
.flags = CLK_GET_RATE_NOCACHE,
777
+
},
778
+
};
779
+
780
+
static struct clk_regmap g12a_hdmi_pll_od = {
781
+
.data = &(struct clk_regmap_div_data){
782
+
.offset = HHI_HDMI_PLL_CNTL0,
783
+
.shift = 16,
784
+
.width = 2,
785
+
.flags = CLK_DIVIDER_POWER_OF_TWO,
786
+
},
787
+
.hw.init = &(struct clk_init_data){
788
+
.name = "hdmi_pll_od",
789
+
.ops = &clk_regmap_divider_ro_ops,
790
+
.parent_hws = (const struct clk_hw *[]) {
791
+
&g12a_hdmi_pll_dco.hw
792
+
},
793
+
.num_parents = 1,
794
+
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
795
+
},
796
+
};
797
+
798
+
static struct clk_regmap g12a_hdmi_pll_od2 = {
799
+
.data = &(struct clk_regmap_div_data){
800
+
.offset = HHI_HDMI_PLL_CNTL0,
801
+
.shift = 18,
802
+
.width = 2,
803
+
.flags = CLK_DIVIDER_POWER_OF_TWO,
804
+
},
805
+
.hw.init = &(struct clk_init_data){
806
+
.name = "hdmi_pll_od2",
807
+
.ops = &clk_regmap_divider_ro_ops,
808
+
.parent_hws = (const struct clk_hw *[]) {
809
+
&g12a_hdmi_pll_od.hw
810
+
},
811
+
.num_parents = 1,
812
+
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
813
+
},
814
+
};
815
+
816
+
static struct clk_regmap g12a_hdmi_pll = {
817
+
.data = &(struct clk_regmap_div_data){
818
+
.offset = HHI_HDMI_PLL_CNTL0,
819
+
.shift = 20,
820
+
.width = 2,
821
+
.flags = CLK_DIVIDER_POWER_OF_TWO,
822
+
},
823
+
.hw.init = &(struct clk_init_data){
824
+
.name = "hdmi_pll",
825
+
.ops = &clk_regmap_divider_ro_ops,
826
+
.parent_hws = (const struct clk_hw *[]) {
827
+
&g12a_hdmi_pll_od2.hw
828
+
},
829
+
.num_parents = 1,
830
+
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
831
+
},
832
+
};
833
+
389
834
static struct clk_fixed_factor g12a_fclk_div2_div = {
390
835
.mult = 1,
391
836
.div = 2,
···
904
459
},
905
460
};
906
461
462
+
463
+
static struct clk_fixed_factor g12a_fclk_div4_div = {
464
+
.mult = 1,
465
+
.div = 4,
466
+
.hw.init = &(struct clk_init_data){
467
+
.name = "fclk_div4_div",
468
+
.ops = &clk_fixed_factor_ops,
469
+
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
470
+
.num_parents = 1,
471
+
},
472
+
};
473
+
474
+
static struct clk_regmap g12a_fclk_div4 = {
475
+
.data = &(struct clk_regmap_gate_data){
476
+
.offset = HHI_FIX_PLL_CNTL1,
477
+
.bit_idx = 21,
478
+
},
479
+
.hw.init = &(struct clk_init_data){
480
+
.name = "fclk_div4",
481
+
.ops = &clk_regmap_gate_ops,
482
+
.parent_hws = (const struct clk_hw *[]) {
483
+
&g12a_fclk_div4_div.hw
484
+
},
485
+
.num_parents = 1,
486
+
},
487
+
};
488
+
489
+
static struct clk_fixed_factor g12a_fclk_div5_div = {
490
+
.mult = 1,
491
+
.div = 5,
492
+
.hw.init = &(struct clk_init_data){
493
+
.name = "fclk_div5_div",
494
+
.ops = &clk_fixed_factor_ops,
495
+
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
496
+
.num_parents = 1,
497
+
},
498
+
};
499
+
500
+
static struct clk_regmap g12a_fclk_div5 = {
501
+
.data = &(struct clk_regmap_gate_data){
502
+
.offset = HHI_FIX_PLL_CNTL1,
503
+
.bit_idx = 22,
504
+
},
505
+
.hw.init = &(struct clk_init_data){
506
+
.name = "fclk_div5",
507
+
.ops = &clk_regmap_gate_ops,
508
+
.parent_hws = (const struct clk_hw *[]) {
509
+
&g12a_fclk_div5_div.hw
510
+
},
511
+
.num_parents = 1,
512
+
},
513
+
};
514
+
515
+
static struct clk_fixed_factor g12a_fclk_div7_div = {
516
+
.mult = 1,
517
+
.div = 7,
518
+
.hw.init = &(struct clk_init_data){
519
+
.name = "fclk_div7_div",
520
+
.ops = &clk_fixed_factor_ops,
521
+
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
522
+
.num_parents = 1,
523
+
},
524
+
};
525
+
526
+
static struct clk_regmap g12a_fclk_div7 = {
527
+
.data = &(struct clk_regmap_gate_data){
528
+
.offset = HHI_FIX_PLL_CNTL1,
529
+
.bit_idx = 23,
530
+
},
531
+
.hw.init = &(struct clk_init_data){
532
+
.name = "fclk_div7",
533
+
.ops = &clk_regmap_gate_ops,
534
+
.parent_hws = (const struct clk_hw *[]) {
535
+
&g12a_fclk_div7_div.hw
536
+
},
537
+
.num_parents = 1,
538
+
},
539
+
};
540
+
541
+
static struct clk_fixed_factor g12a_fclk_div2p5_div = {
542
+
.mult = 1,
543
+
.div = 5,
544
+
.hw.init = &(struct clk_init_data){
545
+
.name = "fclk_div2p5_div",
546
+
.ops = &clk_fixed_factor_ops,
547
+
.parent_hws = (const struct clk_hw *[]) {
548
+
&g12a_fixed_pll_dco.hw
549
+
},
550
+
.num_parents = 1,
551
+
},
552
+
};
553
+
554
+
static struct clk_regmap g12a_fclk_div2p5 = {
555
+
.data = &(struct clk_regmap_gate_data){
556
+
.offset = HHI_FIX_PLL_CNTL1,
557
+
.bit_idx = 25,
558
+
},
559
+
.hw.init = &(struct clk_init_data){
560
+
.name = "fclk_div2p5",
561
+
.ops = &clk_regmap_gate_ops,
562
+
.parent_hws = (const struct clk_hw *[]) {
563
+
&g12a_fclk_div2p5_div.hw
564
+
},
565
+
.num_parents = 1,
566
+
},
567
+
};
568
+
569
+
static struct clk_fixed_factor g12a_mpll_50m_div = {
570
+
.mult = 1,
571
+
.div = 80,
572
+
.hw.init = &(struct clk_init_data){
573
+
.name = "mpll_50m_div",
574
+
.ops = &clk_fixed_factor_ops,
575
+
.parent_hws = (const struct clk_hw *[]) {
576
+
&g12a_fixed_pll_dco.hw
577
+
},
578
+
.num_parents = 1,
579
+
},
580
+
};
581
+
582
+
static struct clk_regmap g12a_mpll_50m = {
583
+
.data = &(struct clk_regmap_mux_data){
584
+
.offset = HHI_FIX_PLL_CNTL3,
585
+
.mask = 0x1,
586
+
.shift = 5,
587
+
},
588
+
.hw.init = &(struct clk_init_data){
589
+
.name = "mpll_50m",
590
+
.ops = &clk_regmap_mux_ro_ops,
591
+
.parent_data = (const struct clk_parent_data []) {
592
+
{ .fw_name = "xtal", },
593
+
{ .hw = &g12a_mpll_50m_div.hw },
594
+
},
595
+
.num_parents = 2,
596
+
},
597
+
};
598
+
599
+
static struct clk_fixed_factor g12a_mpll_prediv = {
600
+
.mult = 1,
601
+
.div = 2,
602
+
.hw.init = &(struct clk_init_data){
603
+
.name = "mpll_prediv",
604
+
.ops = &clk_fixed_factor_ops,
605
+
.parent_hws = (const struct clk_hw *[]) {
606
+
&g12a_fixed_pll_dco.hw
607
+
},
608
+
.num_parents = 1,
609
+
},
610
+
};
611
+
907
612
/* Datasheet names this field as "premux0" */
908
-
static struct clk_regmap g12a_cpu_clk_premux0 = {
613
+
static struct clk_regmap g12a_cpu_clk_dyn0_sel = {
909
614
.data = &(struct clk_regmap_mux_data){
910
615
.offset = HHI_SYS_CPU_CLK_CNTL0,
911
616
.mask = 0x3,
···
1075
480
},
1076
481
};
1077
482
483
+
/* Datasheet names this field as "mux0_divn_tcnt" */
484
+
static struct clk_regmap g12a_cpu_clk_dyn0_div = {
485
+
.data = &(struct meson_clk_cpu_dyndiv_data){
486
+
.div = {
487
+
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
488
+
.shift = 4,
489
+
.width = 6,
490
+
},
491
+
.dyn = {
492
+
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
493
+
.shift = 26,
494
+
.width = 1,
495
+
},
496
+
},
497
+
.hw.init = &(struct clk_init_data){
498
+
.name = "cpu_clk_dyn0_div",
499
+
.ops = &meson_clk_cpu_dyndiv_ops,
500
+
.parent_hws = (const struct clk_hw *[]) {
501
+
&g12a_cpu_clk_dyn0_sel.hw
502
+
},
503
+
.num_parents = 1,
504
+
.flags = CLK_SET_RATE_PARENT,
505
+
},
506
+
};
507
+
508
+
/* Datasheet names this field as "postmux0" */
509
+
static struct clk_regmap g12a_cpu_clk_dyn0 = {
510
+
.data = &(struct clk_regmap_mux_data){
511
+
.offset = HHI_SYS_CPU_CLK_CNTL0,
512
+
.mask = 0x1,
513
+
.shift = 2,
514
+
.flags = CLK_MUX_ROUND_CLOSEST,
515
+
},
516
+
.hw.init = &(struct clk_init_data){
517
+
.name = "cpu_clk_dyn0",
518
+
.ops = &clk_regmap_mux_ops,
519
+
.parent_hws = (const struct clk_hw *[]) {
520
+
&g12a_cpu_clk_dyn0_sel.hw,
521
+
&g12a_cpu_clk_dyn0_div.hw,
522
+
},
523
+
.num_parents = 2,
524
+
.flags = CLK_SET_RATE_PARENT,
525
+
},
526
+
};
527
+
1078
528
/* Datasheet names this field as "premux1" */
1079
-
static struct clk_regmap g12a_cpu_clk_premux1 = {
529
+
static struct clk_regmap g12a_cpu_clk_dyn1_sel = {
1080
530
.data = &(struct clk_regmap_mux_data){
1081
531
.offset = HHI_SYS_CPU_CLK_CNTL0,
1082
532
.mask = 0x3,
···
1141
501
},
1142
502
};
1143
503
1144
-
/* Datasheet names this field as "mux0_divn_tcnt" */
1145
-
static struct clk_regmap g12a_cpu_clk_mux0_div = {
1146
-
.data = &(struct meson_clk_cpu_dyndiv_data){
1147
-
.div = {
1148
-
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
1149
-
.shift = 4,
1150
-
.width = 6,
1151
-
},
1152
-
.dyn = {
1153
-
.reg_off = HHI_SYS_CPU_CLK_CNTL0,
1154
-
.shift = 26,
1155
-
.width = 1,
1156
-
},
1157
-
},
1158
-
.hw.init = &(struct clk_init_data){
1159
-
.name = "cpu_clk_dyn0_div",
1160
-
.ops = &meson_clk_cpu_dyndiv_ops,
1161
-
.parent_hws = (const struct clk_hw *[]) {
1162
-
&g12a_cpu_clk_premux0.hw
1163
-
},
1164
-
.num_parents = 1,
1165
-
.flags = CLK_SET_RATE_PARENT,
1166
-
},
1167
-
};
1168
-
1169
-
/* Datasheet names this field as "postmux0" */
1170
-
static struct clk_regmap g12a_cpu_clk_postmux0 = {
1171
-
.data = &(struct clk_regmap_mux_data){
1172
-
.offset = HHI_SYS_CPU_CLK_CNTL0,
1173
-
.mask = 0x1,
1174
-
.shift = 2,
1175
-
.flags = CLK_MUX_ROUND_CLOSEST,
1176
-
},
1177
-
.hw.init = &(struct clk_init_data){
1178
-
.name = "cpu_clk_dyn0",
1179
-
.ops = &clk_regmap_mux_ops,
1180
-
.parent_hws = (const struct clk_hw *[]) {
1181
-
&g12a_cpu_clk_premux0.hw,
1182
-
&g12a_cpu_clk_mux0_div.hw,
1183
-
},
1184
-
.num_parents = 2,
1185
-
.flags = CLK_SET_RATE_PARENT,
1186
-
},
1187
-
};
1188
-
1189
504
/* Datasheet names this field as "Mux1_divn_tcnt" */
1190
-
static struct clk_regmap g12a_cpu_clk_mux1_div = {
505
+
static struct clk_regmap g12a_cpu_clk_dyn1_div = {
1191
506
.data = &(struct clk_regmap_div_data){
1192
507
.offset = HHI_SYS_CPU_CLK_CNTL0,
1193
508
.shift = 20,
···
1152
557
.name = "cpu_clk_dyn1_div",
1153
558
.ops = &clk_regmap_divider_ro_ops,
1154
559
.parent_hws = (const struct clk_hw *[]) {
1155
-
&g12a_cpu_clk_premux1.hw
560
+
&g12a_cpu_clk_dyn1_sel.hw
1156
561
},
1157
562
.num_parents = 1,
1158
563
},
1159
564
};
1160
565
1161
566
/* Datasheet names this field as "postmux1" */
1162
-
static struct clk_regmap g12a_cpu_clk_postmux1 = {
567
+
static struct clk_regmap g12a_cpu_clk_dyn1 = {
1163
568
.data = &(struct clk_regmap_mux_data){
1164
569
.offset = HHI_SYS_CPU_CLK_CNTL0,
1165
570
.mask = 0x1,
···
1169
574
.name = "cpu_clk_dyn1",
1170
575
.ops = &clk_regmap_mux_ops,
1171
576
.parent_hws = (const struct clk_hw *[]) {
1172
-
&g12a_cpu_clk_premux1.hw,
1173
-
&g12a_cpu_clk_mux1_div.hw,
577
+
&g12a_cpu_clk_dyn1_sel.hw,
578
+
&g12a_cpu_clk_dyn1_div.hw,
1174
579
},
1175
580
.num_parents = 2,
1176
581
/* This sub-tree is used a parking clock */
···
1190
595
.name = "cpu_clk_dyn",
1191
596
.ops = &clk_regmap_mux_ops,
1192
597
.parent_hws = (const struct clk_hw *[]) {
1193
-
&g12a_cpu_clk_postmux0.hw,
1194
-
&g12a_cpu_clk_postmux1.hw,
598
+
&g12a_cpu_clk_dyn0.hw,
599
+
&g12a_cpu_clk_dyn1.hw,
1195
600
},
1196
601
.num_parents = 2,
1197
602
.flags = CLK_SET_RATE_PARENT,
···
1239
644
};
1240
645
1241
646
/* Datasheet names this field as "premux0" */
1242
-
static struct clk_regmap g12b_cpub_clk_premux0 = {
647
+
static struct clk_regmap g12b_cpub_clk_dyn0_sel = {
1243
648
.data = &(struct clk_regmap_mux_data){
1244
649
.offset = HHI_SYS_CPUB_CLK_CNTL,
1245
650
.mask = 0x3,
···
1260
665
};
1261
666
1262
667
/* Datasheet names this field as "mux0_divn_tcnt" */
1263
-
static struct clk_regmap g12b_cpub_clk_mux0_div = {
668
+
static struct clk_regmap g12b_cpub_clk_dyn0_div = {
1264
669
.data = &(struct meson_clk_cpu_dyndiv_data){
1265
670
.div = {
1266
671
.reg_off = HHI_SYS_CPUB_CLK_CNTL,
···
1277
682
.name = "cpub_clk_dyn0_div",
1278
683
.ops = &meson_clk_cpu_dyndiv_ops,
1279
684
.parent_hws = (const struct clk_hw *[]) {
1280
-
&g12b_cpub_clk_premux0.hw
685
+
&g12b_cpub_clk_dyn0_sel.hw
1281
686
},
1282
687
.num_parents = 1,
1283
688
.flags = CLK_SET_RATE_PARENT,
···
1285
690
};
1286
691
1287
692
/* Datasheet names this field as "postmux0" */
1288
-
static struct clk_regmap g12b_cpub_clk_postmux0 = {
693
+
static struct clk_regmap g12b_cpub_clk_dyn0 = {
1289
694
.data = &(struct clk_regmap_mux_data){
1290
695
.offset = HHI_SYS_CPUB_CLK_CNTL,
1291
696
.mask = 0x1,
···
1296
701
.name = "cpub_clk_dyn0",
1297
702
.ops = &clk_regmap_mux_ops,
1298
703
.parent_hws = (const struct clk_hw *[]) {
1299
-
&g12b_cpub_clk_premux0.hw,
1300
-
&g12b_cpub_clk_mux0_div.hw
704
+
&g12b_cpub_clk_dyn0_sel.hw,
705
+
&g12b_cpub_clk_dyn0_div.hw
1301
706
},
1302
707
.num_parents = 2,
1303
708
.flags = CLK_SET_RATE_PARENT,
···
1305
710
};
1306
711
1307
712
/* Datasheet names this field as "premux1" */
1308
-
static struct clk_regmap g12b_cpub_clk_premux1 = {
713
+
static struct clk_regmap g12b_cpub_clk_dyn1_sel = {
1309
714
.data = &(struct clk_regmap_mux_data){
1310
715
.offset = HHI_SYS_CPUB_CLK_CNTL,
1311
716
.mask = 0x3,
···
1326
731
};
1327
732
1328
733
/* Datasheet names this field as "Mux1_divn_tcnt" */
1329
-
static struct clk_regmap g12b_cpub_clk_mux1_div = {
734
+
static struct clk_regmap g12b_cpub_clk_dyn1_div = {
1330
735
.data = &(struct clk_regmap_div_data){
1331
736
.offset = HHI_SYS_CPUB_CLK_CNTL,
1332
737
.shift = 20,
···
1336
741
.name = "cpub_clk_dyn1_div",
1337
742
.ops = &clk_regmap_divider_ro_ops,
1338
743
.parent_hws = (const struct clk_hw *[]) {
1339
-
&g12b_cpub_clk_premux1.hw
744
+
&g12b_cpub_clk_dyn1_sel.hw
1340
745
},
1341
746
.num_parents = 1,
1342
747
},
1343
748
};
1344
749
1345
750
/* Datasheet names this field as "postmux1" */
1346
-
static struct clk_regmap g12b_cpub_clk_postmux1 = {
751
+
static struct clk_regmap g12b_cpub_clk_dyn1 = {
1347
752
.data = &(struct clk_regmap_mux_data){
1348
753
.offset = HHI_SYS_CPUB_CLK_CNTL,
1349
754
.mask = 0x1,
···
1353
758
.name = "cpub_clk_dyn1",
1354
759
.ops = &clk_regmap_mux_ops,
1355
760
.parent_hws = (const struct clk_hw *[]) {
1356
-
&g12b_cpub_clk_premux1.hw,
1357
-
&g12b_cpub_clk_mux1_div.hw
761
+
&g12b_cpub_clk_dyn1_sel.hw,
762
+
&g12b_cpub_clk_dyn1_div.hw
1358
763
},
1359
764
.num_parents = 2,
1360
765
/* This sub-tree is used a parking clock */
···
1374
779
.name = "cpub_clk_dyn",
1375
780
.ops = &clk_regmap_mux_ops,
1376
781
.parent_hws = (const struct clk_hw *[]) {
1377
-
&g12b_cpub_clk_postmux0.hw,
1378
-
&g12b_cpub_clk_postmux1.hw
782
+
&g12b_cpub_clk_dyn0.hw,
783
+
&g12b_cpub_clk_dyn1.hw
1379
784
},
1380
785
.num_parents = 2,
1381
786
.flags = CLK_SET_RATE_PARENT,
···
1402
807
},
1403
808
};
1404
809
1405
-
static struct clk_regmap sm1_gp1_pll;
1406
-
1407
810
/* Datasheet names this field as "premux0" */
1408
-
static struct clk_regmap sm1_dsu_clk_premux0 = {
811
+
static struct clk_regmap sm1_dsu_clk_dyn0_sel = {
1409
812
.data = &(struct clk_regmap_mux_data){
1410
813
.offset = HHI_SYS_CPU_CLK_CNTL5,
1411
814
.mask = 0x3,
···
1422
829
},
1423
830
};
1424
831
832
+
/* Datasheet names this field as "Mux0_divn_tcnt" */
833
+
static struct clk_regmap sm1_dsu_clk_dyn0_div = {
834
+
.data = &(struct clk_regmap_div_data){
835
+
.offset = HHI_SYS_CPU_CLK_CNTL5,
836
+
.shift = 4,
837
+
.width = 6,
838
+
},
839
+
.hw.init = &(struct clk_init_data){
840
+
.name = "dsu_clk_dyn0_div",
841
+
.ops = &clk_regmap_divider_ro_ops,
842
+
.parent_hws = (const struct clk_hw *[]) {
843
+
&sm1_dsu_clk_dyn0_sel.hw
844
+
},
845
+
.num_parents = 1,
846
+
},
847
+
};
848
+
849
+
/* Datasheet names this field as "postmux0" */
850
+
static struct clk_regmap sm1_dsu_clk_dyn0 = {
851
+
.data = &(struct clk_regmap_mux_data){
852
+
.offset = HHI_SYS_CPU_CLK_CNTL5,
853
+
.mask = 0x1,
854
+
.shift = 2,
855
+
},
856
+
.hw.init = &(struct clk_init_data){
857
+
.name = "dsu_clk_dyn0",
858
+
.ops = &clk_regmap_mux_ro_ops,
859
+
.parent_hws = (const struct clk_hw *[]) {
860
+
&sm1_dsu_clk_dyn0_sel.hw,
861
+
&sm1_dsu_clk_dyn0_div.hw,
862
+
},
863
+
.num_parents = 2,
864
+
},
865
+
};
866
+
1425
867
/* Datasheet names this field as "premux1" */
1426
-
static struct clk_regmap sm1_dsu_clk_premux1 = {
868
+
static struct clk_regmap sm1_dsu_clk_dyn1_sel = {
1427
869
.data = &(struct clk_regmap_mux_data){
1428
870
.offset = HHI_SYS_CPU_CLK_CNTL5,
1429
871
.mask = 0x3,
···
1477
849
},
1478
850
};
1479
851
1480
-
/* Datasheet names this field as "Mux0_divn_tcnt" */
1481
-
static struct clk_regmap sm1_dsu_clk_mux0_div = {
1482
-
.data = &(struct clk_regmap_div_data){
1483
-
.offset = HHI_SYS_CPU_CLK_CNTL5,
1484
-
.shift = 4,
1485
-
.width = 6,
1486
-
},
1487
-
.hw.init = &(struct clk_init_data){
1488
-
.name = "dsu_clk_dyn0_div",
1489
-
.ops = &clk_regmap_divider_ro_ops,
1490
-
.parent_hws = (const struct clk_hw *[]) {
1491
-
&sm1_dsu_clk_premux0.hw
1492
-
},
1493
-
.num_parents = 1,
1494
-
},
1495
-
};
1496
-
1497
-
/* Datasheet names this field as "postmux0" */
1498
-
static struct clk_regmap sm1_dsu_clk_postmux0 = {
1499
-
.data = &(struct clk_regmap_mux_data){
1500
-
.offset = HHI_SYS_CPU_CLK_CNTL5,
1501
-
.mask = 0x1,
1502
-
.shift = 2,
1503
-
},
1504
-
.hw.init = &(struct clk_init_data){
1505
-
.name = "dsu_clk_dyn0",
1506
-
.ops = &clk_regmap_mux_ro_ops,
1507
-
.parent_hws = (const struct clk_hw *[]) {
1508
-
&sm1_dsu_clk_premux0.hw,
1509
-
&sm1_dsu_clk_mux0_div.hw,
1510
-
},
1511
-
.num_parents = 2,
1512
-
},
1513
-
};
1514
-
1515
852
/* Datasheet names this field as "Mux1_divn_tcnt" */
1516
-
static struct clk_regmap sm1_dsu_clk_mux1_div = {
853
+
static struct clk_regmap sm1_dsu_clk_dyn1_div = {
1517
854
.data = &(struct clk_regmap_div_data){
1518
855
.offset = HHI_SYS_CPU_CLK_CNTL5,
1519
856
.shift = 20,
···
1488
895
.name = "dsu_clk_dyn1_div",
1489
896
.ops = &clk_regmap_divider_ro_ops,
1490
897
.parent_hws = (const struct clk_hw *[]) {
1491
-
&sm1_dsu_clk_premux1.hw
898
+
&sm1_dsu_clk_dyn1_sel.hw
1492
899
},
1493
900
.num_parents = 1,
1494
901
},
1495
902
};
1496
903
1497
904
/* Datasheet names this field as "postmux1" */
1498
-
static struct clk_regmap sm1_dsu_clk_postmux1 = {
905
+
static struct clk_regmap sm1_dsu_clk_dyn1 = {
1499
906
.data = &(struct clk_regmap_mux_data){
1500
907
.offset = HHI_SYS_CPU_CLK_CNTL5,
1501
908
.mask = 0x1,
···
1505
912
.name = "dsu_clk_dyn1",
1506
913
.ops = &clk_regmap_mux_ro_ops,
1507
914
.parent_hws = (const struct clk_hw *[]) {
1508
-
&sm1_dsu_clk_premux1.hw,
1509
-
&sm1_dsu_clk_mux1_div.hw,
915
+
&sm1_dsu_clk_dyn1_sel.hw,
916
+
&sm1_dsu_clk_dyn1_div.hw,
1510
917
},
1511
918
.num_parents = 2,
1512
919
},
···
1523
930
.name = "dsu_clk_dyn",
1524
931
.ops = &clk_regmap_mux_ro_ops,
1525
932
.parent_hws = (const struct clk_hw *[]) {
1526
-
&sm1_dsu_clk_postmux0.hw,
1527
-
&sm1_dsu_clk_postmux1.hw,
933
+
&sm1_dsu_clk_dyn0.hw,
934
+
&sm1_dsu_clk_dyn1.hw,
1528
935
},
1529
936
.num_parents = 2,
1530
937
},
···
1636
1043
.notifier_call = g12a_cpu_clk_mux_notifier_cb,
1637
1044
};
1638
1045
1639
-
struct g12a_cpu_clk_postmux_nb_data {
1046
+
struct g12a_cpu_clk_dyn_nb_data {
1640
1047
struct notifier_block nb;
1641
1048
struct clk_hw *xtal;
1642
1049
struct clk_hw *cpu_clk_dyn;
···
1645
1052
struct clk_hw *cpu_clk_premux1;
1646
1053
};
1647
1054
1648
-
static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
1649
-
unsigned long event, void *data)
1055
+
static int g12a_cpu_clk_dyn_notifier_cb(struct notifier_block *nb,
1056
+
unsigned long event, void *data)
1650
1057
{
1651
-
struct g12a_cpu_clk_postmux_nb_data *nb_data =
1652
-
container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
1058
+
struct g12a_cpu_clk_dyn_nb_data *nb_data =
1059
+
container_of(nb, struct g12a_cpu_clk_dyn_nb_data, nb);
1653
1060
1654
1061
switch (event) {
1655
1062
case PRE_RATE_CHANGE:
1656
1063
/*
1657
-
* This notifier means cpu_clk_postmux0 clock will be changed
1064
+
* This notifier means cpu_clk_dyn0 clock will be changed
1658
1065
* to feed cpu_clk, this is the current path :
1659
1066
* cpu_clk
1660
1067
* \- cpu_clk_dyn
1661
-
* \- cpu_clk_postmux0
1662
-
* \- cpu_clk_muxX_div
1663
-
* \- cpu_clk_premux0
1068
+
* \- cpu_clk_dyn0
1069
+
* \- cpu_clk_dyn0_div
1070
+
* \- cpu_clk_dyn0_sel
1664
1071
* \- fclk_div3 or fclk_div2
1665
1072
* OR
1666
-
* \- cpu_clk_premux0
1073
+
* \- cpu_clk_dyn0_sel
1667
1074
* \- fclk_div3 or fclk_div2
1668
1075
*/
1669
1076
1670
-
/* Setup cpu_clk_premux1 to xtal */
1077
+
/* Setup cpu_clk_dyn1_sel to xtal */
1671
1078
clk_hw_set_parent(nb_data->cpu_clk_premux1,
1672
1079
nb_data->xtal);
1673
1080
1674
-
/* Setup cpu_clk_postmux1 to bypass divider */
1081
+
/* Setup cpu_clk_dyn1 to bypass divider */
1675
1082
clk_hw_set_parent(nb_data->cpu_clk_postmux1,
1676
1083
nb_data->cpu_clk_premux1);
1677
1084
···
1683
1090
* Now, cpu_clk is 24MHz in the current path :
1684
1091
* cpu_clk
1685
1092
* \- cpu_clk_dyn
1686
-
* \- cpu_clk_postmux1
1687
-
* \- cpu_clk_premux1
1093
+
* \- cpu_clk_dyn1
1094
+
* \- cpu_clk_dyn1_sel
1688
1095
* \- xtal
1689
1096
*/
1690
1097
···
1694
1101
1695
1102
case POST_RATE_CHANGE:
1696
1103
/*
1697
-
* The cpu_clk_postmux0 has ben updated, now switch back
1698
-
* cpu_clk_dyn to cpu_clk_postmux0 and take the changes
1104
+
* The cpu_clk_dyn0 has ben updated, now switch back
1105
+
* cpu_clk_dyn to cpu_clk_dyn0 and take the changes
1699
1106
* in account.
1700
1107
*/
1701
1108
···
1707
1114
* new path :
1708
1115
* cpu_clk
1709
1116
* \- cpu_clk_dyn
1710
-
* \- cpu_clk_postmux0
1711
-
* \- cpu_clk_muxX_div
1712
-
* \- cpu_clk_premux0
1117
+
* \- cpu_clk_dyn0
1118
+
* \- cpu_clk_dyn0_div
1119
+
* \- cpu_clk_dyn0_sel
1713
1120
* \- fclk_div3 or fclk_div2
1714
1121
* OR
1715
-
* \- cpu_clk_premux0
1122
+
* \- cpu_clk_dyn0_sel
1716
1123
* \- fclk_div3 or fclk_div2
1717
1124
*/
1718
1125
···
1725
1132
}
1726
1133
}
1727
1134
1728
-
static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1135
+
static struct g12a_cpu_clk_dyn_nb_data g12a_cpu_clk_dyn0_nb_data = {
1729
1136
.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1730
-
.cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1731
-
.cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1732
-
.cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1733
-
.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1137
+
.cpu_clk_postmux0 = &g12a_cpu_clk_dyn0.hw,
1138
+
.cpu_clk_postmux1 = &g12a_cpu_clk_dyn1.hw,
1139
+
.cpu_clk_premux1 = &g12a_cpu_clk_dyn1_sel.hw,
1140
+
.nb.notifier_call = g12a_cpu_clk_dyn_notifier_cb,
1734
1141
};
1735
1142
1736
-
static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1143
+
static struct g12a_cpu_clk_dyn_nb_data g12b_cpub_clk_dyn0_nb_data = {
1737
1144
.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1738
-
.cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1739
-
.cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1740
-
.cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1741
-
.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1145
+
.cpu_clk_postmux0 = &g12b_cpub_clk_dyn0.hw,
1146
+
.cpu_clk_postmux1 = &g12b_cpub_clk_dyn1.hw,
1147
+
.cpu_clk_premux1 = &g12b_cpub_clk_dyn1_sel.hw,
1148
+
.nb.notifier_call = g12a_cpu_clk_dyn_notifier_cb,
1742
1149
};
1743
1150
1744
1151
struct g12a_sys_pll_nb_data {
···
2144
1551
},
2145
1552
};
2146
1553
2147
-
static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1554
+
static u32 g12b_cpub_clk_if_parents_val_table[] = { 1, 2, 3, 4, 5, 6, 7 };
1555
+
static const struct clk_hw *g12b_cpub_clk_if_parents[] = {
1556
+
&g12b_cpub_clk_div2.hw,
1557
+
&g12b_cpub_clk_div3.hw,
1558
+
&g12b_cpub_clk_div4.hw,
1559
+
&g12b_cpub_clk_div5.hw,
1560
+
&g12b_cpub_clk_div6.hw,
1561
+
&g12b_cpub_clk_div7.hw,
1562
+
&g12b_cpub_clk_div8.hw,
1563
+
};
1564
+
2148
1565
static struct clk_regmap g12b_cpub_clk_apb_sel = {
2149
1566
.data = &(struct clk_regmap_mux_data){
2150
1567
.offset = HHI_SYS_CPUB_CLK_CNTL1,
2151
1568
.mask = 7,
2152
1569
.shift = 3,
2153
-
.table = mux_table_cpub,
1570
+
.table = g12b_cpub_clk_if_parents_val_table,
2154
1571
},
2155
1572
.hw.init = &(struct clk_init_data){
2156
1573
.name = "cpub_clk_apb_sel",
2157
1574
.ops = &clk_regmap_mux_ro_ops,
2158
-
.parent_hws = (const struct clk_hw *[]) {
2159
-
&g12b_cpub_clk_div2.hw,
2160
-
&g12b_cpub_clk_div3.hw,
2161
-
&g12b_cpub_clk_div4.hw,
2162
-
&g12b_cpub_clk_div5.hw,
2163
-
&g12b_cpub_clk_div6.hw,
2164
-
&g12b_cpub_clk_div7.hw,
2165
-
&g12b_cpub_clk_div8.hw
2166
-
},
2167
-
.num_parents = 7,
1575
+
.parent_hws = g12b_cpub_clk_if_parents,
1576
+
.num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2168
1577
},
2169
1578
};
2170
1579
···
2195
1600
.offset = HHI_SYS_CPUB_CLK_CNTL1,
2196
1601
.mask = 7,
2197
1602
.shift = 6,
2198
-
.table = mux_table_cpub,
1603
+
.table = g12b_cpub_clk_if_parents_val_table,
2199
1604
},
2200
1605
.hw.init = &(struct clk_init_data){
2201
1606
.name = "cpub_clk_atb_sel",
2202
1607
.ops = &clk_regmap_mux_ro_ops,
2203
-
.parent_hws = (const struct clk_hw *[]) {
2204
-
&g12b_cpub_clk_div2.hw,
2205
-
&g12b_cpub_clk_div3.hw,
2206
-
&g12b_cpub_clk_div4.hw,
2207
-
&g12b_cpub_clk_div5.hw,
2208
-
&g12b_cpub_clk_div6.hw,
2209
-
&g12b_cpub_clk_div7.hw,
2210
-
&g12b_cpub_clk_div8.hw
2211
-
},
2212
-
.num_parents = 7,
1608
+
.parent_hws = g12b_cpub_clk_if_parents,
1609
+
.num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2213
1610
},
2214
1611
};
2215
1612
···
2230
1643
.offset = HHI_SYS_CPUB_CLK_CNTL1,
2231
1644
.mask = 7,
2232
1645
.shift = 9,
2233
-
.table = mux_table_cpub,
1646
+
.table = g12b_cpub_clk_if_parents_val_table,
2234
1647
},
2235
1648
.hw.init = &(struct clk_init_data){
2236
1649
.name = "cpub_clk_axi_sel",
2237
1650
.ops = &clk_regmap_mux_ro_ops,
2238
-
.parent_hws = (const struct clk_hw *[]) {
2239
-
&g12b_cpub_clk_div2.hw,
2240
-
&g12b_cpub_clk_div3.hw,
2241
-
&g12b_cpub_clk_div4.hw,
2242
-
&g12b_cpub_clk_div5.hw,
2243
-
&g12b_cpub_clk_div6.hw,
2244
-
&g12b_cpub_clk_div7.hw,
2245
-
&g12b_cpub_clk_div8.hw
2246
-
},
2247
-
.num_parents = 7,
1651
+
.parent_hws = g12b_cpub_clk_if_parents,
1652
+
.num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2248
1653
},
2249
1654
};
2250
1655
···
2265
1686
.offset = HHI_SYS_CPUB_CLK_CNTL1,
2266
1687
.mask = 7,
2267
1688
.shift = 20,
2268
-
.table = mux_table_cpub,
1689
+
.table = g12b_cpub_clk_if_parents_val_table,
2269
1690
},
2270
1691
.hw.init = &(struct clk_init_data){
2271
1692
.name = "cpub_clk_trace_sel",
2272
1693
.ops = &clk_regmap_mux_ro_ops,
2273
-
.parent_hws = (const struct clk_hw *[]) {
2274
-
&g12b_cpub_clk_div2.hw,
2275
-
&g12b_cpub_clk_div3.hw,
2276
-
&g12b_cpub_clk_div4.hw,
2277
-
&g12b_cpub_clk_div5.hw,
2278
-
&g12b_cpub_clk_div6.hw,
2279
-
&g12b_cpub_clk_div7.hw,
2280
-
&g12b_cpub_clk_div8.hw
2281
-
},
2282
-
.num_parents = 7,
1694
+
.parent_hws = g12b_cpub_clk_if_parents,
1695
+
.num_parents = ARRAY_SIZE(g12b_cpub_clk_if_parents),
2283
1696
},
2284
1697
};
2285
1698
···
2292
1721
* This clock is set by the ROM monitor code,
2293
1722
* Linux should not change it at runtime
2294
1723
*/
2295
-
},
2296
-
};
2297
-
2298
-
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
2299
-
.min = 125,
2300
-
.max = 255,
2301
-
};
2302
-
2303
-
/*
2304
-
* Internal gp0 pll emulation configuration parameters
2305
-
*/
2306
-
static const struct reg_sequence g12a_gp0_init_regs[] = {
2307
-
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
2308
-
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
2309
-
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
2310
-
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
2311
-
{ .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
2312
-
{ .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
2313
-
};
2314
-
2315
-
static struct clk_regmap g12a_gp0_pll_dco = {
2316
-
.data = &(struct meson_clk_pll_data){
2317
-
.en = {
2318
-
.reg_off = HHI_GP0_PLL_CNTL0,
2319
-
.shift = 28,
2320
-
.width = 1,
2321
-
},
2322
-
.m = {
2323
-
.reg_off = HHI_GP0_PLL_CNTL0,
2324
-
.shift = 0,
2325
-
.width = 8,
2326
-
},
2327
-
.n = {
2328
-
.reg_off = HHI_GP0_PLL_CNTL0,
2329
-
.shift = 10,
2330
-
.width = 5,
2331
-
},
2332
-
.frac = {
2333
-
.reg_off = HHI_GP0_PLL_CNTL1,
2334
-
.shift = 0,
2335
-
.width = 17,
2336
-
},
2337
-
.l = {
2338
-
.reg_off = HHI_GP0_PLL_CNTL0,
2339
-
.shift = 31,
2340
-
.width = 1,
2341
-
},
2342
-
.rst = {
2343
-
.reg_off = HHI_GP0_PLL_CNTL0,
2344
-
.shift = 29,
2345
-
.width = 1,
2346
-
},
2347
-
.range = &g12a_gp0_pll_mult_range,
2348
-
.init_regs = g12a_gp0_init_regs,
2349
-
.init_count = ARRAY_SIZE(g12a_gp0_init_regs),
2350
-
},
2351
-
.hw.init = &(struct clk_init_data){
2352
-
.name = "gp0_pll_dco",
2353
-
.ops = &meson_clk_pll_ops,
2354
-
.parent_data = &(const struct clk_parent_data) {
2355
-
.fw_name = "xtal",
2356
-
},
2357
-
.num_parents = 1,
2358
-
},
2359
-
};
2360
-
2361
-
static struct clk_regmap g12a_gp0_pll = {
2362
-
.data = &(struct clk_regmap_div_data){
2363
-
.offset = HHI_GP0_PLL_CNTL0,
2364
-
.shift = 16,
2365
-
.width = 3,
2366
-
.flags = (CLK_DIVIDER_POWER_OF_TWO |
2367
-
CLK_DIVIDER_ROUND_CLOSEST),
2368
-
},
2369
-
.hw.init = &(struct clk_init_data){
2370
-
.name = "gp0_pll",
2371
-
.ops = &clk_regmap_divider_ops,
2372
-
.parent_hws = (const struct clk_hw *[]) {
2373
-
&g12a_gp0_pll_dco.hw
2374
-
},
2375
-
.num_parents = 1,
2376
-
.flags = CLK_SET_RATE_PARENT,
2377
-
},
2378
-
};
2379
-
2380
-
static struct clk_regmap sm1_gp1_pll_dco = {
2381
-
.data = &(struct meson_clk_pll_data){
2382
-
.en = {
2383
-
.reg_off = HHI_GP1_PLL_CNTL0,
2384
-
.shift = 28,
2385
-
.width = 1,
2386
-
},
2387
-
.m = {
2388
-
.reg_off = HHI_GP1_PLL_CNTL0,
2389
-
.shift = 0,
2390
-
.width = 8,
2391
-
},
2392
-
.n = {
2393
-
.reg_off = HHI_GP1_PLL_CNTL0,
2394
-
.shift = 10,
2395
-
.width = 5,
2396
-
},
2397
-
.frac = {
2398
-
.reg_off = HHI_GP1_PLL_CNTL1,
2399
-
.shift = 0,
2400
-
.width = 17,
2401
-
},
2402
-
.l = {
2403
-
.reg_off = HHI_GP1_PLL_CNTL0,
2404
-
.shift = 31,
2405
-
.width = 1,
2406
-
},
2407
-
.rst = {
2408
-
.reg_off = HHI_GP1_PLL_CNTL0,
2409
-
.shift = 29,
2410
-
.width = 1,
2411
-
},
2412
-
},
2413
-
.hw.init = &(struct clk_init_data){
2414
-
.name = "gp1_pll_dco",
2415
-
.ops = &meson_clk_pll_ro_ops,
2416
-
.parent_data = &(const struct clk_parent_data) {
2417
-
.fw_name = "xtal",
2418
-
},
2419
-
.num_parents = 1,
2420
-
/* This clock feeds the DSU, avoid disabling it */
2421
-
.flags = CLK_IS_CRITICAL,
2422
-
},
2423
-
};
2424
-
2425
-
static struct clk_regmap sm1_gp1_pll = {
2426
-
.data = &(struct clk_regmap_div_data){
2427
-
.offset = HHI_GP1_PLL_CNTL0,
2428
-
.shift = 16,
2429
-
.width = 3,
2430
-
.flags = (CLK_DIVIDER_POWER_OF_TWO |
2431
-
CLK_DIVIDER_ROUND_CLOSEST),
2432
-
},
2433
-
.hw.init = &(struct clk_init_data){
2434
-
.name = "gp1_pll",
2435
-
.ops = &clk_regmap_divider_ro_ops,
2436
-
.parent_hws = (const struct clk_hw *[]) {
2437
-
&sm1_gp1_pll_dco.hw
2438
-
},
2439
-
.num_parents = 1,
2440
-
},
2441
-
};
2442
-
2443
-
/*
2444
-
* Internal hifi pll emulation configuration parameters
2445
-
*/
2446
-
static const struct reg_sequence g12a_hifi_init_regs[] = {
2447
-
{ .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
2448
-
{ .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
2449
-
{ .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
2450
-
{ .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
2451
-
{ .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
2452
-
{ .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
2453
-
};
2454
-
2455
-
static struct clk_regmap g12a_hifi_pll_dco = {
2456
-
.data = &(struct meson_clk_pll_data){
2457
-
.en = {
2458
-
.reg_off = HHI_HIFI_PLL_CNTL0,
2459
-
.shift = 28,
2460
-
.width = 1,
2461
-
},
2462
-
.m = {
2463
-
.reg_off = HHI_HIFI_PLL_CNTL0,
2464
-
.shift = 0,
2465
-
.width = 8,
2466
-
},
2467
-
.n = {
2468
-
.reg_off = HHI_HIFI_PLL_CNTL0,
2469
-
.shift = 10,
2470
-
.width = 5,
2471
-
},
2472
-
.frac = {
2473
-
.reg_off = HHI_HIFI_PLL_CNTL1,
2474
-
.shift = 0,
2475
-
.width = 17,
2476
-
},
2477
-
.l = {
2478
-
.reg_off = HHI_HIFI_PLL_CNTL0,
2479
-
.shift = 31,
2480
-
.width = 1,
2481
-
},
2482
-
.rst = {
2483
-
.reg_off = HHI_HIFI_PLL_CNTL0,
2484
-
.shift = 29,
2485
-
.width = 1,
2486
-
},
2487
-
.range = &g12a_gp0_pll_mult_range,
2488
-
.init_regs = g12a_hifi_init_regs,
2489
-
.init_count = ARRAY_SIZE(g12a_hifi_init_regs),
2490
-
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
2491
-
},
2492
-
.hw.init = &(struct clk_init_data){
2493
-
.name = "hifi_pll_dco",
2494
-
.ops = &meson_clk_pll_ops,
2495
-
.parent_data = &(const struct clk_parent_data) {
2496
-
.fw_name = "xtal",
2497
-
},
2498
-
.num_parents = 1,
2499
-
},
2500
-
};
2501
-
2502
-
static struct clk_regmap g12a_hifi_pll = {
2503
-
.data = &(struct clk_regmap_div_data){
2504
-
.offset = HHI_HIFI_PLL_CNTL0,
2505
-
.shift = 16,
2506
-
.width = 2,
2507
-
.flags = (CLK_DIVIDER_POWER_OF_TWO |
2508
-
CLK_DIVIDER_ROUND_CLOSEST),
2509
-
},
2510
-
.hw.init = &(struct clk_init_data){
2511
-
.name = "hifi_pll",
2512
-
.ops = &clk_regmap_divider_ops,
2513
-
.parent_hws = (const struct clk_hw *[]) {
2514
-
&g12a_hifi_pll_dco.hw
2515
-
},
2516
-
.num_parents = 1,
2517
-
.flags = CLK_SET_RATE_PARENT,
2518
-
},
2519
-
};
2520
-
2521
-
/*
2522
-
* The Meson G12A PCIE PLL is fined tuned to deliver a very precise
2523
-
* 100MHz reference clock for the PCIe Analog PHY, and thus requires
2524
-
* a strict register sequence to enable the PLL.
2525
-
*/
2526
-
static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
2527
-
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
2528
-
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
2529
-
{ .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
2530
-
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
2531
-
{ .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
2532
-
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
2533
-
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
2534
-
{ .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
2535
-
{ .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
2536
-
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
2537
-
{ .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
2538
-
{ .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
2539
-
};
2540
-
2541
-
/* Keep a single entry table for recalc/round_rate() ops */
2542
-
static const struct pll_params_table g12a_pcie_pll_table[] = {
2543
-
PLL_PARAMS(150, 1),
2544
-
{0, 0},
2545
-
};
2546
-
2547
-
static struct clk_regmap g12a_pcie_pll_dco = {
2548
-
.data = &(struct meson_clk_pll_data){
2549
-
.en = {
2550
-
.reg_off = HHI_PCIE_PLL_CNTL0,
2551
-
.shift = 28,
2552
-
.width = 1,
2553
-
},
2554
-
.m = {
2555
-
.reg_off = HHI_PCIE_PLL_CNTL0,
2556
-
.shift = 0,
2557
-
.width = 8,
2558
-
},
2559
-
.n = {
2560
-
.reg_off = HHI_PCIE_PLL_CNTL0,
2561
-
.shift = 10,
2562
-
.width = 5,
2563
-
},
2564
-
.frac = {
2565
-
.reg_off = HHI_PCIE_PLL_CNTL1,
2566
-
.shift = 0,
2567
-
.width = 12,
2568
-
},
2569
-
.l = {
2570
-
.reg_off = HHI_PCIE_PLL_CNTL0,
2571
-
.shift = 31,
2572
-
.width = 1,
2573
-
},
2574
-
.rst = {
2575
-
.reg_off = HHI_PCIE_PLL_CNTL0,
2576
-
.shift = 29,
2577
-
.width = 1,
2578
-
},
2579
-
.table = g12a_pcie_pll_table,
2580
-
.init_regs = g12a_pcie_pll_init_regs,
2581
-
.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
2582
-
},
2583
-
.hw.init = &(struct clk_init_data){
2584
-
.name = "pcie_pll_dco",
2585
-
.ops = &meson_clk_pcie_pll_ops,
2586
-
.parent_data = &(const struct clk_parent_data) {
2587
-
.fw_name = "xtal",
2588
-
},
2589
-
.num_parents = 1,
2590
-
},
2591
-
};
2592
-
2593
-
static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
2594
-
.mult = 1,
2595
-
.div = 2,
2596
-
.hw.init = &(struct clk_init_data){
2597
-
.name = "pcie_pll_dco_div2",
2598
-
.ops = &clk_fixed_factor_ops,
2599
-
.parent_hws = (const struct clk_hw *[]) {
2600
-
&g12a_pcie_pll_dco.hw
2601
-
},
2602
-
.num_parents = 1,
2603
-
.flags = CLK_SET_RATE_PARENT,
2604
-
},
2605
-
};
2606
-
2607
-
static struct clk_regmap g12a_pcie_pll_od = {
2608
-
.data = &(struct clk_regmap_div_data){
2609
-
.offset = HHI_PCIE_PLL_CNTL0,
2610
-
.shift = 16,
2611
-
.width = 5,
2612
-
.flags = CLK_DIVIDER_ROUND_CLOSEST |
2613
-
CLK_DIVIDER_ONE_BASED |
2614
-
CLK_DIVIDER_ALLOW_ZERO,
2615
-
},
2616
-
.hw.init = &(struct clk_init_data){
2617
-
.name = "pcie_pll_od",
2618
-
.ops = &clk_regmap_divider_ops,
2619
-
.parent_hws = (const struct clk_hw *[]) {
2620
-
&g12a_pcie_pll_dco_div2.hw
2621
-
},
2622
-
.num_parents = 1,
2623
-
.flags = CLK_SET_RATE_PARENT,
2624
-
},
2625
-
};
2626
-
2627
-
static struct clk_fixed_factor g12a_pcie_pll = {
2628
-
.mult = 1,
2629
-
.div = 2,
2630
-
.hw.init = &(struct clk_init_data){
2631
-
.name = "pcie_pll_pll",
2632
-
.ops = &clk_fixed_factor_ops,
2633
-
.parent_hws = (const struct clk_hw *[]) {
2634
-
&g12a_pcie_pll_od.hw
2635
-
},
2636
-
.num_parents = 1,
2637
-
.flags = CLK_SET_RATE_PARENT,
2638
-
},
2639
-
};
2640
-
2641
-
static struct clk_regmap g12a_hdmi_pll_dco = {
2642
-
.data = &(struct meson_clk_pll_data){
2643
-
.en = {
2644
-
.reg_off = HHI_HDMI_PLL_CNTL0,
2645
-
.shift = 28,
2646
-
.width = 1,
2647
-
},
2648
-
.m = {
2649
-
.reg_off = HHI_HDMI_PLL_CNTL0,
2650
-
.shift = 0,
2651
-
.width = 8,
2652
-
},
2653
-
.n = {
2654
-
.reg_off = HHI_HDMI_PLL_CNTL0,
2655
-
.shift = 10,
2656
-
.width = 5,
2657
-
},
2658
-
.frac = {
2659
-
.reg_off = HHI_HDMI_PLL_CNTL1,
2660
-
.shift = 0,
2661
-
.width = 16,
2662
-
},
2663
-
.l = {
2664
-
.reg_off = HHI_HDMI_PLL_CNTL0,
2665
-
.shift = 30,
2666
-
.width = 1,
2667
-
},
2668
-
.rst = {
2669
-
.reg_off = HHI_HDMI_PLL_CNTL0,
2670
-
.shift = 29,
2671
-
.width = 1,
2672
-
},
2673
-
},
2674
-
.hw.init = &(struct clk_init_data){
2675
-
.name = "hdmi_pll_dco",
2676
-
.ops = &meson_clk_pll_ro_ops,
2677
-
.parent_data = &(const struct clk_parent_data) {
2678
-
.fw_name = "xtal",
2679
-
},
2680
-
.num_parents = 1,
2681
-
/*
2682
-
* Display directly handle hdmi pll registers ATM, we need
2683
-
* NOCACHE to keep our view of the clock as accurate as possible
2684
-
*/
2685
-
.flags = CLK_GET_RATE_NOCACHE,
2686
-
},
2687
-
};
2688
-
2689
-
static struct clk_regmap g12a_hdmi_pll_od = {
2690
-
.data = &(struct clk_regmap_div_data){
2691
-
.offset = HHI_HDMI_PLL_CNTL0,
2692
-
.shift = 16,
2693
-
.width = 2,
2694
-
.flags = CLK_DIVIDER_POWER_OF_TWO,
2695
-
},
2696
-
.hw.init = &(struct clk_init_data){
2697
-
.name = "hdmi_pll_od",
2698
-
.ops = &clk_regmap_divider_ro_ops,
2699
-
.parent_hws = (const struct clk_hw *[]) {
2700
-
&g12a_hdmi_pll_dco.hw
2701
-
},
2702
-
.num_parents = 1,
2703
-
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2704
-
},
2705
-
};
2706
-
2707
-
static struct clk_regmap g12a_hdmi_pll_od2 = {
2708
-
.data = &(struct clk_regmap_div_data){
2709
-
.offset = HHI_HDMI_PLL_CNTL0,
2710
-
.shift = 18,
2711
-
.width = 2,
2712
-
.flags = CLK_DIVIDER_POWER_OF_TWO,
2713
-
},
2714
-
.hw.init = &(struct clk_init_data){
2715
-
.name = "hdmi_pll_od2",
2716
-
.ops = &clk_regmap_divider_ro_ops,
2717
-
.parent_hws = (const struct clk_hw *[]) {
2718
-
&g12a_hdmi_pll_od.hw
2719
-
},
2720
-
.num_parents = 1,
2721
-
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2722
-
},
2723
-
};
2724
-
2725
-
static struct clk_regmap g12a_hdmi_pll = {
2726
-
.data = &(struct clk_regmap_div_data){
2727
-
.offset = HHI_HDMI_PLL_CNTL0,
2728
-
.shift = 20,
2729
-
.width = 2,
2730
-
.flags = CLK_DIVIDER_POWER_OF_TWO,
2731
-
},
2732
-
.hw.init = &(struct clk_init_data){
2733
-
.name = "hdmi_pll",
2734
-
.ops = &clk_regmap_divider_ro_ops,
2735
-
.parent_hws = (const struct clk_hw *[]) {
2736
-
&g12a_hdmi_pll_od2.hw
2737
-
},
2738
-
.num_parents = 1,
2739
-
.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2740
-
},
2741
-
};
2742
-
2743
-
static struct clk_fixed_factor g12a_fclk_div4_div = {
2744
-
.mult = 1,
2745
-
.div = 4,
2746
-
.hw.init = &(struct clk_init_data){
2747
-
.name = "fclk_div4_div",
2748
-
.ops = &clk_fixed_factor_ops,
2749
-
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2750
-
.num_parents = 1,
2751
-
},
2752
-
};
2753
-
2754
-
static struct clk_regmap g12a_fclk_div4 = {
2755
-
.data = &(struct clk_regmap_gate_data){
2756
-
.offset = HHI_FIX_PLL_CNTL1,
2757
-
.bit_idx = 21,
2758
-
},
2759
-
.hw.init = &(struct clk_init_data){
2760
-
.name = "fclk_div4",
2761
-
.ops = &clk_regmap_gate_ops,
2762
-
.parent_hws = (const struct clk_hw *[]) {
2763
-
&g12a_fclk_div4_div.hw
2764
-
},
2765
-
.num_parents = 1,
2766
-
},
2767
-
};
2768
-
2769
-
static struct clk_fixed_factor g12a_fclk_div5_div = {
2770
-
.mult = 1,
2771
-
.div = 5,
2772
-
.hw.init = &(struct clk_init_data){
2773
-
.name = "fclk_div5_div",
2774
-
.ops = &clk_fixed_factor_ops,
2775
-
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2776
-
.num_parents = 1,
2777
-
},
2778
-
};
2779
-
2780
-
static struct clk_regmap g12a_fclk_div5 = {
2781
-
.data = &(struct clk_regmap_gate_data){
2782
-
.offset = HHI_FIX_PLL_CNTL1,
2783
-
.bit_idx = 22,
2784
-
},
2785
-
.hw.init = &(struct clk_init_data){
2786
-
.name = "fclk_div5",
2787
-
.ops = &clk_regmap_gate_ops,
2788
-
.parent_hws = (const struct clk_hw *[]) {
2789
-
&g12a_fclk_div5_div.hw
2790
-
},
2791
-
.num_parents = 1,
2792
-
},
2793
-
};
2794
-
2795
-
static struct clk_fixed_factor g12a_fclk_div7_div = {
2796
-
.mult = 1,
2797
-
.div = 7,
2798
-
.hw.init = &(struct clk_init_data){
2799
-
.name = "fclk_div7_div",
2800
-
.ops = &clk_fixed_factor_ops,
2801
-
.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2802
-
.num_parents = 1,
2803
-
},
2804
-
};
2805
-
2806
-
static struct clk_regmap g12a_fclk_div7 = {
2807
-
.data = &(struct clk_regmap_gate_data){
2808
-
.offset = HHI_FIX_PLL_CNTL1,
2809
-
.bit_idx = 23,
2810
-
},
2811
-
.hw.init = &(struct clk_init_data){
2812
-
.name = "fclk_div7",
2813
-
.ops = &clk_regmap_gate_ops,
2814
-
.parent_hws = (const struct clk_hw *[]) {
2815
-
&g12a_fclk_div7_div.hw
2816
-
},
2817
-
.num_parents = 1,
2818
-
},
2819
-
};
2820
-
2821
-
static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2822
-
.mult = 1,
2823
-
.div = 5,
2824
-
.hw.init = &(struct clk_init_data){
2825
-
.name = "fclk_div2p5_div",
2826
-
.ops = &clk_fixed_factor_ops,
2827
-
.parent_hws = (const struct clk_hw *[]) {
2828
-
&g12a_fixed_pll_dco.hw
2829
-
},
2830
-
.num_parents = 1,
2831
-
},
2832
-
};
2833
-
2834
-
static struct clk_regmap g12a_fclk_div2p5 = {
2835
-
.data = &(struct clk_regmap_gate_data){
2836
-
.offset = HHI_FIX_PLL_CNTL1,
2837
-
.bit_idx = 25,
2838
-
},
2839
-
.hw.init = &(struct clk_init_data){
2840
-
.name = "fclk_div2p5",
2841
-
.ops = &clk_regmap_gate_ops,
2842
-
.parent_hws = (const struct clk_hw *[]) {
2843
-
&g12a_fclk_div2p5_div.hw
2844
-
},
2845
-
.num_parents = 1,
2846
-
},
2847
-
};
2848
-
2849
-
static struct clk_fixed_factor g12a_mpll_50m_div = {
2850
-
.mult = 1,
2851
-
.div = 80,
2852
-
.hw.init = &(struct clk_init_data){
2853
-
.name = "mpll_50m_div",
2854
-
.ops = &clk_fixed_factor_ops,
2855
-
.parent_hws = (const struct clk_hw *[]) {
2856
-
&g12a_fixed_pll_dco.hw
2857
-
},
2858
-
.num_parents = 1,
2859
-
},
2860
-
};
2861
-
2862
-
static struct clk_regmap g12a_mpll_50m = {
2863
-
.data = &(struct clk_regmap_mux_data){
2864
-
.offset = HHI_FIX_PLL_CNTL3,
2865
-
.mask = 0x1,
2866
-
.shift = 5,
2867
-
},
2868
-
.hw.init = &(struct clk_init_data){
2869
-
.name = "mpll_50m",
2870
-
.ops = &clk_regmap_mux_ro_ops,
2871
-
.parent_data = (const struct clk_parent_data []) {
2872
-
{ .fw_name = "xtal", },
2873
-
{ .hw = &g12a_mpll_50m_div.hw },
2874
-
},
2875
-
.num_parents = 2,
2876
-
},
2877
-
};
2878
-
2879
-
static struct clk_fixed_factor g12a_mpll_prediv = {
2880
-
.mult = 1,
2881
-
.div = 2,
2882
-
.hw.init = &(struct clk_init_data){
2883
-
.name = "mpll_prediv",
2884
-
.ops = &clk_fixed_factor_ops,
2885
-
.parent_hws = (const struct clk_hw *[]) {
2886
-
&g12a_fixed_pll_dco.hw
2887
-
},
2888
-
.num_parents = 1,
2889
1724
},
2890
1725
};
2891
1726
···
2507
2530
},
2508
2531
};
2509
2532
2510
-
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
2511
-
static const struct clk_parent_data clk81_parent_data[] = {
2533
+
/* clk81 is often referred as "mpeg_clk" */
2534
+
static u32 g12a_clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
2535
+
static const struct clk_parent_data g12a_clk81_parents[] = {
2512
2536
{ .fw_name = "xtal", },
2513
2537
{ .hw = &g12a_fclk_div7.hw },
2514
2538
{ .hw = &g12a_mpll1.hw },
···
2519
2541
{ .hw = &g12a_fclk_div5.hw },
2520
2542
};
2521
2543
2522
-
static struct clk_regmap g12a_mpeg_clk_sel = {
2544
+
static struct clk_regmap g12a_clk81_sel = {
2523
2545
.data = &(struct clk_regmap_mux_data){
2524
2546
.offset = HHI_MPEG_CLK_CNTL,
2525
2547
.mask = 0x7,
2526
2548
.shift = 12,
2527
-
.table = mux_table_clk81,
2549
+
.table = g12a_clk81_parents_val_table,
2528
2550
},
2529
2551
.hw.init = &(struct clk_init_data){
2530
-
.name = "mpeg_clk_sel",
2552
+
.name = "clk81_sel",
2531
2553
.ops = &clk_regmap_mux_ro_ops,
2532
-
.parent_data = clk81_parent_data,
2533
-
.num_parents = ARRAY_SIZE(clk81_parent_data),
2554
+
.parent_data = g12a_clk81_parents,
2555
+
.num_parents = ARRAY_SIZE(g12a_clk81_parents),
2534
2556
},
2535
2557
};
2536
2558
2537
-
static struct clk_regmap g12a_mpeg_clk_div = {
2559
+
static struct clk_regmap g12a_clk81_div = {
2538
2560
.data = &(struct clk_regmap_div_data){
2539
2561
.offset = HHI_MPEG_CLK_CNTL,
2540
2562
.shift = 0,
2541
2563
.width = 7,
2542
2564
},
2543
2565
.hw.init = &(struct clk_init_data){
2544
-
.name = "mpeg_clk_div",
2566
+
.name = "clk81_div",
2545
2567
.ops = &clk_regmap_divider_ops,
2546
2568
.parent_hws = (const struct clk_hw *[]) {
2547
-
&g12a_mpeg_clk_sel.hw
2569
+
&g12a_clk81_sel.hw
2548
2570
},
2549
2571
.num_parents = 1,
2550
2572
.flags = CLK_SET_RATE_PARENT,
···
2560
2582
.name = "clk81",
2561
2583
.ops = &clk_regmap_gate_ops,
2562
2584
.parent_hws = (const struct clk_hw *[]) {
2563
-
&g12a_mpeg_clk_div.hw
2585
+
&g12a_clk81_div.hw
2564
2586
},
2565
2587
.num_parents = 1,
2566
2588
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2567
2589
},
2568
2590
};
2569
2591
2570
-
static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2592
+
static const struct clk_parent_data g12a_sd_emmc_clk0_parents[] = {
2571
2593
{ .fw_name = "xtal", },
2572
2594
{ .hw = &g12a_fclk_div2.hw },
2573
2595
{ .hw = &g12a_fclk_div3.hw },
···
2591
2613
.hw.init = &(struct clk_init_data) {
2592
2614
.name = "sd_emmc_a_clk0_sel",
2593
2615
.ops = &clk_regmap_mux_ops,
2594
-
.parent_data = g12a_sd_emmc_clk0_parent_data,
2595
-
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2616
+
.parent_data = g12a_sd_emmc_clk0_parents,
2617
+
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parents),
2596
2618
.flags = CLK_SET_RATE_PARENT,
2597
2619
},
2598
2620
};
···
2640
2662
.hw.init = &(struct clk_init_data) {
2641
2663
.name = "sd_emmc_b_clk0_sel",
2642
2664
.ops = &clk_regmap_mux_ops,
2643
-
.parent_data = g12a_sd_emmc_clk0_parent_data,
2644
-
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2665
+
.parent_data = g12a_sd_emmc_clk0_parents,
2666
+
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parents),
2645
2667
.flags = CLK_SET_RATE_PARENT,
2646
2668
},
2647
2669
};
···
2689
2711
.hw.init = &(struct clk_init_data) {
2690
2712
.name = "sd_emmc_c_clk0_sel",
2691
2713
.ops = &clk_regmap_mux_ops,
2692
-
.parent_data = g12a_sd_emmc_clk0_parent_data,
2693
-
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2714
+
.parent_data = g12a_sd_emmc_clk0_parents,
2715
+
.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parents),
2694
2716
.flags = CLK_SET_RATE_PARENT,
2695
2717
},
2696
2718
};
···
2752
2774
},
2753
2775
};
2754
2776
2755
-
static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2777
+
static const struct clk_hw *g12a_vid_pll_parents[] = {
2756
2778
&g12a_vid_pll_div.hw,
2757
2779
&g12a_hdmi_pll.hw,
2758
2780
};
···
2770
2792
* bit 18 selects from 2 possible parents:
2771
2793
* vid_pll_div or hdmi_pll
2772
2794
*/
2773
-
.parent_hws = g12a_vid_pll_parent_hws,
2774
-
.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2795
+
.parent_hws = g12a_vid_pll_parents,
2796
+
.num_parents = ARRAY_SIZE(g12a_vid_pll_parents),
2775
2797
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2776
2798
},
2777
2799
};
···
2794
2816
2795
2817
/* VPU Clock */
2796
2818
2797
-
static const struct clk_hw *g12a_vpu_parent_hws[] = {
2819
+
static const struct clk_hw *g12a_vpu_parents[] = {
2798
2820
&g12a_fclk_div3.hw,
2799
2821
&g12a_fclk_div4.hw,
2800
2822
&g12a_fclk_div5.hw,
···
2814
2836
.hw.init = &(struct clk_init_data){
2815
2837
.name = "vpu_0_sel",
2816
2838
.ops = &clk_regmap_mux_ops,
2817
-
.parent_hws = g12a_vpu_parent_hws,
2818
-
.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2839
+
.parent_hws = g12a_vpu_parents,
2840
+
.num_parents = ARRAY_SIZE(g12a_vpu_parents),
2819
2841
.flags = CLK_SET_RATE_NO_REPARENT,
2820
2842
},
2821
2843
};
···
2858
2880
.hw.init = &(struct clk_init_data){
2859
2881
.name = "vpu_1_sel",
2860
2882
.ops = &clk_regmap_mux_ops,
2861
-
.parent_hws = g12a_vpu_parent_hws,
2862
-
.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2883
+
.parent_hws = g12a_vpu_parents,
2884
+
.num_parents = ARRAY_SIZE(g12a_vpu_parents),
2863
2885
.flags = CLK_SET_RATE_NO_REPARENT,
2864
2886
},
2865
2887
};
···
2917
2939
2918
2940
/* VDEC clocks */
2919
2941
2920
-
static const struct clk_hw *g12a_vdec_parent_hws[] = {
2942
+
static const struct clk_hw *g12a_vdec_parents[] = {
2921
2943
&g12a_fclk_div2p5.hw,
2922
2944
&g12a_fclk_div3.hw,
2923
2945
&g12a_fclk_div4.hw,
···
2937
2959
.hw.init = &(struct clk_init_data){
2938
2960
.name = "vdec_1_sel",
2939
2961
.ops = &clk_regmap_mux_ops,
2940
-
.parent_hws = g12a_vdec_parent_hws,
2941
-
.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2962
+
.parent_hws = g12a_vdec_parents,
2963
+
.num_parents = ARRAY_SIZE(g12a_vdec_parents),
2942
2964
.flags = CLK_SET_RATE_PARENT,
2943
2965
},
2944
2966
};
···
2987
3009
.hw.init = &(struct clk_init_data){
2988
3010
.name = "vdec_hevcf_sel",
2989
3011
.ops = &clk_regmap_mux_ops,
2990
-
.parent_hws = g12a_vdec_parent_hws,
2991
-
.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
3012
+
.parent_hws = g12a_vdec_parents,
3013
+
.num_parents = ARRAY_SIZE(g12a_vdec_parents),
2992
3014
.flags = CLK_SET_RATE_PARENT,
2993
3015
},
2994
3016
};
···
3037
3059
.hw.init = &(struct clk_init_data){
3038
3060
.name = "vdec_hevc_sel",
3039
3061
.ops = &clk_regmap_mux_ops,
3040
-
.parent_hws = g12a_vdec_parent_hws,
3041
-
.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
3062
+
.parent_hws = g12a_vdec_parents,
3063
+
.num_parents = ARRAY_SIZE(g12a_vdec_parents),
3042
3064
.flags = CLK_SET_RATE_PARENT,
3043
3065
},
3044
3066
};
···
3079
3101
3080
3102
/* VAPB Clock */
3081
3103
3082
-
static const struct clk_hw *g12a_vapb_parent_hws[] = {
3104
+
static const struct clk_hw *g12a_vapb_parents[] = {
3083
3105
&g12a_fclk_div4.hw,
3084
3106
&g12a_fclk_div3.hw,
3085
3107
&g12a_fclk_div5.hw,
···
3099
3121
.hw.init = &(struct clk_init_data){
3100
3122
.name = "vapb_0_sel",
3101
3123
.ops = &clk_regmap_mux_ops,
3102
-
.parent_hws = g12a_vapb_parent_hws,
3103
-
.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3124
+
.parent_hws = g12a_vapb_parents,
3125
+
.num_parents = ARRAY_SIZE(g12a_vapb_parents),
3104
3126
.flags = CLK_SET_RATE_NO_REPARENT,
3105
3127
},
3106
3128
};
···
3147
3169
.hw.init = &(struct clk_init_data){
3148
3170
.name = "vapb_1_sel",
3149
3171
.ops = &clk_regmap_mux_ops,
3150
-
.parent_hws = g12a_vapb_parent_hws,
3151
-
.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3172
+
.parent_hws = g12a_vapb_parents,
3173
+
.num_parents = ARRAY_SIZE(g12a_vapb_parents),
3152
3174
.flags = CLK_SET_RATE_NO_REPARENT,
3153
3175
},
3154
3176
};
···
3222
3244
},
3223
3245
};
3224
3246
3225
-
static const struct clk_hw *g12a_vclk_parent_hws[] = {
3247
+
static const struct clk_hw *g12a_vclk_parents[] = {
3226
3248
&g12a_vid_pll.hw,
3227
3249
&g12a_gp0_pll.hw,
3228
3250
&g12a_hifi_pll.hw,
···
3242
3264
.hw.init = &(struct clk_init_data){
3243
3265
.name = "vclk_sel",
3244
3266
.ops = &clk_regmap_mux_ops,
3245
-
.parent_hws = g12a_vclk_parent_hws,
3246
-
.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3267
+
.parent_hws = g12a_vclk_parents,
3268
+
.num_parents = ARRAY_SIZE(g12a_vclk_parents),
3247
3269
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3248
3270
},
3249
3271
};
···
3257
3279
.hw.init = &(struct clk_init_data){
3258
3280
.name = "vclk2_sel",
3259
3281
.ops = &clk_regmap_mux_ops,
3260
-
.parent_hws = g12a_vclk_parent_hws,
3261
-
.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3282
+
.parent_hws = g12a_vclk_parents,
3283
+
.num_parents = ARRAY_SIZE(g12a_vclk_parents),
3262
3284
.flags = CLK_SET_RATE_NO_REPARENT,
3263
3285
},
3264
3286
};
···
3621
3643
},
3622
3644
};
3623
3645
3624
-
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3625
-
static const struct clk_hw *g12a_cts_parent_hws[] = {
3646
+
static u32 g12a_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3647
+
static const struct clk_hw *g12a_cts_parents[] = {
3626
3648
&g12a_vclk_div1.hw,
3627
3649
&g12a_vclk_div2.hw,
3628
3650
&g12a_vclk_div4.hw,
···
3640
3662
.offset = HHI_VID_CLK_DIV,
3641
3663
.mask = 0xf,
3642
3664
.shift = 28,
3643
-
.table = mux_table_cts_sel,
3665
+
.table = g12a_cts_parents_val_table,
3644
3666
},
3645
3667
.hw.init = &(struct clk_init_data){
3646
3668
.name = "cts_enci_sel",
3647
3669
.ops = &clk_regmap_mux_ops,
3648
-
.parent_hws = g12a_cts_parent_hws,
3649
-
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3670
+
.parent_hws = g12a_cts_parents,
3671
+
.num_parents = ARRAY_SIZE(g12a_cts_parents),
3650
3672
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3651
3673
},
3652
3674
};
···
3656
3678
.offset = HHI_VID_CLK_DIV,
3657
3679
.mask = 0xf,
3658
3680
.shift = 20,
3659
-
.table = mux_table_cts_sel,
3681
+
.table = g12a_cts_parents_val_table,
3660
3682
},
3661
3683
.hw.init = &(struct clk_init_data){
3662
3684
.name = "cts_encp_sel",
3663
3685
.ops = &clk_regmap_mux_ops,
3664
-
.parent_hws = g12a_cts_parent_hws,
3665
-
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3686
+
.parent_hws = g12a_cts_parents,
3687
+
.num_parents = ARRAY_SIZE(g12a_cts_parents),
3666
3688
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3667
3689
},
3668
3690
};
···
3672
3694
.offset = HHI_VIID_CLK_DIV,
3673
3695
.mask = 0xf,
3674
3696
.shift = 12,
3675
-
.table = mux_table_cts_sel,
3697
+
.table = g12a_cts_parents_val_table,
3676
3698
},
3677
3699
.hw.init = &(struct clk_init_data){
3678
3700
.name = "cts_encl_sel",
3679
3701
.ops = &clk_regmap_mux_ops,
3680
-
.parent_hws = g12a_cts_parent_hws,
3681
-
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3702
+
.parent_hws = g12a_cts_parents,
3703
+
.num_parents = ARRAY_SIZE(g12a_cts_parents),
3682
3704
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
3683
3705
},
3684
3706
};
···
3688
3710
.offset = HHI_VIID_CLK_DIV,
3689
3711
.mask = 0xf,
3690
3712
.shift = 28,
3691
-
.table = mux_table_cts_sel,
3713
+
.table = g12a_cts_parents_val_table,
3692
3714
},
3693
3715
.hw.init = &(struct clk_init_data){
3694
3716
.name = "cts_vdac_sel",
3695
3717
.ops = &clk_regmap_mux_ops,
3696
-
.parent_hws = g12a_cts_parent_hws,
3697
-
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3718
+
.parent_hws = g12a_cts_parents,
3719
+
.num_parents = ARRAY_SIZE(g12a_cts_parents),
3698
3720
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3699
3721
},
3700
3722
};
3701
3723
3702
3724
/* TOFIX: add support for cts_tcon */
3703
-
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3704
-
static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3725
+
static u32 g12a_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3726
+
static const struct clk_hw *g12a_hdmi_tx_parents[] = {
3705
3727
&g12a_vclk_div1.hw,
3706
3728
&g12a_vclk_div2.hw,
3707
3729
&g12a_vclk_div4.hw,
···
3719
3741
.offset = HHI_HDMI_CLK_CNTL,
3720
3742
.mask = 0xf,
3721
3743
.shift = 16,
3722
-
.table = mux_table_hdmi_tx_sel,
3744
+
.table = g12a_hdmi_tx_parents_val_table,
3723
3745
},
3724
3746
.hw.init = &(struct clk_init_data){
3725
3747
.name = "hdmi_tx_sel",
3726
3748
.ops = &clk_regmap_mux_ops,
3727
-
.parent_hws = g12a_cts_hdmi_tx_parent_hws,
3728
-
.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3749
+
.parent_hws = g12a_hdmi_tx_parents,
3750
+
.num_parents = ARRAY_SIZE(g12a_hdmi_tx_parents),
3729
3751
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3730
3752
},
3731
3753
};
···
3812
3834
3813
3835
/* MIPI DSI Host Clocks */
3814
3836
3815
-
static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
3837
+
static const struct clk_hw *g12a_mipi_dsi_pxclk_parents[] = {
3816
3838
&g12a_vid_pll.hw,
3817
3839
&g12a_gp0_pll.hw,
3818
3840
&g12a_hifi_pll.hw,
···
3833
3855
.hw.init = &(struct clk_init_data){
3834
3856
.name = "mipi_dsi_pxclk_sel",
3835
3857
.ops = &clk_regmap_mux_ops,
3836
-
.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
3837
-
.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
3858
+
.parent_hws = g12a_mipi_dsi_pxclk_parents,
3859
+
.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parents),
3838
3860
.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
3839
3861
},
3840
3862
};
···
3885
3907
3886
3908
/* MIPI ISP Clocks */
3887
3909
3888
-
static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
3910
+
static const struct clk_parent_data g12b_mipi_isp_parents[] = {
3889
3911
{ .fw_name = "xtal", },
3890
3912
{ .hw = &g12a_gp0_pll.hw },
3891
3913
{ .hw = &g12a_hifi_pll.hw },
···
3905
3927
.hw.init = &(struct clk_init_data){
3906
3928
.name = "mipi_isp_sel",
3907
3929
.ops = &clk_regmap_mux_ops,
3908
-
.parent_data = g12b_mipi_isp_parent_data,
3909
-
.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
3930
+
.parent_data = g12b_mipi_isp_parents,
3931
+
.num_parents = ARRAY_SIZE(g12b_mipi_isp_parents),
3910
3932
},
3911
3933
};
3912
3934
···
3945
3967
3946
3968
/* HDMI Clocks */
3947
3969
3948
-
static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3970
+
static const struct clk_parent_data g12a_hdmi_parents[] = {
3949
3971
{ .fw_name = "xtal", },
3950
3972
{ .hw = &g12a_fclk_div4.hw },
3951
3973
{ .hw = &g12a_fclk_div3.hw },
···
3962
3984
.hw.init = &(struct clk_init_data){
3963
3985
.name = "hdmi_sel",
3964
3986
.ops = &clk_regmap_mux_ops,
3965
-
.parent_data = g12a_hdmi_parent_data,
3966
-
.num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3987
+
.parent_data = g12a_hdmi_parents,
3988
+
.num_parents = ARRAY_SIZE(g12a_hdmi_parents),
3967
3989
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3968
3990
},
3969
3991
};
···
4003
4025
* mux because it does top-to-bottom updates the each clock tree and
4004
4026
* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
4005
4027
*/
4006
-
static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
4028
+
static const struct clk_parent_data g12a_mali_parents[] = {
4007
4029
{ .fw_name = "xtal", },
4008
4030
{ .hw = &g12a_gp0_pll.hw },
4009
4031
{ .hw = &g12a_hifi_pll.hw },
···
4023
4045
.hw.init = &(struct clk_init_data){
4024
4046
.name = "mali_0_sel",
4025
4047
.ops = &clk_regmap_mux_ops,
4026
-
.parent_data = g12a_mali_0_1_parent_data,
4027
-
.num_parents = 8,
4048
+
.parent_data = g12a_mali_parents,
4049
+
.num_parents = ARRAY_SIZE(g12a_mali_parents),
4028
4050
/*
4029
4051
* Don't request the parent to change the rate because
4030
4052
* all GPU frequencies can be derived from the fclk_*
···
4077
4099
.hw.init = &(struct clk_init_data){
4078
4100
.name = "mali_1_sel",
4079
4101
.ops = &clk_regmap_mux_ops,
4080
-
.parent_data = g12a_mali_0_1_parent_data,
4081
-
.num_parents = 8,
4102
+
.parent_data = g12a_mali_parents,
4103
+
.num_parents = ARRAY_SIZE(g12a_mali_parents),
4082
4104
/*
4083
4105
* Don't request the parent to change the rate because
4084
4106
* all GPU frequencies can be derived from the fclk_*
···
4122
4144
},
4123
4145
};
4124
4146
4125
-
static const struct clk_hw *g12a_mali_parent_hws[] = {
4126
-
&g12a_mali_0.hw,
4127
-
&g12a_mali_1.hw,
4128
-
};
4129
-
4130
4147
static struct clk_regmap g12a_mali = {
4131
4148
.data = &(struct clk_regmap_mux_data){
4132
4149
.offset = HHI_MALI_CLK_CNTL,
···
4131
4158
.hw.init = &(struct clk_init_data){
4132
4159
.name = "mali",
4133
4160
.ops = &clk_regmap_mux_ops,
4134
-
.parent_hws = g12a_mali_parent_hws,
4161
+
.parent_hws = (const struct clk_hw *[]) {
4162
+
&g12a_mali_0.hw,
4163
+
&g12a_mali_1.hw,
4164
+
},
4135
4165
.num_parents = 2,
4136
4166
.flags = CLK_SET_RATE_PARENT,
4137
4167
},
···
4173
4197
4174
4198
/* SPICC SCLK source clock */
4175
4199
4176
-
static const struct clk_parent_data spicc_sclk_parent_data[] = {
4200
+
static const struct clk_parent_data g12a_spicc_sclk_parents[] = {
4177
4201
{ .fw_name = "xtal", },
4178
4202
{ .hw = &g12a_clk81.hw },
4179
4203
{ .hw = &g12a_fclk_div4.hw },
···
4192
4216
.hw.init = &(struct clk_init_data){
4193
4217
.name = "spicc0_sclk_sel",
4194
4218
.ops = &clk_regmap_mux_ops,
4195
-
.parent_data = spicc_sclk_parent_data,
4196
-
.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4219
+
.parent_data = g12a_spicc_sclk_parents,
4220
+
.num_parents = ARRAY_SIZE(g12a_spicc_sclk_parents),
4197
4221
},
4198
4222
};
4199
4223
···
4239
4263
.hw.init = &(struct clk_init_data){
4240
4264
.name = "spicc1_sclk_sel",
4241
4265
.ops = &clk_regmap_mux_ops,
4242
-
.parent_data = spicc_sclk_parent_data,
4243
-
.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4266
+
.parent_data = g12a_spicc_sclk_parents,
4267
+
.num_parents = ARRAY_SIZE(g12a_spicc_sclk_parents),
4244
4268
},
4245
4269
};
4246
4270
···
4279
4303
4280
4304
/* Neural Network Accelerator source clock */
4281
4305
4282
-
static const struct clk_parent_data nna_clk_parent_data[] = {
4306
+
static const struct clk_parent_data sm1_nna_clk_parents[] = {
4283
4307
{ .fw_name = "xtal", },
4284
4308
{ .hw = &g12a_gp0_pll.hw, },
4285
4309
{ .hw = &g12a_hifi_pll.hw, },
···
4299
4323
.hw.init = &(struct clk_init_data){
4300
4324
.name = "nna_axi_clk_sel",
4301
4325
.ops = &clk_regmap_mux_ops,
4302
-
.parent_data = nna_clk_parent_data,
4303
-
.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4326
+
.parent_data = sm1_nna_clk_parents,
4327
+
.num_parents = ARRAY_SIZE(sm1_nna_clk_parents),
4304
4328
},
4305
4329
};
4306
4330
···
4346
4370
.hw.init = &(struct clk_init_data){
4347
4371
.name = "nna_core_clk_sel",
4348
4372
.ops = &clk_regmap_mux_ops,
4349
-
.parent_data = nna_clk_parent_data,
4350
-
.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4373
+
.parent_data = sm1_nna_clk_parents,
4374
+
.num_parents = ARRAY_SIZE(sm1_nna_clk_parents),
4351
4375
},
4352
4376
};
4353
4377
···
4384
4408
},
4385
4409
};
4386
4410
4387
-
#define MESON_GATE(_name, _reg, _bit) \
4388
-
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4411
+
static const struct clk_parent_data g12a_pclk_parents = { .hw = &g12a_clk81.hw };
4389
4412
4390
-
#define MESON_GATE_RO(_name, _reg, _bit) \
4391
-
MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4413
+
#define G12A_PCLK(_name, _reg, _bit, _flags) \
4414
+
MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags)
4392
4415
4393
-
/* Everything Else (EE) domain gates */
4394
-
static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
4395
-
static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
4396
-
static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2);
4397
-
static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
4398
-
static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
4399
-
static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
4400
-
static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
4401
-
static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
4402
-
static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
4403
-
static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
4404
-
static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
4405
-
static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
4406
-
static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
4407
-
static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
4408
-
static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
4409
-
static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
4410
-
static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
4411
-
static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);
4412
-
static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 24);
4413
-
static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25);
4414
-
static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26);
4415
-
static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28);
4416
+
#define G12A_PCLK_RO(_name, _reg, _bit, _flags) \
4417
+
MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags)
4416
4418
4417
-
static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0);
4418
-
static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3);
4419
-
static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4);
4420
-
static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11);
4421
-
static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13);
4422
-
static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16);
4423
-
static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20);
4424
-
static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23);
4425
-
static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24);
4426
-
static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25);
4427
-
static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26);
4428
-
static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27);
4429
-
static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29);
4419
+
/*
4420
+
* Everything Else (EE) domain gates
4421
+
*
4422
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
4423
+
* Users are encouraged to test without it and submit changes to:
4424
+
* - remove the flag if not necessary
4425
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
4426
+
* if appropriate.
4427
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
4428
+
* for a particular clock.
4429
+
*/
4430
+
static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED);
4431
+
static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED);
4432
+
static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED);
4433
+
static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSED);
4434
+
static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4, CLK_IGNORE_UNUSED);
4435
+
static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED);
4436
+
static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED);
4437
+
static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED);
4438
+
static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED);
4439
+
static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED);
4440
+
static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED);
4441
+
static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED);
4442
+
static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED);
4443
+
static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED);
4444
+
static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED);
4445
+
static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED);
4446
+
static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20, CLK_IGNORE_UNUSED);
4447
+
static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED);
4448
+
static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED);
4449
+
static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED);
4450
+
static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED);
4451
+
static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED);
4430
4452
4431
-
static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1);
4432
-
static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
4433
-
static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
4434
-
static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
4435
-
static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
4436
-
static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
4437
-
static MESON_GATE(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17);
4438
-
static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
4439
-
static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
4440
-
static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
4441
-
static MESON_GATE(g12b_csi_phy1, HHI_GCLK_MPEG2, 28);
4442
-
static MESON_GATE(g12b_csi_phy0, HHI_GCLK_MPEG2, 29);
4443
-
static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
4453
+
static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED);
4454
+
static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED);
4455
+
static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED);
4456
+
static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSED);
4457
+
static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED);
4458
+
static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED);
4459
+
static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED);
4460
+
static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED);
4461
+
static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED);
4462
+
static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED);
4463
+
static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED);
4464
+
static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27, CLK_IGNORE_UNUSED);
4465
+
static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED);
4444
4466
4445
-
static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
4446
-
static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2);
4447
-
static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3);
4448
-
static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4);
4449
-
static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5);
4450
-
static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6);
4451
-
static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7);
4452
-
static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8);
4453
-
static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9);
4454
-
static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10);
4455
-
static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14);
4456
-
static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16);
4457
-
static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20);
4458
-
static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21);
4459
-
static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22);
4460
-
static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23);
4461
-
static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24);
4462
-
static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25);
4463
-
static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26);
4467
+
static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED);
4468
+
static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED);
4469
+
static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED);
4470
+
static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED);
4471
+
static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6, CLK_IGNORE_UNUSED);
4472
+
static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED);
4473
+
static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17, CLK_IGNORE_UNUSED);
4474
+
static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED);
4475
+
static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED);
4476
+
static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED);
4477
+
static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28, CLK_IGNORE_UNUSED);
4478
+
static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED);
4479
+
static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED);
4464
4480
4465
-
static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0);
4466
-
static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1);
4467
-
static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2);
4468
-
static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3);
4469
-
static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
4481
+
static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED);
4482
+
static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED);
4483
+
static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED);
4484
+
static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED);
4485
+
static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5, CLK_IGNORE_UNUSED);
4486
+
static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6, CLK_IGNORE_UNUSED);
4487
+
static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7, CLK_IGNORE_UNUSED);
4488
+
static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED);
4489
+
static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED);
4490
+
static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED);
4491
+
static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED);
4492
+
static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED);
4493
+
static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED);
4494
+
static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED);
4495
+
static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED);
4496
+
static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23, CLK_IGNORE_UNUSED);
4497
+
static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED);
4498
+
static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED);
4499
+
static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED);
4500
+
4501
+
static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0, 0);
4502
+
static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1, 0);
4503
+
static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2, 0);
4504
+
static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3, 0);
4505
+
static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4, 0);
4470
4506
4471
4507
/* Array of all clocks provided by this provider */
4472
4508
static struct clk_hw *g12a_hw_clks[] = {
···
4491
4503
[CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4492
4504
[CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4493
4505
[CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4494
-
[CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4495
-
[CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4506
+
[CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4507
+
[CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4496
4508
[CLKID_CLK81] = &g12a_clk81.hw,
4497
4509
[CLKID_MPLL0] = &g12a_mpll0.hw,
4498
4510
[CLKID_MPLL1] = &g12a_mpll1.hw,
···
4664
4676
[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4665
4677
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4666
4678
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4667
-
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4668
-
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4669
-
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4670
-
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4671
-
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4672
-
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4679
+
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
4680
+
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
4681
+
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
4682
+
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
4683
+
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
4684
+
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
4673
4685
[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4674
4686
[CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4675
4687
[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
···
4718
4730
[CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4719
4731
[CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4720
4732
[CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4721
-
[CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4722
-
[CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4733
+
[CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
4734
+
[CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4723
4735
[CLKID_CLK81] = &g12a_clk81.hw,
4724
4736
[CLKID_MPLL0] = &g12a_mpll0.hw,
4725
4737
[CLKID_MPLL1] = &g12a_mpll1.hw,
···
4891
4903
[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4892
4904
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4893
4905
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4894
-
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4895
-
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4896
-
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4897
-
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4898
-
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4899
-
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4906
+
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
4907
+
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
4908
+
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
4909
+
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
4910
+
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
4911
+
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
4900
4912
[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4901
4913
[CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4902
4914
[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
···
4928
4940
[CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4929
4941
[CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4930
4942
[CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4931
-
[CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4932
-
[CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4933
-
[CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4934
-
[CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4935
-
[CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4936
-
[CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4943
+
[CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_dyn0_sel.hw,
4944
+
[CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_dyn0_div.hw,
4945
+
[CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_dyn0.hw,
4946
+
[CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_dyn1_sel.hw,
4947
+
[CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_dyn1_div.hw,
4948
+
[CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_dyn1.hw,
4937
4949
[CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4938
4950
[CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4939
4951
[CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
···
4986
4998
[CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4987
4999
[CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4988
5000
[CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4989
-
[CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4990
-
[CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
5001
+
[CLKID_MPEG_SEL] = &g12a_clk81_sel.hw,
5002
+
[CLKID_MPEG_DIV] = &g12a_clk81_div.hw,
4991
5003
[CLKID_CLK81] = &g12a_clk81.hw,
4992
5004
[CLKID_MPLL0] = &g12a_mpll0.hw,
4993
5005
[CLKID_MPLL1] = &g12a_mpll1.hw,
···
5159
5171
[CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
5160
5172
[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
5161
5173
[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
5162
-
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
5163
-
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
5164
-
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
5165
-
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
5166
-
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
5167
-
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
5174
+
[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_dyn0_sel.hw,
5175
+
[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_dyn0_div.hw,
5176
+
[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_dyn0.hw,
5177
+
[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_dyn1_sel.hw,
5178
+
[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_dyn1_div.hw,
5179
+
[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_dyn1.hw,
5168
5180
[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
5169
5181
[CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
5170
5182
[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
···
5194
5206
[CLKID_TS] = &g12a_ts.hw,
5195
5207
[CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
5196
5208
[CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
5197
-
[CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
5198
-
[CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
5199
-
[CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
5200
-
[CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
5201
-
[CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
5202
-
[CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
5209
+
[CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_dyn0_sel.hw,
5210
+
[CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_dyn0_div.hw,
5211
+
[CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_dyn0.hw,
5212
+
[CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_dyn1_sel.hw,
5213
+
[CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_dyn1_div.hw,
5214
+
[CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_dyn1.hw,
5203
5215
[CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
5204
5216
[CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
5205
5217
[CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
···
5229
5241
5230
5242
#define DVFS_CON_ID "dvfs"
5231
5243
5232
-
static int meson_g12a_dvfs_setup_common(struct device *dev,
5233
-
struct clk_hw **hws)
5244
+
static int g12a_dvfs_setup_common(struct device *dev, struct clk_hw **hws)
5234
5245
{
5235
5246
struct clk *notifier_clk;
5236
5247
struct clk_hw *xtal;
···
5238
5251
xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5239
5252
5240
5253
/* Setup clock notifier for cpu_clk_postmux0 */
5241
-
g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
5242
-
notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
5254
+
g12a_cpu_clk_dyn0_nb_data.xtal = xtal;
5255
+
notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn0.hw,
5243
5256
DVFS_CON_ID);
5244
5257
ret = devm_clk_notifier_register(dev, notifier_clk,
5245
-
&g12a_cpu_clk_postmux0_nb_data.nb);
5258
+
&g12a_cpu_clk_dyn0_nb_data.nb);
5246
5259
if (ret) {
5247
-
dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");
5260
+
dev_err(dev, "failed to register the cpu_clk_dyn0 notifier\n");
5248
5261
return ret;
5249
5262
}
5250
5263
···
5261
5274
return 0;
5262
5275
}
5263
5276
5264
-
static int meson_g12b_dvfs_setup(struct platform_device *pdev)
5277
+
static int g12b_dvfs_setup(struct platform_device *pdev)
5265
5278
{
5266
5279
struct clk_hw **hws = g12b_hw_clks;
5267
5280
struct device *dev = &pdev->dev;
···
5269
5282
struct clk_hw *xtal;
5270
5283
int ret;
5271
5284
5272
-
ret = meson_g12a_dvfs_setup_common(dev, hws);
5285
+
ret = g12a_dvfs_setup_common(dev, hws);
5273
5286
if (ret)
5274
5287
return ret;
5275
5288
···
5298
5311
/* Add notifiers for the second CPU cluster */
5299
5312
5300
5313
/* Setup clock notifier for cpub_clk_postmux0 */
5301
-
g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
5302
-
notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
5314
+
g12b_cpub_clk_dyn0_nb_data.xtal = xtal;
5315
+
notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn0.hw,
5303
5316
DVFS_CON_ID);
5304
5317
ret = devm_clk_notifier_register(dev, notifier_clk,
5305
-
&g12b_cpub_clk_postmux0_nb_data.nb);
5318
+
&g12b_cpub_clk_dyn0_nb_data.nb);
5306
5319
if (ret) {
5307
-
dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");
5320
+
dev_err(dev, "failed to register the cpub_clk_dyn0 notifier\n");
5308
5321
return ret;
5309
5322
}
5310
5323
5311
5324
/* Setup clock notifier for cpub_clk_dyn mux */
5312
-
notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
5325
+
notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw,
5326
+
DVFS_CON_ID);
5313
5327
ret = devm_clk_notifier_register(dev, notifier_clk,
5314
5328
&g12a_cpu_clk_mux_nb);
5315
5329
if (ret) {
···
5339
5351
return 0;
5340
5352
}
5341
5353
5342
-
static int meson_g12a_dvfs_setup(struct platform_device *pdev)
5354
+
static int g12a_dvfs_setup(struct platform_device *pdev)
5343
5355
{
5344
5356
struct clk_hw **hws = g12a_hw_clks;
5345
5357
struct device *dev = &pdev->dev;
5346
5358
struct clk *notifier_clk;
5347
5359
int ret;
5348
5360
5349
-
ret = meson_g12a_dvfs_setup_common(dev, hws);
5361
+
ret = g12a_dvfs_setup_common(dev, hws);
5350
5362
if (ret)
5351
5363
return ret;
5352
5364
···
5371
5383
return 0;
5372
5384
}
5373
5385
5374
-
struct meson_g12a_data {
5375
-
const struct meson_eeclkc_data eeclkc_data;
5386
+
struct g12a_clkc_data {
5387
+
const struct meson_clkc_data clkc_data;
5376
5388
int (*dvfs_setup)(struct platform_device *pdev);
5377
5389
};
5378
5390
5379
-
static int meson_g12a_probe(struct platform_device *pdev)
5391
+
static int g12a_clkc_probe(struct platform_device *pdev)
5380
5392
{
5381
-
const struct meson_eeclkc_data *eeclkc_data;
5382
-
const struct meson_g12a_data *g12a_data;
5393
+
const struct meson_clkc_data *clkc_data;
5394
+
const struct g12a_clkc_data *g12a_data;
5383
5395
int ret;
5384
5396
5385
-
eeclkc_data = of_device_get_match_data(&pdev->dev);
5386
-
if (!eeclkc_data)
5397
+
clkc_data = of_device_get_match_data(&pdev->dev);
5398
+
if (!clkc_data)
5387
5399
return -EINVAL;
5388
5400
5389
-
ret = meson_eeclkc_probe(pdev);
5401
+
ret = meson_clkc_syscon_probe(pdev);
5390
5402
if (ret)
5391
5403
return ret;
5392
5404
5393
-
g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5394
-
eeclkc_data);
5405
+
g12a_data = container_of(clkc_data, struct g12a_clkc_data,
5406
+
clkc_data);
5395
5407
5396
5408
if (g12a_data->dvfs_setup)
5397
5409
return g12a_data->dvfs_setup(pdev);
···
5399
5411
return 0;
5400
5412
}
5401
5413
5402
-
static const struct meson_g12a_data g12a_clkc_data = {
5403
-
.eeclkc_data = {
5414
+
static const struct g12a_clkc_data g12a_clkc_data = {
5415
+
.clkc_data = {
5404
5416
.hw_clks = {
5405
5417
.hws = g12a_hw_clks,
5406
5418
.num = ARRAY_SIZE(g12a_hw_clks),
···
5408
5420
.init_regs = g12a_init_regs,
5409
5421
.init_count = ARRAY_SIZE(g12a_init_regs),
5410
5422
},
5411
-
.dvfs_setup = meson_g12a_dvfs_setup,
5423
+
.dvfs_setup = g12a_dvfs_setup,
5412
5424
};
5413
5425
5414
-
static const struct meson_g12a_data g12b_clkc_data = {
5415
-
.eeclkc_data = {
5426
+
static const struct g12a_clkc_data g12b_clkc_data = {
5427
+
.clkc_data = {
5416
5428
.hw_clks = {
5417
5429
.hws = g12b_hw_clks,
5418
5430
.num = ARRAY_SIZE(g12b_hw_clks),
5419
5431
},
5420
5432
},
5421
-
.dvfs_setup = meson_g12b_dvfs_setup,
5433
+
.dvfs_setup = g12b_dvfs_setup,
5422
5434
};
5423
5435
5424
-
static const struct meson_g12a_data sm1_clkc_data = {
5425
-
.eeclkc_data = {
5436
+
static const struct g12a_clkc_data sm1_clkc_data = {
5437
+
.clkc_data = {
5426
5438
.hw_clks = {
5427
5439
.hws = sm1_hw_clks,
5428
5440
.num = ARRAY_SIZE(sm1_hw_clks),
5429
5441
},
5430
5442
},
5431
-
.dvfs_setup = meson_g12a_dvfs_setup,
5443
+
.dvfs_setup = g12a_dvfs_setup,
5432
5444
};
5433
5445
5434
-
static const struct of_device_id clkc_match_table[] = {
5446
+
static const struct of_device_id g12a_clkc_match_table[] = {
5435
5447
{
5436
5448
.compatible = "amlogic,g12a-clkc",
5437
-
.data = &g12a_clkc_data.eeclkc_data
5449
+
.data = &g12a_clkc_data.clkc_data
5438
5450
},
5439
5451
{
5440
5452
.compatible = "amlogic,g12b-clkc",
5441
-
.data = &g12b_clkc_data.eeclkc_data
5453
+
.data = &g12b_clkc_data.clkc_data
5442
5454
},
5443
5455
{
5444
5456
.compatible = "amlogic,sm1-clkc",
5445
-
.data = &sm1_clkc_data.eeclkc_data
5457
+
.data = &sm1_clkc_data.clkc_data
5446
5458
},
5447
5459
{}
5448
5460
};
5449
-
MODULE_DEVICE_TABLE(of, clkc_match_table);
5461
+
MODULE_DEVICE_TABLE(of, g12a_clkc_match_table);
5450
5462
5451
-
static struct platform_driver g12a_driver = {
5452
-
.probe = meson_g12a_probe,
5463
+
static struct platform_driver g12a_clkc_driver = {
5464
+
.probe = g12a_clkc_probe,
5453
5465
.driver = {
5454
5466
.name = "g12a-clkc",
5455
-
.of_match_table = clkc_match_table,
5467
+
.of_match_table = g12a_clkc_match_table,
5456
5468
},
5457
5469
};
5458
-
module_platform_driver(g12a_driver);
5470
+
module_platform_driver(g12a_clkc_driver);
5459
5471
5460
5472
MODULE_DESCRIPTION("Amlogic G12/SM1 Main Clock Controller driver");
5461
5473
MODULE_LICENSE("GPL");
+57
-66
drivers/clk/meson/gxbb-aoclk.c
+57
-66
drivers/clk/meson/gxbb-aoclk.c
···
23
23
#define AO_RTC_ALT_CLK_CNTL0 0x94
24
24
#define AO_RTC_ALT_CLK_CNTL1 0x98
25
25
26
-
#define GXBB_AO_GATE(_name, _bit) \
27
-
static struct clk_regmap _name##_ao = { \
28
-
.data = &(struct clk_regmap_gate_data) { \
29
-
.offset = AO_RTI_GEN_CNTL_REG0, \
30
-
.bit_idx = (_bit), \
31
-
}, \
32
-
.hw.init = &(struct clk_init_data) { \
33
-
.name = #_name "_ao", \
34
-
.ops = &clk_regmap_gate_ops, \
35
-
.parent_data = &(const struct clk_parent_data) { \
36
-
.fw_name = "mpeg-clk", \
37
-
}, \
38
-
.num_parents = 1, \
39
-
.flags = CLK_IGNORE_UNUSED, \
40
-
}, \
41
-
}
26
+
static const struct clk_parent_data gxbb_ao_pclk_parents = { .fw_name = "mpeg-clk" };
42
27
43
-
GXBB_AO_GATE(remote, 0);
44
-
GXBB_AO_GATE(i2c_master, 1);
45
-
GXBB_AO_GATE(i2c_slave, 2);
46
-
GXBB_AO_GATE(uart1, 3);
47
-
GXBB_AO_GATE(uart2, 5);
48
-
GXBB_AO_GATE(ir_blaster, 6);
28
+
#define GXBB_AO_PCLK(_name, _bit, _flags) \
29
+
MESON_PCLK(gxbb_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
30
+
&gxbb_ao_pclk_parents, _flags)
49
31
50
-
static struct clk_regmap ao_cts_oscin = {
32
+
static GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED);
33
+
static GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED);
34
+
static GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED);
35
+
static GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED);
36
+
static GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED);
37
+
static GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED);
38
+
39
+
static struct clk_regmap gxbb_ao_cts_oscin = {
51
40
.data = &(struct clk_regmap_gate_data){
52
41
.offset = AO_RTI_PWR_CNTL_REG0,
53
42
.bit_idx = 6,
···
51
62
},
52
63
};
53
64
54
-
static struct clk_regmap ao_32k_pre = {
65
+
static struct clk_regmap gxbb_ao_32k_pre = {
55
66
.data = &(struct clk_regmap_gate_data){
56
67
.offset = AO_RTC_ALT_CLK_CNTL0,
57
68
.bit_idx = 31,
···
59
70
.hw.init = &(struct clk_init_data){
60
71
.name = "ao_32k_pre",
61
72
.ops = &clk_regmap_gate_ops,
62
-
.parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
73
+
.parent_hws = (const struct clk_hw *[]) { &gxbb_ao_cts_oscin.hw },
63
74
.num_parents = 1,
64
75
},
65
76
};
···
74
85
}, {}
75
86
};
76
87
77
-
static struct clk_regmap ao_32k_div = {
88
+
static struct clk_regmap gxbb_ao_32k_div = {
78
89
.data = &(struct meson_clk_dualdiv_data){
79
90
.n1 = {
80
91
.reg_off = AO_RTC_ALT_CLK_CNTL0,
···
106
117
.hw.init = &(struct clk_init_data){
107
118
.name = "ao_32k_div",
108
119
.ops = &meson_clk_dualdiv_ops,
109
-
.parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
120
+
.parent_hws = (const struct clk_hw *[]) { &gxbb_ao_32k_pre.hw },
110
121
.num_parents = 1,
111
122
},
112
123
};
113
124
114
-
static struct clk_regmap ao_32k_sel = {
125
+
static struct clk_regmap gxbb_ao_32k_sel = {
115
126
.data = &(struct clk_regmap_mux_data) {
116
127
.offset = AO_RTC_ALT_CLK_CNTL1,
117
128
.mask = 0x1,
···
122
133
.name = "ao_32k_sel",
123
134
.ops = &clk_regmap_mux_ops,
124
135
.parent_hws = (const struct clk_hw *[]) {
125
-
&ao_32k_div.hw,
126
-
&ao_32k_pre.hw
136
+
&gxbb_ao_32k_div.hw,
137
+
&gxbb_ao_32k_pre.hw
127
138
},
128
139
.num_parents = 2,
129
140
.flags = CLK_SET_RATE_PARENT,
130
141
},
131
142
};
132
143
133
-
static struct clk_regmap ao_32k = {
144
+
static struct clk_regmap gxbb_ao_32k = {
134
145
.data = &(struct clk_regmap_gate_data){
135
146
.offset = AO_RTC_ALT_CLK_CNTL0,
136
147
.bit_idx = 30,
···
138
149
.hw.init = &(struct clk_init_data){
139
150
.name = "ao_32k",
140
151
.ops = &clk_regmap_gate_ops,
141
-
.parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
152
+
.parent_hws = (const struct clk_hw *[]) { &gxbb_ao_32k_sel.hw },
142
153
.num_parents = 1,
143
154
.flags = CLK_SET_RATE_PARENT,
144
155
},
145
156
};
146
157
147
-
static struct clk_regmap ao_cts_rtc_oscin = {
158
+
static struct clk_regmap gxbb_ao_cts_rtc_oscin = {
148
159
.data = &(struct clk_regmap_mux_data) {
149
160
.offset = AO_RTI_PWR_CNTL_REG0,
150
161
.mask = 0x7,
···
159
170
{ .fw_name = "ext-32k-0", },
160
171
{ .fw_name = "ext-32k-1", },
161
172
{ .fw_name = "ext-32k-2", },
162
-
{ .hw = &ao_32k.hw },
173
+
{ .hw = &gxbb_ao_32k.hw },
163
174
},
164
175
.num_parents = 4,
165
176
.flags = CLK_SET_RATE_PARENT,
166
177
},
167
178
};
168
179
169
-
static struct clk_regmap ao_clk81 = {
180
+
static struct clk_regmap gxbb_ao_clk81 = {
170
181
.data = &(struct clk_regmap_mux_data) {
171
182
.offset = AO_RTI_PWR_CNTL_REG0,
172
183
.mask = 0x1,
···
178
189
.ops = &clk_regmap_mux_ro_ops,
179
190
.parent_data = (const struct clk_parent_data []) {
180
191
{ .fw_name = "mpeg-clk", },
181
-
{ .hw = &ao_cts_rtc_oscin.hw },
192
+
{ .hw = &gxbb_ao_cts_rtc_oscin.hw },
182
193
},
183
194
.num_parents = 2,
184
195
.flags = CLK_SET_RATE_PARENT,
185
196
},
186
197
};
187
198
188
-
static struct clk_regmap ao_cts_cec = {
199
+
static struct clk_regmap gxbb_ao_cts_cec = {
189
200
.data = &(struct clk_regmap_mux_data) {
190
201
.offset = AO_CRT_CLK_CNTL1,
191
202
.mask = 0x1,
···
210
221
*/
211
222
.parent_data = (const struct clk_parent_data []) {
212
223
{ .name = "fixme", .index = -1, },
213
-
{ .hw = &ao_cts_rtc_oscin.hw },
224
+
{ .hw = &gxbb_ao_cts_rtc_oscin.hw },
214
225
},
215
226
.num_parents = 2,
216
227
.flags = CLK_SET_RATE_PARENT,
217
228
},
218
229
};
219
230
220
-
static const unsigned int gxbb_aoclk_reset[] = {
231
+
static const unsigned int gxbb_ao_reset[] = {
221
232
[RESET_AO_REMOTE] = 16,
222
233
[RESET_AO_I2C_MASTER] = 18,
223
234
[RESET_AO_I2C_SLAVE] = 19,
···
226
237
[RESET_AO_IR_BLASTER] = 23,
227
238
};
228
239
229
-
static struct clk_hw *gxbb_aoclk_hw_clks[] = {
230
-
[CLKID_AO_REMOTE] = &remote_ao.hw,
231
-
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
232
-
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
233
-
[CLKID_AO_UART1] = &uart1_ao.hw,
234
-
[CLKID_AO_UART2] = &uart2_ao.hw,
235
-
[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
236
-
[CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
237
-
[CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
238
-
[CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
239
-
[CLKID_AO_32K_DIV] = &ao_32k_div.hw,
240
-
[CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
241
-
[CLKID_AO_32K] = &ao_32k.hw,
242
-
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
243
-
[CLKID_AO_CLK81] = &ao_clk81.hw,
240
+
static struct clk_hw *gxbb_ao_hw_clks[] = {
241
+
[CLKID_AO_REMOTE] = &gxbb_ao_remote.hw,
242
+
[CLKID_AO_I2C_MASTER] = &gxbb_ao_i2c_master.hw,
243
+
[CLKID_AO_I2C_SLAVE] = &gxbb_ao_i2c_slave.hw,
244
+
[CLKID_AO_UART1] = &gxbb_ao_uart1.hw,
245
+
[CLKID_AO_UART2] = &gxbb_ao_uart2.hw,
246
+
[CLKID_AO_IR_BLASTER] = &gxbb_ao_ir_blaster.hw,
247
+
[CLKID_AO_CEC_32K] = &gxbb_ao_cts_cec.hw,
248
+
[CLKID_AO_CTS_OSCIN] = &gxbb_ao_cts_oscin.hw,
249
+
[CLKID_AO_32K_PRE] = &gxbb_ao_32k_pre.hw,
250
+
[CLKID_AO_32K_DIV] = &gxbb_ao_32k_div.hw,
251
+
[CLKID_AO_32K_SEL] = &gxbb_ao_32k_sel.hw,
252
+
[CLKID_AO_32K] = &gxbb_ao_32k.hw,
253
+
[CLKID_AO_CTS_RTC_OSCIN] = &gxbb_ao_cts_rtc_oscin.hw,
254
+
[CLKID_AO_CLK81] = &gxbb_ao_clk81.hw,
244
255
};
245
256
246
-
static const struct meson_aoclk_data gxbb_aoclkc_data = {
257
+
static const struct meson_aoclk_data gxbb_ao_clkc_data = {
247
258
.reset_reg = AO_RTI_GEN_CNTL_REG0,
248
-
.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
249
-
.reset = gxbb_aoclk_reset,
250
-
.hw_clks = {
251
-
.hws = gxbb_aoclk_hw_clks,
252
-
.num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
259
+
.num_reset = ARRAY_SIZE(gxbb_ao_reset),
260
+
.reset = gxbb_ao_reset,
261
+
.clkc_data = {
262
+
.hw_clks = {
263
+
.hws = gxbb_ao_hw_clks,
264
+
.num = ARRAY_SIZE(gxbb_ao_hw_clks),
265
+
},
253
266
},
254
267
};
255
268
256
-
static const struct of_device_id gxbb_aoclkc_match_table[] = {
269
+
static const struct of_device_id gxbb_ao_clkc_match_table[] = {
257
270
{
258
271
.compatible = "amlogic,meson-gx-aoclkc",
259
-
.data = &gxbb_aoclkc_data,
272
+
.data = &gxbb_ao_clkc_data.clkc_data,
260
273
},
261
274
{ }
262
275
};
263
-
MODULE_DEVICE_TABLE(of, gxbb_aoclkc_match_table);
276
+
MODULE_DEVICE_TABLE(of, gxbb_ao_clkc_match_table);
264
277
265
-
static struct platform_driver gxbb_aoclkc_driver = {
278
+
static struct platform_driver gxbb_ao_clkc_driver = {
266
279
.probe = meson_aoclkc_probe,
267
280
.driver = {
268
281
.name = "gxbb-aoclkc",
269
-
.of_match_table = gxbb_aoclkc_match_table,
282
+
.of_match_table = gxbb_ao_clkc_match_table,
270
283
},
271
284
};
272
-
module_platform_driver(gxbb_aoclkc_driver);
285
+
module_platform_driver(gxbb_ao_clkc_driver);
273
286
274
287
MODULE_DESCRIPTION("Amlogic GXBB Always-ON Clock Controller driver");
275
288
MODULE_LICENSE("GPL");
+309
-294
drivers/clk/meson/gxbb.c
+309
-294
drivers/clk/meson/gxbb.c
···
13
13
#include "clk-regmap.h"
14
14
#include "clk-pll.h"
15
15
#include "clk-mpll.h"
16
-
#include "meson-eeclk.h"
16
+
#include "meson-clkc-utils.h"
17
17
#include "vid-pll-div.h"
18
18
19
19
#include <dt-bindings/clock/gxbb-clkc.h>
···
115
115
#define HHI_VID_LOCK_CLK_CNTL 0x3c8
116
116
#define HHI_BT656_CLK_CNTL 0x3d4
117
117
#define HHI_SAR_CLK_CNTL 0x3d8
118
-
119
-
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
120
-
PLL_PARAMS(32, 1),
121
-
PLL_PARAMS(33, 1),
122
-
PLL_PARAMS(34, 1),
123
-
PLL_PARAMS(35, 1),
124
-
PLL_PARAMS(36, 1),
125
-
PLL_PARAMS(37, 1),
126
-
PLL_PARAMS(38, 1),
127
-
PLL_PARAMS(39, 1),
128
-
PLL_PARAMS(40, 1),
129
-
PLL_PARAMS(41, 1),
130
-
PLL_PARAMS(42, 1),
131
-
PLL_PARAMS(43, 1),
132
-
PLL_PARAMS(44, 1),
133
-
PLL_PARAMS(45, 1),
134
-
PLL_PARAMS(46, 1),
135
-
PLL_PARAMS(47, 1),
136
-
PLL_PARAMS(48, 1),
137
-
PLL_PARAMS(49, 1),
138
-
PLL_PARAMS(50, 1),
139
-
PLL_PARAMS(51, 1),
140
-
PLL_PARAMS(52, 1),
141
-
PLL_PARAMS(53, 1),
142
-
PLL_PARAMS(54, 1),
143
-
PLL_PARAMS(55, 1),
144
-
PLL_PARAMS(56, 1),
145
-
PLL_PARAMS(57, 1),
146
-
PLL_PARAMS(58, 1),
147
-
PLL_PARAMS(59, 1),
148
-
PLL_PARAMS(60, 1),
149
-
PLL_PARAMS(61, 1),
150
-
PLL_PARAMS(62, 1),
151
-
{ /* sentinel */ },
152
-
};
153
-
154
-
static const struct pll_params_table gxl_gp0_pll_params_table[] = {
155
-
PLL_PARAMS(42, 1),
156
-
PLL_PARAMS(43, 1),
157
-
PLL_PARAMS(44, 1),
158
-
PLL_PARAMS(45, 1),
159
-
PLL_PARAMS(46, 1),
160
-
PLL_PARAMS(47, 1),
161
-
PLL_PARAMS(48, 1),
162
-
PLL_PARAMS(49, 1),
163
-
PLL_PARAMS(50, 1),
164
-
PLL_PARAMS(51, 1),
165
-
PLL_PARAMS(52, 1),
166
-
PLL_PARAMS(53, 1),
167
-
PLL_PARAMS(54, 1),
168
-
PLL_PARAMS(55, 1),
169
-
PLL_PARAMS(56, 1),
170
-
PLL_PARAMS(57, 1),
171
-
PLL_PARAMS(58, 1),
172
-
PLL_PARAMS(59, 1),
173
-
PLL_PARAMS(60, 1),
174
-
PLL_PARAMS(61, 1),
175
-
PLL_PARAMS(62, 1),
176
-
PLL_PARAMS(63, 1),
177
-
PLL_PARAMS(64, 1),
178
-
PLL_PARAMS(65, 1),
179
-
PLL_PARAMS(66, 1),
180
-
{ /* sentinel */ },
181
-
};
182
118
183
119
static struct clk_regmap gxbb_fixed_pll_dco = {
184
120
.data = &(struct meson_clk_pll_data){
···
459
523
},
460
524
};
461
525
462
-
static const struct reg_sequence gxbb_gp0_init_regs[] = {
526
+
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
527
+
PLL_PARAMS(32, 1),
528
+
PLL_PARAMS(33, 1),
529
+
PLL_PARAMS(34, 1),
530
+
PLL_PARAMS(35, 1),
531
+
PLL_PARAMS(36, 1),
532
+
PLL_PARAMS(37, 1),
533
+
PLL_PARAMS(38, 1),
534
+
PLL_PARAMS(39, 1),
535
+
PLL_PARAMS(40, 1),
536
+
PLL_PARAMS(41, 1),
537
+
PLL_PARAMS(42, 1),
538
+
PLL_PARAMS(43, 1),
539
+
PLL_PARAMS(44, 1),
540
+
PLL_PARAMS(45, 1),
541
+
PLL_PARAMS(46, 1),
542
+
PLL_PARAMS(47, 1),
543
+
PLL_PARAMS(48, 1),
544
+
PLL_PARAMS(49, 1),
545
+
PLL_PARAMS(50, 1),
546
+
PLL_PARAMS(51, 1),
547
+
PLL_PARAMS(52, 1),
548
+
PLL_PARAMS(53, 1),
549
+
PLL_PARAMS(54, 1),
550
+
PLL_PARAMS(55, 1),
551
+
PLL_PARAMS(56, 1),
552
+
PLL_PARAMS(57, 1),
553
+
PLL_PARAMS(58, 1),
554
+
PLL_PARAMS(59, 1),
555
+
PLL_PARAMS(60, 1),
556
+
PLL_PARAMS(61, 1),
557
+
PLL_PARAMS(62, 1),
558
+
{ /* sentinel */ },
559
+
};
560
+
561
+
static const struct reg_sequence gxbb_gp0_pll_init_regs[] = {
463
562
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
464
563
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
465
564
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
···
528
557
.width = 1,
529
558
},
530
559
.table = gxbb_gp0_pll_params_table,
531
-
.init_regs = gxbb_gp0_init_regs,
532
-
.init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
560
+
.init_regs = gxbb_gp0_pll_init_regs,
561
+
.init_count = ARRAY_SIZE(gxbb_gp0_pll_init_regs),
533
562
},
534
563
.hw.init = &(struct clk_init_data){
535
564
.name = "gp0_pll_dco",
···
541
570
},
542
571
};
543
572
544
-
static const struct reg_sequence gxl_gp0_init_regs[] = {
573
+
static const struct pll_params_table gxl_gp0_pll_params_table[] = {
574
+
PLL_PARAMS(42, 1),
575
+
PLL_PARAMS(43, 1),
576
+
PLL_PARAMS(44, 1),
577
+
PLL_PARAMS(45, 1),
578
+
PLL_PARAMS(46, 1),
579
+
PLL_PARAMS(47, 1),
580
+
PLL_PARAMS(48, 1),
581
+
PLL_PARAMS(49, 1),
582
+
PLL_PARAMS(50, 1),
583
+
PLL_PARAMS(51, 1),
584
+
PLL_PARAMS(52, 1),
585
+
PLL_PARAMS(53, 1),
586
+
PLL_PARAMS(54, 1),
587
+
PLL_PARAMS(55, 1),
588
+
PLL_PARAMS(56, 1),
589
+
PLL_PARAMS(57, 1),
590
+
PLL_PARAMS(58, 1),
591
+
PLL_PARAMS(59, 1),
592
+
PLL_PARAMS(60, 1),
593
+
PLL_PARAMS(61, 1),
594
+
PLL_PARAMS(62, 1),
595
+
PLL_PARAMS(63, 1),
596
+
PLL_PARAMS(64, 1),
597
+
PLL_PARAMS(65, 1),
598
+
PLL_PARAMS(66, 1),
599
+
{ /* sentinel */ },
600
+
};
601
+
602
+
static const struct reg_sequence gxl_gp0_pll_init_regs[] = {
545
603
{ .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
546
604
{ .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
547
605
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
···
611
611
.width = 1,
612
612
},
613
613
.table = gxl_gp0_pll_params_table,
614
-
.init_regs = gxl_gp0_init_regs,
615
-
.init_count = ARRAY_SIZE(gxl_gp0_init_regs),
614
+
.init_regs = gxl_gp0_pll_init_regs,
615
+
.init_count = ARRAY_SIZE(gxl_gp0_pll_init_regs),
616
616
},
617
617
.hw.init = &(struct clk_init_data){
618
618
.name = "gp0_pll_dco",
···
972
972
},
973
973
};
974
974
975
-
static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
976
-
static const struct clk_parent_data clk81_parent_data[] = {
975
+
/* clk81 is often referred as "mpeg_clk" */
976
+
static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
977
+
static const struct clk_parent_data clk81_parents[] = {
977
978
{ .fw_name = "xtal", },
978
979
{ .hw = &gxbb_fclk_div7.hw },
979
980
{ .hw = &gxbb_mpll1.hw },
···
984
983
{ .hw = &gxbb_fclk_div5.hw },
985
984
};
986
985
987
-
static struct clk_regmap gxbb_mpeg_clk_sel = {
986
+
static struct clk_regmap gxbb_clk81_sel = {
988
987
.data = &(struct clk_regmap_mux_data){
989
988
.offset = HHI_MPEG_CLK_CNTL,
990
989
.mask = 0x7,
991
990
.shift = 12,
992
-
.table = mux_table_clk81,
991
+
.table = clk81_parents_val_table,
993
992
},
994
993
.hw.init = &(struct clk_init_data){
995
-
.name = "mpeg_clk_sel",
994
+
.name = "clk81_sel",
996
995
.ops = &clk_regmap_mux_ro_ops,
997
996
/*
998
997
* bits 14:12 selects from 8 possible parents:
999
998
* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
1000
999
* fclk_div4, fclk_div3, fclk_div5
1001
1000
*/
1002
-
.parent_data = clk81_parent_data,
1003
-
.num_parents = ARRAY_SIZE(clk81_parent_data),
1001
+
.parent_data = clk81_parents,
1002
+
.num_parents = ARRAY_SIZE(clk81_parents),
1004
1003
},
1005
1004
};
1006
1005
1007
-
static struct clk_regmap gxbb_mpeg_clk_div = {
1006
+
static struct clk_regmap gxbb_clk81_div = {
1008
1007
.data = &(struct clk_regmap_div_data){
1009
1008
.offset = HHI_MPEG_CLK_CNTL,
1010
1009
.shift = 0,
1011
1010
.width = 7,
1012
1011
},
1013
1012
.hw.init = &(struct clk_init_data){
1014
-
.name = "mpeg_clk_div",
1013
+
.name = "clk81_div",
1015
1014
.ops = &clk_regmap_divider_ro_ops,
1016
1015
.parent_hws = (const struct clk_hw *[]) {
1017
-
&gxbb_mpeg_clk_sel.hw
1016
+
&gxbb_clk81_sel.hw
1018
1017
},
1019
1018
.num_parents = 1,
1020
1019
},
···
1030
1029
.name = "clk81",
1031
1030
.ops = &clk_regmap_gate_ops,
1032
1031
.parent_hws = (const struct clk_hw *[]) {
1033
-
&gxbb_mpeg_clk_div.hw
1032
+
&gxbb_clk81_div.hw
1034
1033
},
1035
1034
.num_parents = 1,
1036
1035
.flags = CLK_IS_CRITICAL,
···
1095
1094
* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1096
1095
*/
1097
1096
1098
-
static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
1097
+
static const struct clk_parent_data gxbb_mali_parents[] = {
1099
1098
{ .fw_name = "xtal", },
1100
1099
{ .hw = &gxbb_gp0_pll.hw },
1101
1100
{ .hw = &gxbb_mpll2.hw },
···
1115
1114
.hw.init = &(struct clk_init_data){
1116
1115
.name = "mali_0_sel",
1117
1116
.ops = &clk_regmap_mux_ops,
1118
-
.parent_data = gxbb_mali_0_1_parent_data,
1119
-
.num_parents = 8,
1117
+
.parent_data = gxbb_mali_parents,
1118
+
.num_parents = ARRAY_SIZE(gxbb_mali_parents),
1120
1119
/*
1121
1120
* Don't request the parent to change the rate because
1122
1121
* all GPU frequencies can be derived from the fclk_*
···
1169
1168
.hw.init = &(struct clk_init_data){
1170
1169
.name = "mali_1_sel",
1171
1170
.ops = &clk_regmap_mux_ops,
1172
-
.parent_data = gxbb_mali_0_1_parent_data,
1173
-
.num_parents = 8,
1171
+
.parent_data = gxbb_mali_parents,
1172
+
.num_parents = ARRAY_SIZE(gxbb_mali_parents),
1174
1173
/*
1175
1174
* Don't request the parent to change the rate because
1176
1175
* all GPU frequencies can be derived from the fclk_*
···
1214
1213
},
1215
1214
};
1216
1215
1217
-
static const struct clk_hw *gxbb_mali_parent_hws[] = {
1218
-
&gxbb_mali_0.hw,
1219
-
&gxbb_mali_1.hw,
1220
-
};
1221
-
1222
1216
static struct clk_regmap gxbb_mali = {
1223
1217
.data = &(struct clk_regmap_mux_data){
1224
1218
.offset = HHI_MALI_CLK_CNTL,
···
1223
1227
.hw.init = &(struct clk_init_data){
1224
1228
.name = "mali",
1225
1229
.ops = &clk_regmap_mux_ops,
1226
-
.parent_hws = gxbb_mali_parent_hws,
1230
+
.parent_hws = (const struct clk_hw *[]) {
1231
+
&gxbb_mali_0.hw,
1232
+
&gxbb_mali_1.hw,
1233
+
},
1227
1234
.num_parents = 2,
1228
1235
.flags = CLK_SET_RATE_PARENT,
1229
1236
},
1237
+
};
1238
+
1239
+
static u32 gxbb_cts_mclk_parents_val_table[] = { 1, 2, 3 };
1240
+
static const struct clk_hw *gxbb_cts_mclk_parents[] = {
1241
+
&gxbb_mpll0.hw,
1242
+
&gxbb_mpll1.hw,
1243
+
&gxbb_mpll2.hw,
1230
1244
};
1231
1245
1232
1246
static struct clk_regmap gxbb_cts_amclk_sel = {
···
1244
1238
.offset = HHI_AUD_CLK_CNTL,
1245
1239
.mask = 0x3,
1246
1240
.shift = 9,
1247
-
.table = (u32[]){ 1, 2, 3 },
1241
+
.table = gxbb_cts_mclk_parents_val_table,
1248
1242
.flags = CLK_MUX_ROUND_CLOSEST,
1249
1243
},
1250
1244
.hw.init = &(struct clk_init_data){
1251
1245
.name = "cts_amclk_sel",
1252
1246
.ops = &clk_regmap_mux_ops,
1253
-
.parent_hws = (const struct clk_hw *[]) {
1254
-
&gxbb_mpll0.hw,
1255
-
&gxbb_mpll1.hw,
1256
-
&gxbb_mpll2.hw,
1257
-
},
1258
-
.num_parents = 3,
1247
+
.parent_hws = gxbb_cts_mclk_parents,
1248
+
.num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents),
1259
1249
},
1260
1250
};
1261
1251
···
1294
1292
.offset = HHI_AUD_CLK_CNTL2,
1295
1293
.mask = 0x3,
1296
1294
.shift = 25,
1297
-
.table = (u32[]){ 1, 2, 3 },
1295
+
.table = gxbb_cts_mclk_parents_val_table,
1298
1296
.flags = CLK_MUX_ROUND_CLOSEST,
1299
1297
},
1300
1298
.hw.init = &(struct clk_init_data) {
1301
1299
.name = "cts_mclk_i958_sel",
1302
1300
.ops = &clk_regmap_mux_ops,
1303
-
.parent_hws = (const struct clk_hw *[]) {
1304
-
&gxbb_mpll0.hw,
1305
-
&gxbb_mpll1.hw,
1306
-
&gxbb_mpll2.hw,
1307
-
},
1308
-
.num_parents = 3,
1301
+
.parent_hws = gxbb_cts_mclk_parents,
1302
+
.num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents),
1309
1303
},
1310
1304
};
1311
1305
···
1366
1368
* This clock does not exist yet in this controller or the AO one
1367
1369
*/
1368
1370
static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 };
1369
-
static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1371
+
static const struct clk_parent_data gxbb_32k_clk_parents[] = {
1370
1372
{ .fw_name = "xtal", },
1371
1373
{ .hw = &gxbb_fclk_div3.hw },
1372
1374
{ .hw = &gxbb_fclk_div5.hw },
···
1378
1380
.mask = 0x3,
1379
1381
.shift = 16,
1380
1382
.table = gxbb_32k_clk_parents_val_table,
1381
-
},
1383
+
},
1382
1384
.hw.init = &(struct clk_init_data){
1383
1385
.name = "32k_clk_sel",
1384
1386
.ops = &clk_regmap_mux_ops,
1385
-
.parent_data = gxbb_32k_clk_parent_data,
1387
+
.parent_data = gxbb_32k_clk_parents,
1386
1388
.num_parents = 4,
1387
1389
.flags = CLK_SET_RATE_PARENT,
1388
1390
},
···
1421
1423
},
1422
1424
};
1423
1425
1424
-
static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1426
+
static const struct clk_parent_data gxbb_sd_emmc_clk0_parents[] = {
1425
1427
{ .fw_name = "xtal", },
1426
1428
{ .hw = &gxbb_fclk_div2.hw },
1427
1429
{ .hw = &gxbb_fclk_div3.hw },
···
1445
1447
.hw.init = &(struct clk_init_data) {
1446
1448
.name = "sd_emmc_a_clk0_sel",
1447
1449
.ops = &clk_regmap_mux_ops,
1448
-
.parent_data = gxbb_sd_emmc_clk0_parent_data,
1449
-
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1450
+
.parent_data = gxbb_sd_emmc_clk0_parents,
1451
+
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents),
1450
1452
.flags = CLK_SET_RATE_PARENT,
1451
1453
},
1452
1454
};
···
1495
1497
.hw.init = &(struct clk_init_data) {
1496
1498
.name = "sd_emmc_b_clk0_sel",
1497
1499
.ops = &clk_regmap_mux_ops,
1498
-
.parent_data = gxbb_sd_emmc_clk0_parent_data,
1499
-
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1500
+
.parent_data = gxbb_sd_emmc_clk0_parents,
1501
+
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents),
1500
1502
.flags = CLK_SET_RATE_PARENT,
1501
1503
},
1502
1504
};
···
1545
1547
.hw.init = &(struct clk_init_data) {
1546
1548
.name = "sd_emmc_c_clk0_sel",
1547
1549
.ops = &clk_regmap_mux_ops,
1548
-
.parent_data = gxbb_sd_emmc_clk0_parent_data,
1549
-
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1550
+
.parent_data = gxbb_sd_emmc_clk0_parents,
1551
+
.num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents),
1550
1552
.flags = CLK_SET_RATE_PARENT,
1551
1553
},
1552
1554
};
···
1587
1589
1588
1590
/* VPU Clock */
1589
1591
1590
-
static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1592
+
static const struct clk_hw *gxbb_vpu_parents[] = {
1591
1593
&gxbb_fclk_div4.hw,
1592
1594
&gxbb_fclk_div3.hw,
1593
1595
&gxbb_fclk_div5.hw,
···
1607
1609
* bits 9:10 selects from 4 possible parents:
1608
1610
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1609
1611
*/
1610
-
.parent_hws = gxbb_vpu_parent_hws,
1611
-
.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1612
+
.parent_hws = gxbb_vpu_parents,
1613
+
.num_parents = ARRAY_SIZE(gxbb_vpu_parents),
1612
1614
.flags = CLK_SET_RATE_NO_REPARENT,
1613
1615
},
1614
1616
};
···
1655
1657
* bits 25:26 selects from 4 possible parents:
1656
1658
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1657
1659
*/
1658
-
.parent_hws = gxbb_vpu_parent_hws,
1659
-
.num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1660
+
.parent_hws = gxbb_vpu_parents,
1661
+
.num_parents = ARRAY_SIZE(gxbb_vpu_parents),
1660
1662
.flags = CLK_SET_RATE_NO_REPARENT,
1661
1663
},
1662
1664
};
···
1714
1716
1715
1717
/* VAPB Clock */
1716
1718
1717
-
static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1719
+
static const struct clk_hw *gxbb_vapb_parents[] = {
1718
1720
&gxbb_fclk_div4.hw,
1719
1721
&gxbb_fclk_div3.hw,
1720
1722
&gxbb_fclk_div5.hw,
···
1734
1736
* bits 9:10 selects from 4 possible parents:
1735
1737
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1736
1738
*/
1737
-
.parent_hws = gxbb_vapb_parent_hws,
1738
-
.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1739
+
.parent_hws = gxbb_vapb_parents,
1740
+
.num_parents = ARRAY_SIZE(gxbb_vapb_parents),
1739
1741
.flags = CLK_SET_RATE_NO_REPARENT,
1740
1742
},
1741
1743
};
···
1786
1788
* bits 25:26 selects from 4 possible parents:
1787
1789
* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1788
1790
*/
1789
-
.parent_hws = gxbb_vapb_parent_hws,
1790
-
.num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1791
+
.parent_hws = gxbb_vapb_parents,
1792
+
.num_parents = ARRAY_SIZE(gxbb_vapb_parents),
1791
1793
.flags = CLK_SET_RATE_NO_REPARENT,
1792
1794
},
1793
1795
};
···
1895
1897
},
1896
1898
};
1897
1899
1898
-
static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1900
+
static const struct clk_parent_data gxbb_vid_pll_parents[] = {
1899
1901
{ .hw = &gxbb_vid_pll_div.hw },
1900
1902
/*
1901
1903
* Note:
···
1920
1922
* bit 18 selects from 2 possible parents:
1921
1923
* vid_pll_div or hdmi_pll
1922
1924
*/
1923
-
.parent_data = gxbb_vid_pll_parent_data,
1924
-
.num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1925
+
.parent_data = gxbb_vid_pll_parents,
1926
+
.num_parents = ARRAY_SIZE(gxbb_vid_pll_parents),
1925
1927
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1926
1928
},
1927
1929
};
···
1942
1944
},
1943
1945
};
1944
1946
1945
-
static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1947
+
static const struct clk_hw *gxbb_vclk_parents[] = {
1946
1948
&gxbb_vid_pll.hw,
1947
1949
&gxbb_fclk_div4.hw,
1948
1950
&gxbb_fclk_div3.hw,
···
1966
1968
* vid_pll, fclk_div4, fclk_div3, fclk_div5,
1967
1969
* vid_pll, fclk_div7, mp1
1968
1970
*/
1969
-
.parent_hws = gxbb_vclk_parent_hws,
1970
-
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1971
+
.parent_hws = gxbb_vclk_parents,
1972
+
.num_parents = ARRAY_SIZE(gxbb_vclk_parents),
1971
1973
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1972
1974
},
1973
1975
};
···
1986
1988
* vid_pll, fclk_div4, fclk_div3, fclk_div5,
1987
1989
* vid_pll, fclk_div7, mp1
1988
1990
*/
1989
-
.parent_hws = gxbb_vclk_parent_hws,
1990
-
.num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1991
+
.parent_hws = gxbb_vclk_parents,
1992
+
.num_parents = ARRAY_SIZE(gxbb_vclk_parents),
1991
1993
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1992
1994
},
1993
1995
};
···
2326
2328
},
2327
2329
};
2328
2330
2329
-
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2330
-
static const struct clk_hw *gxbb_cts_parent_hws[] = {
2331
+
static u32 gxbb_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2332
+
static const struct clk_hw *gxbb_cts_parents[] = {
2331
2333
&gxbb_vclk_div1.hw,
2332
2334
&gxbb_vclk_div2.hw,
2333
2335
&gxbb_vclk_div4.hw,
···
2345
2347
.offset = HHI_VID_CLK_DIV,
2346
2348
.mask = 0xf,
2347
2349
.shift = 28,
2348
-
.table = mux_table_cts_sel,
2350
+
.table = gxbb_cts_parents_val_table,
2349
2351
},
2350
2352
.hw.init = &(struct clk_init_data){
2351
2353
.name = "cts_enci_sel",
2352
2354
.ops = &clk_regmap_mux_ops,
2353
-
.parent_hws = gxbb_cts_parent_hws,
2354
-
.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2355
+
.parent_hws = gxbb_cts_parents,
2356
+
.num_parents = ARRAY_SIZE(gxbb_cts_parents),
2355
2357
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2356
2358
},
2357
2359
};
···
2361
2363
.offset = HHI_VID_CLK_DIV,
2362
2364
.mask = 0xf,
2363
2365
.shift = 20,
2364
-
.table = mux_table_cts_sel,
2366
+
.table = gxbb_cts_parents_val_table,
2365
2367
},
2366
2368
.hw.init = &(struct clk_init_data){
2367
2369
.name = "cts_encp_sel",
2368
2370
.ops = &clk_regmap_mux_ops,
2369
-
.parent_hws = gxbb_cts_parent_hws,
2370
-
.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2371
+
.parent_hws = gxbb_cts_parents,
2372
+
.num_parents = ARRAY_SIZE(gxbb_cts_parents),
2371
2373
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2372
2374
},
2373
2375
};
···
2377
2379
.offset = HHI_VIID_CLK_DIV,
2378
2380
.mask = 0xf,
2379
2381
.shift = 28,
2380
-
.table = mux_table_cts_sel,
2382
+
.table = gxbb_cts_parents_val_table,
2381
2383
},
2382
2384
.hw.init = &(struct clk_init_data){
2383
2385
.name = "cts_vdac_sel",
2384
2386
.ops = &clk_regmap_mux_ops,
2385
-
.parent_hws = gxbb_cts_parent_hws,
2386
-
.num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2387
-
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2388
-
},
2389
-
};
2390
-
2391
-
/* TOFIX: add support for cts_tcon */
2392
-
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2393
-
static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2394
-
&gxbb_vclk_div1.hw,
2395
-
&gxbb_vclk_div2.hw,
2396
-
&gxbb_vclk_div4.hw,
2397
-
&gxbb_vclk_div6.hw,
2398
-
&gxbb_vclk_div12.hw,
2399
-
&gxbb_vclk2_div1.hw,
2400
-
&gxbb_vclk2_div2.hw,
2401
-
&gxbb_vclk2_div4.hw,
2402
-
&gxbb_vclk2_div6.hw,
2403
-
&gxbb_vclk2_div12.hw,
2404
-
};
2405
-
2406
-
static struct clk_regmap gxbb_hdmi_tx_sel = {
2407
-
.data = &(struct clk_regmap_mux_data){
2408
-
.offset = HHI_HDMI_CLK_CNTL,
2409
-
.mask = 0xf,
2410
-
.shift = 16,
2411
-
.table = mux_table_hdmi_tx_sel,
2412
-
},
2413
-
.hw.init = &(struct clk_init_data){
2414
-
.name = "hdmi_tx_sel",
2415
-
.ops = &clk_regmap_mux_ops,
2416
-
/*
2417
-
* bits 31:28 selects from 12 possible parents:
2418
-
* vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2419
-
* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2420
-
* cts_tcon
2421
-
*/
2422
-
.parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2423
-
.num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2387
+
.parent_hws = gxbb_cts_parents,
2388
+
.num_parents = ARRAY_SIZE(gxbb_cts_parents),
2424
2389
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2425
2390
},
2426
2391
};
···
2436
2475
},
2437
2476
};
2438
2477
2478
+
/* TOFIX: add support for cts_tcon */
2479
+
static u32 gxbb_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2480
+
static const struct clk_hw *gxbb_hdmi_tx_parents[] = {
2481
+
&gxbb_vclk_div1.hw,
2482
+
&gxbb_vclk_div2.hw,
2483
+
&gxbb_vclk_div4.hw,
2484
+
&gxbb_vclk_div6.hw,
2485
+
&gxbb_vclk_div12.hw,
2486
+
&gxbb_vclk2_div1.hw,
2487
+
&gxbb_vclk2_div2.hw,
2488
+
&gxbb_vclk2_div4.hw,
2489
+
&gxbb_vclk2_div6.hw,
2490
+
&gxbb_vclk2_div12.hw,
2491
+
};
2492
+
2493
+
static struct clk_regmap gxbb_hdmi_tx_sel = {
2494
+
.data = &(struct clk_regmap_mux_data){
2495
+
.offset = HHI_HDMI_CLK_CNTL,
2496
+
.mask = 0xf,
2497
+
.shift = 16,
2498
+
.table = gxbb_hdmi_tx_parents_val_table,
2499
+
},
2500
+
.hw.init = &(struct clk_init_data){
2501
+
.name = "hdmi_tx_sel",
2502
+
.ops = &clk_regmap_mux_ops,
2503
+
/*
2504
+
* bits 31:28 selects from 12 possible parents:
2505
+
* vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2506
+
* vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2507
+
* cts_tcon
2508
+
*/
2509
+
.parent_hws = gxbb_hdmi_tx_parents,
2510
+
.num_parents = ARRAY_SIZE(gxbb_hdmi_tx_parents),
2511
+
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2512
+
},
2513
+
};
2514
+
2439
2515
static struct clk_regmap gxbb_hdmi_tx = {
2440
2516
.data = &(struct clk_regmap_gate_data){
2441
2517
.offset = HHI_VID_CLK_CNTL2,
···
2491
2493
2492
2494
/* HDMI Clocks */
2493
2495
2494
-
static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2496
+
static const struct clk_parent_data gxbb_hdmi_parents[] = {
2495
2497
{ .fw_name = "xtal", },
2496
2498
{ .hw = &gxbb_fclk_div4.hw },
2497
2499
{ .hw = &gxbb_fclk_div3.hw },
···
2508
2510
.hw.init = &(struct clk_init_data){
2509
2511
.name = "hdmi_sel",
2510
2512
.ops = &clk_regmap_mux_ops,
2511
-
.parent_data = gxbb_hdmi_parent_data,
2512
-
.num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2513
+
.parent_data = gxbb_hdmi_parents,
2514
+
.num_parents = ARRAY_SIZE(gxbb_hdmi_parents),
2513
2515
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2514
2516
},
2515
2517
};
···
2545
2547
2546
2548
/* VDEC clocks */
2547
2549
2548
-
static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2550
+
static const struct clk_hw *gxbb_vdec_parents[] = {
2549
2551
&gxbb_fclk_div4.hw,
2550
2552
&gxbb_fclk_div3.hw,
2551
2553
&gxbb_fclk_div5.hw,
···
2562
2564
.hw.init = &(struct clk_init_data){
2563
2565
.name = "vdec_1_sel",
2564
2566
.ops = &clk_regmap_mux_ops,
2565
-
.parent_hws = gxbb_vdec_parent_hws,
2566
-
.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2567
+
.parent_hws = gxbb_vdec_parents,
2568
+
.num_parents = ARRAY_SIZE(gxbb_vdec_parents),
2567
2569
.flags = CLK_SET_RATE_PARENT,
2568
2570
},
2569
2571
};
···
2612
2614
.hw.init = &(struct clk_init_data){
2613
2615
.name = "vdec_hevc_sel",
2614
2616
.ops = &clk_regmap_mux_ops,
2615
-
.parent_hws = gxbb_vdec_parent_hws,
2616
-
.num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2617
+
.parent_hws = gxbb_vdec_parents,
2618
+
.num_parents = ARRAY_SIZE(gxbb_vdec_parents),
2617
2619
.flags = CLK_SET_RATE_PARENT,
2618
2620
},
2619
2621
};
···
2652
2654
},
2653
2655
};
2654
2656
2655
-
static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
2656
-
9, 10, 11, 13, 14, };
2657
-
static const struct clk_parent_data gen_clk_parent_data[] = {
2657
+
static u32 gxbb_gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, };
2658
+
static const struct clk_parent_data gxbb_gen_clk_parents[] = {
2658
2659
{ .fw_name = "xtal", },
2659
2660
{ .hw = &gxbb_vdec_1.hw },
2660
2661
{ .hw = &gxbb_vdec_hevc.hw },
···
2672
2675
.offset = HHI_GEN_CLK_CNTL,
2673
2676
.mask = 0xf,
2674
2677
.shift = 12,
2675
-
.table = mux_table_gen_clk,
2678
+
.table = gxbb_gen_clk_parents_val_table,
2676
2679
},
2677
2680
.hw.init = &(struct clk_init_data){
2678
2681
.name = "gen_clk_sel",
···
2683
2686
* vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2684
2687
* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2685
2688
*/
2686
-
.parent_data = gen_clk_parent_data,
2687
-
.num_parents = ARRAY_SIZE(gen_clk_parent_data),
2689
+
.parent_data = gxbb_gen_clk_parents,
2690
+
.num_parents = ARRAY_SIZE(gxbb_gen_clk_parents),
2688
2691
},
2689
2692
};
2690
2693
···
2721
2724
},
2722
2725
};
2723
2726
2724
-
#define MESON_GATE(_name, _reg, _bit) \
2725
-
MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2727
+
static const struct clk_parent_data gxbb_pclk_parents = { .hw = &gxbb_clk81.hw };
2726
2728
2727
-
/* Everything Else (EE) domain gates */
2728
-
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2729
-
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2730
-
static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2731
-
static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2732
-
static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2733
-
static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2734
-
static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2735
-
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2736
-
static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2737
-
static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2738
-
static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2739
-
static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2740
-
static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2741
-
static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2742
-
static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2743
-
static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2744
-
static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2745
-
static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2746
-
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2747
-
static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2748
-
static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2749
-
static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2750
-
static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2729
+
#define GXBB_PCLK(_name, _reg, _bit, _flags) \
2730
+
MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags)
2751
2731
2752
-
static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2753
-
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2754
-
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2755
-
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2756
-
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2757
-
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2758
-
static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2759
-
static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2760
-
static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2761
-
static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2762
-
static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2763
-
static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2764
-
static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2765
-
static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2766
-
static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2767
-
static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2768
-
static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2732
+
/*
2733
+
* Everything Else (EE) domain gates
2734
+
*
2735
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
2736
+
* Users are encouraged to test without it and submit changes to:
2737
+
* - remove the flag if not necessary
2738
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
2739
+
* if appropriate.
2740
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
2741
+
* for a particular clock.
2742
+
*/
2743
+
static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED);
2744
+
static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED);
2745
+
static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED);
2746
+
static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED);
2747
+
static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED);
2748
+
static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED);
2749
+
static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED);
2750
+
static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED);
2751
+
static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED);
2752
+
static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED);
2753
+
static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED);
2754
+
static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED);
2755
+
static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED);
2756
+
static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED);
2757
+
static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED);
2758
+
static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED);
2759
+
static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED);
2760
+
static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED);
2761
+
static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED);
2762
+
static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED);
2763
+
static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED);
2764
+
static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED);
2765
+
static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED);
2769
2766
2770
-
static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2771
-
static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2772
-
static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2773
-
static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2774
-
static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2775
-
static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2776
-
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2777
-
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2778
-
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2779
-
static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2780
-
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2781
-
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2782
-
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2767
+
static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED);
2768
+
static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED);
2769
+
static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED);
2770
+
static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED);
2771
+
static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED);
2772
+
static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED);
2773
+
static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED);
2774
+
static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED);
2775
+
static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED);
2776
+
static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED);
2777
+
static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED);
2778
+
static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED);
2779
+
static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED);
2780
+
static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED);
2781
+
static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED);
2782
+
static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED);
2783
+
static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED);
2783
2784
2784
-
static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2785
-
static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2786
-
static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2787
-
static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2788
-
static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2789
-
static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2790
-
static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2791
-
static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2792
-
static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2793
-
static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2794
-
static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2795
-
static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2796
-
static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2797
-
static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2798
-
static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2799
-
static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2785
+
static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED);
2786
+
static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED);
2787
+
static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED);
2788
+
static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED);
2789
+
static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED);
2790
+
static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED);
2791
+
static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED);
2792
+
static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED);
2793
+
static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED);
2794
+
static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED);
2795
+
static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED);
2796
+
static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED);
2797
+
static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED);
2798
+
2799
+
static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED);
2800
+
static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED);
2801
+
static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED);
2802
+
static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED);
2803
+
static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED);
2804
+
static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED);
2805
+
static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED);
2806
+
static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED);
2807
+
static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED);
2808
+
static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED);
2809
+
static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED);
2810
+
static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED);
2811
+
static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED);
2812
+
static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED);
2813
+
static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED);
2814
+
static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED);
2800
2815
2801
2816
/* Always On (AO) domain gates */
2802
2817
2803
-
static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2804
-
static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2805
-
static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2806
-
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2807
-
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2818
+
static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED);
2819
+
static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED);
2820
+
static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED);
2821
+
static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED);
2822
+
static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED);
2808
2823
2809
2824
/* AIU gates */
2810
-
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2811
-
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2812
-
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2813
-
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2814
-
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2815
-
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2816
-
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2817
-
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2825
+
static const struct clk_parent_data gxbb_aiu_glue_parents = { .hw = &gxbb_aiu.hw };
2826
+
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parents, CLK_IGNORE_UNUSED);
2827
+
2828
+
static const struct clk_parent_data gxbb_aiu_pclk_parents = { .hw = &gxbb_aiu_glue.hw };
2829
+
#define GXBB_AIU_PCLK(_name, _bit, _flags) \
2830
+
MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags)
2831
+
2832
+
static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED);
2833
+
static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED);
2834
+
static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED);
2835
+
static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED);
2836
+
static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED);
2837
+
static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED);
2838
+
static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED);
2818
2839
2819
2840
/* Array of all clocks provided by this provider */
2820
2841
···
2846
2831
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2847
2832
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2848
2833
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2849
-
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2850
-
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2834
+
[CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw,
2835
+
[CLKID_MPEG_DIV] = &gxbb_clk81_div.hw,
2851
2836
[CLKID_CLK81] = &gxbb_clk81.hw,
2852
2837
[CLKID_MPLL0] = &gxbb_mpll0.hw,
2853
2838
[CLKID_MPLL1] = &gxbb_mpll1.hw,
···
3054
3039
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
3055
3040
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
3056
3041
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
3057
-
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
3058
-
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
3042
+
[CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw,
3043
+
[CLKID_MPEG_DIV] = &gxbb_clk81_div.hw,
3059
3044
[CLKID_CLK81] = &gxbb_clk81.hw,
3060
3045
[CLKID_MPLL0] = &gxbb_mpll0.hw,
3061
3046
[CLKID_MPLL1] = &gxbb_mpll1.hw,
···
3252
3237
[CLKID_ACODEC] = &gxl_acodec.hw,
3253
3238
};
3254
3239
3255
-
static const struct meson_eeclkc_data gxbb_clkc_data = {
3240
+
static const struct meson_clkc_data gxbb_clkc_data = {
3256
3241
.hw_clks = {
3257
3242
.hws = gxbb_hw_clks,
3258
3243
.num = ARRAY_SIZE(gxbb_hw_clks),
3259
3244
},
3260
3245
};
3261
3246
3262
-
static const struct meson_eeclkc_data gxl_clkc_data = {
3247
+
static const struct meson_clkc_data gxl_clkc_data = {
3263
3248
.hw_clks = {
3264
3249
.hws = gxl_hw_clks,
3265
3250
.num = ARRAY_SIZE(gxl_hw_clks),
3266
3251
},
3267
3252
};
3268
3253
3269
-
static const struct of_device_id clkc_match_table[] = {
3254
+
static const struct of_device_id gxbb_clkc_match_table[] = {
3270
3255
{ .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3271
3256
{ .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3272
3257
{},
3273
3258
};
3274
-
MODULE_DEVICE_TABLE(of, clkc_match_table);
3259
+
MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table);
3275
3260
3276
-
static struct platform_driver gxbb_driver = {
3277
-
.probe = meson_eeclkc_probe,
3261
+
static struct platform_driver gxbb_clkc_driver = {
3262
+
.probe = meson_clkc_syscon_probe,
3278
3263
.driver = {
3279
3264
.name = "gxbb-clkc",
3280
-
.of_match_table = clkc_match_table,
3265
+
.of_match_table = gxbb_clkc_match_table,
3281
3266
},
3282
3267
};
3283
-
module_platform_driver(gxbb_driver);
3268
+
module_platform_driver(gxbb_clkc_driver);
3284
3269
3285
3270
MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver");
3286
3271
MODULE_LICENSE("GPL");
+14
-18
drivers/clk/meson/meson-aoclk.c
+14
-18
drivers/clk/meson/meson-aoclk.c
···
37
37
int meson_aoclkc_probe(struct platform_device *pdev)
38
38
{
39
39
struct meson_aoclk_reset_controller *rstc;
40
-
struct meson_aoclk_data *data;
40
+
const struct meson_clkc_data *clkc_data;
41
+
const struct meson_aoclk_data *data;
41
42
struct device *dev = &pdev->dev;
42
43
struct device_node *np;
43
44
struct regmap *regmap;
44
-
int ret, clkid;
45
+
int ret;
45
46
46
-
data = (struct meson_aoclk_data *) of_device_get_match_data(dev);
47
-
if (!data)
48
-
return -ENODEV;
47
+
clkc_data = of_device_get_match_data(dev);
48
+
if (!clkc_data)
49
+
return -EINVAL;
50
+
51
+
ret = meson_clkc_syscon_probe(pdev);
52
+
if (ret)
53
+
return ret;
54
+
55
+
data = container_of(clkc_data, struct meson_aoclk_data,
56
+
clkc_data);
49
57
50
58
rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
51
59
if (!rstc)
···
79
71
return ret;
80
72
}
81
73
82
-
/* Register all clks */
83
-
for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
84
-
if (!data->hw_clks.hws[clkid])
85
-
continue;
86
-
87
-
ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
88
-
if (ret) {
89
-
dev_err(dev, "Clock registration failed\n");
90
-
return ret;
91
-
}
92
-
}
93
-
94
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
74
+
return 0;
95
75
}
96
76
EXPORT_SYMBOL_NS_GPL(meson_aoclkc_probe, "CLK_MESON");
97
77
+1
-1
drivers/clk/meson/meson-aoclk.h
+1
-1
drivers/clk/meson/meson-aoclk.h
···
20
20
#include "meson-clkc-utils.h"
21
21
22
22
struct meson_aoclk_data {
23
+
const struct meson_clkc_data clkc_data;
23
24
const unsigned int reset_reg;
24
25
const int num_reset;
25
26
const unsigned int *reset;
26
-
struct meson_clk_hw_data hw_clks;
27
27
};
28
28
29
29
struct meson_aoclk_reset_controller {
+85
-1
drivers/clk/meson/meson-clkc-utils.c
+85
-1
drivers/clk/meson/meson-clkc-utils.c
···
3
3
* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
4
4
*/
5
5
6
-
#include <linux/of_device.h>
7
6
#include <linux/clk-provider.h>
7
+
#include <linux/mfd/syscon.h>
8
8
#include <linux/module.h>
9
+
#include <linux/of_device.h>
10
+
#include <linux/platform_device.h>
11
+
#include <linux/regmap.h>
12
+
9
13
#include "meson-clkc-utils.h"
10
14
11
15
struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
···
25
21
return data->hws[idx];
26
22
}
27
23
EXPORT_SYMBOL_NS_GPL(meson_clk_hw_get, "CLK_MESON");
24
+
25
+
static int meson_clkc_init(struct device *dev, struct regmap *map)
26
+
{
27
+
const struct meson_clkc_data *data;
28
+
struct clk_hw *hw;
29
+
int ret, i;
30
+
31
+
data = of_device_get_match_data(dev);
32
+
if (!data)
33
+
return -EINVAL;
34
+
35
+
if (data->init_count)
36
+
regmap_multi_reg_write(map, data->init_regs, data->init_count);
37
+
38
+
for (i = 0; i < data->hw_clks.num; i++) {
39
+
hw = data->hw_clks.hws[i];
40
+
41
+
/* array might be sparse */
42
+
if (!hw)
43
+
continue;
44
+
45
+
ret = devm_clk_hw_register(dev, hw);
46
+
if (ret) {
47
+
dev_err(dev, "registering %s clock failed\n",
48
+
hw->init->name);
49
+
return ret;
50
+
}
51
+
}
52
+
53
+
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
54
+
}
55
+
56
+
int meson_clkc_syscon_probe(struct platform_device *pdev)
57
+
{
58
+
struct device *dev = &pdev->dev;
59
+
struct device_node *np;
60
+
struct regmap *map;
61
+
62
+
np = of_get_parent(dev->of_node);
63
+
map = syscon_node_to_regmap(np);
64
+
of_node_put(np);
65
+
if (IS_ERR(map)) {
66
+
dev_err(dev, "failed to get parent syscon regmap\n");
67
+
return PTR_ERR(map);
68
+
}
69
+
70
+
return meson_clkc_init(dev, map);
71
+
}
72
+
EXPORT_SYMBOL_NS_GPL(meson_clkc_syscon_probe, "CLK_MESON");
73
+
74
+
int meson_clkc_mmio_probe(struct platform_device *pdev)
75
+
{
76
+
const struct meson_clkc_data *data;
77
+
struct device *dev = &pdev->dev;
78
+
struct resource *res;
79
+
void __iomem *base;
80
+
struct regmap *map;
81
+
struct regmap_config regmap_cfg = {
82
+
.reg_bits = 32,
83
+
.val_bits = 32,
84
+
.reg_stride = 4,
85
+
};
86
+
87
+
data = of_device_get_match_data(dev);
88
+
if (!data)
89
+
return -EINVAL;
90
+
91
+
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
92
+
if (IS_ERR(base))
93
+
return PTR_ERR(base);
94
+
95
+
regmap_cfg.max_register = resource_size(res) - regmap_cfg.reg_stride;
96
+
97
+
map = devm_regmap_init_mmio(dev, base, ®map_cfg);
98
+
if (IS_ERR(map))
99
+
return PTR_ERR(map);
100
+
101
+
return meson_clkc_init(dev, map);
102
+
}
103
+
EXPORT_SYMBOL_NS_GPL(meson_clkc_mmio_probe, "CLK_MESON");
28
104
29
105
MODULE_DESCRIPTION("Amlogic Clock Controller Utilities");
30
106
MODULE_LICENSE("GPL");
+89
drivers/clk/meson/meson-clkc-utils.h
+89
drivers/clk/meson/meson-clkc-utils.h
···
9
9
#include <linux/of_device.h>
10
10
#include <linux/clk-provider.h>
11
11
12
+
struct platform_device;
13
+
12
14
struct meson_clk_hw_data {
13
15
struct clk_hw **hws;
14
16
unsigned int num;
15
17
};
16
18
17
19
struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
20
+
21
+
struct meson_clkc_data {
22
+
const struct reg_sequence *init_regs;
23
+
unsigned int init_count;
24
+
struct meson_clk_hw_data hw_clks;
25
+
};
26
+
27
+
int meson_clkc_syscon_probe(struct platform_device *pdev);
28
+
int meson_clkc_mmio_probe(struct platform_device *pdev);
29
+
30
+
#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \
31
+
struct clk_regmap _name = { \
32
+
.data = &(struct clk_regmap_gate_data) { \
33
+
.offset = (_reg), \
34
+
.bit_idx = (_bit), \
35
+
}, \
36
+
.hw.init = &(struct clk_init_data) { \
37
+
.name = #_name, \
38
+
.ops = _ops, \
39
+
.parent_data = (_pdata), \
40
+
.num_parents = 1, \
41
+
.flags = (_flags), \
42
+
}, \
43
+
}
44
+
45
+
#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \
46
+
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
47
+
48
+
#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \
49
+
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
50
+
51
+
/* Helpers for the usual sel/div/gate composite clocks */
52
+
#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \
53
+
_table, _dflags, _iflags) \
54
+
struct clk_regmap _prefix##_name##_sel = { \
55
+
.data = &(struct clk_regmap_mux_data) { \
56
+
.offset = (_reg), \
57
+
.mask = (_mask), \
58
+
.shift = (_shift), \
59
+
.flags = (_dflags), \
60
+
.table = (_table), \
61
+
}, \
62
+
.hw.init = &(struct clk_init_data){ \
63
+
.name = #_name "_sel", \
64
+
.ops = &clk_regmap_mux_ops, \
65
+
.parent_data = _pdata, \
66
+
.num_parents = ARRAY_SIZE(_pdata), \
67
+
.flags = (_iflags), \
68
+
}, \
69
+
}
70
+
71
+
#define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \
72
+
_dflags, _iflags) \
73
+
struct clk_regmap _prefix##_name##_div = { \
74
+
.data = &(struct clk_regmap_div_data) { \
75
+
.offset = (_reg), \
76
+
.shift = (_shift), \
77
+
.width = (_width), \
78
+
.flags = (_dflags), \
79
+
}, \
80
+
.hw.init = &(struct clk_init_data) { \
81
+
.name = #_name "_div", \
82
+
.ops = &clk_regmap_divider_ops, \
83
+
.parent_hws = (const struct clk_hw *[]) { \
84
+
&_prefix##_name##_sel.hw \
85
+
}, \
86
+
.num_parents = 1, \
87
+
.flags = (_iflags), \
88
+
}, \
89
+
}
90
+
91
+
#define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \
92
+
struct clk_regmap _prefix##_name = { \
93
+
.data = &(struct clk_regmap_gate_data) { \
94
+
.offset = (_reg), \
95
+
.bit_idx = (_bit), \
96
+
}, \
97
+
.hw.init = &(struct clk_init_data) { \
98
+
.name = #_name, \
99
+
.ops = &clk_regmap_gate_ops, \
100
+
.parent_hws = (const struct clk_hw *[]) { \
101
+
&_prefix##_name##_div.hw \
102
+
}, \
103
+
.num_parents = 1, \
104
+
.flags = (_iflags), \
105
+
}, \
106
+
}
18
107
19
108
#endif
-60
drivers/clk/meson/meson-eeclk.c
-60
drivers/clk/meson/meson-eeclk.c
···
1
-
// SPDX-License-Identifier: GPL-2.0
2
-
/*
3
-
* Copyright (c) 2019 BayLibre, SAS.
4
-
* Author: Jerome Brunet <jbrunet@baylibre.com>
5
-
*/
6
-
7
-
#include <linux/clk-provider.h>
8
-
#include <linux/of.h>
9
-
#include <linux/platform_device.h>
10
-
#include <linux/mfd/syscon.h>
11
-
#include <linux/regmap.h>
12
-
#include <linux/module.h>
13
-
14
-
#include "clk-regmap.h"
15
-
#include "meson-eeclk.h"
16
-
17
-
int meson_eeclkc_probe(struct platform_device *pdev)
18
-
{
19
-
const struct meson_eeclkc_data *data;
20
-
struct device *dev = &pdev->dev;
21
-
struct device_node *np;
22
-
struct regmap *map;
23
-
int ret, i;
24
-
25
-
data = of_device_get_match_data(dev);
26
-
if (!data)
27
-
return -EINVAL;
28
-
29
-
/* Get the hhi system controller node */
30
-
np = of_get_parent(dev->of_node);
31
-
map = syscon_node_to_regmap(np);
32
-
of_node_put(np);
33
-
if (IS_ERR(map)) {
34
-
dev_err(dev,
35
-
"failed to get HHI regmap\n");
36
-
return PTR_ERR(map);
37
-
}
38
-
39
-
if (data->init_count)
40
-
regmap_multi_reg_write(map, data->init_regs, data->init_count);
41
-
42
-
for (i = 0; i < data->hw_clks.num; i++) {
43
-
/* array might be sparse */
44
-
if (!data->hw_clks.hws[i])
45
-
continue;
46
-
47
-
ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]);
48
-
if (ret) {
49
-
dev_err(dev, "Clock registration failed\n");
50
-
return ret;
51
-
}
52
-
}
53
-
54
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
55
-
}
56
-
EXPORT_SYMBOL_NS_GPL(meson_eeclkc_probe, "CLK_MESON");
57
-
58
-
MODULE_DESCRIPTION("Amlogic Main Clock Controller Helpers");
59
-
MODULE_LICENSE("GPL");
60
-
MODULE_IMPORT_NS("CLK_MESON");
-24
drivers/clk/meson/meson-eeclk.h
-24
drivers/clk/meson/meson-eeclk.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Copyright (c) 2019 BayLibre, SAS.
4
-
* Author: Jerome Brunet <jbrunet@baylibre.com>
5
-
*/
6
-
7
-
#ifndef __MESON_CLKC_H
8
-
#define __MESON_CLKC_H
9
-
10
-
#include <linux/clk-provider.h>
11
-
#include "clk-regmap.h"
12
-
#include "meson-clkc-utils.h"
13
-
14
-
struct platform_device;
15
-
16
-
struct meson_eeclkc_data {
17
-
const struct reg_sequence *init_regs;
18
-
unsigned int init_count;
19
-
struct meson_clk_hw_data hw_clks;
20
-
};
21
-
22
-
int meson_eeclkc_probe(struct platform_device *pdev);
23
-
24
-
#endif /* __MESON_CLKC_H */
+18
-46
drivers/clk/meson/meson8-ddr.c
+18
-46
drivers/clk/meson/meson8-ddr.c
···
12
12
13
13
#include "clk-regmap.h"
14
14
#include "clk-pll.h"
15
+
#include "meson-clkc-utils.h"
15
16
16
17
#define AM_DDR_PLL_CNTL 0x00
17
18
#define AM_DDR_PLL_CNTL1 0x04
···
78
77
},
79
78
};
80
79
81
-
static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
82
-
.hws = {
83
-
[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
84
-
[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
80
+
static struct clk_hw *meson8_ddr_hw_clks[] = {
81
+
[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
82
+
[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
83
+
};
84
+
85
+
static const struct meson_clkc_data meson8_ddr_clkc_data = {
86
+
.hw_clks = {
87
+
.hws = meson8_ddr_hw_clks,
88
+
.num = ARRAY_SIZE(meson8_ddr_hw_clks),
85
89
},
86
-
.num = 2,
87
90
};
88
-
89
-
static const struct regmap_config meson8_ddr_clkc_regmap_config = {
90
-
.reg_bits = 8,
91
-
.val_bits = 32,
92
-
.reg_stride = 4,
93
-
.max_register = DDR_CLK_STS,
94
-
};
95
-
96
-
static int meson8_ddr_clkc_probe(struct platform_device *pdev)
97
-
{
98
-
struct regmap *regmap;
99
-
void __iomem *base;
100
-
struct clk_hw *hw;
101
-
int ret, i;
102
-
103
-
base = devm_platform_ioremap_resource(pdev, 0);
104
-
if (IS_ERR(base))
105
-
return PTR_ERR(base);
106
-
107
-
regmap = devm_regmap_init_mmio(&pdev->dev, base,
108
-
&meson8_ddr_clkc_regmap_config);
109
-
if (IS_ERR(regmap))
110
-
return PTR_ERR(regmap);
111
-
112
-
/* Register all clks */
113
-
for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) {
114
-
hw = meson8_ddr_clk_hw_onecell_data.hws[i];
115
-
116
-
ret = devm_clk_hw_register(&pdev->dev, hw);
117
-
if (ret) {
118
-
dev_err(&pdev->dev, "Clock registration failed\n");
119
-
return ret;
120
-
}
121
-
}
122
-
123
-
return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
124
-
&meson8_ddr_clk_hw_onecell_data);
125
-
}
126
91
127
92
static const struct of_device_id meson8_ddr_clkc_match_table[] = {
128
-
{ .compatible = "amlogic,meson8-ddr-clkc" },
129
-
{ .compatible = "amlogic,meson8b-ddr-clkc" },
93
+
{
94
+
.compatible = "amlogic,meson8-ddr-clkc",
95
+
.data = &meson8_ddr_clkc_data,
96
+
}, {
97
+
.compatible = "amlogic,meson8b-ddr-clkc",
98
+
.data = &meson8_ddr_clkc_data,
99
+
},
130
100
{ /* sentinel */ }
131
101
};
132
102
133
103
static struct platform_driver meson8_ddr_clkc_driver = {
134
-
.probe = meson8_ddr_clkc_probe,
104
+
.probe = meson_clkc_mmio_probe,
135
105
.driver = {
136
106
.name = "meson8-ddr-clkc",
137
107
.of_match_table = meson8_ddr_clkc_match_table,
+354
-380
drivers/clk/meson/meson8b.c
+354
-380
drivers/clk/meson/meson8b.c
···
214
214
{ .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 },
215
215
};
216
216
217
-
static const struct pll_params_table hdmi_pll_params_table[] = {
217
+
static const struct pll_params_table meson8b_hdmi_pll_params_table[] = {
218
218
PLL_PARAMS(40, 1),
219
219
PLL_PARAMS(42, 1),
220
220
PLL_PARAMS(44, 1),
···
267
267
.shift = 29,
268
268
.width = 1,
269
269
},
270
-
.table = hdmi_pll_params_table,
270
+
.table = meson8b_hdmi_pll_params_table,
271
271
.init_regs = meson8b_hdmi_pll_init_regs,
272
272
.init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs),
273
273
},
···
670
670
},
671
671
};
672
672
673
-
static u32 mux_table_clk81[] = { 6, 5, 7 };
674
-
static struct clk_regmap meson8b_mpeg_clk_sel = {
673
+
/* clk81 is often referred as "mpeg_clk" */
674
+
static u32 meson8b_clk81_parents_val_table[] = { 6, 5, 7 };
675
+
static struct clk_regmap meson8b_clk81_sel = {
675
676
.data = &(struct clk_regmap_mux_data){
676
677
.offset = HHI_MPEG_CLK_CNTL,
677
678
.mask = 0x7,
678
679
.shift = 12,
679
-
.table = mux_table_clk81,
680
+
.table = meson8b_clk81_parents_val_table,
680
681
},
681
682
.hw.init = &(struct clk_init_data){
682
-
.name = "mpeg_clk_sel",
683
+
.name = "clk81_sel",
683
684
.ops = &clk_regmap_mux_ro_ops,
684
685
/*
685
686
* FIXME bits 14:12 selects from 8 possible parents:
···
696
695
},
697
696
};
698
697
699
-
static struct clk_regmap meson8b_mpeg_clk_div = {
698
+
static struct clk_regmap meson8b_clk81_div = {
700
699
.data = &(struct clk_regmap_div_data){
701
700
.offset = HHI_MPEG_CLK_CNTL,
702
701
.shift = 0,
703
702
.width = 7,
704
703
},
705
704
.hw.init = &(struct clk_init_data){
706
-
.name = "mpeg_clk_div",
705
+
.name = "clk81_div",
707
706
.ops = &clk_regmap_divider_ro_ops,
708
707
.parent_hws = (const struct clk_hw *[]) {
709
-
&meson8b_mpeg_clk_sel.hw
708
+
&meson8b_clk81_sel.hw
710
709
},
711
710
.num_parents = 1,
712
711
},
···
721
720
.name = "clk81",
722
721
.ops = &clk_regmap_gate_ops,
723
722
.parent_hws = (const struct clk_hw *[]) {
724
-
&meson8b_mpeg_clk_div.hw
723
+
&meson8b_clk81_div.hw
725
724
},
726
725
.num_parents = 1,
727
726
.flags = CLK_IS_CRITICAL,
···
775
774
},
776
775
};
777
776
778
-
static const struct clk_div_table cpu_scale_table[] = {
777
+
static const struct clk_div_table meson8b_cpu_scale_div_table[] = {
779
778
{ .val = 1, .div = 4 },
780
779
{ .val = 2, .div = 6 },
781
780
{ .val = 3, .div = 8 },
···
792
791
.offset = HHI_SYS_CPU_CLK_CNTL1,
793
792
.shift = 20,
794
793
.width = 10,
795
-
.table = cpu_scale_table,
794
+
.table = meson8b_cpu_scale_div_table,
796
795
.flags = CLK_DIVIDER_ALLOW_ZERO,
797
796
},
798
797
.hw.init = &(struct clk_init_data){
···
806
805
},
807
806
};
808
807
809
-
static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
808
+
static u32 meson8b_cpu_scale_out_parents_val_table[] = { 0, 1, 3 };
810
809
static struct clk_regmap meson8b_cpu_scale_out_sel = {
811
810
.data = &(struct clk_regmap_mux_data){
812
811
.offset = HHI_SYS_CPU_CLK_CNTL0,
813
812
.mask = 0x3,
814
813
.shift = 2,
815
-
.table = mux_table_cpu_scale_out_sel,
814
+
.table = meson8b_cpu_scale_out_parents_val_table,
816
815
},
817
816
.hw.init = &(struct clk_init_data){
818
817
.name = "cpu_scale_out_sel",
···
894
893
},
895
894
};
896
895
897
-
static struct clk_regmap meson8b_nand_clk_gate = {
896
+
static struct clk_regmap meson8b_nand_clk = {
898
897
.data = &(struct clk_regmap_gate_data){
899
898
.offset = HHI_NAND_CLK_CNTL,
900
899
.bit_idx = 8,
901
900
},
902
901
.hw.init = &(struct clk_init_data){
903
-
.name = "nand_clk_gate",
902
+
.name = "nand_clk",
904
903
.ops = &clk_regmap_gate_ops,
905
904
.parent_hws = (const struct clk_hw *[]) {
906
905
&meson8b_nand_clk_div.hw
···
1001
1000
},
1002
1001
};
1003
1002
1004
-
static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
1005
-
static struct clk_regmap meson8b_apb_clk_sel = {
1003
+
static u32 meson8b_cpu_if_parents_val_table[] = { 1, 2, 3, 4, 5, 6, 7 };
1004
+
static const struct clk_hw *meson8b_cpu_if_parents[] = {
1005
+
&meson8b_cpu_clk_div2.hw,
1006
+
&meson8b_cpu_clk_div3.hw,
1007
+
&meson8b_cpu_clk_div4.hw,
1008
+
&meson8b_cpu_clk_div5.hw,
1009
+
&meson8b_cpu_clk_div6.hw,
1010
+
&meson8b_cpu_clk_div7.hw,
1011
+
&meson8b_cpu_clk_div8.hw,
1012
+
};
1013
+
1014
+
static struct clk_regmap meson8b_apb_sel = {
1006
1015
.data = &(struct clk_regmap_mux_data){
1007
1016
.offset = HHI_SYS_CPU_CLK_CNTL1,
1008
1017
.mask = 0x7,
1009
1018
.shift = 3,
1010
-
.table = mux_table_apb,
1019
+
.table = meson8b_cpu_if_parents_val_table,
1011
1020
},
1012
1021
.hw.init = &(struct clk_init_data){
1013
-
.name = "apb_clk_sel",
1022
+
.name = "apb_sel",
1014
1023
.ops = &clk_regmap_mux_ops,
1015
-
.parent_hws = (const struct clk_hw *[]) {
1016
-
&meson8b_cpu_clk_div2.hw,
1017
-
&meson8b_cpu_clk_div3.hw,
1018
-
&meson8b_cpu_clk_div4.hw,
1019
-
&meson8b_cpu_clk_div5.hw,
1020
-
&meson8b_cpu_clk_div6.hw,
1021
-
&meson8b_cpu_clk_div7.hw,
1022
-
&meson8b_cpu_clk_div8.hw,
1023
-
},
1024
-
.num_parents = 7,
1024
+
.parent_hws = meson8b_cpu_if_parents,
1025
+
.num_parents = ARRAY_SIZE(meson8b_cpu_if_parents),
1025
1026
},
1026
1027
};
1027
1028
1028
-
static struct clk_regmap meson8b_apb_clk_gate = {
1029
+
static struct clk_regmap meson8b_apb = {
1029
1030
.data = &(struct clk_regmap_gate_data){
1030
1031
.offset = HHI_SYS_CPU_CLK_CNTL1,
1031
1032
.bit_idx = 16,
1032
1033
.flags = CLK_GATE_SET_TO_DISABLE,
1033
1034
},
1034
1035
.hw.init = &(struct clk_init_data){
1035
-
.name = "apb_clk_dis",
1036
+
.name = "apb",
1036
1037
.ops = &clk_regmap_gate_ro_ops,
1037
1038
.parent_hws = (const struct clk_hw *[]) {
1038
-
&meson8b_apb_clk_sel.hw
1039
+
&meson8b_apb_sel.hw
1039
1040
},
1040
1041
.num_parents = 1,
1041
1042
.flags = CLK_SET_RATE_PARENT,
1042
1043
},
1043
1044
};
1044
1045
1045
-
static struct clk_regmap meson8b_periph_clk_sel = {
1046
+
static struct clk_regmap meson8b_periph_sel = {
1046
1047
.data = &(struct clk_regmap_mux_data){
1047
1048
.offset = HHI_SYS_CPU_CLK_CNTL1,
1048
1049
.mask = 0x7,
1049
1050
.shift = 6,
1050
1051
},
1051
1052
.hw.init = &(struct clk_init_data){
1052
-
.name = "periph_clk_sel",
1053
+
.name = "periph_sel",
1053
1054
.ops = &clk_regmap_mux_ops,
1054
-
.parent_hws = (const struct clk_hw *[]) {
1055
-
&meson8b_cpu_clk_div2.hw,
1056
-
&meson8b_cpu_clk_div3.hw,
1057
-
&meson8b_cpu_clk_div4.hw,
1058
-
&meson8b_cpu_clk_div5.hw,
1059
-
&meson8b_cpu_clk_div6.hw,
1060
-
&meson8b_cpu_clk_div7.hw,
1061
-
&meson8b_cpu_clk_div8.hw,
1062
-
},
1063
-
.num_parents = 7,
1055
+
.parent_hws = meson8b_cpu_if_parents,
1056
+
.num_parents = ARRAY_SIZE(meson8b_cpu_if_parents),
1064
1057
},
1065
1058
};
1066
1059
1067
-
static struct clk_regmap meson8b_periph_clk_gate = {
1060
+
static struct clk_regmap meson8b_periph = {
1068
1061
.data = &(struct clk_regmap_gate_data){
1069
1062
.offset = HHI_SYS_CPU_CLK_CNTL1,
1070
1063
.bit_idx = 17,
1071
1064
.flags = CLK_GATE_SET_TO_DISABLE,
1072
1065
},
1073
1066
.hw.init = &(struct clk_init_data){
1074
-
.name = "periph_clk_dis",
1067
+
.name = "periph",
1075
1068
.ops = &clk_regmap_gate_ro_ops,
1076
1069
.parent_hws = (const struct clk_hw *[]) {
1077
-
&meson8b_periph_clk_sel.hw
1070
+
&meson8b_periph_sel.hw
1078
1071
},
1079
1072
.num_parents = 1,
1080
1073
.flags = CLK_SET_RATE_PARENT,
1081
1074
},
1082
1075
};
1083
1076
1084
-
static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
1085
-
static struct clk_regmap meson8b_axi_clk_sel = {
1077
+
static struct clk_regmap meson8b_axi_sel = {
1086
1078
.data = &(struct clk_regmap_mux_data){
1087
1079
.offset = HHI_SYS_CPU_CLK_CNTL1,
1088
1080
.mask = 0x7,
1089
1081
.shift = 9,
1090
-
.table = mux_table_axi,
1082
+
.table = meson8b_cpu_if_parents_val_table,
1091
1083
},
1092
1084
.hw.init = &(struct clk_init_data){
1093
-
.name = "axi_clk_sel",
1085
+
.name = "axi_sel",
1094
1086
.ops = &clk_regmap_mux_ops,
1095
-
.parent_hws = (const struct clk_hw *[]) {
1096
-
&meson8b_cpu_clk_div2.hw,
1097
-
&meson8b_cpu_clk_div3.hw,
1098
-
&meson8b_cpu_clk_div4.hw,
1099
-
&meson8b_cpu_clk_div5.hw,
1100
-
&meson8b_cpu_clk_div6.hw,
1101
-
&meson8b_cpu_clk_div7.hw,
1102
-
&meson8b_cpu_clk_div8.hw,
1103
-
},
1104
-
.num_parents = 7,
1087
+
.parent_hws = meson8b_cpu_if_parents,
1088
+
.num_parents = ARRAY_SIZE(meson8b_cpu_if_parents),
1105
1089
},
1106
1090
};
1107
1091
1108
-
static struct clk_regmap meson8b_axi_clk_gate = {
1092
+
static struct clk_regmap meson8b_axi = {
1109
1093
.data = &(struct clk_regmap_gate_data){
1110
1094
.offset = HHI_SYS_CPU_CLK_CNTL1,
1111
1095
.bit_idx = 18,
1112
1096
.flags = CLK_GATE_SET_TO_DISABLE,
1113
1097
},
1114
1098
.hw.init = &(struct clk_init_data){
1115
-
.name = "axi_clk_dis",
1099
+
.name = "axi",
1116
1100
.ops = &clk_regmap_gate_ro_ops,
1117
1101
.parent_hws = (const struct clk_hw *[]) {
1118
-
&meson8b_axi_clk_sel.hw
1102
+
&meson8b_axi_sel.hw
1119
1103
},
1120
1104
.num_parents = 1,
1121
1105
.flags = CLK_SET_RATE_PARENT,
1122
1106
},
1123
1107
};
1124
1108
1125
-
static struct clk_regmap meson8b_l2_dram_clk_sel = {
1109
+
static struct clk_regmap meson8b_l2_dram_sel = {
1126
1110
.data = &(struct clk_regmap_mux_data){
1127
1111
.offset = HHI_SYS_CPU_CLK_CNTL1,
1128
1112
.mask = 0x7,
1129
1113
.shift = 12,
1130
1114
},
1131
1115
.hw.init = &(struct clk_init_data){
1132
-
.name = "l2_dram_clk_sel",
1116
+
.name = "l2_dram_sel",
1133
1117
.ops = &clk_regmap_mux_ops,
1134
-
.parent_hws = (const struct clk_hw *[]) {
1135
-
&meson8b_cpu_clk_div2.hw,
1136
-
&meson8b_cpu_clk_div3.hw,
1137
-
&meson8b_cpu_clk_div4.hw,
1138
-
&meson8b_cpu_clk_div5.hw,
1139
-
&meson8b_cpu_clk_div6.hw,
1140
-
&meson8b_cpu_clk_div7.hw,
1141
-
&meson8b_cpu_clk_div8.hw,
1142
-
},
1143
-
.num_parents = 7,
1118
+
.parent_hws = meson8b_cpu_if_parents,
1119
+
.num_parents = ARRAY_SIZE(meson8b_cpu_if_parents),
1144
1120
},
1145
1121
};
1146
1122
1147
-
static struct clk_regmap meson8b_l2_dram_clk_gate = {
1123
+
static struct clk_regmap meson8b_l2_dram = {
1148
1124
.data = &(struct clk_regmap_gate_data){
1149
1125
.offset = HHI_SYS_CPU_CLK_CNTL1,
1150
1126
.bit_idx = 19,
1151
1127
.flags = CLK_GATE_SET_TO_DISABLE,
1152
1128
},
1153
1129
.hw.init = &(struct clk_init_data){
1154
-
.name = "l2_dram_clk_dis",
1130
+
.name = "l2_dram",
1155
1131
.ops = &clk_regmap_gate_ro_ops,
1156
1132
.parent_hws = (const struct clk_hw *[]) {
1157
-
&meson8b_l2_dram_clk_sel.hw
1133
+
&meson8b_l2_dram_sel.hw
1158
1134
},
1159
1135
.num_parents = 1,
1160
1136
.flags = CLK_SET_RATE_PARENT,
···
1264
1286
},
1265
1287
};
1266
1288
1267
-
static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1289
+
static const struct clk_hw *meson8b_vclk_parents[] = {
1268
1290
&meson8b_vid_pll_final_div.hw,
1269
1291
&meson8b_fclk_div4.hw,
1270
1292
&meson8b_fclk_div3.hw,
···
1283
1305
.hw.init = &(struct clk_init_data){
1284
1306
.name = "vclk_in_sel",
1285
1307
.ops = &clk_regmap_mux_ops,
1286
-
.parent_hws = meson8b_vclk_mux_parent_hws,
1287
-
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1308
+
.parent_hws = meson8b_vclk_parents,
1309
+
.num_parents = ARRAY_SIZE(meson8b_vclk_parents),
1288
1310
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1289
1311
},
1290
1312
};
···
1321
1343
},
1322
1344
};
1323
1345
1324
-
static struct clk_regmap meson8b_vclk_div1_gate = {
1346
+
static struct clk_regmap meson8b_vclk_div1 = {
1325
1347
.data = &(struct clk_regmap_gate_data){
1326
1348
.offset = HHI_VID_CLK_CNTL,
1327
1349
.bit_idx = 0,
1328
1350
},
1329
1351
.hw.init = &(struct clk_init_data){
1330
-
.name = "vclk_div1_en",
1352
+
.name = "vclk_div1",
1331
1353
.ops = &clk_regmap_gate_ops,
1332
1354
.parent_hws = (const struct clk_hw *[]) {
1333
1355
&meson8b_vclk_en.hw
···
1341
1363
.mult = 1,
1342
1364
.div = 2,
1343
1365
.hw.init = &(struct clk_init_data){
1344
-
.name = "vclk_div2",
1366
+
.name = "vclk_div2_div",
1345
1367
.ops = &clk_fixed_factor_ops,
1346
1368
.parent_hws = (const struct clk_hw *[]) {
1347
1369
&meson8b_vclk_en.hw
···
1351
1373
}
1352
1374
};
1353
1375
1354
-
static struct clk_regmap meson8b_vclk_div2_div_gate = {
1376
+
static struct clk_regmap meson8b_vclk_div2 = {
1355
1377
.data = &(struct clk_regmap_gate_data){
1356
1378
.offset = HHI_VID_CLK_CNTL,
1357
1379
.bit_idx = 1,
1358
1380
},
1359
1381
.hw.init = &(struct clk_init_data){
1360
-
.name = "vclk_div2_en",
1382
+
.name = "vclk_div2",
1361
1383
.ops = &clk_regmap_gate_ops,
1362
1384
.parent_hws = (const struct clk_hw *[]) {
1363
1385
&meson8b_vclk_div2_div.hw
···
1371
1393
.mult = 1,
1372
1394
.div = 4,
1373
1395
.hw.init = &(struct clk_init_data){
1374
-
.name = "vclk_div4",
1396
+
.name = "vclk_div4_div",
1375
1397
.ops = &clk_fixed_factor_ops,
1376
1398
.parent_hws = (const struct clk_hw *[]) {
1377
1399
&meson8b_vclk_en.hw
···
1381
1403
}
1382
1404
};
1383
1405
1384
-
static struct clk_regmap meson8b_vclk_div4_div_gate = {
1406
+
static struct clk_regmap meson8b_vclk_div4 = {
1385
1407
.data = &(struct clk_regmap_gate_data){
1386
1408
.offset = HHI_VID_CLK_CNTL,
1387
1409
.bit_idx = 2,
1388
1410
},
1389
1411
.hw.init = &(struct clk_init_data){
1390
-
.name = "vclk_div4_en",
1412
+
.name = "vclk_div4",
1391
1413
.ops = &clk_regmap_gate_ops,
1392
1414
.parent_hws = (const struct clk_hw *[]) {
1393
1415
&meson8b_vclk_div4_div.hw
···
1401
1423
.mult = 1,
1402
1424
.div = 6,
1403
1425
.hw.init = &(struct clk_init_data){
1404
-
.name = "vclk_div6",
1426
+
.name = "vclk_div6_div",
1405
1427
.ops = &clk_fixed_factor_ops,
1406
1428
.parent_hws = (const struct clk_hw *[]) {
1407
1429
&meson8b_vclk_en.hw
···
1411
1433
}
1412
1434
};
1413
1435
1414
-
static struct clk_regmap meson8b_vclk_div6_div_gate = {
1436
+
static struct clk_regmap meson8b_vclk_div6 = {
1415
1437
.data = &(struct clk_regmap_gate_data){
1416
1438
.offset = HHI_VID_CLK_CNTL,
1417
1439
.bit_idx = 3,
1418
1440
},
1419
1441
.hw.init = &(struct clk_init_data){
1420
-
.name = "vclk_div6_en",
1442
+
.name = "vclk_div6",
1421
1443
.ops = &clk_regmap_gate_ops,
1422
1444
.parent_hws = (const struct clk_hw *[]) {
1423
1445
&meson8b_vclk_div6_div.hw
···
1431
1453
.mult = 1,
1432
1454
.div = 12,
1433
1455
.hw.init = &(struct clk_init_data){
1434
-
.name = "vclk_div12",
1456
+
.name = "vclk_div12_div",
1435
1457
.ops = &clk_fixed_factor_ops,
1436
1458
.parent_hws = (const struct clk_hw *[]) {
1437
1459
&meson8b_vclk_en.hw
···
1441
1463
}
1442
1464
};
1443
1465
1444
-
static struct clk_regmap meson8b_vclk_div12_div_gate = {
1466
+
static struct clk_regmap meson8b_vclk_div12 = {
1445
1467
.data = &(struct clk_regmap_gate_data){
1446
1468
.offset = HHI_VID_CLK_CNTL,
1447
1469
.bit_idx = 4,
1448
1470
},
1449
1471
.hw.init = &(struct clk_init_data){
1450
-
.name = "vclk_div12_en",
1472
+
.name = "vclk_div12",
1451
1473
.ops = &clk_regmap_gate_ops,
1452
1474
.parent_hws = (const struct clk_hw *[]) {
1453
1475
&meson8b_vclk_div12_div.hw
···
1466
1488
.hw.init = &(struct clk_init_data){
1467
1489
.name = "vclk2_in_sel",
1468
1490
.ops = &clk_regmap_mux_ops,
1469
-
.parent_hws = meson8b_vclk_mux_parent_hws,
1470
-
.num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1491
+
.parent_hws = meson8b_vclk_parents,
1492
+
.num_parents = ARRAY_SIZE(meson8b_vclk_parents),
1471
1493
.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1472
1494
},
1473
1495
};
1474
1496
1475
-
static struct clk_regmap meson8b_vclk2_clk_in_en = {
1497
+
static struct clk_regmap meson8b_vclk2_in_en = {
1476
1498
.data = &(struct clk_regmap_gate_data){
1477
1499
.offset = HHI_VIID_CLK_DIV,
1478
1500
.bit_idx = 16,
···
1488
1510
},
1489
1511
};
1490
1512
1491
-
static struct clk_regmap meson8b_vclk2_clk_en = {
1513
+
static struct clk_regmap meson8b_vclk2_en = {
1492
1514
.data = &(struct clk_regmap_gate_data){
1493
1515
.offset = HHI_VIID_CLK_DIV,
1494
1516
.bit_idx = 19,
···
1497
1519
.name = "vclk2_en",
1498
1520
.ops = &clk_regmap_gate_ops,
1499
1521
.parent_hws = (const struct clk_hw *[]) {
1500
-
&meson8b_vclk2_clk_in_en.hw
1522
+
&meson8b_vclk2_in_en.hw
1501
1523
},
1502
1524
.num_parents = 1,
1503
1525
.flags = CLK_SET_RATE_PARENT,
1504
1526
},
1505
1527
};
1506
1528
1507
-
static struct clk_regmap meson8b_vclk2_div1_gate = {
1529
+
static struct clk_regmap meson8b_vclk2_div1 = {
1508
1530
.data = &(struct clk_regmap_gate_data){
1509
1531
.offset = HHI_VIID_CLK_DIV,
1510
1532
.bit_idx = 0,
1511
1533
},
1512
1534
.hw.init = &(struct clk_init_data){
1513
-
.name = "vclk2_div1_en",
1535
+
.name = "vclk2_div1",
1514
1536
.ops = &clk_regmap_gate_ops,
1515
1537
.parent_hws = (const struct clk_hw *[]) {
1516
-
&meson8b_vclk2_clk_en.hw
1538
+
&meson8b_vclk2_en.hw
1517
1539
},
1518
1540
.num_parents = 1,
1519
1541
.flags = CLK_SET_RATE_PARENT,
···
1524
1546
.mult = 1,
1525
1547
.div = 2,
1526
1548
.hw.init = &(struct clk_init_data){
1527
-
.name = "vclk2_div2",
1549
+
.name = "vclk2_div2_div",
1528
1550
.ops = &clk_fixed_factor_ops,
1529
1551
.parent_hws = (const struct clk_hw *[]) {
1530
-
&meson8b_vclk2_clk_en.hw
1552
+
&meson8b_vclk2_en.hw
1531
1553
},
1532
1554
.num_parents = 1,
1533
1555
.flags = CLK_SET_RATE_PARENT,
1534
1556
}
1535
1557
};
1536
1558
1537
-
static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1559
+
static struct clk_regmap meson8b_vclk2_div2 = {
1538
1560
.data = &(struct clk_regmap_gate_data){
1539
1561
.offset = HHI_VIID_CLK_DIV,
1540
1562
.bit_idx = 1,
1541
1563
},
1542
1564
.hw.init = &(struct clk_init_data){
1543
-
.name = "vclk2_div2_en",
1565
+
.name = "vclk2_div2",
1544
1566
.ops = &clk_regmap_gate_ops,
1545
1567
.parent_hws = (const struct clk_hw *[]) {
1546
1568
&meson8b_vclk2_div2_div.hw
···
1554
1576
.mult = 1,
1555
1577
.div = 4,
1556
1578
.hw.init = &(struct clk_init_data){
1557
-
.name = "vclk2_div4",
1579
+
.name = "vclk2_div4_div",
1558
1580
.ops = &clk_fixed_factor_ops,
1559
1581
.parent_hws = (const struct clk_hw *[]) {
1560
-
&meson8b_vclk2_clk_en.hw
1582
+
&meson8b_vclk2_en.hw
1561
1583
},
1562
1584
.num_parents = 1,
1563
1585
.flags = CLK_SET_RATE_PARENT,
1564
1586
}
1565
1587
};
1566
1588
1567
-
static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1589
+
static struct clk_regmap meson8b_vclk2_div4 = {
1568
1590
.data = &(struct clk_regmap_gate_data){
1569
1591
.offset = HHI_VIID_CLK_DIV,
1570
1592
.bit_idx = 2,
1571
1593
},
1572
1594
.hw.init = &(struct clk_init_data){
1573
-
.name = "vclk2_div4_en",
1595
+
.name = "vclk2_div4",
1574
1596
.ops = &clk_regmap_gate_ops,
1575
1597
.parent_hws = (const struct clk_hw *[]) {
1576
1598
&meson8b_vclk2_div4_div.hw
···
1584
1606
.mult = 1,
1585
1607
.div = 6,
1586
1608
.hw.init = &(struct clk_init_data){
1587
-
.name = "vclk2_div6",
1609
+
.name = "vclk2_div6_div",
1588
1610
.ops = &clk_fixed_factor_ops,
1589
1611
.parent_hws = (const struct clk_hw *[]) {
1590
-
&meson8b_vclk2_clk_en.hw
1612
+
&meson8b_vclk2_en.hw
1591
1613
},
1592
1614
.num_parents = 1,
1593
1615
.flags = CLK_SET_RATE_PARENT,
1594
1616
}
1595
1617
};
1596
1618
1597
-
static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1619
+
static struct clk_regmap meson8b_vclk2_div6 = {
1598
1620
.data = &(struct clk_regmap_gate_data){
1599
1621
.offset = HHI_VIID_CLK_DIV,
1600
1622
.bit_idx = 3,
1601
1623
},
1602
1624
.hw.init = &(struct clk_init_data){
1603
-
.name = "vclk2_div6_en",
1625
+
.name = "vclk2_div6",
1604
1626
.ops = &clk_regmap_gate_ops,
1605
1627
.parent_hws = (const struct clk_hw *[]) {
1606
1628
&meson8b_vclk2_div6_div.hw
···
1614
1636
.mult = 1,
1615
1637
.div = 12,
1616
1638
.hw.init = &(struct clk_init_data){
1617
-
.name = "vclk2_div12",
1639
+
.name = "vclk2_div12_div",
1618
1640
.ops = &clk_fixed_factor_ops,
1619
1641
.parent_hws = (const struct clk_hw *[]) {
1620
-
&meson8b_vclk2_clk_en.hw
1642
+
&meson8b_vclk2_en.hw
1621
1643
},
1622
1644
.num_parents = 1,
1623
1645
.flags = CLK_SET_RATE_PARENT,
1624
1646
}
1625
1647
};
1626
1648
1627
-
static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1649
+
static struct clk_regmap meson8b_vclk2_div12 = {
1628
1650
.data = &(struct clk_regmap_gate_data){
1629
1651
.offset = HHI_VIID_CLK_DIV,
1630
1652
.bit_idx = 4,
1631
1653
},
1632
1654
.hw.init = &(struct clk_init_data){
1633
-
.name = "vclk2_div12_en",
1655
+
.name = "vclk2_div12",
1634
1656
.ops = &clk_regmap_gate_ops,
1635
1657
.parent_hws = (const struct clk_hw *[]) {
1636
1658
&meson8b_vclk2_div12_div.hw
···
1640
1662
},
1641
1663
};
1642
1664
1643
-
static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1644
-
&meson8b_vclk_div1_gate.hw,
1645
-
&meson8b_vclk_div2_div_gate.hw,
1646
-
&meson8b_vclk_div4_div_gate.hw,
1647
-
&meson8b_vclk_div6_div_gate.hw,
1648
-
&meson8b_vclk_div12_div_gate.hw,
1665
+
static const struct clk_hw *meson8b_vclk_enc_parents[] = {
1666
+
&meson8b_vclk_div1.hw,
1667
+
&meson8b_vclk_div2.hw,
1668
+
&meson8b_vclk_div4.hw,
1669
+
&meson8b_vclk_div6.hw,
1670
+
&meson8b_vclk_div12.hw,
1649
1671
};
1650
1672
1651
1673
static struct clk_regmap meson8b_cts_enct_sel = {
···
1657
1679
.hw.init = &(struct clk_init_data){
1658
1680
.name = "cts_enct_sel",
1659
1681
.ops = &clk_regmap_mux_ops,
1660
-
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
1661
-
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1682
+
.parent_hws = meson8b_vclk_enc_parents,
1683
+
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents),
1662
1684
.flags = CLK_SET_RATE_PARENT,
1663
1685
},
1664
1686
};
···
1688
1710
.hw.init = &(struct clk_init_data){
1689
1711
.name = "cts_encp_sel",
1690
1712
.ops = &clk_regmap_mux_ops,
1691
-
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
1692
-
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1713
+
.parent_hws = meson8b_vclk_enc_parents,
1714
+
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents),
1693
1715
.flags = CLK_SET_RATE_PARENT,
1694
1716
},
1695
1717
};
···
1719
1741
.hw.init = &(struct clk_init_data){
1720
1742
.name = "cts_enci_sel",
1721
1743
.ops = &clk_regmap_mux_ops,
1722
-
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
1723
-
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1744
+
.parent_hws = meson8b_vclk_enc_parents,
1745
+
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents),
1724
1746
.flags = CLK_SET_RATE_PARENT,
1725
1747
},
1726
1748
};
···
1750
1772
.hw.init = &(struct clk_init_data){
1751
1773
.name = "hdmi_tx_pixel_sel",
1752
1774
.ops = &clk_regmap_mux_ops,
1753
-
.parent_hws = meson8b_vclk_enc_mux_parent_hws,
1754
-
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1775
+
.parent_hws = meson8b_vclk_enc_parents,
1776
+
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents),
1755
1777
.flags = CLK_SET_RATE_PARENT,
1756
1778
},
1757
1779
};
···
1772
1794
},
1773
1795
};
1774
1796
1775
-
static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1776
-
&meson8b_vclk2_div1_gate.hw,
1777
-
&meson8b_vclk2_div2_div_gate.hw,
1778
-
&meson8b_vclk2_div4_div_gate.hw,
1779
-
&meson8b_vclk2_div6_div_gate.hw,
1780
-
&meson8b_vclk2_div12_div_gate.hw,
1781
-
};
1782
-
1783
1797
static struct clk_regmap meson8b_cts_encl_sel = {
1784
1798
.data = &(struct clk_regmap_mux_data){
1785
1799
.offset = HHI_VIID_CLK_DIV,
···
1781
1811
.hw.init = &(struct clk_init_data){
1782
1812
.name = "cts_encl_sel",
1783
1813
.ops = &clk_regmap_mux_ops,
1784
-
.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1785
-
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1814
+
.parent_hws = meson8b_vclk_enc_parents,
1815
+
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents),
1786
1816
.flags = CLK_SET_RATE_PARENT,
1787
1817
},
1788
1818
};
···
1812
1842
.hw.init = &(struct clk_init_data){
1813
1843
.name = "cts_vdac0_sel",
1814
1844
.ops = &clk_regmap_mux_ops,
1815
-
.parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1816
-
.num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1845
+
.parent_hws = meson8b_vclk_enc_parents,
1846
+
.num_parents = ARRAY_SIZE(meson8b_vclk_enc_parents),
1817
1847
.flags = CLK_SET_RATE_PARENT,
1818
1848
},
1819
1849
};
···
1896
1926
* CLK_SET_RATE_GATE is set.
1897
1927
* Meson8 only has mali_0 and no glitch-free mux.
1898
1928
*/
1899
-
static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
1929
+
static u32 meson8b_mali_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1930
+
static const struct clk_parent_data meson8b_mali_parents[] = {
1900
1931
{ .fw_name = "xtal", .name = "xtal", .index = -1, },
1901
1932
{ .hw = &meson8b_mpll2.hw, },
1902
1933
{ .hw = &meson8b_mpll1.hw, },
···
1907
1936
{ .hw = &meson8b_fclk_div5.hw, },
1908
1937
};
1909
1938
1910
-
static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1911
-
1912
1939
static struct clk_regmap meson8b_mali_0_sel = {
1913
1940
.data = &(struct clk_regmap_mux_data){
1914
1941
.offset = HHI_MALI_CLK_CNTL,
1915
1942
.mask = 0x7,
1916
1943
.shift = 9,
1917
-
.table = meson8b_mali_0_1_mux_table,
1944
+
.table = meson8b_mali_parents_val_table,
1918
1945
},
1919
1946
.hw.init = &(struct clk_init_data){
1920
1947
.name = "mali_0_sel",
1921
1948
.ops = &clk_regmap_mux_ops,
1922
-
.parent_data = meson8b_mali_0_1_parent_data,
1923
-
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1949
+
.parent_data = meson8b_mali_parents,
1950
+
.num_parents = ARRAY_SIZE(meson8b_mali_parents),
1924
1951
/*
1925
1952
* Don't propagate rate changes up because the only changeable
1926
1953
* parents are mpll1 and mpll2 but we need those for audio and
···
1967
1998
.offset = HHI_MALI_CLK_CNTL,
1968
1999
.mask = 0x7,
1969
2000
.shift = 25,
1970
-
.table = meson8b_mali_0_1_mux_table,
2001
+
.table = meson8b_mali_parents_val_table,
1971
2002
},
1972
2003
.hw.init = &(struct clk_init_data){
1973
2004
.name = "mali_1_sel",
1974
2005
.ops = &clk_regmap_mux_ops,
1975
-
.parent_data = meson8b_mali_0_1_parent_data,
1976
-
.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
2006
+
.parent_data = meson8b_mali_parents,
2007
+
.num_parents = ARRAY_SIZE(meson8b_mali_parents),
1977
2008
/*
1978
2009
* Don't propagate rate changes up because the only changeable
1979
2010
* parents are mpll1 and mpll2 but we need those for audio and
···
2108
2139
},
2109
2140
};
2110
2141
2111
-
static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
2142
+
static const struct clk_hw *meson8b_vpu_parents[] = {
2112
2143
&meson8b_fclk_div4.hw,
2113
2144
&meson8b_fclk_div3.hw,
2114
2145
&meson8b_fclk_div5.hw,
2115
2146
&meson8b_fclk_div7.hw,
2116
-
};
2117
-
2118
-
static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
2119
-
&meson8b_fclk_div4.hw,
2120
-
&meson8b_fclk_div3.hw,
2121
-
&meson8b_fclk_div5.hw,
2122
-
&meson8m2_gp_pll.hw,
2123
2147
};
2124
2148
2125
2149
static struct clk_regmap meson8b_vpu_0_sel = {
···
2124
2162
.hw.init = &(struct clk_init_data){
2125
2163
.name = "vpu_0_sel",
2126
2164
.ops = &clk_regmap_mux_ops,
2127
-
.parent_hws = meson8b_vpu_0_1_parent_hws,
2128
-
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2165
+
.parent_hws = meson8b_vpu_parents,
2166
+
.num_parents = ARRAY_SIZE(meson8b_vpu_parents),
2129
2167
.flags = CLK_SET_RATE_PARENT,
2130
2168
},
2169
+
};
2170
+
2171
+
static const struct clk_hw *mmeson8m2_vpu_parents[] = {
2172
+
&meson8b_fclk_div4.hw,
2173
+
&meson8b_fclk_div3.hw,
2174
+
&meson8b_fclk_div5.hw,
2175
+
&meson8m2_gp_pll.hw,
2131
2176
};
2132
2177
2133
2178
static struct clk_regmap meson8m2_vpu_0_sel = {
···
2146
2177
.hw.init = &(struct clk_init_data){
2147
2178
.name = "vpu_0_sel",
2148
2179
.ops = &clk_regmap_mux_ops,
2149
-
.parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2150
-
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2180
+
.parent_hws = mmeson8m2_vpu_parents,
2181
+
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_parents),
2151
2182
.flags = CLK_SET_RATE_PARENT,
2152
2183
},
2153
2184
};
···
2202
2233
.hw.init = &(struct clk_init_data){
2203
2234
.name = "vpu_1_sel",
2204
2235
.ops = &clk_regmap_mux_ops,
2205
-
.parent_hws = meson8b_vpu_0_1_parent_hws,
2206
-
.num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2236
+
.parent_hws = meson8b_vpu_parents,
2237
+
.num_parents = ARRAY_SIZE(meson8b_vpu_parents),
2207
2238
.flags = CLK_SET_RATE_PARENT,
2208
2239
},
2209
2240
};
···
2217
2248
.hw.init = &(struct clk_init_data){
2218
2249
.name = "vpu_1_sel",
2219
2250
.ops = &clk_regmap_mux_ops,
2220
-
.parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2221
-
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2251
+
.parent_hws = mmeson8m2_vpu_parents,
2252
+
.num_parents = ARRAY_SIZE(mmeson8m2_vpu_parents),
2222
2253
.flags = CLK_SET_RATE_PARENT,
2223
2254
},
2224
2255
};
···
2290
2321
},
2291
2322
};
2292
2323
2293
-
static const struct clk_hw *meson8b_vdec_parent_hws[] = {
2324
+
static const struct clk_hw *meson8b_vdec_parents[] = {
2294
2325
&meson8b_fclk_div4.hw,
2295
2326
&meson8b_fclk_div3.hw,
2296
2327
&meson8b_fclk_div5.hw,
···
2309
2340
.hw.init = &(struct clk_init_data){
2310
2341
.name = "vdec_1_sel",
2311
2342
.ops = &clk_regmap_mux_ops,
2312
-
.parent_hws = meson8b_vdec_parent_hws,
2313
-
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2343
+
.parent_hws = meson8b_vdec_parents,
2344
+
.num_parents = ARRAY_SIZE(meson8b_vdec_parents),
2314
2345
.flags = CLK_SET_RATE_PARENT,
2315
2346
},
2316
2347
};
···
2412
2443
.hw.init = &(struct clk_init_data){
2413
2444
.name = "vdec_hcodec_sel",
2414
2445
.ops = &clk_regmap_mux_ops,
2415
-
.parent_hws = meson8b_vdec_parent_hws,
2416
-
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2446
+
.parent_hws = meson8b_vdec_parents,
2447
+
.num_parents = ARRAY_SIZE(meson8b_vdec_parents),
2417
2448
.flags = CLK_SET_RATE_PARENT,
2418
2449
},
2419
2450
};
···
2462
2493
.hw.init = &(struct clk_init_data){
2463
2494
.name = "vdec_2_sel",
2464
2495
.ops = &clk_regmap_mux_ops,
2465
-
.parent_hws = meson8b_vdec_parent_hws,
2466
-
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2496
+
.parent_hws = meson8b_vdec_parents,
2497
+
.num_parents = ARRAY_SIZE(meson8b_vdec_parents),
2467
2498
.flags = CLK_SET_RATE_PARENT,
2468
2499
},
2469
2500
};
···
2512
2543
.hw.init = &(struct clk_init_data){
2513
2544
.name = "vdec_hevc_sel",
2514
2545
.ops = &clk_regmap_mux_ops,
2515
-
.parent_hws = meson8b_vdec_parent_hws,
2516
-
.num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2546
+
.parent_hws = meson8b_vdec_parents,
2547
+
.num_parents = ARRAY_SIZE(meson8b_vdec_parents),
2517
2548
.flags = CLK_SET_RATE_PARENT,
2518
2549
},
2519
2550
};
···
2572
2603
};
2573
2604
2574
2605
/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2575
-
static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2606
+
static u32 meson8b_cts_mclk_parents_val_table[] = { 1, 2, 3 };
2607
+
static const struct clk_hw *meson8b_cts_mclk_parents[] = {
2576
2608
&meson8b_mpll0.hw,
2577
2609
&meson8b_mpll1.hw,
2578
2610
&meson8b_mpll2.hw
2579
2611
};
2580
-
2581
-
static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2582
2612
2583
2613
static struct clk_regmap meson8b_cts_amclk_sel = {
2584
2614
.data = &(struct clk_regmap_mux_data){
2585
2615
.offset = HHI_AUD_CLK_CNTL,
2586
2616
.mask = 0x3,
2587
2617
.shift = 9,
2588
-
.table = meson8b_cts_amclk_mux_table,
2618
+
.table = meson8b_cts_mclk_parents_val_table,
2589
2619
.flags = CLK_MUX_ROUND_CLOSEST,
2590
2620
},
2591
2621
.hw.init = &(struct clk_init_data){
2592
2622
.name = "cts_amclk_sel",
2593
2623
.ops = &clk_regmap_mux_ops,
2594
-
.parent_hws = meson8b_cts_amclk_parent_hws,
2595
-
.num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2624
+
.parent_hws = meson8b_cts_mclk_parents,
2625
+
.num_parents = ARRAY_SIZE(meson8b_cts_mclk_parents),
2596
2626
},
2597
2627
};
2598
2628
···
2629
2661
},
2630
2662
};
2631
2663
2632
-
/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2633
-
static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2634
-
&meson8b_mpll0.hw,
2635
-
&meson8b_mpll1.hw,
2636
-
&meson8b_mpll2.hw
2637
-
};
2638
-
2639
-
static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2640
-
2641
2664
static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2642
2665
.data = &(struct clk_regmap_mux_data){
2643
2666
.offset = HHI_AUD_CLK_CNTL2,
2644
2667
.mask = 0x3,
2645
2668
.shift = 25,
2646
-
.table = meson8b_cts_mclk_i958_mux_table,
2669
+
.table = meson8b_cts_mclk_parents_val_table,
2647
2670
.flags = CLK_MUX_ROUND_CLOSEST,
2648
2671
},
2649
2672
.hw.init = &(struct clk_init_data) {
2650
2673
.name = "cts_mclk_i958_sel",
2651
2674
.ops = &clk_regmap_mux_ops,
2652
-
.parent_hws = meson8b_cts_mclk_i958_parent_hws,
2653
-
.num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2675
+
.parent_hws = meson8b_cts_mclk_parents,
2676
+
.num_parents = ARRAY_SIZE(meson8b_cts_mclk_parents),
2654
2677
},
2655
2678
};
2656
2679
···
2701
2742
},
2702
2743
};
2703
2744
2704
-
#define MESON_GATE(_name, _reg, _bit) \
2705
-
MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2745
+
static const struct clk_parent_data meson8b_pclk_parents = { .hw = &meson8b_clk81.hw };
2706
2746
2707
-
/* Everything Else (EE) domain gates */
2747
+
#define MESON8B_PCLK(_name, _reg, _bit, _flags) \
2748
+
MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags)
2708
2749
2709
-
static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2710
-
static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2711
-
static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2712
-
static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2713
-
static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2714
-
static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2715
-
static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2716
-
static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2717
-
static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2718
-
static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2719
-
static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2720
-
static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2721
-
static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2722
-
static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2723
-
static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2724
-
static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2725
-
static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2726
-
static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2727
-
static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2750
+
/*
2751
+
* Everything Else (EE) domain gates
2752
+
*
2753
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
2754
+
* Users are encouraged to test without it and submit changes to:
2755
+
* - remove the flag if not necessary
2756
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
2757
+
* if appropriate.
2758
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
2759
+
* for a particular clock.
2760
+
*/
2761
+
static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED);
2762
+
static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED);
2763
+
static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED);
2764
+
static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED);
2765
+
static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED);
2766
+
static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED);
2767
+
static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED);
2768
+
static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED);
2769
+
static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED);
2770
+
static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED);
2771
+
static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED);
2772
+
static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED);
2773
+
static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED);
2774
+
static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED);
2775
+
static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED);
2776
+
static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED);
2777
+
static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED);
2778
+
static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED);
2779
+
static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED);
2728
2780
2729
-
static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2730
-
static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2731
-
static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2732
-
static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2733
-
static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2734
-
static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2735
-
static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2736
-
static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2737
-
static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2738
-
static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2739
-
static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2740
-
static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2741
-
static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2742
-
static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2743
-
static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2744
-
static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2745
-
static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2781
+
static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED);
2782
+
static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED);
2783
+
static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED);
2784
+
static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED);
2785
+
static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED);
2786
+
static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED);
2787
+
static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED);
2788
+
static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED);
2789
+
static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED);
2790
+
static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED);
2791
+
static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED);
2792
+
static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED);
2793
+
static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED);
2794
+
static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED);
2795
+
static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED);
2796
+
static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED);
2797
+
static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED);
2746
2798
2747
-
static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2748
-
static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2749
-
static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2750
-
static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2751
-
static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2752
-
static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2753
-
static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2754
-
static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2755
-
static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2756
-
static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2757
-
static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2758
-
static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2759
-
static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2799
+
static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED);
2800
+
static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED);
2801
+
static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED);
2802
+
static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED);
2803
+
static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED);
2804
+
static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED);
2805
+
static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED);
2806
+
static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED);
2807
+
static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED);
2808
+
static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED);
2809
+
static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED);
2810
+
static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED);
2811
+
static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED);
2760
2812
2761
-
static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2762
-
static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2763
-
static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2764
-
static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2765
-
static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2766
-
static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2767
-
static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2768
-
static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2769
-
static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2770
-
static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2771
-
static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2772
-
static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2773
-
static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2774
-
static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2775
-
static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2776
-
static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2813
+
static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED);
2814
+
static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED);
2815
+
static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED);
2816
+
static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED);
2817
+
static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED);
2818
+
static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED);
2819
+
static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED);
2820
+
static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED);
2821
+
static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED);
2822
+
static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED);
2823
+
static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED);
2824
+
static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED);
2825
+
static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED);
2826
+
static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED);
2827
+
static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED);
2828
+
static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED);
2777
2829
2778
2830
/* AIU gates */
2779
-
#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2780
-
MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2831
+
static const struct clk_parent_data meson8b_aiu_glue_parents = { .hw = &meson8b_aiu.hw };
2832
+
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6,
2833
+
&meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED);
2781
2834
2782
-
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2783
-
static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2784
-
static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2785
-
static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2786
-
static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2787
-
static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2788
-
static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2789
-
static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2835
+
static const struct clk_parent_data meson8b_aiu_pclk_parents = { .hw = &meson8b_aiu_glue.hw };
2836
+
#define MESON8B_AIU_PCLK(_name, _bit, _flags) \
2837
+
MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags)
2838
+
2839
+
static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED);
2840
+
static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED);
2841
+
static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED);
2842
+
static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED);
2843
+
static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED);
2844
+
static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED);
2845
+
static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED);
2790
2846
2791
2847
/* Always On (AO) domain gates */
2792
2848
2793
-
static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2794
-
static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2795
-
static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2796
-
static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2849
+
static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED);
2850
+
static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED);
2851
+
static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED);
2852
+
static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED);
2797
2853
2798
2854
static struct clk_hw *meson8_hw_clks[] = {
2799
-
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2800
-
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2801
-
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2802
-
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2803
-
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2804
-
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2805
-
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2806
-
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2807
-
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2808
-
[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2809
-
[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2810
-
[CLKID_CLK81] = &meson8b_clk81.hw,
2855
+
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2856
+
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2857
+
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2858
+
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2859
+
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2860
+
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2861
+
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2862
+
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2863
+
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2864
+
[CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw,
2865
+
[CLKID_MPEG_DIV] = &meson8b_clk81_div.hw,
2866
+
[CLKID_CLK81] = &meson8b_clk81.hw,
2811
2867
[CLKID_DDR] = &meson8b_ddr.hw,
2812
2868
[CLKID_DOS] = &meson8b_dos.hw,
2813
2869
[CLKID_ISA] = &meson8b_isa.hw,
···
2919
2945
[CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2920
2946
[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2921
2947
[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2922
-
[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2948
+
[CLKID_NAND_CLK] = &meson8b_nand_clk.hw,
2923
2949
[CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2924
2950
[CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2925
2951
[CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
···
2930
2956
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2931
2957
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2932
2958
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2933
-
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2934
-
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
2935
-
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2936
-
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2937
-
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2938
-
[CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2939
-
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2940
-
[CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2959
+
[CLKID_APB_SEL] = &meson8b_apb_sel.hw,
2960
+
[CLKID_APB] = &meson8b_apb.hw,
2961
+
[CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw,
2962
+
[CLKID_PERIPH] = &meson8b_periph.hw,
2963
+
[CLKID_AXI_SEL] = &meson8b_axi_sel.hw,
2964
+
[CLKID_AXI] = &meson8b_axi.hw,
2965
+
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw,
2966
+
[CLKID_L2_DRAM] = &meson8b_l2_dram.hw,
2941
2967
[CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2942
2968
[CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2943
2969
[CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
···
2948
2974
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2949
2975
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2950
2976
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
2951
-
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2977
+
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw,
2952
2978
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2953
-
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2979
+
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw,
2954
2980
[CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2955
-
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2981
+
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw,
2956
2982
[CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2957
-
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2983
+
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw,
2958
2984
[CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2959
-
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2985
+
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw,
2960
2986
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2961
-
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2962
-
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
2963
-
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2987
+
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw,
2988
+
[CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw,
2989
+
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw,
2964
2990
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2965
-
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2991
+
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw,
2966
2992
[CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2967
-
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2993
+
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw,
2968
2994
[CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2969
-
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2995
+
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw,
2970
2996
[CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2971
-
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2997
+
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw,
2972
2998
[CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2973
2999
[CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2974
3000
[CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
···
3015
3041
};
3016
3042
3017
3043
static struct clk_hw *meson8b_hw_clks[] = {
3018
-
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3019
-
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3020
-
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3021
-
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3022
-
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3023
-
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3024
-
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3025
-
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3026
-
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3027
-
[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3028
-
[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3029
-
[CLKID_CLK81] = &meson8b_clk81.hw,
3044
+
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3045
+
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3046
+
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3047
+
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3048
+
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3049
+
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3050
+
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3051
+
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3052
+
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3053
+
[CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw,
3054
+
[CLKID_MPEG_DIV] = &meson8b_clk81_div.hw,
3055
+
[CLKID_CLK81] = &meson8b_clk81.hw,
3030
3056
[CLKID_DDR] = &meson8b_ddr.hw,
3031
3057
[CLKID_DOS] = &meson8b_dos.hw,
3032
3058
[CLKID_ISA] = &meson8b_isa.hw,
···
3123
3149
[CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
3124
3150
[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
3125
3151
[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
3126
-
[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
3152
+
[CLKID_NAND_CLK] = &meson8b_nand_clk.hw,
3127
3153
[CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
3128
3154
[CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
3129
3155
[CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
···
3134
3160
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
3135
3161
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
3136
3162
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
3137
-
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
3138
-
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
3139
-
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
3140
-
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
3141
-
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
3142
-
[CLKID_AXI] = &meson8b_axi_clk_gate.hw,
3143
-
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
3144
-
[CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
3163
+
[CLKID_APB_SEL] = &meson8b_apb_sel.hw,
3164
+
[CLKID_APB] = &meson8b_apb.hw,
3165
+
[CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw,
3166
+
[CLKID_PERIPH] = &meson8b_periph.hw,
3167
+
[CLKID_AXI_SEL] = &meson8b_axi_sel.hw,
3168
+
[CLKID_AXI] = &meson8b_axi.hw,
3169
+
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw,
3170
+
[CLKID_L2_DRAM] = &meson8b_l2_dram.hw,
3145
3171
[CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
3146
3172
[CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
3147
3173
[CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
···
3152
3178
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
3153
3179
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3154
3180
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
3155
-
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3181
+
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw,
3156
3182
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
3157
-
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3183
+
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw,
3158
3184
[CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
3159
-
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3185
+
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw,
3160
3186
[CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
3161
-
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3187
+
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw,
3162
3188
[CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
3163
-
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3189
+
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw,
3164
3190
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
3165
-
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3166
-
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
3167
-
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3191
+
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw,
3192
+
[CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw,
3193
+
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw,
3168
3194
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
3169
-
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
3195
+
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw,
3170
3196
[CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
3171
-
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
3197
+
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw,
3172
3198
[CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
3173
-
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
3199
+
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw,
3174
3200
[CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
3175
-
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
3201
+
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw,
3176
3202
[CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
3177
3203
[CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
3178
3204
[CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
···
3230
3256
};
3231
3257
3232
3258
static struct clk_hw *meson8m2_hw_clks[] = {
3233
-
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3234
-
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3235
-
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3236
-
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3237
-
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3238
-
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3239
-
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3240
-
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3241
-
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3242
-
[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3243
-
[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3244
-
[CLKID_CLK81] = &meson8b_clk81.hw,
3259
+
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3260
+
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3261
+
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3262
+
[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3263
+
[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3264
+
[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3265
+
[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3266
+
[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3267
+
[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3268
+
[CLKID_MPEG_SEL] = &meson8b_clk81_sel.hw,
3269
+
[CLKID_MPEG_DIV] = &meson8b_clk81_div.hw,
3270
+
[CLKID_CLK81] = &meson8b_clk81.hw,
3245
3271
[CLKID_DDR] = &meson8b_ddr.hw,
3246
3272
[CLKID_DOS] = &meson8b_dos.hw,
3247
3273
[CLKID_ISA] = &meson8b_isa.hw,
···
3338
3364
[CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
3339
3365
[CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
3340
3366
[CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
3341
-
[CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
3367
+
[CLKID_NAND_CLK] = &meson8b_nand_clk.hw,
3342
3368
[CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
3343
3369
[CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
3344
3370
[CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
···
3349
3375
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
3350
3376
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
3351
3377
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
3352
-
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
3353
-
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
3354
-
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
3355
-
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
3356
-
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
3357
-
[CLKID_AXI] = &meson8b_axi_clk_gate.hw,
3358
-
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
3359
-
[CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
3378
+
[CLKID_APB_SEL] = &meson8b_apb_sel.hw,
3379
+
[CLKID_APB] = &meson8b_apb.hw,
3380
+
[CLKID_PERIPH_SEL] = &meson8b_periph_sel.hw,
3381
+
[CLKID_PERIPH] = &meson8b_periph.hw,
3382
+
[CLKID_AXI_SEL] = &meson8b_axi_sel.hw,
3383
+
[CLKID_AXI] = &meson8b_axi.hw,
3384
+
[CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_sel.hw,
3385
+
[CLKID_L2_DRAM] = &meson8b_l2_dram.hw,
3360
3386
[CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
3361
3387
[CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
3362
3388
[CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
···
3367
3393
[CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
3368
3394
[CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
3369
3395
[CLKID_VCLK_EN] = &meson8b_vclk_en.hw,
3370
-
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
3396
+
[CLKID_VCLK_DIV1] = &meson8b_vclk_div1.hw,
3371
3397
[CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
3372
-
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
3398
+
[CLKID_VCLK_DIV2] = &meson8b_vclk_div2.hw,
3373
3399
[CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
3374
-
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3400
+
[CLKID_VCLK_DIV4] = &meson8b_vclk_div4.hw,
3375
3401
[CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
3376
-
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
3402
+
[CLKID_VCLK_DIV6] = &meson8b_vclk_div6.hw,
3377
3403
[CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
3378
-
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
3404
+
[CLKID_VCLK_DIV12] = &meson8b_vclk_div12.hw,
3379
3405
[CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
3380
-
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
3381
-
[CLKID_VCLK2_EN] = &meson8b_vclk2_clk_en.hw,
3382
-
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3406
+
[CLKID_VCLK2_IN_EN] = &meson8b_vclk2_in_en.hw,
3407
+
[CLKID_VCLK2_EN] = &meson8b_vclk2_en.hw,
3408
+
[CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1.hw,
3383
3409
[CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
3384
-
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
3410
+
[CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2.hw,
3385
3411
[CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
3386
-
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
3412
+
[CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4.hw,
3387
3413
[CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
3388
-
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
3414
+
[CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6.hw,
3389
3415
[CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
3390
-
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
3416
+
[CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12.hw,
3391
3417
[CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
3392
3418
[CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
3393
3419
[CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
+349
-809
drivers/clk/meson/s4-peripherals.c
+349
-809
drivers/clk/meson/s4-peripherals.c
···
62
62
#define CLKCTRL_PWM_CLK_IJ_CTRL 0x190
63
63
#define CLKCTRL_DEMOD_CLK_CTRL 0x200
64
64
65
+
#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
66
+
MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
67
+
68
+
#define S4_COMP_DIV(_name, _reg, _shift, _width) \
69
+
MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
70
+
71
+
#define S4_COMP_GATE(_name, _reg, _bit) \
72
+
MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
73
+
65
74
static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
66
75
.data = &(struct clk_regmap_gate_data){
67
76
.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
···
191
182
};
192
183
193
184
/* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */
194
-
static u32 mux_table_sys_ab_clk_sel[] = { 0, 1, 2, 3, 4, 6, 7 };
195
-
static const struct clk_parent_data sys_ab_clk_parent_data[] = {
185
+
static u32 s4_sysclk_parents_val_table[] = { 0, 1, 2, 3, 4, 6, 7 };
186
+
static const struct clk_parent_data s4_sysclk_parents[] = {
196
187
{ .fw_name = "xtal" },
197
188
{ .fw_name = "fclk_div2" },
198
189
{ .fw_name = "fclk_div3" },
···
214
205
.offset = CLKCTRL_SYS_CLK_CTRL0,
215
206
.mask = 0x7,
216
207
.shift = 26,
217
-
.table = mux_table_sys_ab_clk_sel,
208
+
.table = s4_sysclk_parents_val_table,
218
209
},
219
210
.hw.init = &(struct clk_init_data){
220
211
.name = "sysclk_b_sel",
221
212
.ops = &clk_regmap_mux_ro_ops,
222
-
.parent_data = sys_ab_clk_parent_data,
223
-
.num_parents = ARRAY_SIZE(sys_ab_clk_parent_data),
213
+
.parent_data = s4_sysclk_parents,
214
+
.num_parents = ARRAY_SIZE(s4_sysclk_parents),
224
215
},
225
216
};
226
217
···
260
251
.offset = CLKCTRL_SYS_CLK_CTRL0,
261
252
.mask = 0x7,
262
253
.shift = 10,
263
-
.table = mux_table_sys_ab_clk_sel,
254
+
.table = s4_sysclk_parents_val_table,
264
255
},
265
256
.hw.init = &(struct clk_init_data){
266
257
.name = "sysclk_a_sel",
267
258
.ops = &clk_regmap_mux_ro_ops,
268
-
.parent_data = sys_ab_clk_parent_data,
269
-
.num_parents = ARRAY_SIZE(sys_ab_clk_parent_data),
259
+
.parent_data = s4_sysclk_parents,
260
+
.num_parents = ARRAY_SIZE(s4_sysclk_parents),
270
261
},
271
262
};
272
263
···
532
523
},
533
524
};
534
525
535
-
static const struct clk_parent_data s4_sc_parent_data[] = {
526
+
static const struct clk_parent_data s4_sc_clk_parents[] = {
536
527
{ .fw_name = "fclk_div4" },
537
528
{ .fw_name = "fclk_div3" },
538
529
{ .fw_name = "fclk_div5" },
539
530
{ .fw_name = "xtal", }
540
531
};
541
532
542
-
static struct clk_regmap s4_sc_clk_mux = {
533
+
static struct clk_regmap s4_sc_clk_sel = {
543
534
.data = &(struct clk_regmap_mux_data){
544
535
.offset = CLKCTRL_SC_CLK_CTRL,
545
536
.mask = 0x3,
546
537
.shift = 9,
547
538
},
548
539
.hw.init = &(struct clk_init_data) {
549
-
.name = "sc_clk_mux",
540
+
.name = "sc_clk_sel",
550
541
.ops = &clk_regmap_mux_ops,
551
-
.parent_data = s4_sc_parent_data,
552
-
.num_parents = ARRAY_SIZE(s4_sc_parent_data),
542
+
.parent_data = s4_sc_clk_parents,
543
+
.num_parents = ARRAY_SIZE(s4_sc_clk_parents),
553
544
.flags = CLK_SET_RATE_PARENT,
554
545
},
555
546
};
···
564
555
.name = "sc_clk_div",
565
556
.ops = &clk_regmap_divider_ops,
566
557
.parent_hws = (const struct clk_hw *[]) {
567
-
&s4_sc_clk_mux.hw
558
+
&s4_sc_clk_sel.hw
568
559
},
569
560
.num_parents = 1,
570
561
.flags = CLK_SET_RATE_PARENT,
571
562
},
572
563
};
573
564
574
-
static struct clk_regmap s4_sc_clk_gate = {
565
+
static struct clk_regmap s4_sc_clk = {
575
566
.data = &(struct clk_regmap_gate_data){
576
567
.offset = CLKCTRL_SC_CLK_CTRL,
577
568
.bit_idx = 8,
578
569
},
579
570
.hw.init = &(struct clk_init_data){
580
-
.name = "sc_clk_gate",
571
+
.name = "sc_clk",
581
572
.ops = &clk_regmap_gate_ops,
582
573
.parent_hws = (const struct clk_hw *[]) {
583
574
&s4_sc_clk_div.hw
···
587
578
},
588
579
};
589
580
590
-
static struct clk_regmap s4_12_24M_clk_gate = {
581
+
static struct clk_regmap s4_12_24M = {
591
582
.data = &(struct clk_regmap_gate_data){
592
583
.offset = CLKCTRL_CLK12_24_CTRL,
593
584
.bit_idx = 11,
594
585
},
595
586
.hw.init = &(struct clk_init_data) {
596
-
.name = "12_24m_gate",
587
+
.name = "12_24M",
597
588
.ops = &clk_regmap_gate_ops,
598
589
.parent_data = (const struct clk_parent_data []) {
599
590
{ .fw_name = "xtal", }
···
602
593
},
603
594
};
604
595
605
-
static struct clk_fixed_factor s4_12M_clk_div = {
596
+
static struct clk_fixed_factor s4_12M_div = {
606
597
.mult = 1,
607
598
.div = 2,
608
599
.hw.init = &(struct clk_init_data){
609
-
.name = "12M",
600
+
.name = "12M_div",
610
601
.ops = &clk_fixed_factor_ops,
611
602
.parent_hws = (const struct clk_hw *[]) {
612
-
&s4_12_24M_clk_gate.hw
603
+
&s4_12_24M.hw
613
604
},
614
605
.num_parents = 1,
615
606
.flags = CLK_SET_RATE_PARENT,
616
607
},
617
608
};
618
609
619
-
static struct clk_regmap s4_12_24M_clk = {
610
+
static struct clk_regmap s4_12_24M_sel = {
620
611
.data = &(struct clk_regmap_mux_data){
621
612
.offset = CLKCTRL_CLK12_24_CTRL,
622
613
.mask = 0x1,
623
614
.shift = 10,
624
615
},
625
616
.hw.init = &(struct clk_init_data) {
626
-
.name = "12_24m",
617
+
.name = "12_24M_sel",
627
618
.ops = &clk_regmap_mux_ops,
628
619
.parent_hws = (const struct clk_hw *[]) {
629
-
&s4_12_24M_clk_gate.hw,
630
-
&s4_12M_clk_div.hw,
620
+
&s4_12_24M.hw,
621
+
&s4_12M_div.hw,
631
622
},
632
623
.num_parents = 2,
633
624
.flags = CLK_SET_RATE_PARENT,
···
696
687
},
697
688
};
698
689
699
-
static const struct clk_parent_data s4_vclk_parent_data[] = {
690
+
static const struct clk_parent_data s4_vclk_parents[] = {
700
691
{ .hw = &s4_vid_pll.hw },
701
692
{ .fw_name = "gp0_pll", },
702
693
{ .fw_name = "hifi_pll", },
···
716
707
.hw.init = &(struct clk_init_data){
717
708
.name = "vclk_sel",
718
709
.ops = &clk_regmap_mux_ops,
719
-
.parent_data = s4_vclk_parent_data,
720
-
.num_parents = ARRAY_SIZE(s4_vclk_parent_data),
710
+
.parent_data = s4_vclk_parents,
711
+
.num_parents = ARRAY_SIZE(s4_vclk_parents),
721
712
.flags = 0,
722
713
},
723
714
};
···
731
722
.hw.init = &(struct clk_init_data){
732
723
.name = "vclk2_sel",
733
724
.ops = &clk_regmap_mux_ops,
734
-
.parent_data = s4_vclk_parent_data,
735
-
.num_parents = ARRAY_SIZE(s4_vclk_parent_data),
725
+
.parent_data = s4_vclk_parents,
726
+
.num_parents = ARRAY_SIZE(s4_vclk_parents),
736
727
.flags = 0,
737
728
},
738
729
};
···
1080
1071
};
1081
1072
1082
1073
/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */
1083
-
static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1084
-
static const struct clk_hw *s4_cts_parent_hws[] = {
1074
+
static u32 s4_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1075
+
static const struct clk_hw *s4_cts_parents[] = {
1085
1076
&s4_vclk_div1.hw,
1086
1077
&s4_vclk_div2.hw,
1087
1078
&s4_vclk_div4.hw,
···
1099
1090
.offset = CLKCTRL_VID_CLK_DIV,
1100
1091
.mask = 0xf,
1101
1092
.shift = 28,
1102
-
.table = mux_table_cts_sel,
1093
+
.table = s4_cts_parents_val_table,
1103
1094
},
1104
1095
.hw.init = &(struct clk_init_data){
1105
1096
.name = "cts_enci_sel",
1106
1097
.ops = &clk_regmap_mux_ops,
1107
-
.parent_hws = s4_cts_parent_hws,
1108
-
.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
1098
+
.parent_hws = s4_cts_parents,
1099
+
.num_parents = ARRAY_SIZE(s4_cts_parents),
1109
1100
.flags = CLK_SET_RATE_PARENT,
1110
1101
},
1111
1102
};
···
1115
1106
.offset = CLKCTRL_VID_CLK_DIV,
1116
1107
.mask = 0xf,
1117
1108
.shift = 20,
1118
-
.table = mux_table_cts_sel,
1109
+
.table = s4_cts_parents_val_table,
1119
1110
},
1120
1111
.hw.init = &(struct clk_init_data){
1121
1112
.name = "cts_encp_sel",
1122
1113
.ops = &clk_regmap_mux_ops,
1123
-
.parent_hws = s4_cts_parent_hws,
1124
-
.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
1114
+
.parent_hws = s4_cts_parents,
1115
+
.num_parents = ARRAY_SIZE(s4_cts_parents),
1125
1116
.flags = CLK_SET_RATE_PARENT,
1126
1117
},
1127
1118
};
···
1131
1122
.offset = CLKCTRL_VIID_CLK_DIV,
1132
1123
.mask = 0xf,
1133
1124
.shift = 28,
1134
-
.table = mux_table_cts_sel,
1125
+
.table = s4_cts_parents_val_table,
1135
1126
},
1136
1127
.hw.init = &(struct clk_init_data){
1137
1128
.name = "cts_vdac_sel",
1138
1129
.ops = &clk_regmap_mux_ops,
1139
-
.parent_hws = s4_cts_parent_hws,
1140
-
.num_parents = ARRAY_SIZE(s4_cts_parent_hws),
1130
+
.parent_hws = s4_cts_parents,
1131
+
.num_parents = ARRAY_SIZE(s4_cts_parents),
1141
1132
.flags = CLK_SET_RATE_PARENT,
1142
1133
},
1143
1134
};
1144
1135
1145
1136
/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */
1146
-
static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1147
-
static const struct clk_hw *s4_cts_hdmi_tx_parent_hws[] = {
1137
+
static u32 s4_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1138
+
static const struct clk_hw *s4_hdmi_tx_parents[] = {
1148
1139
&s4_vclk_div1.hw,
1149
1140
&s4_vclk_div2.hw,
1150
1141
&s4_vclk_div4.hw,
···
1162
1153
.offset = CLKCTRL_HDMI_CLK_CTRL,
1163
1154
.mask = 0xf,
1164
1155
.shift = 16,
1165
-
.table = mux_table_hdmi_tx_sel,
1156
+
.table = s4_hdmi_tx_parents_val_table,
1166
1157
},
1167
1158
.hw.init = &(struct clk_init_data){
1168
1159
.name = "hdmi_tx_sel",
1169
1160
.ops = &clk_regmap_mux_ops,
1170
-
.parent_hws = s4_cts_hdmi_tx_parent_hws,
1171
-
.num_parents = ARRAY_SIZE(s4_cts_hdmi_tx_parent_hws),
1161
+
.parent_hws = s4_hdmi_tx_parents,
1162
+
.num_parents = ARRAY_SIZE(s4_hdmi_tx_parents),
1172
1163
.flags = CLK_SET_RATE_PARENT,
1173
1164
},
1174
1165
};
···
1238
1229
};
1239
1230
1240
1231
/* HDMI Clocks */
1241
-
static const struct clk_parent_data s4_hdmi_parent_data[] = {
1232
+
static const struct clk_parent_data s4_hdmi_parents[] = {
1242
1233
{ .fw_name = "xtal", },
1243
1234
{ .fw_name = "fclk_div4", },
1244
1235
{ .fw_name = "fclk_div3", },
···
1255
1246
.hw.init = &(struct clk_init_data){
1256
1247
.name = "hdmi_sel",
1257
1248
.ops = &clk_regmap_mux_ops,
1258
-
.parent_data = s4_hdmi_parent_data,
1259
-
.num_parents = ARRAY_SIZE(s4_hdmi_parent_data),
1249
+
.parent_data = s4_hdmi_parents,
1250
+
.num_parents = ARRAY_SIZE(s4_hdmi_parents),
1260
1251
.flags = CLK_SET_RATE_PARENT,
1261
1252
},
1262
1253
};
···
1307
1298
},
1308
1299
};
1309
1300
1310
-
static struct clk_regmap s4_ts_clk_gate = {
1301
+
static struct clk_regmap s4_ts_clk = {
1311
1302
.data = &(struct clk_regmap_gate_data){
1312
1303
.offset = CLKCTRL_TS_CLK_CTRL,
1313
1304
.bit_idx = 8,
···
1329
1320
* mux because it does top-to-bottom updates the each clock tree and
1330
1321
* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1331
1322
*/
1332
-
static const struct clk_parent_data s4_mali_0_1_parent_data[] = {
1323
+
static const struct clk_parent_data s4_mali_parents[] = {
1333
1324
{ .fw_name = "xtal", },
1334
1325
{ .fw_name = "gp0_pll", },
1335
1326
{ .fw_name = "hifi_pll", },
···
1349
1340
.hw.init = &(struct clk_init_data){
1350
1341
.name = "mali_0_sel",
1351
1342
.ops = &clk_regmap_mux_ops,
1352
-
.parent_data = s4_mali_0_1_parent_data,
1353
-
.num_parents = ARRAY_SIZE(s4_mali_0_1_parent_data),
1343
+
.parent_data = s4_mali_parents,
1344
+
.num_parents = ARRAY_SIZE(s4_mali_parents),
1354
1345
/*
1355
1346
* Don't request the parent to change the rate because
1356
1347
* all GPU frequencies can be derived from the fclk_*
···
1403
1394
.hw.init = &(struct clk_init_data){
1404
1395
.name = "mali_1_sel",
1405
1396
.ops = &clk_regmap_mux_ops,
1406
-
.parent_data = s4_mali_0_1_parent_data,
1407
-
.num_parents = ARRAY_SIZE(s4_mali_0_1_parent_data),
1397
+
.parent_data = s4_mali_parents,
1398
+
.num_parents = ARRAY_SIZE(s4_mali_parents),
1408
1399
.flags = 0,
1409
1400
},
1410
1401
};
···
1442
1433
},
1443
1434
};
1444
1435
1445
-
static const struct clk_hw *s4_mali_parent_hws[] = {
1446
-
&s4_mali_0.hw,
1447
-
&s4_mali_1.hw
1448
-
};
1449
-
1450
-
static struct clk_regmap s4_mali_mux = {
1436
+
static struct clk_regmap s4_mali_sel = {
1451
1437
.data = &(struct clk_regmap_mux_data){
1452
1438
.offset = CLKCTRL_MALI_CLK_CTRL,
1453
1439
.mask = 1,
1454
1440
.shift = 31,
1455
1441
},
1456
1442
.hw.init = &(struct clk_init_data){
1457
-
.name = "mali",
1443
+
.name = "mali_sel",
1458
1444
.ops = &clk_regmap_mux_ops,
1459
-
.parent_hws = s4_mali_parent_hws,
1445
+
.parent_hws = (const struct clk_hw *[]) {
1446
+
&s4_mali_0.hw,
1447
+
&s4_mali_1.hw,
1448
+
},
1460
1449
.num_parents = 2,
1461
1450
.flags = CLK_SET_RATE_PARENT,
1462
1451
},
1463
1452
};
1464
1453
1465
1454
/* VDEC clocks */
1466
-
static const struct clk_parent_data s4_dec_parent_data[] = {
1455
+
static const struct clk_parent_data s4_dec_parents[] = {
1467
1456
{ .fw_name = "fclk_div2p5", },
1468
1457
{ .fw_name = "fclk_div3", },
1469
1458
{ .fw_name = "fclk_div4", },
···
1472
1465
{ .fw_name = "xtal", }
1473
1466
};
1474
1467
1475
-
static struct clk_regmap s4_vdec_p0_mux = {
1468
+
static struct clk_regmap s4_vdec_p0_sel = {
1476
1469
.data = &(struct clk_regmap_mux_data){
1477
1470
.offset = CLKCTRL_VDEC_CLK_CTRL,
1478
1471
.mask = 0x7,
···
1480
1473
.flags = CLK_MUX_ROUND_CLOSEST,
1481
1474
},
1482
1475
.hw.init = &(struct clk_init_data) {
1483
-
.name = "vdec_p0_mux",
1476
+
.name = "vdec_p0_sel",
1484
1477
.ops = &clk_regmap_mux_ops,
1485
-
.parent_data = s4_dec_parent_data,
1486
-
.num_parents = ARRAY_SIZE(s4_dec_parent_data),
1478
+
.parent_data = s4_dec_parents,
1479
+
.num_parents = ARRAY_SIZE(s4_dec_parents),
1487
1480
.flags = 0,
1488
1481
},
1489
1482
};
···
1499
1492
.name = "vdec_p0_div",
1500
1493
.ops = &clk_regmap_divider_ops,
1501
1494
.parent_hws = (const struct clk_hw *[]) {
1502
-
&s4_vdec_p0_mux.hw
1495
+
&s4_vdec_p0_sel.hw
1503
1496
},
1504
1497
.num_parents = 1,
1505
1498
.flags = CLK_SET_RATE_PARENT,
···
1522
1515
},
1523
1516
};
1524
1517
1525
-
static struct clk_regmap s4_vdec_p1_mux = {
1518
+
static struct clk_regmap s4_vdec_p1_sel = {
1526
1519
.data = &(struct clk_regmap_mux_data){
1527
1520
.offset = CLKCTRL_VDEC3_CLK_CTRL,
1528
1521
.mask = 0x7,
···
1530
1523
.flags = CLK_MUX_ROUND_CLOSEST,
1531
1524
},
1532
1525
.hw.init = &(struct clk_init_data) {
1533
-
.name = "vdec_p1_mux",
1526
+
.name = "vdec_p1_sel",
1534
1527
.ops = &clk_regmap_mux_ops,
1535
-
.parent_data = s4_dec_parent_data,
1536
-
.num_parents = ARRAY_SIZE(s4_dec_parent_data),
1528
+
.parent_data = s4_dec_parents,
1529
+
.num_parents = ARRAY_SIZE(s4_dec_parents),
1537
1530
.flags = 0,
1538
1531
},
1539
1532
};
···
1549
1542
.name = "vdec_p1_div",
1550
1543
.ops = &clk_regmap_divider_ops,
1551
1544
.parent_hws = (const struct clk_hw *[]) {
1552
-
&s4_vdec_p1_mux.hw
1545
+
&s4_vdec_p1_sel.hw
1553
1546
},
1554
1547
.num_parents = 1,
1555
1548
.flags = CLK_SET_RATE_PARENT,
···
1572
1565
},
1573
1566
};
1574
1567
1575
-
static const struct clk_hw *s4_vdec_mux_parent_hws[] = {
1576
-
&s4_vdec_p0.hw,
1577
-
&s4_vdec_p1.hw
1578
-
};
1579
-
1580
-
static struct clk_regmap s4_vdec_mux = {
1568
+
static struct clk_regmap s4_vdec_sel = {
1581
1569
.data = &(struct clk_regmap_mux_data){
1582
1570
.offset = CLKCTRL_VDEC3_CLK_CTRL,
1583
1571
.mask = 0x1,
1584
1572
.shift = 15,
1585
1573
},
1586
1574
.hw.init = &(struct clk_init_data) {
1587
-
.name = "vdec_mux",
1575
+
.name = "vdec_sel",
1588
1576
.ops = &clk_regmap_mux_ops,
1589
-
.parent_hws = s4_vdec_mux_parent_hws,
1590
-
.num_parents = ARRAY_SIZE(s4_vdec_mux_parent_hws),
1577
+
.parent_hws = (const struct clk_hw *[]) {
1578
+
&s4_vdec_p0.hw,
1579
+
&s4_vdec_p1.hw,
1580
+
},
1581
+
.num_parents = 2,
1591
1582
.flags = CLK_SET_RATE_PARENT,
1592
1583
},
1593
1584
};
1594
1585
1595
-
static struct clk_regmap s4_hevcf_p0_mux = {
1586
+
static struct clk_regmap s4_hevcf_p0_sel = {
1596
1587
.data = &(struct clk_regmap_mux_data){
1597
1588
.offset = CLKCTRL_VDEC2_CLK_CTRL,
1598
1589
.mask = 0x7,
···
1598
1593
.flags = CLK_MUX_ROUND_CLOSEST,
1599
1594
},
1600
1595
.hw.init = &(struct clk_init_data) {
1601
-
.name = "hevcf_p0_mux",
1596
+
.name = "hevcf_p0_sel",
1602
1597
.ops = &clk_regmap_mux_ops,
1603
-
.parent_data = s4_dec_parent_data,
1604
-
.num_parents = ARRAY_SIZE(s4_dec_parent_data),
1598
+
.parent_data = s4_dec_parents,
1599
+
.num_parents = ARRAY_SIZE(s4_dec_parents),
1605
1600
.flags = 0,
1606
1601
},
1607
1602
};
···
1617
1612
.name = "hevcf_p0_div",
1618
1613
.ops = &clk_regmap_divider_ops,
1619
1614
.parent_hws = (const struct clk_hw *[]) {
1620
-
&s4_hevcf_p0_mux.hw
1615
+
&s4_hevcf_p0_sel.hw
1621
1616
},
1622
1617
.num_parents = 1,
1623
1618
.flags = CLK_SET_RATE_PARENT,
···
1630
1625
.bit_idx = 8,
1631
1626
},
1632
1627
.hw.init = &(struct clk_init_data){
1633
-
.name = "hevcf_p0_gate",
1628
+
.name = "hevcf_p0",
1634
1629
.ops = &clk_regmap_gate_ops,
1635
1630
.parent_hws = (const struct clk_hw *[]) {
1636
1631
&s4_hevcf_p0_div.hw
···
1640
1635
},
1641
1636
};
1642
1637
1643
-
static struct clk_regmap s4_hevcf_p1_mux = {
1638
+
static struct clk_regmap s4_hevcf_p1_sel = {
1644
1639
.data = &(struct clk_regmap_mux_data){
1645
1640
.offset = CLKCTRL_VDEC4_CLK_CTRL,
1646
1641
.mask = 0x7,
···
1648
1643
.flags = CLK_MUX_ROUND_CLOSEST,
1649
1644
},
1650
1645
.hw.init = &(struct clk_init_data) {
1651
-
.name = "hevcf_p1_mux",
1646
+
.name = "hevcf_p1_sel",
1652
1647
.ops = &clk_regmap_mux_ops,
1653
-
.parent_data = s4_dec_parent_data,
1654
-
.num_parents = ARRAY_SIZE(s4_dec_parent_data),
1648
+
.parent_data = s4_dec_parents,
1649
+
.num_parents = ARRAY_SIZE(s4_dec_parents),
1655
1650
.flags = 0,
1656
1651
},
1657
1652
};
···
1667
1662
.name = "hevcf_p1_div",
1668
1663
.ops = &clk_regmap_divider_ops,
1669
1664
.parent_hws = (const struct clk_hw *[]) {
1670
-
&s4_hevcf_p1_mux.hw
1665
+
&s4_hevcf_p1_sel.hw
1671
1666
},
1672
1667
.num_parents = 1,
1673
1668
.flags = CLK_SET_RATE_PARENT,
···
1690
1685
},
1691
1686
};
1692
1687
1693
-
static const struct clk_hw *s4_hevcf_mux_parent_hws[] = {
1694
-
&s4_hevcf_p0.hw,
1695
-
&s4_hevcf_p1.hw
1696
-
};
1697
-
1698
-
static struct clk_regmap s4_hevcf_mux = {
1688
+
static struct clk_regmap s4_hevcf_sel = {
1699
1689
.data = &(struct clk_regmap_mux_data){
1700
1690
.offset = CLKCTRL_VDEC4_CLK_CTRL,
1701
1691
.mask = 0x1,
1702
1692
.shift = 15,
1703
1693
},
1704
1694
.hw.init = &(struct clk_init_data) {
1705
-
.name = "hevcf",
1695
+
.name = "hevcf_sel",
1706
1696
.ops = &clk_regmap_mux_ops,
1707
-
.parent_hws = s4_hevcf_mux_parent_hws,
1708
-
.num_parents = ARRAY_SIZE(s4_hevcf_mux_parent_hws),
1697
+
.parent_hws = (const struct clk_hw *[]) {
1698
+
&s4_hevcf_p0.hw,
1699
+
&s4_hevcf_p1.hw,
1700
+
},
1701
+
.num_parents = 2,
1709
1702
.flags = CLK_SET_RATE_PARENT,
1710
1703
},
1711
1704
};
1712
1705
1713
1706
/* VPU Clock */
1714
-
static const struct clk_parent_data s4_vpu_parent_data[] = {
1707
+
static const struct clk_parent_data s4_vpu_parents[] = {
1715
1708
{ .fw_name = "fclk_div3", },
1716
1709
{ .fw_name = "fclk_div4", },
1717
1710
{ .fw_name = "fclk_div5", },
···
1729
1726
.hw.init = &(struct clk_init_data){
1730
1727
.name = "vpu_0_sel",
1731
1728
.ops = &clk_regmap_mux_ops,
1732
-
.parent_data = s4_vpu_parent_data,
1733
-
.num_parents = ARRAY_SIZE(s4_vpu_parent_data),
1729
+
.parent_data = s4_vpu_parents,
1730
+
.num_parents = ARRAY_SIZE(s4_vpu_parents),
1734
1731
.flags = 0,
1735
1732
},
1736
1733
};
···
1773
1770
.hw.init = &(struct clk_init_data){
1774
1771
.name = "vpu_1_sel",
1775
1772
.ops = &clk_regmap_mux_ops,
1776
-
.parent_data = s4_vpu_parent_data,
1777
-
.num_parents = ARRAY_SIZE(s4_vpu_parent_data),
1773
+
.parent_data = s4_vpu_parents,
1774
+
.num_parents = ARRAY_SIZE(s4_vpu_parents),
1778
1775
.flags = 0,
1779
1776
},
1780
1777
};
···
1826
1823
},
1827
1824
};
1828
1825
1829
-
static const struct clk_parent_data vpu_clkb_tmp_parent_data[] = {
1826
+
static const struct clk_parent_data vpu_clkb_tmp_parents[] = {
1830
1827
{ .hw = &s4_vpu.hw },
1831
1828
{ .fw_name = "fclk_div4", },
1832
1829
{ .fw_name = "fclk_div5", },
1833
1830
{ .fw_name = "fclk_div7", }
1834
1831
};
1835
1832
1836
-
static struct clk_regmap s4_vpu_clkb_tmp_mux = {
1833
+
static struct clk_regmap s4_vpu_clkb_tmp_sel = {
1837
1834
.data = &(struct clk_regmap_mux_data){
1838
1835
.offset = CLKCTRL_VPU_CLKB_CTRL,
1839
1836
.mask = 0x3,
1840
1837
.shift = 20,
1841
1838
},
1842
1839
.hw.init = &(struct clk_init_data) {
1843
-
.name = "vpu_clkb_tmp_mux",
1840
+
.name = "vpu_clkb_tmp_sel",
1844
1841
.ops = &clk_regmap_mux_ops,
1845
-
.parent_data = vpu_clkb_tmp_parent_data,
1846
-
.num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_data),
1842
+
.parent_data = vpu_clkb_tmp_parents,
1843
+
.num_parents = ARRAY_SIZE(vpu_clkb_tmp_parents),
1847
1844
.flags = CLK_SET_RATE_PARENT,
1848
1845
},
1849
1846
};
···
1858
1855
.name = "vpu_clkb_tmp_div",
1859
1856
.ops = &clk_regmap_divider_ops,
1860
1857
.parent_hws = (const struct clk_hw *[]) {
1861
-
&s4_vpu_clkb_tmp_mux.hw
1858
+
&s4_vpu_clkb_tmp_sel.hw
1862
1859
},
1863
1860
.num_parents = 1,
1864
1861
.flags = CLK_SET_RATE_PARENT,
···
1914
1911
},
1915
1912
};
1916
1913
1917
-
static const struct clk_parent_data s4_vpu_clkc_parent_data[] = {
1914
+
static const struct clk_parent_data s4_vpu_clkc_parents[] = {
1918
1915
{ .fw_name = "fclk_div4", },
1919
1916
{ .fw_name = "fclk_div3", },
1920
1917
{ .fw_name = "fclk_div5", },
···
1925
1922
{ .fw_name = "gp0_pll", },
1926
1923
};
1927
1924
1928
-
static struct clk_regmap s4_vpu_clkc_p0_mux = {
1925
+
static struct clk_regmap s4_vpu_clkc_p0_sel = {
1929
1926
.data = &(struct clk_regmap_mux_data){
1930
1927
.offset = CLKCTRL_VPU_CLKC_CTRL,
1931
1928
.mask = 0x7,
1932
1929
.shift = 9,
1933
1930
},
1934
1931
.hw.init = &(struct clk_init_data) {
1935
-
.name = "vpu_clkc_p0_mux",
1932
+
.name = "vpu_clkc_p0_sel",
1936
1933
.ops = &clk_regmap_mux_ops,
1937
-
.parent_data = s4_vpu_clkc_parent_data,
1938
-
.num_parents = ARRAY_SIZE(s4_vpu_clkc_parent_data),
1934
+
.parent_data = s4_vpu_clkc_parents,
1935
+
.num_parents = ARRAY_SIZE(s4_vpu_clkc_parents),
1939
1936
.flags = 0,
1940
1937
},
1941
1938
};
···
1950
1947
.name = "vpu_clkc_p0_div",
1951
1948
.ops = &clk_regmap_divider_ops,
1952
1949
.parent_hws = (const struct clk_hw *[]) {
1953
-
&s4_vpu_clkc_p0_mux.hw
1950
+
&s4_vpu_clkc_p0_sel.hw
1954
1951
},
1955
1952
.num_parents = 1,
1956
1953
.flags = CLK_SET_RATE_PARENT,
···
1973
1970
},
1974
1971
};
1975
1972
1976
-
static struct clk_regmap s4_vpu_clkc_p1_mux = {
1973
+
static struct clk_regmap s4_vpu_clkc_p1_sel = {
1977
1974
.data = &(struct clk_regmap_mux_data){
1978
1975
.offset = CLKCTRL_VPU_CLKC_CTRL,
1979
1976
.mask = 0x7,
1980
1977
.shift = 25,
1981
1978
},
1982
1979
.hw.init = &(struct clk_init_data) {
1983
-
.name = "vpu_clkc_p1_mux",
1980
+
.name = "vpu_clkc_p1_sel",
1984
1981
.ops = &clk_regmap_mux_ops,
1985
-
.parent_data = s4_vpu_clkc_parent_data,
1986
-
.num_parents = ARRAY_SIZE(s4_vpu_clkc_parent_data),
1982
+
.parent_data = s4_vpu_clkc_parents,
1983
+
.num_parents = ARRAY_SIZE(s4_vpu_clkc_parents),
1987
1984
.flags = 0,
1988
1985
},
1989
1986
};
···
1998
1995
.name = "vpu_clkc_p1_div",
1999
1996
.ops = &clk_regmap_divider_ops,
2000
1997
.parent_hws = (const struct clk_hw *[]) {
2001
-
&s4_vpu_clkc_p1_mux.hw
1998
+
&s4_vpu_clkc_p1_sel.hw
2002
1999
},
2003
2000
.num_parents = 1,
2004
2001
.flags = CLK_SET_RATE_PARENT,
···
2021
2018
},
2022
2019
};
2023
2020
2024
-
static const struct clk_hw *s4_vpu_mux_parent_hws[] = {
2025
-
&s4_vpu_clkc_p0.hw,
2026
-
&s4_vpu_clkc_p1.hw
2027
-
};
2028
-
2029
-
static struct clk_regmap s4_vpu_clkc_mux = {
2021
+
static struct clk_regmap s4_vpu_clkc_sel = {
2030
2022
.data = &(struct clk_regmap_mux_data){
2031
2023
.offset = CLKCTRL_VPU_CLKC_CTRL,
2032
2024
.mask = 0x1,
2033
2025
.shift = 31,
2034
2026
},
2035
2027
.hw.init = &(struct clk_init_data) {
2036
-
.name = "vpu_clkc_mux",
2028
+
.name = "vpu_clkc_sel",
2037
2029
.ops = &clk_regmap_mux_ops,
2038
-
.parent_hws = s4_vpu_mux_parent_hws,
2039
-
.num_parents = ARRAY_SIZE(s4_vpu_mux_parent_hws),
2030
+
.parent_hws = (const struct clk_hw *[]) {
2031
+
&s4_vpu_clkc_p0.hw,
2032
+
&s4_vpu_clkc_p1.hw,
2033
+
},
2034
+
.num_parents = 2,
2040
2035
.flags = CLK_SET_RATE_PARENT,
2041
2036
},
2042
2037
};
2043
2038
2044
2039
/* VAPB Clock */
2045
-
static const struct clk_parent_data s4_vapb_parent_data[] = {
2040
+
static const struct clk_parent_data s4_vapb_parents[] = {
2046
2041
{ .fw_name = "fclk_div4", },
2047
2042
{ .fw_name = "fclk_div3", },
2048
2043
{ .fw_name = "fclk_div5", },
···
2060
2059
.hw.init = &(struct clk_init_data){
2061
2060
.name = "vapb_0_sel",
2062
2061
.ops = &clk_regmap_mux_ops,
2063
-
.parent_data = s4_vapb_parent_data,
2064
-
.num_parents = ARRAY_SIZE(s4_vapb_parent_data),
2062
+
.parent_data = s4_vapb_parents,
2063
+
.num_parents = ARRAY_SIZE(s4_vapb_parents),
2065
2064
.flags = 0,
2066
2065
},
2067
2066
};
···
2108
2107
.hw.init = &(struct clk_init_data){
2109
2108
.name = "vapb_1_sel",
2110
2109
.ops = &clk_regmap_mux_ops,
2111
-
.parent_data = s4_vapb_parent_data,
2112
-
.num_parents = ARRAY_SIZE(s4_vapb_parent_data),
2110
+
.parent_data = s4_vapb_parents,
2111
+
.num_parents = ARRAY_SIZE(s4_vapb_parents),
2113
2112
.flags = 0,
2114
2113
},
2115
2114
};
···
2165
2164
},
2166
2165
};
2167
2166
2168
-
static struct clk_regmap s4_ge2d_gate = {
2167
+
static struct clk_regmap s4_ge2d = {
2169
2168
.data = &(struct clk_regmap_gate_data){
2170
2169
.offset = CLKCTRL_VAPBCLK_CTRL,
2171
2170
.bit_idx = 30,
2172
2171
},
2173
2172
.hw.init = &(struct clk_init_data) {
2174
-
.name = "ge2d_clk",
2173
+
.name = "ge2d",
2175
2174
.ops = &clk_regmap_gate_ops,
2176
2175
.parent_hws = (const struct clk_hw *[]) { &s4_vapb.hw },
2177
2176
.num_parents = 1,
···
2179
2178
},
2180
2179
};
2181
2180
2182
-
static const struct clk_parent_data s4_esmclk_parent_data[] = {
2181
+
static const struct clk_parent_data s4_hdcp22_esmclk_parents[] = {
2183
2182
{ .fw_name = "fclk_div7", },
2184
2183
{ .fw_name = "fclk_div4", },
2185
2184
{ .fw_name = "fclk_div3", },
2186
2185
{ .fw_name = "fclk_div5", },
2187
2186
};
2188
2187
2189
-
static struct clk_regmap s4_hdcp22_esmclk_mux = {
2188
+
static struct clk_regmap s4_hdcp22_esmclk_sel = {
2190
2189
.data = &(struct clk_regmap_mux_data){
2191
2190
.offset = CLKCTRL_HDCP22_CTRL,
2192
2191
.mask = 0x3,
2193
2192
.shift = 9,
2194
2193
},
2195
2194
.hw.init = &(struct clk_init_data) {
2196
-
.name = "hdcp22_esmclk_mux",
2195
+
.name = "hdcp22_esmclk_sel",
2197
2196
.ops = &clk_regmap_mux_ops,
2198
-
.parent_data = s4_esmclk_parent_data,
2199
-
.num_parents = ARRAY_SIZE(s4_esmclk_parent_data),
2197
+
.parent_data = s4_hdcp22_esmclk_parents,
2198
+
.num_parents = ARRAY_SIZE(s4_hdcp22_esmclk_parents),
2200
2199
.flags = CLK_SET_RATE_PARENT,
2201
2200
},
2202
2201
};
···
2211
2210
.name = "hdcp22_esmclk_div",
2212
2211
.ops = &clk_regmap_divider_ops,
2213
2212
.parent_hws = (const struct clk_hw *[]) {
2214
-
&s4_hdcp22_esmclk_mux.hw
2213
+
&s4_hdcp22_esmclk_sel.hw
2215
2214
},
2216
2215
.num_parents = 1,
2217
2216
.flags = CLK_SET_RATE_PARENT,
2218
2217
},
2219
2218
};
2220
2219
2221
-
static struct clk_regmap s4_hdcp22_esmclk_gate = {
2220
+
static struct clk_regmap s4_hdcp22_esmclk = {
2222
2221
.data = &(struct clk_regmap_gate_data){
2223
2222
.offset = CLKCTRL_HDCP22_CTRL,
2224
2223
.bit_idx = 8,
2225
2224
},
2226
2225
.hw.init = &(struct clk_init_data){
2227
-
.name = "hdcp22_esmclk_gate",
2226
+
.name = "hdcp22_esmclk",
2228
2227
.ops = &clk_regmap_gate_ops,
2229
2228
.parent_hws = (const struct clk_hw *[]) {
2230
2229
&s4_hdcp22_esmclk_div.hw
···
2234
2233
},
2235
2234
};
2236
2235
2237
-
static const struct clk_parent_data s4_skpclk_parent_data[] = {
2236
+
static const struct clk_parent_data s4_hdcp22_skpclk_parents[] = {
2238
2237
{ .fw_name = "xtal", },
2239
2238
{ .fw_name = "fclk_div4", },
2240
2239
{ .fw_name = "fclk_div3", },
2241
2240
{ .fw_name = "fclk_div5", },
2242
2241
};
2243
2242
2244
-
static struct clk_regmap s4_hdcp22_skpclk_mux = {
2243
+
static struct clk_regmap s4_hdcp22_skpclk_sel = {
2245
2244
.data = &(struct clk_regmap_mux_data){
2246
2245
.offset = CLKCTRL_HDCP22_CTRL,
2247
2246
.mask = 0x3,
2248
2247
.shift = 25,
2249
2248
},
2250
2249
.hw.init = &(struct clk_init_data) {
2251
-
.name = "hdcp22_skpclk_mux",
2250
+
.name = "hdcp22_skpclk_sel",
2252
2251
.ops = &clk_regmap_mux_ops,
2253
-
.parent_data = s4_skpclk_parent_data,
2254
-
.num_parents = ARRAY_SIZE(s4_skpclk_parent_data),
2252
+
.parent_data = s4_hdcp22_skpclk_parents,
2253
+
.num_parents = ARRAY_SIZE(s4_hdcp22_skpclk_parents),
2255
2254
.flags = CLK_SET_RATE_PARENT,
2256
2255
},
2257
2256
};
···
2266
2265
.name = "hdcp22_skpclk_div",
2267
2266
.ops = &clk_regmap_divider_ops,
2268
2267
.parent_hws = (const struct clk_hw *[]) {
2269
-
&s4_hdcp22_skpclk_mux.hw
2268
+
&s4_hdcp22_skpclk_sel.hw
2270
2269
},
2271
2270
.num_parents = 1,
2272
2271
.flags = CLK_SET_RATE_PARENT,
2273
2272
},
2274
2273
};
2275
2274
2276
-
static struct clk_regmap s4_hdcp22_skpclk_gate = {
2275
+
static struct clk_regmap s4_hdcp22_skpclk = {
2277
2276
.data = &(struct clk_regmap_gate_data){
2278
2277
.offset = CLKCTRL_HDCP22_CTRL,
2279
2278
.bit_idx = 24,
2280
2279
},
2281
2280
.hw.init = &(struct clk_init_data){
2282
-
.name = "hdcp22_skpclk_gate",
2281
+
.name = "hdcp22_skpclk",
2283
2282
.ops = &clk_regmap_gate_ops,
2284
2283
.parent_hws = (const struct clk_hw *[]) {
2285
2284
&s4_hdcp22_skpclk_div.hw
···
2289
2288
},
2290
2289
};
2291
2290
2292
-
static const struct clk_parent_data s4_vdin_parent_data[] = {
2291
+
static const struct clk_parent_data s4_vdin_parents[] = {
2293
2292
{ .fw_name = "xtal", },
2294
2293
{ .fw_name = "fclk_div4", },
2295
2294
{ .fw_name = "fclk_div3", },
···
2297
2296
{ .hw = &s4_vid_pll.hw }
2298
2297
};
2299
2298
2300
-
static struct clk_regmap s4_vdin_meas_mux = {
2299
+
static struct clk_regmap s4_vdin_meas_sel = {
2301
2300
.data = &(struct clk_regmap_mux_data){
2302
2301
.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2303
2302
.mask = 0x7,
2304
2303
.shift = 9,
2305
2304
},
2306
2305
.hw.init = &(struct clk_init_data) {
2307
-
.name = "vdin_meas_mux",
2306
+
.name = "vdin_meas_sel",
2308
2307
.ops = &clk_regmap_mux_ops,
2309
-
.parent_data = s4_vdin_parent_data,
2310
-
.num_parents = ARRAY_SIZE(s4_vdin_parent_data),
2308
+
.parent_data = s4_vdin_parents,
2309
+
.num_parents = ARRAY_SIZE(s4_vdin_parents),
2311
2310
.flags = CLK_SET_RATE_PARENT,
2312
2311
},
2313
2312
};
···
2322
2321
.name = "vdin_meas_div",
2323
2322
.ops = &clk_regmap_divider_ops,
2324
2323
.parent_hws = (const struct clk_hw *[]) {
2325
-
&s4_vdin_meas_mux.hw
2324
+
&s4_vdin_meas_sel.hw
2326
2325
},
2327
2326
.num_parents = 1,
2328
2327
.flags = CLK_SET_RATE_PARENT,
2329
2328
},
2330
2329
};
2331
2330
2332
-
static struct clk_regmap s4_vdin_meas_gate = {
2331
+
static struct clk_regmap s4_vdin_meas = {
2333
2332
.data = &(struct clk_regmap_gate_data){
2334
2333
.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2335
2334
.bit_idx = 8,
2336
2335
},
2337
2336
.hw.init = &(struct clk_init_data){
2338
-
.name = "vdin_meas_gate",
2337
+
.name = "vdin_meas",
2339
2338
.ops = &clk_regmap_gate_ops,
2340
2339
.parent_hws = (const struct clk_hw *[]) {
2341
2340
&s4_vdin_meas_div.hw
···
2346
2345
};
2347
2346
2348
2347
/* EMMC/NAND clock */
2349
-
static const struct clk_parent_data s4_sd_emmc_clk0_parent_data[] = {
2348
+
static const struct clk_parent_data s4_sd_emmc_clk0_parents[] = {
2350
2349
{ .fw_name = "xtal", },
2351
2350
{ .fw_name = "fclk_div2", },
2352
2351
{ .fw_name = "fclk_div3", },
···
2366
2365
.hw.init = &(struct clk_init_data) {
2367
2366
.name = "sd_emmc_c_clk0_sel",
2368
2367
.ops = &clk_regmap_mux_ops,
2369
-
.parent_data = s4_sd_emmc_clk0_parent_data,
2370
-
.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
2368
+
.parent_data = s4_sd_emmc_clk0_parents,
2369
+
.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2371
2370
.flags = 0,
2372
2371
},
2373
2372
};
···
2414
2413
.hw.init = &(struct clk_init_data) {
2415
2414
.name = "sd_emmc_a_clk0_sel",
2416
2415
.ops = &clk_regmap_mux_ops,
2417
-
.parent_data = s4_sd_emmc_clk0_parent_data,
2418
-
.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
2416
+
.parent_data = s4_sd_emmc_clk0_parents,
2417
+
.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2419
2418
.flags = 0,
2420
2419
},
2421
2420
};
···
2462
2461
.hw.init = &(struct clk_init_data) {
2463
2462
.name = "sd_emmc_b_clk0_sel",
2464
2463
.ops = &clk_regmap_mux_ops,
2465
-
.parent_data = s4_sd_emmc_clk0_parent_data,
2466
-
.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parent_data),
2464
+
.parent_data = s4_sd_emmc_clk0_parents,
2465
+
.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2467
2466
.flags = 0,
2468
2467
},
2469
2468
};
···
2502
2501
};
2503
2502
2504
2503
/* SPICC Clock */
2505
-
static const struct clk_parent_data s4_spicc_parent_data[] = {
2504
+
static const struct clk_parent_data s4_spicc_parents[] = {
2506
2505
{ .fw_name = "xtal", },
2507
2506
{ .hw = &s4_sys_clk.hw },
2508
2507
{ .fw_name = "fclk_div4", },
···
2512
2511
{ .fw_name = "fclk_div7", },
2513
2512
};
2514
2513
2515
-
static struct clk_regmap s4_spicc0_mux = {
2514
+
static struct clk_regmap s4_spicc0_sel = {
2516
2515
.data = &(struct clk_regmap_mux_data){
2517
2516
.offset = CLKCTRL_SPICC_CLK_CTRL,
2518
2517
.mask = 0x7,
2519
2518
.shift = 7,
2520
2519
},
2521
2520
.hw.init = &(struct clk_init_data) {
2522
-
.name = "spicc0_mux",
2521
+
.name = "spicc0_sel",
2523
2522
.ops = &clk_regmap_mux_ops,
2524
-
.parent_data = s4_spicc_parent_data,
2525
-
.num_parents = ARRAY_SIZE(s4_spicc_parent_data),
2523
+
.parent_data = s4_spicc_parents,
2524
+
.num_parents = ARRAY_SIZE(s4_spicc_parents),
2526
2525
.flags = CLK_SET_RATE_PARENT,
2527
2526
},
2528
2527
};
···
2537
2536
.name = "spicc0_div",
2538
2537
.ops = &clk_regmap_divider_ops,
2539
2538
.parent_hws = (const struct clk_hw *[]) {
2540
-
&s4_spicc0_mux.hw
2539
+
&s4_spicc0_sel.hw
2541
2540
},
2542
2541
.num_parents = 1,
2543
2542
.flags = CLK_SET_RATE_PARENT,
2544
2543
},
2545
2544
};
2546
2545
2547
-
static struct clk_regmap s4_spicc0_gate = {
2546
+
static struct clk_regmap s4_spicc0_en = {
2548
2547
.data = &(struct clk_regmap_gate_data){
2549
2548
.offset = CLKCTRL_SPICC_CLK_CTRL,
2550
2549
.bit_idx = 6,
2551
2550
},
2552
2551
.hw.init = &(struct clk_init_data){
2553
-
.name = "spicc0",
2552
+
.name = "spicc0_en",
2554
2553
.ops = &clk_regmap_gate_ops,
2555
2554
.parent_hws = (const struct clk_hw *[]) {
2556
2555
&s4_spicc0_div.hw
···
2561
2560
};
2562
2561
2563
2562
/* PWM Clock */
2564
-
static const struct clk_parent_data s4_pwm_parent_data[] = {
2563
+
static const struct clk_parent_data s4_pwm_parents[] = {
2565
2564
{ .fw_name = "xtal", },
2566
2565
{ .hw = &s4_vid_pll.hw },
2567
2566
{ .fw_name = "fclk_div4", },
2568
2567
{ .fw_name = "fclk_div3", },
2569
2568
};
2570
2569
2571
-
static struct clk_regmap s4_pwm_a_mux = {
2572
-
.data = &(struct clk_regmap_mux_data) {
2573
-
.offset = CLKCTRL_PWM_CLK_AB_CTRL,
2574
-
.mask = 0x3,
2575
-
.shift = 9,
2576
-
},
2577
-
.hw.init = &(struct clk_init_data){
2578
-
.name = "pwm_a_mux",
2579
-
.ops = &clk_regmap_mux_ops,
2580
-
.parent_data = s4_pwm_parent_data,
2581
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2582
-
.flags = 0,
2583
-
},
2584
-
};
2570
+
static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents);
2571
+
static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8);
2572
+
static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8);
2585
2573
2586
-
static struct clk_regmap s4_pwm_a_div = {
2587
-
.data = &(struct clk_regmap_div_data) {
2588
-
.offset = CLKCTRL_PWM_CLK_AB_CTRL,
2589
-
.shift = 0,
2590
-
.width = 8,
2591
-
},
2592
-
.hw.init = &(struct clk_init_data){
2593
-
.name = "pwm_a_div",
2594
-
.ops = &clk_regmap_divider_ops,
2595
-
.parent_hws = (const struct clk_hw *[]) {
2596
-
&s4_pwm_a_mux.hw
2597
-
},
2598
-
.num_parents = 1,
2599
-
.flags = CLK_SET_RATE_PARENT,
2600
-
},
2601
-
};
2574
+
static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents);
2575
+
static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8);
2576
+
static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24);
2602
2577
2603
-
static struct clk_regmap s4_pwm_a_gate = {
2604
-
.data = &(struct clk_regmap_gate_data) {
2605
-
.offset = CLKCTRL_PWM_CLK_AB_CTRL,
2606
-
.bit_idx = 8,
2607
-
},
2608
-
.hw.init = &(struct clk_init_data){
2609
-
.name = "pwm_a_gate",
2610
-
.ops = &clk_regmap_gate_ops,
2611
-
.parent_hws = (const struct clk_hw *[]) {
2612
-
&s4_pwm_a_div.hw
2613
-
},
2614
-
.num_parents = 1,
2615
-
.flags = CLK_SET_RATE_PARENT,
2616
-
},
2617
-
};
2578
+
static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents);
2579
+
static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8);
2580
+
static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8);
2618
2581
2619
-
static struct clk_regmap s4_pwm_b_mux = {
2620
-
.data = &(struct clk_regmap_mux_data) {
2621
-
.offset = CLKCTRL_PWM_CLK_AB_CTRL,
2622
-
.mask = 0x3,
2623
-
.shift = 25,
2624
-
},
2625
-
.hw.init = &(struct clk_init_data){
2626
-
.name = "pwm_b_mux",
2627
-
.ops = &clk_regmap_mux_ops,
2628
-
.parent_data = s4_pwm_parent_data,
2629
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2630
-
.flags = 0,
2631
-
},
2632
-
};
2582
+
static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents);
2583
+
static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8);
2584
+
static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24);
2633
2585
2634
-
static struct clk_regmap s4_pwm_b_div = {
2635
-
.data = &(struct clk_regmap_div_data) {
2636
-
.offset = CLKCTRL_PWM_CLK_AB_CTRL,
2637
-
.shift = 16,
2638
-
.width = 8,
2639
-
},
2640
-
.hw.init = &(struct clk_init_data){
2641
-
.name = "pwm_b_div",
2642
-
.ops = &clk_regmap_divider_ops,
2643
-
.parent_hws = (const struct clk_hw *[]) {
2644
-
&s4_pwm_b_mux.hw
2645
-
},
2646
-
.num_parents = 1,
2647
-
.flags = CLK_SET_RATE_PARENT,
2648
-
},
2649
-
};
2586
+
static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents);
2587
+
static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8);
2588
+
static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8);
2650
2589
2651
-
static struct clk_regmap s4_pwm_b_gate = {
2652
-
.data = &(struct clk_regmap_gate_data) {
2653
-
.offset = CLKCTRL_PWM_CLK_AB_CTRL,
2654
-
.bit_idx = 24,
2655
-
},
2656
-
.hw.init = &(struct clk_init_data){
2657
-
.name = "pwm_b_gate",
2658
-
.ops = &clk_regmap_gate_ops,
2659
-
.parent_hws = (const struct clk_hw *[]) {
2660
-
&s4_pwm_b_div.hw
2661
-
},
2662
-
.num_parents = 1,
2663
-
.flags = CLK_SET_RATE_PARENT,
2664
-
},
2665
-
};
2590
+
static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents);
2591
+
static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8);
2592
+
static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24);
2666
2593
2667
-
static struct clk_regmap s4_pwm_c_mux = {
2668
-
.data = &(struct clk_regmap_mux_data) {
2669
-
.offset = CLKCTRL_PWM_CLK_CD_CTRL,
2670
-
.mask = 0x3,
2671
-
.shift = 9,
2672
-
},
2673
-
.hw.init = &(struct clk_init_data){
2674
-
.name = "pwm_c_mux",
2675
-
.ops = &clk_regmap_mux_ops,
2676
-
.parent_data = s4_pwm_parent_data,
2677
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2678
-
.flags = 0,
2679
-
},
2680
-
};
2594
+
static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents);
2595
+
static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8);
2596
+
static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8);
2681
2597
2682
-
static struct clk_regmap s4_pwm_c_div = {
2683
-
.data = &(struct clk_regmap_div_data) {
2684
-
.offset = CLKCTRL_PWM_CLK_CD_CTRL,
2685
-
.shift = 0,
2686
-
.width = 8,
2687
-
},
2688
-
.hw.init = &(struct clk_init_data){
2689
-
.name = "pwm_c_div",
2690
-
.ops = &clk_regmap_divider_ops,
2691
-
.parent_hws = (const struct clk_hw *[]) {
2692
-
&s4_pwm_c_mux.hw
2693
-
},
2694
-
.num_parents = 1,
2695
-
},
2696
-
};
2598
+
static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents);
2599
+
static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8);
2600
+
static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24);
2697
2601
2698
-
static struct clk_regmap s4_pwm_c_gate = {
2699
-
.data = &(struct clk_regmap_gate_data) {
2700
-
.offset = CLKCTRL_PWM_CLK_CD_CTRL,
2701
-
.bit_idx = 8,
2702
-
},
2703
-
.hw.init = &(struct clk_init_data){
2704
-
.name = "pwm_c_gate",
2705
-
.ops = &clk_regmap_gate_ops,
2706
-
.parent_hws = (const struct clk_hw *[]) {
2707
-
&s4_pwm_c_div.hw
2708
-
},
2709
-
.num_parents = 1,
2710
-
.flags = CLK_SET_RATE_PARENT,
2711
-
},
2712
-
};
2602
+
static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents);
2603
+
static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8);
2604
+
static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8);
2713
2605
2714
-
static struct clk_regmap s4_pwm_d_mux = {
2715
-
.data = &(struct clk_regmap_mux_data) {
2716
-
.offset = CLKCTRL_PWM_CLK_CD_CTRL,
2717
-
.mask = 0x3,
2718
-
.shift = 25,
2719
-
},
2720
-
.hw.init = &(struct clk_init_data){
2721
-
.name = "pwm_d_mux",
2722
-
.ops = &clk_regmap_mux_ops,
2723
-
.parent_data = s4_pwm_parent_data,
2724
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2725
-
.flags = 0,
2726
-
},
2727
-
};
2606
+
static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents);
2607
+
static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8);
2608
+
static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24);
2728
2609
2729
-
static struct clk_regmap s4_pwm_d_div = {
2730
-
.data = &(struct clk_regmap_div_data) {
2731
-
.offset = CLKCTRL_PWM_CLK_CD_CTRL,
2732
-
.shift = 16,
2733
-
.width = 8,
2734
-
},
2735
-
.hw.init = &(struct clk_init_data){
2736
-
.name = "pwm_d_div",
2737
-
.ops = &clk_regmap_divider_ops,
2738
-
.parent_hws = (const struct clk_hw *[]) {
2739
-
&s4_pwm_d_mux.hw
2740
-
},
2741
-
.num_parents = 1,
2742
-
.flags = CLK_SET_RATE_PARENT,
2743
-
},
2744
-
};
2745
-
2746
-
static struct clk_regmap s4_pwm_d_gate = {
2747
-
.data = &(struct clk_regmap_gate_data) {
2748
-
.offset = CLKCTRL_PWM_CLK_CD_CTRL,
2749
-
.bit_idx = 24,
2750
-
},
2751
-
.hw.init = &(struct clk_init_data){
2752
-
.name = "pwm_d_gate",
2753
-
.ops = &clk_regmap_gate_ops,
2754
-
.parent_hws = (const struct clk_hw *[]) {
2755
-
&s4_pwm_d_div.hw
2756
-
},
2757
-
.num_parents = 1,
2758
-
.flags = CLK_SET_RATE_PARENT,
2759
-
},
2760
-
};
2761
-
2762
-
static struct clk_regmap s4_pwm_e_mux = {
2763
-
.data = &(struct clk_regmap_mux_data) {
2764
-
.offset = CLKCTRL_PWM_CLK_EF_CTRL,
2765
-
.mask = 0x3,
2766
-
.shift = 9,
2767
-
},
2768
-
.hw.init = &(struct clk_init_data){
2769
-
.name = "pwm_e_mux",
2770
-
.ops = &clk_regmap_mux_ops,
2771
-
.parent_data = s4_pwm_parent_data,
2772
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2773
-
.flags = 0,
2774
-
},
2775
-
};
2776
-
2777
-
static struct clk_regmap s4_pwm_e_div = {
2778
-
.data = &(struct clk_regmap_div_data) {
2779
-
.offset = CLKCTRL_PWM_CLK_EF_CTRL,
2780
-
.shift = 0,
2781
-
.width = 8,
2782
-
},
2783
-
.hw.init = &(struct clk_init_data){
2784
-
.name = "pwm_e_div",
2785
-
.ops = &clk_regmap_divider_ops,
2786
-
.parent_hws = (const struct clk_hw *[]) {
2787
-
&s4_pwm_e_mux.hw
2788
-
},
2789
-
.num_parents = 1,
2790
-
.flags = CLK_SET_RATE_PARENT,
2791
-
},
2792
-
};
2793
-
2794
-
static struct clk_regmap s4_pwm_e_gate = {
2795
-
.data = &(struct clk_regmap_gate_data) {
2796
-
.offset = CLKCTRL_PWM_CLK_EF_CTRL,
2797
-
.bit_idx = 8,
2798
-
},
2799
-
.hw.init = &(struct clk_init_data){
2800
-
.name = "pwm_e_gate",
2801
-
.ops = &clk_regmap_gate_ops,
2802
-
.parent_hws = (const struct clk_hw *[]) {
2803
-
&s4_pwm_e_div.hw
2804
-
},
2805
-
.num_parents = 1,
2806
-
.flags = CLK_SET_RATE_PARENT,
2807
-
},
2808
-
};
2809
-
2810
-
static struct clk_regmap s4_pwm_f_mux = {
2811
-
.data = &(struct clk_regmap_mux_data) {
2812
-
.offset = CLKCTRL_PWM_CLK_EF_CTRL,
2813
-
.mask = 0x3,
2814
-
.shift = 25,
2815
-
},
2816
-
.hw.init = &(struct clk_init_data){
2817
-
.name = "pwm_f_mux",
2818
-
.ops = &clk_regmap_mux_ops,
2819
-
.parent_data = s4_pwm_parent_data,
2820
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2821
-
.flags = 0,
2822
-
},
2823
-
};
2824
-
2825
-
static struct clk_regmap s4_pwm_f_div = {
2826
-
.data = &(struct clk_regmap_div_data) {
2827
-
.offset = CLKCTRL_PWM_CLK_EF_CTRL,
2828
-
.shift = 16,
2829
-
.width = 8,
2830
-
},
2831
-
.hw.init = &(struct clk_init_data){
2832
-
.name = "pwm_f_div",
2833
-
.ops = &clk_regmap_divider_ops,
2834
-
.parent_hws = (const struct clk_hw *[]) {
2835
-
&s4_pwm_f_mux.hw
2836
-
},
2837
-
.num_parents = 1,
2838
-
.flags = CLK_SET_RATE_PARENT,
2839
-
},
2840
-
};
2841
-
2842
-
static struct clk_regmap s4_pwm_f_gate = {
2843
-
.data = &(struct clk_regmap_gate_data) {
2844
-
.offset = CLKCTRL_PWM_CLK_EF_CTRL,
2845
-
.bit_idx = 24,
2846
-
},
2847
-
.hw.init = &(struct clk_init_data){
2848
-
.name = "pwm_f_gate",
2849
-
.ops = &clk_regmap_gate_ops,
2850
-
.parent_hws = (const struct clk_hw *[]) {
2851
-
&s4_pwm_f_div.hw
2852
-
},
2853
-
.num_parents = 1,
2854
-
.flags = CLK_SET_RATE_PARENT,
2855
-
},
2856
-
};
2857
-
2858
-
static struct clk_regmap s4_pwm_g_mux = {
2859
-
.data = &(struct clk_regmap_mux_data) {
2860
-
.offset = CLKCTRL_PWM_CLK_GH_CTRL,
2861
-
.mask = 0x3,
2862
-
.shift = 9,
2863
-
},
2864
-
.hw.init = &(struct clk_init_data){
2865
-
.name = "pwm_g_mux",
2866
-
.ops = &clk_regmap_mux_ops,
2867
-
.parent_data = s4_pwm_parent_data,
2868
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2869
-
.flags = 0,
2870
-
},
2871
-
};
2872
-
2873
-
static struct clk_regmap s4_pwm_g_div = {
2874
-
.data = &(struct clk_regmap_div_data) {
2875
-
.offset = CLKCTRL_PWM_CLK_GH_CTRL,
2876
-
.shift = 0,
2877
-
.width = 8,
2878
-
},
2879
-
.hw.init = &(struct clk_init_data){
2880
-
.name = "pwm_g_div",
2881
-
.ops = &clk_regmap_divider_ops,
2882
-
.parent_hws = (const struct clk_hw *[]) {
2883
-
&s4_pwm_g_mux.hw
2884
-
},
2885
-
.num_parents = 1,
2886
-
.flags = CLK_SET_RATE_PARENT,
2887
-
},
2888
-
};
2889
-
2890
-
static struct clk_regmap s4_pwm_g_gate = {
2891
-
.data = &(struct clk_regmap_gate_data) {
2892
-
.offset = CLKCTRL_PWM_CLK_GH_CTRL,
2893
-
.bit_idx = 8,
2894
-
},
2895
-
.hw.init = &(struct clk_init_data){
2896
-
.name = "pwm_g_gate",
2897
-
.ops = &clk_regmap_gate_ops,
2898
-
.parent_hws = (const struct clk_hw *[]) {
2899
-
&s4_pwm_g_div.hw
2900
-
},
2901
-
.num_parents = 1,
2902
-
.flags = CLK_SET_RATE_PARENT,
2903
-
},
2904
-
};
2905
-
2906
-
static struct clk_regmap s4_pwm_h_mux = {
2907
-
.data = &(struct clk_regmap_mux_data) {
2908
-
.offset = CLKCTRL_PWM_CLK_GH_CTRL,
2909
-
.mask = 0x3,
2910
-
.shift = 25,
2911
-
},
2912
-
.hw.init = &(struct clk_init_data){
2913
-
.name = "pwm_h_mux",
2914
-
.ops = &clk_regmap_mux_ops,
2915
-
.parent_data = s4_pwm_parent_data,
2916
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2917
-
.flags = 0,
2918
-
},
2919
-
};
2920
-
2921
-
static struct clk_regmap s4_pwm_h_div = {
2922
-
.data = &(struct clk_regmap_div_data) {
2923
-
.offset = CLKCTRL_PWM_CLK_GH_CTRL,
2924
-
.shift = 16,
2925
-
.width = 8,
2926
-
},
2927
-
.hw.init = &(struct clk_init_data){
2928
-
.name = "pwm_h_div",
2929
-
.ops = &clk_regmap_divider_ops,
2930
-
.parent_hws = (const struct clk_hw *[]) {
2931
-
&s4_pwm_h_mux.hw
2932
-
},
2933
-
.num_parents = 1,
2934
-
.flags = CLK_SET_RATE_PARENT,
2935
-
},
2936
-
};
2937
-
2938
-
static struct clk_regmap s4_pwm_h_gate = {
2939
-
.data = &(struct clk_regmap_gate_data) {
2940
-
.offset = CLKCTRL_PWM_CLK_GH_CTRL,
2941
-
.bit_idx = 24,
2942
-
},
2943
-
.hw.init = &(struct clk_init_data){
2944
-
.name = "pwm_h_gate",
2945
-
.ops = &clk_regmap_gate_ops,
2946
-
.parent_hws = (const struct clk_hw *[]) {
2947
-
&s4_pwm_h_div.hw
2948
-
},
2949
-
.num_parents = 1,
2950
-
.flags = CLK_SET_RATE_PARENT,
2951
-
},
2952
-
};
2953
-
2954
-
static struct clk_regmap s4_pwm_i_mux = {
2955
-
.data = &(struct clk_regmap_mux_data) {
2956
-
.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
2957
-
.mask = 0x3,
2958
-
.shift = 9,
2959
-
},
2960
-
.hw.init = &(struct clk_init_data){
2961
-
.name = "pwm_i_mux",
2962
-
.ops = &clk_regmap_mux_ops,
2963
-
.parent_data = s4_pwm_parent_data,
2964
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
2965
-
.flags = 0,
2966
-
},
2967
-
};
2968
-
2969
-
static struct clk_regmap s4_pwm_i_div = {
2970
-
.data = &(struct clk_regmap_div_data) {
2971
-
.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
2972
-
.shift = 0,
2973
-
.width = 8,
2974
-
},
2975
-
.hw.init = &(struct clk_init_data){
2976
-
.name = "pwm_i_div",
2977
-
.ops = &clk_regmap_divider_ops,
2978
-
.parent_hws = (const struct clk_hw *[]) {
2979
-
&s4_pwm_i_mux.hw
2980
-
},
2981
-
.num_parents = 1,
2982
-
.flags = CLK_SET_RATE_PARENT,
2983
-
},
2984
-
};
2985
-
2986
-
static struct clk_regmap s4_pwm_i_gate = {
2987
-
.data = &(struct clk_regmap_gate_data) {
2988
-
.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
2989
-
.bit_idx = 8,
2990
-
},
2991
-
.hw.init = &(struct clk_init_data){
2992
-
.name = "pwm_i_gate",
2993
-
.ops = &clk_regmap_gate_ops,
2994
-
.parent_hws = (const struct clk_hw *[]) {
2995
-
&s4_pwm_i_div.hw
2996
-
},
2997
-
.num_parents = 1,
2998
-
.flags = CLK_SET_RATE_PARENT,
2999
-
},
3000
-
};
3001
-
3002
-
static struct clk_regmap s4_pwm_j_mux = {
3003
-
.data = &(struct clk_regmap_mux_data) {
3004
-
.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
3005
-
.mask = 0x3,
3006
-
.shift = 25,
3007
-
},
3008
-
.hw.init = &(struct clk_init_data){
3009
-
.name = "pwm_j_mux",
3010
-
.ops = &clk_regmap_mux_ops,
3011
-
.parent_data = s4_pwm_parent_data,
3012
-
.num_parents = ARRAY_SIZE(s4_pwm_parent_data),
3013
-
.flags = 0,
3014
-
},
3015
-
};
3016
-
3017
-
static struct clk_regmap s4_pwm_j_div = {
3018
-
.data = &(struct clk_regmap_div_data) {
3019
-
.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
3020
-
.shift = 16,
3021
-
.width = 8,
3022
-
},
3023
-
.hw.init = &(struct clk_init_data){
3024
-
.name = "pwm_j_div",
3025
-
.ops = &clk_regmap_divider_ops,
3026
-
.parent_hws = (const struct clk_hw *[]) {
3027
-
&s4_pwm_j_mux.hw
3028
-
},
3029
-
.num_parents = 1,
3030
-
.flags = CLK_SET_RATE_PARENT,
3031
-
},
3032
-
};
3033
-
3034
-
static struct clk_regmap s4_pwm_j_gate = {
3035
-
.data = &(struct clk_regmap_gate_data) {
3036
-
.offset = CLKCTRL_PWM_CLK_IJ_CTRL,
3037
-
.bit_idx = 24,
3038
-
},
3039
-
.hw.init = &(struct clk_init_data){
3040
-
.name = "pwm_j_gate",
3041
-
.ops = &clk_regmap_gate_ops,
3042
-
.parent_hws = (const struct clk_hw *[]) {
3043
-
&s4_pwm_j_div.hw
3044
-
},
3045
-
.num_parents = 1,
3046
-
.flags = CLK_SET_RATE_PARENT,
3047
-
},
3048
-
};
3049
-
3050
-
static struct clk_regmap s4_saradc_mux = {
2610
+
static struct clk_regmap s4_saradc_sel = {
3051
2611
.data = &(struct clk_regmap_mux_data) {
3052
2612
.offset = CLKCTRL_SAR_CLK_CTRL,
3053
2613
.mask = 0x3,
3054
2614
.shift = 9,
3055
2615
},
3056
2616
.hw.init = &(struct clk_init_data){
3057
-
.name = "saradc_mux",
2617
+
.name = "saradc_sel",
3058
2618
.ops = &clk_regmap_mux_ops,
3059
2619
.parent_data = (const struct clk_parent_data []) {
3060
2620
{ .fw_name = "xtal", },
···
2636
3074
.name = "saradc_div",
2637
3075
.ops = &clk_regmap_divider_ops,
2638
3076
.parent_hws = (const struct clk_hw *[]) {
2639
-
&s4_saradc_mux.hw
3077
+
&s4_saradc_sel.hw
2640
3078
},
2641
3079
.num_parents = 1,
2642
3080
.flags = CLK_SET_RATE_PARENT,
2643
3081
},
2644
3082
};
2645
3083
2646
-
static struct clk_regmap s4_saradc_gate = {
3084
+
static struct clk_regmap s4_saradc = {
2647
3085
.data = &(struct clk_regmap_gate_data) {
2648
3086
.offset = CLKCTRL_SAR_CLK_CTRL,
2649
3087
.bit_idx = 8,
2650
3088
},
2651
3089
.hw.init = &(struct clk_init_data){
2652
-
.name = "saradc_clk",
3090
+
.name = "saradc",
2653
3091
.ops = &clk_regmap_gate_ops,
2654
3092
.parent_hws = (const struct clk_hw *[]) {
2655
3093
&s4_saradc_div.hw
···
2664
3102
* corresponding clock sources are not described in the clock tree and internal clock
2665
3103
* for debug, so they are skipped.
2666
3104
*/
2667
-
static u32 s4_gen_clk_mux_table[] = { 0, 4, 5, 7, 19, 21, 22,
2668
-
23, 24, 25, 26, 27, 28 };
2669
-
static const struct clk_parent_data s4_gen_clk_parent_data[] = {
3105
+
static u32 s4_gen_clk_parents_val_table[] = { 0, 4, 5, 7, 19, 21, 22, 23, 24, 25, 26, 27, 28 };
3106
+
static const struct clk_parent_data s4_gen_clk_parents[] = {
2670
3107
{ .fw_name = "xtal", },
2671
3108
{ .hw = &s4_vid_pll.hw },
2672
3109
{ .fw_name = "gp0_pll", },
···
2686
3125
.offset = CLKCTRL_GEN_CLK_CTRL,
2687
3126
.mask = 0x1f,
2688
3127
.shift = 12,
2689
-
.table = s4_gen_clk_mux_table,
3128
+
.table = s4_gen_clk_parents_val_table,
2690
3129
},
2691
3130
.hw.init = &(struct clk_init_data){
2692
3131
.name = "gen_clk_sel",
2693
3132
.ops = &clk_regmap_mux_ops,
2694
-
.parent_data = s4_gen_clk_parent_data,
2695
-
.num_parents = ARRAY_SIZE(s4_gen_clk_parent_data),
3133
+
.parent_data = s4_gen_clk_parents,
3134
+
.num_parents = ARRAY_SIZE(s4_gen_clk_parents),
2696
3135
/*
2697
3136
* Because the GEN clock can be connected to an external pad
2698
3137
* and may be set up directly from the device tree. Don't
···
2735
3174
},
2736
3175
};
2737
3176
2738
-
#define MESON_GATE(_name, _reg, _bit) \
2739
-
MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw)
3177
+
static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
2740
3178
2741
-
static MESON_GATE(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0);
2742
-
static MESON_GATE(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1);
2743
-
static MESON_GATE(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4);
2744
-
static MESON_GATE(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6);
2745
-
static MESON_GATE(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13);
2746
-
static MESON_GATE(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14);
2747
-
static MESON_GATE(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16);
2748
-
static MESON_GATE(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24);
2749
-
static MESON_GATE(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25);
2750
-
static MESON_GATE(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26);
2751
-
static MESON_GATE(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27);
2752
-
static MESON_GATE(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28);
2753
-
static MESON_GATE(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29);
2754
-
static MESON_GATE(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30);
2755
-
static MESON_GATE(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31);
2756
-
static MESON_GATE(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0);
2757
-
static MESON_GATE(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3);
2758
-
static MESON_GATE(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5);
2759
-
static MESON_GATE(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6);
2760
-
static MESON_GATE(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7);
2761
-
static MESON_GATE(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8);
2762
-
static MESON_GATE(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9);
2763
-
static MESON_GATE(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11);
2764
-
static MESON_GATE(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15);
2765
-
static MESON_GATE(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16);
2766
-
static MESON_GATE(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20);
2767
-
static MESON_GATE(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21);
2768
-
static MESON_GATE(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26);
2769
-
static MESON_GATE(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30);
2770
-
static MESON_GATE(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31);
2771
-
static MESON_GATE(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0);
2772
-
static MESON_GATE(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1);
2773
-
static MESON_GATE(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2);
2774
-
static MESON_GATE(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4);
2775
-
static MESON_GATE(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5);
2776
-
static MESON_GATE(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8);
2777
-
static MESON_GATE(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10);
2778
-
static MESON_GATE(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11);
2779
-
static MESON_GATE(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18);
2780
-
static MESON_GATE(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19);
2781
-
static MESON_GATE(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25);
2782
-
static MESON_GATE(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27);
2783
-
static MESON_GATE(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28);
2784
-
static MESON_GATE(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30);
2785
-
static MESON_GATE(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7);
2786
-
static MESON_GATE(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8);
2787
-
static MESON_GATE(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9);
2788
-
static MESON_GATE(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10);
2789
-
static MESON_GATE(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11);
3179
+
#define S4_PCLK(_name, _reg, _bit, _flags) \
3180
+
MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags)
3181
+
3182
+
/*
3183
+
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
3184
+
* Users are encouraged to test without it and submit changes to:
3185
+
* - remove the flag if not necessary
3186
+
* - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
3187
+
* if appropriate.
3188
+
* - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
3189
+
* for a particular clock.
3190
+
*/
3191
+
static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, CLK_IGNORE_UNUSED);
3192
+
static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, CLK_IGNORE_UNUSED);
3193
+
static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, CLK_IGNORE_UNUSED);
3194
+
static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, CLK_IGNORE_UNUSED);
3195
+
static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, CLK_IGNORE_UNUSED);
3196
+
static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IGNORE_UNUSED);
3197
+
static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, CLK_IGNORE_UNUSED);
3198
+
static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, CLK_IGNORE_UNUSED);
3199
+
static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, CLK_IGNORE_UNUSED);
3200
+
static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26, CLK_IGNORE_UNUSED);
3201
+
static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IGNORE_UNUSED);
3202
+
static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, CLK_IGNORE_UNUSED);
3203
+
static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IGNORE_UNUSED);
3204
+
static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, CLK_IGNORE_UNUSED);
3205
+
static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, CLK_IGNORE_UNUSED);
3206
+
3207
+
static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, CLK_IGNORE_UNUSED);
3208
+
static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, CLK_IGNORE_UNUSED);
3209
+
static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, CLK_IGNORE_UNUSED);
3210
+
static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, CLK_IGNORE_UNUSED);
3211
+
static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, CLK_IGNORE_UNUSED);
3212
+
static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, CLK_IGNORE_UNUSED);
3213
+
static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, CLK_IGNORE_UNUSED);
3214
+
static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, CLK_IGNORE_UNUSED);
3215
+
static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15, CLK_IGNORE_UNUSED);
3216
+
static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16, CLK_IGNORE_UNUSED);
3217
+
static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, CLK_IGNORE_UNUSED);
3218
+
static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, CLK_IGNORE_UNUSED);
3219
+
static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, CLK_IGNORE_UNUSED);
3220
+
static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, CLK_IGNORE_UNUSED);
3221
+
static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, CLK_IGNORE_UNUSED);
3222
+
3223
+
static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, CLK_IGNORE_UNUSED);
3224
+
static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, CLK_IGNORE_UNUSED);
3225
+
static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, CLK_IGNORE_UNUSED);
3226
+
static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, CLK_IGNORE_UNUSED);
3227
+
static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, CLK_IGNORE_UNUSED);
3228
+
static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8, CLK_IGNORE_UNUSED);
3229
+
static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10, CLK_IGNORE_UNUSED);
3230
+
static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, CLK_IGNORE_UNUSED);
3231
+
static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, CLK_IGNORE_UNUSED);
3232
+
static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19, CLK_IGNORE_UNUSED);
3233
+
static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, CLK_IGNORE_UNUSED);
3234
+
static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27, CLK_IGNORE_UNUSED);
3235
+
static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28, CLK_IGNORE_UNUSED);
3236
+
static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IGNORE_UNUSED);
3237
+
3238
+
static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7, CLK_IGNORE_UNUSED);
3239
+
static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8, CLK_IGNORE_UNUSED);
3240
+
static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9, CLK_IGNORE_UNUSED);
3241
+
static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10, CLK_IGNORE_UNUSED);
3242
+
static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11, CLK_IGNORE_UNUSED);
2790
3243
2791
3244
/* Array of all clocks provided by this provider */
2792
-
static struct clk_hw *s4_periphs_hw_clks[] = {
3245
+
static struct clk_hw *s4_peripherals_hw_clks[] = {
2793
3246
[CLKID_RTC_32K_CLKIN] = &s4_rtc_32k_by_oscin_clkin.hw,
2794
3247
[CLKID_RTC_32K_DIV] = &s4_rtc_32k_by_oscin_div.hw,
2795
3248
[CLKID_RTC_32K_SEL] = &s4_rtc_32k_by_oscin_sel.hw,
···
2826
3251
[CLKID_CECB_32K_SEL_PRE] = &s4_cecb_32k_sel_pre.hw,
2827
3252
[CLKID_CECB_32K_SEL] = &s4_cecb_32k_sel.hw,
2828
3253
[CLKID_CECB_32K_CLKOUT] = &s4_cecb_32k_clkout.hw,
2829
-
[CLKID_SC_CLK_SEL] = &s4_sc_clk_mux.hw,
3254
+
[CLKID_SC_CLK_SEL] = &s4_sc_clk_sel.hw,
2830
3255
[CLKID_SC_CLK_DIV] = &s4_sc_clk_div.hw,
2831
-
[CLKID_SC] = &s4_sc_clk_gate.hw,
2832
-
[CLKID_12_24M] = &s4_12_24M_clk_gate.hw,
2833
-
[CLKID_12M_CLK_DIV] = &s4_12M_clk_div.hw,
2834
-
[CLKID_12_24M_CLK_SEL] = &s4_12_24M_clk.hw,
3256
+
[CLKID_SC] = &s4_sc_clk.hw,
3257
+
[CLKID_12_24M] = &s4_12_24M.hw,
3258
+
[CLKID_12M_CLK_DIV] = &s4_12M_div.hw,
3259
+
[CLKID_12_24M_CLK_SEL] = &s4_12_24M_sel.hw,
2835
3260
[CLKID_VID_PLL_DIV] = &s4_vid_pll_div.hw,
2836
3261
[CLKID_VID_PLL_SEL] = &s4_vid_pll_sel.hw,
2837
3262
[CLKID_VID_PLL] = &s4_vid_pll.hw,
···
2873
3298
[CLKID_HDMI_DIV] = &s4_hdmi_div.hw,
2874
3299
[CLKID_HDMI] = &s4_hdmi.hw,
2875
3300
[CLKID_TS_CLK_DIV] = &s4_ts_clk_div.hw,
2876
-
[CLKID_TS] = &s4_ts_clk_gate.hw,
3301
+
[CLKID_TS] = &s4_ts_clk.hw,
2877
3302
[CLKID_MALI_0_SEL] = &s4_mali_0_sel.hw,
2878
3303
[CLKID_MALI_0_DIV] = &s4_mali_0_div.hw,
2879
3304
[CLKID_MALI_0] = &s4_mali_0.hw,
2880
3305
[CLKID_MALI_1_SEL] = &s4_mali_1_sel.hw,
2881
3306
[CLKID_MALI_1_DIV] = &s4_mali_1_div.hw,
2882
3307
[CLKID_MALI_1] = &s4_mali_1.hw,
2883
-
[CLKID_MALI_SEL] = &s4_mali_mux.hw,
2884
-
[CLKID_VDEC_P0_SEL] = &s4_vdec_p0_mux.hw,
3308
+
[CLKID_MALI_SEL] = &s4_mali_sel.hw,
3309
+
[CLKID_VDEC_P0_SEL] = &s4_vdec_p0_sel.hw,
2885
3310
[CLKID_VDEC_P0_DIV] = &s4_vdec_p0_div.hw,
2886
3311
[CLKID_VDEC_P0] = &s4_vdec_p0.hw,
2887
-
[CLKID_VDEC_P1_SEL] = &s4_vdec_p1_mux.hw,
3312
+
[CLKID_VDEC_P1_SEL] = &s4_vdec_p1_sel.hw,
2888
3313
[CLKID_VDEC_P1_DIV] = &s4_vdec_p1_div.hw,
2889
3314
[CLKID_VDEC_P1] = &s4_vdec_p1.hw,
2890
-
[CLKID_VDEC_SEL] = &s4_vdec_mux.hw,
2891
-
[CLKID_HEVCF_P0_SEL] = &s4_hevcf_p0_mux.hw,
3315
+
[CLKID_VDEC_SEL] = &s4_vdec_sel.hw,
3316
+
[CLKID_HEVCF_P0_SEL] = &s4_hevcf_p0_sel.hw,
2892
3317
[CLKID_HEVCF_P0_DIV] = &s4_hevcf_p0_div.hw,
2893
3318
[CLKID_HEVCF_P0] = &s4_hevcf_p0.hw,
2894
-
[CLKID_HEVCF_P1_SEL] = &s4_hevcf_p1_mux.hw,
3319
+
[CLKID_HEVCF_P1_SEL] = &s4_hevcf_p1_sel.hw,
2895
3320
[CLKID_HEVCF_P1_DIV] = &s4_hevcf_p1_div.hw,
2896
3321
[CLKID_HEVCF_P1] = &s4_hevcf_p1.hw,
2897
-
[CLKID_HEVCF_SEL] = &s4_hevcf_mux.hw,
3322
+
[CLKID_HEVCF_SEL] = &s4_hevcf_sel.hw,
2898
3323
[CLKID_VPU_0_SEL] = &s4_vpu_0_sel.hw,
2899
3324
[CLKID_VPU_0_DIV] = &s4_vpu_0_div.hw,
2900
3325
[CLKID_VPU_0] = &s4_vpu_0.hw,
···
2902
3327
[CLKID_VPU_1_DIV] = &s4_vpu_1_div.hw,
2903
3328
[CLKID_VPU_1] = &s4_vpu_1.hw,
2904
3329
[CLKID_VPU] = &s4_vpu.hw,
2905
-
[CLKID_VPU_CLKB_TMP_SEL] = &s4_vpu_clkb_tmp_mux.hw,
3330
+
[CLKID_VPU_CLKB_TMP_SEL] = &s4_vpu_clkb_tmp_sel.hw,
2906
3331
[CLKID_VPU_CLKB_TMP_DIV] = &s4_vpu_clkb_tmp_div.hw,
2907
3332
[CLKID_VPU_CLKB_TMP] = &s4_vpu_clkb_tmp.hw,
2908
3333
[CLKID_VPU_CLKB_DIV] = &s4_vpu_clkb_div.hw,
2909
3334
[CLKID_VPU_CLKB] = &s4_vpu_clkb.hw,
2910
-
[CLKID_VPU_CLKC_P0_SEL] = &s4_vpu_clkc_p0_mux.hw,
3335
+
[CLKID_VPU_CLKC_P0_SEL] = &s4_vpu_clkc_p0_sel.hw,
2911
3336
[CLKID_VPU_CLKC_P0_DIV] = &s4_vpu_clkc_p0_div.hw,
2912
3337
[CLKID_VPU_CLKC_P0] = &s4_vpu_clkc_p0.hw,
2913
-
[CLKID_VPU_CLKC_P1_SEL] = &s4_vpu_clkc_p1_mux.hw,
3338
+
[CLKID_VPU_CLKC_P1_SEL] = &s4_vpu_clkc_p1_sel.hw,
2914
3339
[CLKID_VPU_CLKC_P1_DIV] = &s4_vpu_clkc_p1_div.hw,
2915
3340
[CLKID_VPU_CLKC_P1] = &s4_vpu_clkc_p1.hw,
2916
-
[CLKID_VPU_CLKC_SEL] = &s4_vpu_clkc_mux.hw,
3341
+
[CLKID_VPU_CLKC_SEL] = &s4_vpu_clkc_sel.hw,
2917
3342
[CLKID_VAPB_0_SEL] = &s4_vapb_0_sel.hw,
2918
3343
[CLKID_VAPB_0_DIV] = &s4_vapb_0_div.hw,
2919
3344
[CLKID_VAPB_0] = &s4_vapb_0.hw,
···
2921
3346
[CLKID_VAPB_1_DIV] = &s4_vapb_1_div.hw,
2922
3347
[CLKID_VAPB_1] = &s4_vapb_1.hw,
2923
3348
[CLKID_VAPB] = &s4_vapb.hw,
2924
-
[CLKID_GE2D] = &s4_ge2d_gate.hw,
2925
-
[CLKID_VDIN_MEAS_SEL] = &s4_vdin_meas_mux.hw,
3349
+
[CLKID_GE2D] = &s4_ge2d.hw,
3350
+
[CLKID_VDIN_MEAS_SEL] = &s4_vdin_meas_sel.hw,
2926
3351
[CLKID_VDIN_MEAS_DIV] = &s4_vdin_meas_div.hw,
2927
-
[CLKID_VDIN_MEAS] = &s4_vdin_meas_gate.hw,
3352
+
[CLKID_VDIN_MEAS] = &s4_vdin_meas.hw,
2928
3353
[CLKID_SD_EMMC_C_CLK_SEL] = &s4_sd_emmc_c_clk0_sel.hw,
2929
3354
[CLKID_SD_EMMC_C_CLK_DIV] = &s4_sd_emmc_c_clk0_div.hw,
2930
3355
[CLKID_SD_EMMC_C] = &s4_sd_emmc_c_clk0.hw,
···
2934
3359
[CLKID_SD_EMMC_B_CLK_SEL] = &s4_sd_emmc_b_clk0_sel.hw,
2935
3360
[CLKID_SD_EMMC_B_CLK_DIV] = &s4_sd_emmc_b_clk0_div.hw,
2936
3361
[CLKID_SD_EMMC_B] = &s4_sd_emmc_b_clk0.hw,
2937
-
[CLKID_SPICC0_SEL] = &s4_spicc0_mux.hw,
3362
+
[CLKID_SPICC0_SEL] = &s4_spicc0_sel.hw,
2938
3363
[CLKID_SPICC0_DIV] = &s4_spicc0_div.hw,
2939
-
[CLKID_SPICC0_EN] = &s4_spicc0_gate.hw,
2940
-
[CLKID_PWM_A_SEL] = &s4_pwm_a_mux.hw,
3364
+
[CLKID_SPICC0_EN] = &s4_spicc0_en.hw,
3365
+
[CLKID_PWM_A_SEL] = &s4_pwm_a_sel.hw,
2941
3366
[CLKID_PWM_A_DIV] = &s4_pwm_a_div.hw,
2942
-
[CLKID_PWM_A] = &s4_pwm_a_gate.hw,
2943
-
[CLKID_PWM_B_SEL] = &s4_pwm_b_mux.hw,
3367
+
[CLKID_PWM_A] = &s4_pwm_a.hw,
3368
+
[CLKID_PWM_B_SEL] = &s4_pwm_b_sel.hw,
2944
3369
[CLKID_PWM_B_DIV] = &s4_pwm_b_div.hw,
2945
-
[CLKID_PWM_B] = &s4_pwm_b_gate.hw,
2946
-
[CLKID_PWM_C_SEL] = &s4_pwm_c_mux.hw,
3370
+
[CLKID_PWM_B] = &s4_pwm_b.hw,
3371
+
[CLKID_PWM_C_SEL] = &s4_pwm_c_sel.hw,
2947
3372
[CLKID_PWM_C_DIV] = &s4_pwm_c_div.hw,
2948
-
[CLKID_PWM_C] = &s4_pwm_c_gate.hw,
2949
-
[CLKID_PWM_D_SEL] = &s4_pwm_d_mux.hw,
3373
+
[CLKID_PWM_C] = &s4_pwm_c.hw,
3374
+
[CLKID_PWM_D_SEL] = &s4_pwm_d_sel.hw,
2950
3375
[CLKID_PWM_D_DIV] = &s4_pwm_d_div.hw,
2951
-
[CLKID_PWM_D] = &s4_pwm_d_gate.hw,
2952
-
[CLKID_PWM_E_SEL] = &s4_pwm_e_mux.hw,
3376
+
[CLKID_PWM_D] = &s4_pwm_d.hw,
3377
+
[CLKID_PWM_E_SEL] = &s4_pwm_e_sel.hw,
2953
3378
[CLKID_PWM_E_DIV] = &s4_pwm_e_div.hw,
2954
-
[CLKID_PWM_E] = &s4_pwm_e_gate.hw,
2955
-
[CLKID_PWM_F_SEL] = &s4_pwm_f_mux.hw,
3379
+
[CLKID_PWM_E] = &s4_pwm_e.hw,
3380
+
[CLKID_PWM_F_SEL] = &s4_pwm_f_sel.hw,
2956
3381
[CLKID_PWM_F_DIV] = &s4_pwm_f_div.hw,
2957
-
[CLKID_PWM_F] = &s4_pwm_f_gate.hw,
2958
-
[CLKID_PWM_G_SEL] = &s4_pwm_g_mux.hw,
3382
+
[CLKID_PWM_F] = &s4_pwm_f.hw,
3383
+
[CLKID_PWM_G_SEL] = &s4_pwm_g_sel.hw,
2959
3384
[CLKID_PWM_G_DIV] = &s4_pwm_g_div.hw,
2960
-
[CLKID_PWM_G] = &s4_pwm_g_gate.hw,
2961
-
[CLKID_PWM_H_SEL] = &s4_pwm_h_mux.hw,
3385
+
[CLKID_PWM_G] = &s4_pwm_g.hw,
3386
+
[CLKID_PWM_H_SEL] = &s4_pwm_h_sel.hw,
2962
3387
[CLKID_PWM_H_DIV] = &s4_pwm_h_div.hw,
2963
-
[CLKID_PWM_H] = &s4_pwm_h_gate.hw,
2964
-
[CLKID_PWM_I_SEL] = &s4_pwm_i_mux.hw,
3388
+
[CLKID_PWM_H] = &s4_pwm_h.hw,
3389
+
[CLKID_PWM_I_SEL] = &s4_pwm_i_sel.hw,
2965
3390
[CLKID_PWM_I_DIV] = &s4_pwm_i_div.hw,
2966
-
[CLKID_PWM_I] = &s4_pwm_i_gate.hw,
2967
-
[CLKID_PWM_J_SEL] = &s4_pwm_j_mux.hw,
3391
+
[CLKID_PWM_I] = &s4_pwm_i.hw,
3392
+
[CLKID_PWM_J_SEL] = &s4_pwm_j_sel.hw,
2968
3393
[CLKID_PWM_J_DIV] = &s4_pwm_j_div.hw,
2969
-
[CLKID_PWM_J] = &s4_pwm_j_gate.hw,
2970
-
[CLKID_SARADC_SEL] = &s4_saradc_mux.hw,
3394
+
[CLKID_PWM_J] = &s4_pwm_j.hw,
3395
+
[CLKID_SARADC_SEL] = &s4_saradc_sel.hw,
2971
3396
[CLKID_SARADC_DIV] = &s4_saradc_div.hw,
2972
-
[CLKID_SARADC] = &s4_saradc_gate.hw,
3397
+
[CLKID_SARADC] = &s4_saradc.hw,
2973
3398
[CLKID_GEN_SEL] = &s4_gen_clk_sel.hw,
2974
3399
[CLKID_GEN_DIV] = &s4_gen_clk_div.hw,
2975
3400
[CLKID_GEN] = &s4_gen_clk.hw,
···
3022
3447
[CLKID_PWM_EF] = &s4_pwm_ef.hw,
3023
3448
[CLKID_PWM_GH] = &s4_pwm_gh.hw,
3024
3449
[CLKID_PWM_IJ] = &s4_pwm_ij.hw,
3025
-
[CLKID_HDCP22_ESMCLK_SEL] = &s4_hdcp22_esmclk_mux.hw,
3450
+
[CLKID_HDCP22_ESMCLK_SEL] = &s4_hdcp22_esmclk_sel.hw,
3026
3451
[CLKID_HDCP22_ESMCLK_DIV] = &s4_hdcp22_esmclk_div.hw,
3027
-
[CLKID_HDCP22_ESMCLK] = &s4_hdcp22_esmclk_gate.hw,
3028
-
[CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_mux.hw,
3452
+
[CLKID_HDCP22_ESMCLK] = &s4_hdcp22_esmclk.hw,
3453
+
[CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw,
3029
3454
[CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw,
3030
-
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk_gate.hw,
3455
+
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw,
3031
3456
};
3032
3457
3033
-
static const struct regmap_config clkc_regmap_config = {
3034
-
.reg_bits = 32,
3035
-
.val_bits = 32,
3036
-
.reg_stride = 4,
3037
-
.max_register = CLKCTRL_DEMOD_CLK_CTRL,
3458
+
static const struct meson_clkc_data s4_peripherals_clkc_data = {
3459
+
.hw_clks = {
3460
+
.hws = s4_peripherals_hw_clks,
3461
+
.num = ARRAY_SIZE(s4_peripherals_hw_clks),
3462
+
},
3038
3463
};
3039
3464
3040
-
static struct meson_clk_hw_data s4_periphs_clks = {
3041
-
.hws = s4_periphs_hw_clks,
3042
-
.num = ARRAY_SIZE(s4_periphs_hw_clks),
3043
-
};
3044
-
3045
-
static int meson_s4_periphs_probe(struct platform_device *pdev)
3046
-
{
3047
-
struct device *dev = &pdev->dev;
3048
-
struct regmap *regmap;
3049
-
void __iomem *base;
3050
-
int ret, i;
3051
-
3052
-
base = devm_platform_ioremap_resource(pdev, 0);
3053
-
if (IS_ERR(base))
3054
-
return dev_err_probe(dev, PTR_ERR(base),
3055
-
"can't ioremap resource\n");
3056
-
3057
-
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
3058
-
if (IS_ERR(regmap))
3059
-
return dev_err_probe(dev, PTR_ERR(regmap),
3060
-
"can't init regmap mmio region\n");
3061
-
3062
-
for (i = 0; i < s4_periphs_clks.num; i++) {
3063
-
/* array might be sparse */
3064
-
if (!s4_periphs_clks.hws[i])
3065
-
continue;
3066
-
3067
-
ret = devm_clk_hw_register(dev, s4_periphs_clks.hws[i]);
3068
-
if (ret)
3069
-
return dev_err_probe(dev, ret,
3070
-
"clock[%d] registration failed\n", i);
3071
-
}
3072
-
3073
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_periphs_clks);
3074
-
}
3075
-
3076
-
static const struct of_device_id clkc_match_table[] = {
3465
+
static const struct of_device_id s4_peripherals_clkc_match_table[] = {
3077
3466
{
3078
3467
.compatible = "amlogic,s4-peripherals-clkc",
3468
+
.data = &s4_peripherals_clkc_data,
3079
3469
},
3080
3470
{}
3081
3471
};
3082
-
MODULE_DEVICE_TABLE(of, clkc_match_table);
3472
+
MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table);
3083
3473
3084
-
static struct platform_driver s4_driver = {
3085
-
.probe = meson_s4_periphs_probe,
3474
+
static struct platform_driver s4_peripherals_clkc_driver = {
3475
+
.probe = meson_clkc_mmio_probe,
3086
3476
.driver = {
3087
-
.name = "s4-periphs-clkc",
3088
-
.of_match_table = clkc_match_table,
3477
+
.name = "s4-peripherals-clkc",
3478
+
.of_match_table = s4_peripherals_clkc_match_table,
3089
3479
},
3090
3480
};
3091
-
module_platform_driver(s4_driver);
3481
+
module_platform_driver(s4_peripherals_clkc_driver);
3092
3482
3093
3483
MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver");
3094
3484
MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
+21
-61
drivers/clk/meson/s4-pll.c
+21
-61
drivers/clk/meson/s4-pll.c
···
281
281
/*
282
282
* Internal gp0 pll emulation configuration parameters
283
283
*/
284
-
static const struct reg_sequence s4_gp0_init_regs[] = {
284
+
static const struct reg_sequence s4_gp0_pll_init_regs[] = {
285
285
{ .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
286
286
{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
287
287
{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
···
318
318
.width = 1,
319
319
},
320
320
.range = &s4_gp0_pll_mult_range,
321
-
.init_regs = s4_gp0_init_regs,
322
-
.init_count = ARRAY_SIZE(s4_gp0_init_regs),
321
+
.init_regs = s4_gp0_pll_init_regs,
322
+
.init_count = ARRAY_SIZE(s4_gp0_pll_init_regs),
323
323
},
324
324
.hw.init = &(struct clk_init_data){
325
325
.name = "gp0_pll_dco",
···
353
353
/*
354
354
* Internal hifi pll emulation configuration parameters
355
355
*/
356
-
static const struct reg_sequence s4_hifi_init_regs[] = {
356
+
static const struct reg_sequence s4_hifi_pll_init_regs[] = {
357
357
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
358
358
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
359
359
{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
···
394
394
.width = 1,
395
395
},
396
396
.range = &s4_gp0_pll_mult_range,
397
-
.init_regs = s4_hifi_init_regs,
398
-
.init_count = ARRAY_SIZE(s4_hifi_init_regs),
397
+
.init_regs = s4_hifi_pll_init_regs,
398
+
.init_count = ARRAY_SIZE(s4_hifi_pll_init_regs),
399
399
.frac_max = 100000,
400
400
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
401
401
},
···
794
794
[CLKID_MPLL3] = &s4_mpll3.hw,
795
795
};
796
796
797
-
static const struct reg_sequence s4_init_regs[] = {
797
+
static const struct reg_sequence s4_pll_init_regs[] = {
798
798
{ .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
799
799
};
800
800
801
-
static const struct regmap_config clkc_regmap_config = {
802
-
.reg_bits = 32,
803
-
.val_bits = 32,
804
-
.reg_stride = 4,
805
-
.max_register = ANACTRL_HDMIPLL_CTRL0,
801
+
static const struct meson_clkc_data s4_pll_clkc_data = {
802
+
.hw_clks = {
803
+
.hws = s4_pll_hw_clks,
804
+
.num = ARRAY_SIZE(s4_pll_hw_clks),
805
+
},
806
+
.init_regs = s4_pll_init_regs,
807
+
.init_count = ARRAY_SIZE(s4_pll_init_regs),
806
808
};
807
809
808
-
static struct meson_clk_hw_data s4_pll_clks = {
809
-
.hws = s4_pll_hw_clks,
810
-
.num = ARRAY_SIZE(s4_pll_hw_clks),
811
-
};
812
-
813
-
static int meson_s4_pll_probe(struct platform_device *pdev)
814
-
{
815
-
struct device *dev = &pdev->dev;
816
-
struct regmap *regmap;
817
-
void __iomem *base;
818
-
int ret, i;
819
-
820
-
base = devm_platform_ioremap_resource(pdev, 0);
821
-
if (IS_ERR(base))
822
-
return dev_err_probe(dev, PTR_ERR(base),
823
-
"can't ioremap resource\n");
824
-
825
-
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
826
-
if (IS_ERR(regmap))
827
-
return dev_err_probe(dev, PTR_ERR(regmap),
828
-
"can't init regmap mmio region\n");
829
-
830
-
ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
831
-
if (ret)
832
-
return dev_err_probe(dev, ret,
833
-
"Failed to init registers\n");
834
-
835
-
/* Register clocks */
836
-
for (i = 0; i < s4_pll_clks.num; i++) {
837
-
/* array might be sparse */
838
-
if (!s4_pll_clks.hws[i])
839
-
continue;
840
-
841
-
ret = devm_clk_hw_register(dev, s4_pll_clks.hws[i]);
842
-
if (ret)
843
-
return dev_err_probe(dev, ret,
844
-
"clock[%d] registration failed\n", i);
845
-
}
846
-
847
-
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
848
-
&s4_pll_clks);
849
-
}
850
-
851
-
static const struct of_device_id clkc_match_table[] = {
810
+
static const struct of_device_id s4_pll_clkc_match_table[] = {
852
811
{
853
812
.compatible = "amlogic,s4-pll-clkc",
813
+
.data = &s4_pll_clkc_data,
854
814
},
855
815
{}
856
816
};
857
-
MODULE_DEVICE_TABLE(of, clkc_match_table);
817
+
MODULE_DEVICE_TABLE(of, s4_pll_clkc_match_table);
858
818
859
-
static struct platform_driver s4_driver = {
860
-
.probe = meson_s4_pll_probe,
819
+
static struct platform_driver s4_pll_clkc_driver = {
820
+
.probe = meson_clkc_mmio_probe,
861
821
.driver = {
862
822
.name = "s4-pll-clkc",
863
-
.of_match_table = clkc_match_table,
823
+
.of_match_table = s4_pll_clkc_match_table,
864
824
},
865
825
};
866
-
module_platform_driver(s4_driver);
826
+
module_platform_driver(s4_pll_clkc_driver);
867
827
868
828
MODULE_DESCRIPTION("Amlogic S4 PLL Clock Controller driver");
869
829
MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
+1
drivers/clk/samsung/Makefile
+1
drivers/clk/samsung/Makefile
···
13
13
obj-$(CONFIG_EXYNOS_5410_COMMON_CLK) += clk-exynos5410.o
14
14
obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5420.o
15
15
obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
16
+
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-artpec8.o
16
17
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
17
18
obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
18
19
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
+1044
drivers/clk/samsung/clk-artpec8.c
+1044
drivers/clk/samsung/clk-artpec8.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
4
+
* https://www.samsung.com
5
+
* Copyright (c) 2025 Axis Communications AB.
6
+
* https://www.axis.com
7
+
*
8
+
* Common Clock Framework support for ARTPEC-8 SoC.
9
+
*/
10
+
11
+
#include <linux/clk-provider.h>
12
+
#include <linux/platform_device.h>
13
+
#include <dt-bindings/clock/axis,artpec8-clk.h>
14
+
15
+
#include "clk.h"
16
+
#include "clk-exynos-arm64.h"
17
+
18
+
/* NOTE: Must be equal to the last clock ID increased by one */
19
+
#define CMU_CMU_NR_CLK (CLK_DOUT_CMU_VPP_CORE + 1)
20
+
#define CMU_BUS_NR_CLK (CLK_DOUT_BUS_PCLK + 1)
21
+
#define CMU_CORE_NR_CLK (CLK_DOUT_CORE_PCLK + 1)
22
+
#define CMU_CPUCL_NR_CLK (CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK + 1)
23
+
#define CMU_FSYS_NR_CLK (CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK + 1)
24
+
#define CMU_IMEM_NR_CLK (CLK_GOUT_IMEM_PCLK_TMU0_APBIF + 1)
25
+
#define CMU_PERI_NR_CLK (CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK + 1)
26
+
27
+
/* Register Offset definitions for CMU_CMU (0x12400000) */
28
+
#define PLL_LOCKTIME_PLL_AUDIO 0x0000
29
+
#define PLL_LOCKTIME_PLL_SHARED0 0x0004
30
+
#define PLL_LOCKTIME_PLL_SHARED1 0x0008
31
+
#define PLL_CON0_PLL_AUDIO 0x0100
32
+
#define PLL_CON0_PLL_SHARED0 0x0120
33
+
#define PLL_CON0_PLL_SHARED1 0x0140
34
+
#define CLK_CON_MUX_CLKCMU_2D 0x1000
35
+
#define CLK_CON_MUX_CLKCMU_3D 0x1004
36
+
#define CLK_CON_MUX_CLKCMU_BUS 0x1008
37
+
#define CLK_CON_MUX_CLKCMU_BUS_DLP 0x100c
38
+
#define CLK_CON_MUX_CLKCMU_CDC_CORE 0x1010
39
+
#define CLK_CON_MUX_CLKCMU_FSYS_SCAN0 0x1014
40
+
#define CLK_CON_MUX_CLKCMU_FSYS_SCAN1 0x1018
41
+
#define CLK_CON_MUX_CLKCMU_IMEM_JPEG 0x101c
42
+
#define CLK_CON_MUX_CLKCMU_PERI_DISP 0x1020
43
+
#define CLK_CON_MUX_CLKCMU_CORE_BUS 0x1024
44
+
#define CLK_CON_MUX_CLKCMU_CORE_DLP 0x1028
45
+
#define CLK_CON_MUX_CLKCMU_CPUCL_SWITCH 0x1030
46
+
#define CLK_CON_MUX_CLKCMU_DLP_CORE 0x1034
47
+
#define CLK_CON_MUX_CLKCMU_FSYS_BUS 0x1038
48
+
#define CLK_CON_MUX_CLKCMU_FSYS_IP 0x103c
49
+
#define CLK_CON_MUX_CLKCMU_IMEM_ACLK 0x1054
50
+
#define CLK_CON_MUX_CLKCMU_MIF_BUSP 0x1080
51
+
#define CLK_CON_MUX_CLKCMU_MIF_SWITCH 0x1084
52
+
#define CLK_CON_MUX_CLKCMU_PERI_IP 0x1088
53
+
#define CLK_CON_MUX_CLKCMU_RSP_CORE 0x108c
54
+
#define CLK_CON_MUX_CLKCMU_TRFM_CORE 0x1090
55
+
#define CLK_CON_MUX_CLKCMU_VCA_ACE 0x1094
56
+
#define CLK_CON_MUX_CLKCMU_VCA_OD 0x1098
57
+
#define CLK_CON_MUX_CLKCMU_VIO_CORE 0x109c
58
+
#define CLK_CON_MUX_CLKCMU_VIP0_CORE 0x10a0
59
+
#define CLK_CON_MUX_CLKCMU_VIP1_CORE 0x10a4
60
+
#define CLK_CON_MUX_CLKCMU_VPP_CORE 0x10a8
61
+
62
+
#define CLK_CON_DIV_CLKCMU_BUS 0x1800
63
+
#define CLK_CON_DIV_CLKCMU_BUS_DLP 0x1804
64
+
#define CLK_CON_DIV_CLKCMU_CDC_CORE 0x1808
65
+
#define CLK_CON_DIV_CLKCMU_FSYS_SCAN0 0x180c
66
+
#define CLK_CON_DIV_CLKCMU_FSYS_SCAN1 0x1810
67
+
#define CLK_CON_DIV_CLKCMU_IMEM_JPEG 0x1814
68
+
#define CLK_CON_DIV_CLKCMU_MIF_SWITCH 0x1818
69
+
#define CLK_CON_DIV_CLKCMU_CORE_DLP 0x181c
70
+
#define CLK_CON_DIV_CLKCMU_CORE_MAIN 0x1820
71
+
#define CLK_CON_DIV_CLKCMU_PERI_DISP 0x1824
72
+
#define CLK_CON_DIV_CLKCMU_CPUCL_SWITCH 0x1828
73
+
#define CLK_CON_DIV_CLKCMU_DLP_CORE 0x182c
74
+
#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1830
75
+
#define CLK_CON_DIV_CLKCMU_FSYS_IP 0x1834
76
+
#define CLK_CON_DIV_CLKCMU_VIO_AUDIO 0x1838
77
+
#define CLK_CON_DIV_CLKCMU_GPU_2D 0x1848
78
+
#define CLK_CON_DIV_CLKCMU_GPU_3D 0x184c
79
+
#define CLK_CON_DIV_CLKCMU_IMEM_ACLK 0x1854
80
+
#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1884
81
+
#define CLK_CON_DIV_CLKCMU_PERI_AUDIO 0x1890
82
+
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1894
83
+
#define CLK_CON_DIV_CLKCMU_RSP_CORE 0x1898
84
+
#define CLK_CON_DIV_CLKCMU_TRFM_CORE 0x189c
85
+
#define CLK_CON_DIV_CLKCMU_VCA_ACE 0x18a0
86
+
#define CLK_CON_DIV_CLKCMU_VCA_OD 0x18a4
87
+
#define CLK_CON_DIV_CLKCMU_VIO_CORE 0x18ac
88
+
#define CLK_CON_DIV_CLKCMU_VIP0_CORE 0x18b0
89
+
#define CLK_CON_DIV_CLKCMU_VIP1_CORE 0x18b4
90
+
#define CLK_CON_DIV_CLKCMU_VPP_CORE 0x18b8
91
+
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18bc
92
+
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18c0
93
+
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18c4
94
+
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c8
95
+
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18cc
96
+
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18d0
97
+
98
+
static const unsigned long cmu_cmu_clk_regs[] __initconst = {
99
+
PLL_LOCKTIME_PLL_AUDIO,
100
+
PLL_LOCKTIME_PLL_SHARED0,
101
+
PLL_LOCKTIME_PLL_SHARED1,
102
+
PLL_CON0_PLL_AUDIO,
103
+
PLL_CON0_PLL_SHARED0,
104
+
PLL_CON0_PLL_SHARED1,
105
+
CLK_CON_MUX_CLKCMU_2D,
106
+
CLK_CON_MUX_CLKCMU_3D,
107
+
CLK_CON_MUX_CLKCMU_BUS,
108
+
CLK_CON_MUX_CLKCMU_BUS_DLP,
109
+
CLK_CON_MUX_CLKCMU_CDC_CORE,
110
+
CLK_CON_MUX_CLKCMU_FSYS_SCAN0,
111
+
CLK_CON_MUX_CLKCMU_FSYS_SCAN1,
112
+
CLK_CON_MUX_CLKCMU_IMEM_JPEG,
113
+
CLK_CON_MUX_CLKCMU_PERI_DISP,
114
+
CLK_CON_MUX_CLKCMU_CORE_BUS,
115
+
CLK_CON_MUX_CLKCMU_CORE_DLP,
116
+
CLK_CON_MUX_CLKCMU_CPUCL_SWITCH,
117
+
CLK_CON_MUX_CLKCMU_DLP_CORE,
118
+
CLK_CON_MUX_CLKCMU_FSYS_BUS,
119
+
CLK_CON_MUX_CLKCMU_FSYS_IP,
120
+
CLK_CON_MUX_CLKCMU_IMEM_ACLK,
121
+
CLK_CON_MUX_CLKCMU_MIF_BUSP,
122
+
CLK_CON_MUX_CLKCMU_MIF_SWITCH,
123
+
CLK_CON_MUX_CLKCMU_PERI_IP,
124
+
CLK_CON_MUX_CLKCMU_RSP_CORE,
125
+
CLK_CON_MUX_CLKCMU_TRFM_CORE,
126
+
CLK_CON_MUX_CLKCMU_VCA_ACE,
127
+
CLK_CON_MUX_CLKCMU_VCA_OD,
128
+
CLK_CON_MUX_CLKCMU_VIO_CORE,
129
+
CLK_CON_MUX_CLKCMU_VIP0_CORE,
130
+
CLK_CON_MUX_CLKCMU_VIP1_CORE,
131
+
CLK_CON_MUX_CLKCMU_VPP_CORE,
132
+
CLK_CON_DIV_CLKCMU_BUS,
133
+
CLK_CON_DIV_CLKCMU_BUS_DLP,
134
+
CLK_CON_DIV_CLKCMU_CDC_CORE,
135
+
CLK_CON_DIV_CLKCMU_FSYS_SCAN0,
136
+
CLK_CON_DIV_CLKCMU_FSYS_SCAN1,
137
+
CLK_CON_DIV_CLKCMU_IMEM_JPEG,
138
+
CLK_CON_DIV_CLKCMU_MIF_SWITCH,
139
+
CLK_CON_DIV_CLKCMU_CORE_DLP,
140
+
CLK_CON_DIV_CLKCMU_CORE_MAIN,
141
+
CLK_CON_DIV_CLKCMU_PERI_DISP,
142
+
CLK_CON_DIV_CLKCMU_CPUCL_SWITCH,
143
+
CLK_CON_DIV_CLKCMU_DLP_CORE,
144
+
CLK_CON_DIV_CLKCMU_FSYS_BUS,
145
+
CLK_CON_DIV_CLKCMU_FSYS_IP,
146
+
CLK_CON_DIV_CLKCMU_VIO_AUDIO,
147
+
CLK_CON_DIV_CLKCMU_GPU_2D,
148
+
CLK_CON_DIV_CLKCMU_GPU_3D,
149
+
CLK_CON_DIV_CLKCMU_IMEM_ACLK,
150
+
CLK_CON_DIV_CLKCMU_MIF_BUSP,
151
+
CLK_CON_DIV_CLKCMU_PERI_AUDIO,
152
+
CLK_CON_DIV_CLKCMU_PERI_IP,
153
+
CLK_CON_DIV_CLKCMU_RSP_CORE,
154
+
CLK_CON_DIV_CLKCMU_TRFM_CORE,
155
+
CLK_CON_DIV_CLKCMU_VCA_ACE,
156
+
CLK_CON_DIV_CLKCMU_VCA_OD,
157
+
CLK_CON_DIV_CLKCMU_VIO_CORE,
158
+
CLK_CON_DIV_CLKCMU_VIP0_CORE,
159
+
CLK_CON_DIV_CLKCMU_VIP1_CORE,
160
+
CLK_CON_DIV_CLKCMU_VPP_CORE,
161
+
CLK_CON_DIV_PLL_SHARED0_DIV2,
162
+
CLK_CON_DIV_PLL_SHARED0_DIV3,
163
+
CLK_CON_DIV_PLL_SHARED0_DIV4,
164
+
CLK_CON_DIV_PLL_SHARED1_DIV2,
165
+
CLK_CON_DIV_PLL_SHARED1_DIV3,
166
+
CLK_CON_DIV_PLL_SHARED1_DIV4,
167
+
};
168
+
169
+
static const struct samsung_pll_rate_table artpec8_pll_audio_rates[] __initconst = {
170
+
PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184),
171
+
PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184),
172
+
PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184),
173
+
PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0),
174
+
PLL_36XX_RATE(25 * MHZ, 98303985U, 47, 3, 2, 12184),
175
+
PLL_36XX_RATE(25 * MHZ, 49151992U, 47, 3, 3, 12184),
176
+
};
177
+
178
+
static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst = {
179
+
PLL(pll_1017x, CLK_FOUT_SHARED0_PLL, "fout_pll_shared0", "fin_pll",
180
+
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL),
181
+
PLL(pll_1017x, CLK_FOUT_SHARED1_PLL, "fout_pll_shared1", "fin_pll",
182
+
PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL),
183
+
PLL(pll_1031x, CLK_FOUT_AUDIO_PLL, "fout_pll_audio", "fin_pll",
184
+
PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec8_pll_audio_rates),
185
+
};
186
+
187
+
PNAME(mout_clkcmu_bus_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
188
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
189
+
PNAME(mout_clkcmu_bus_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div4",
190
+
"dout_pll_shared1_div2", "dout_pll_shared1_div4" };
191
+
PNAME(mout_clkcmu_core_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
192
+
"dout_pll_shared0_div4", "dout_pll_shared1_div3" };
193
+
PNAME(mout_clkcmu_core_dlp_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
194
+
"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
195
+
PNAME(mout_clkcmu_cpucl_switch_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
196
+
"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
197
+
PNAME(mout_clkcmu_fsys_bus_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
198
+
"dout_pll_shared1_div4", "dout_pll_shared1_div3" };
199
+
PNAME(mout_clkcmu_fsys_ip_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div3",
200
+
"dout_pll_shared1_div2", "dout_pll_shared0_div3" };
201
+
PNAME(mout_clkcmu_fsys_scan0_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
202
+
PNAME(mout_clkcmu_fsys_scan1_p) = { "dout_pll_shared0_div4", "dout_pll_shared1_div4" };
203
+
PNAME(mout_clkcmu_imem_imem_p) = { "dout_pll_shared1_div4", "dout_pll_shared0_div3",
204
+
"dout_pll_shared1_div3", "dout_pll_shared1_div2" };
205
+
PNAME(mout_clkcmu_imem_jpeg_p) = { "dout_pll_shared0_div2", "dout_pll_shared0_div3",
206
+
"dout_pll_shared1_div2", "dout_pll_shared1_div3" };
207
+
PNAME(mout_clkcmu_cdc_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
208
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
209
+
PNAME(mout_clkcmu_dlp_core_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
210
+
"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
211
+
PNAME(mout_clkcmu_3d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
212
+
"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
213
+
PNAME(mout_clkcmu_2d_p) = { "dout_pll_shared0_div2", "dout_pll_shared1_div2",
214
+
"dout_pll_shared0_div3", "dout_pll_shared1_div3" };
215
+
PNAME(mout_clkcmu_mif_switch_p) = { "dout_pll_shared0", "dout_pll_shared1",
216
+
"dout_pll_shared0_div2", "dout_pll_shared0_div3" };
217
+
PNAME(mout_clkcmu_mif_busp_p) = { "dout_pll_shared0_div3", "dout_pll_shared1_div4",
218
+
"dout_pll_shared0_div4", "dout_pll_shared0_div2" };
219
+
PNAME(mout_clkcmu_peri_disp_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div2",
220
+
"dout_pll_shared1_div4", "dout_pll_shared1_div3" };
221
+
PNAME(mout_clkcmu_peri_ip_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div4",
222
+
"dout_pll_shared1_div4", "dout_pll_shared0_div2" };
223
+
PNAME(mout_clkcmu_rsp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
224
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
225
+
PNAME(mout_clkcmu_trfm_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
226
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
227
+
PNAME(mout_clkcmu_vca_ace_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
228
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
229
+
PNAME(mout_clkcmu_vca_od_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
230
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
231
+
PNAME(mout_clkcmu_vio_core_p) = { "dout_pll_shared0_div3", "dout_pll_shared0_div2",
232
+
"dout_pll_shared1_div2", "dout_pll_shared1_div3" };
233
+
PNAME(mout_clkcmu_vip0_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
234
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
235
+
PNAME(mout_clkcmu_vip1_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
236
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
237
+
PNAME(mout_clkcmu_vpp_core_p) = { "dout_pll_shared1_div2", "dout_pll_shared0_div3",
238
+
"dout_pll_shared1_div3", "dout_pll_shared1_div4" };
239
+
PNAME(mout_clkcmu_pll_shared0_p) = { "fin_pll", "fout_pll_shared0" };
240
+
PNAME(mout_clkcmu_pll_shared1_p) = { "fin_pll", "fout_pll_shared1" };
241
+
PNAME(mout_clkcmu_pll_audio_p) = { "fin_pll", "fout_pll_audio" };
242
+
243
+
static const struct samsung_fixed_factor_clock cmu_fixed_factor_clks[] __initconst = {
244
+
FFACTOR(CLK_DOUT_CMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0),
245
+
};
246
+
247
+
static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst = {
248
+
MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1),
249
+
MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, PLL_CON0_PLL_SHARED1, 4, 1),
250
+
MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, PLL_CON0_PLL_AUDIO, 4, 1),
251
+
MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, CLK_CON_MUX_CLKCMU_BUS, 0, 2),
252
+
MUX(0, "mout_clkcmu_bus_dlp", mout_clkcmu_bus_dlp_p, CLK_CON_MUX_CLKCMU_BUS_DLP, 0, 2),
253
+
MUX(0, "mout_clkcmu_core_bus", mout_clkcmu_core_bus_p, CLK_CON_MUX_CLKCMU_CORE_BUS, 0, 2),
254
+
MUX(0, "mout_clkcmu_core_dlp", mout_clkcmu_core_dlp_p, CLK_CON_MUX_CLKCMU_CORE_DLP, 0, 2),
255
+
MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p,
256
+
CLK_CON_MUX_CLKCMU_CPUCL_SWITCH, 0, 3),
257
+
MUX(0, "mout_clkcmu_fsys_bus", mout_clkcmu_fsys_bus_p, CLK_CON_MUX_CLKCMU_FSYS_BUS, 0, 2),
258
+
MUX(0, "mout_clkcmu_fsys_ip", mout_clkcmu_fsys_ip_p, CLK_CON_MUX_CLKCMU_FSYS_IP, 0, 2),
259
+
MUX(0, "mout_clkcmu_fsys_scan0", mout_clkcmu_fsys_scan0_p,
260
+
CLK_CON_MUX_CLKCMU_FSYS_SCAN0, 0, 1),
261
+
MUX(0, "mout_clkcmu_fsys_scan1", mout_clkcmu_fsys_scan1_p,
262
+
CLK_CON_MUX_CLKCMU_FSYS_SCAN1, 0, 1),
263
+
MUX(0, "mout_clkcmu_imem_imem", mout_clkcmu_imem_imem_p,
264
+
CLK_CON_MUX_CLKCMU_IMEM_ACLK, 0, 2),
265
+
MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p,
266
+
CLK_CON_MUX_CLKCMU_IMEM_JPEG, 0, 2),
267
+
nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, CLK_CON_MUX_CLKCMU_CDC_CORE, 0, 2),
268
+
nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, CLK_CON_MUX_CLKCMU_DLP_CORE, 0, 2),
269
+
MUX(0, "mout_clkcmu_3d", mout_clkcmu_3d_p, CLK_CON_MUX_CLKCMU_3D, 0, 2),
270
+
MUX(0, "mout_clkcmu_2d", mout_clkcmu_2d_p, CLK_CON_MUX_CLKCMU_2D, 0, 2),
271
+
MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p,
272
+
CLK_CON_MUX_CLKCMU_MIF_SWITCH, 0, 2),
273
+
MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, CLK_CON_MUX_CLKCMU_MIF_BUSP, 0, 2),
274
+
MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p,
275
+
CLK_CON_MUX_CLKCMU_PERI_DISP, 0, 2),
276
+
MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, CLK_CON_MUX_CLKCMU_PERI_IP, 0, 2),
277
+
MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, CLK_CON_MUX_CLKCMU_RSP_CORE, 0, 2),
278
+
nMUX(0, "mout_clkcmu_trfm_core", mout_clkcmu_trfm_core_p,
279
+
CLK_CON_MUX_CLKCMU_TRFM_CORE, 0, 2),
280
+
MUX(0, "mout_clkcmu_vca_ace", mout_clkcmu_vca_ace_p, CLK_CON_MUX_CLKCMU_VCA_ACE, 0, 2),
281
+
MUX(0, "mout_clkcmu_vca_od", mout_clkcmu_vca_od_p, CLK_CON_MUX_CLKCMU_VCA_OD, 0, 2),
282
+
MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, CLK_CON_MUX_CLKCMU_VIO_CORE, 0, 2),
283
+
nMUX(0, "mout_clkcmu_vip0_core", mout_clkcmu_vip0_core_p,
284
+
CLK_CON_MUX_CLKCMU_VIP0_CORE, 0, 2),
285
+
nMUX(0, "mout_clkcmu_vip1_core", mout_clkcmu_vip1_core_p,
286
+
CLK_CON_MUX_CLKCMU_VIP1_CORE, 0, 2),
287
+
nMUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, CLK_CON_MUX_CLKCMU_VPP_CORE, 0, 2),
288
+
};
289
+
290
+
static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst = {
291
+
DIV(CLK_DOUT_SHARED0_DIV2, "dout_pll_shared0_div2",
292
+
"mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
293
+
DIV(CLK_DOUT_SHARED0_DIV3, "dout_pll_shared0_div3",
294
+
"mout_clkcmu_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
295
+
DIV(CLK_DOUT_SHARED0_DIV4, "dout_pll_shared0_div4",
296
+
"dout_pll_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
297
+
DIV(CLK_DOUT_SHARED1_DIV2, "dout_pll_shared1_div2",
298
+
"mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
299
+
DIV(CLK_DOUT_SHARED1_DIV3, "dout_pll_shared1_div3",
300
+
"mout_clkcmu_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
301
+
DIV(CLK_DOUT_SHARED1_DIV4, "dout_pll_shared1_div4",
302
+
"dout_pll_shared1_div2", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
303
+
DIV(CLK_DOUT_CMU_BUS, "dout_clkcmu_bus",
304
+
"mout_clkcmu_bus_bus", CLK_CON_DIV_CLKCMU_BUS, 0, 4),
305
+
DIV(CLK_DOUT_CMU_BUS_DLP, "dout_clkcmu_bus_dlp",
306
+
"mout_clkcmu_bus_dlp", CLK_CON_DIV_CLKCMU_BUS_DLP, 0, 4),
307
+
DIV(CLK_DOUT_CMU_CORE_MAIN, "dout_clkcmu_core_main",
308
+
"mout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_MAIN, 0, 4),
309
+
DIV(CLK_DOUT_CMU_CORE_DLP, "dout_clkcmu_core_dlp",
310
+
"mout_clkcmu_core_dlp", CLK_CON_DIV_CLKCMU_CORE_DLP, 0, 4),
311
+
DIV(CLK_DOUT_CMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch",
312
+
"mout_clkcmu_cpucl_switch", CLK_CON_DIV_CLKCMU_CPUCL_SWITCH, 0, 3),
313
+
DIV(CLK_DOUT_CMU_FSYS_BUS, "dout_clkcmu_fsys_bus",
314
+
"mout_clkcmu_fsys_bus", CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
315
+
DIV(CLK_DOUT_CMU_FSYS_IP, "dout_clkcmu_fsys_ip",
316
+
"mout_clkcmu_fsys_ip", CLK_CON_DIV_CLKCMU_FSYS_IP, 0, 9),
317
+
DIV(CLK_DOUT_CMU_FSYS_SCAN0, "dout_clkcmu_fsys_scan0",
318
+
"mout_clkcmu_fsys_scan0", CLK_CON_DIV_CLKCMU_FSYS_SCAN0, 0, 4),
319
+
DIV(CLK_DOUT_CMU_FSYS_SCAN1, "dout_clkcmu_fsys_scan1",
320
+
"mout_clkcmu_fsys_scan1", CLK_CON_DIV_CLKCMU_FSYS_SCAN1, 0, 4),
321
+
DIV(CLK_DOUT_CMU_IMEM_ACLK, "dout_clkcmu_imem_aclk",
322
+
"mout_clkcmu_imem_imem", CLK_CON_DIV_CLKCMU_IMEM_ACLK, 0, 4),
323
+
DIV(CLK_DOUT_CMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg",
324
+
"mout_clkcmu_imem_jpeg", CLK_CON_DIV_CLKCMU_IMEM_JPEG, 0, 4),
325
+
DIV_F(CLK_DOUT_CMU_CDC_CORE, "dout_clkcmu_cdc_core",
326
+
"mout_clkcmu_cdc_core", CLK_CON_DIV_CLKCMU_CDC_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
327
+
DIV_F(CLK_DOUT_CMU_DLP_CORE, "dout_clkcmu_dlp_core",
328
+
"mout_clkcmu_dlp_core", CLK_CON_DIV_CLKCMU_DLP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
329
+
DIV(CLK_DOUT_CMU_GPU_3D, "dout_clkcmu_gpu_3d",
330
+
"mout_clkcmu_3d", CLK_CON_DIV_CLKCMU_GPU_3D, 0, 3),
331
+
DIV(CLK_DOUT_CMU_GPU_2D, "dout_clkcmu_gpu_2d",
332
+
"mout_clkcmu_2d", CLK_CON_DIV_CLKCMU_GPU_2D, 0, 4),
333
+
DIV(CLK_DOUT_CMU_MIF_SWITCH, "dout_clkcmu_mif_switch",
334
+
"mout_clkcmu_mif_switch", CLK_CON_DIV_CLKCMU_MIF_SWITCH, 0, 4),
335
+
DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_clkcmu_mif_busp",
336
+
"mout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3),
337
+
DIV(CLK_DOUT_CMU_PERI_DISP, "dout_clkcmu_peri_disp",
338
+
"mout_clkcmu_peri_disp", CLK_CON_DIV_CLKCMU_PERI_DISP, 0, 4),
339
+
DIV(CLK_DOUT_CMU_PERI_IP, "dout_clkcmu_peri_ip",
340
+
"mout_clkcmu_peri_ip", CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
341
+
DIV(CLK_DOUT_CMU_PERI_AUDIO, "dout_clkcmu_peri_audio",
342
+
"mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_PERI_AUDIO, 0, 4),
343
+
DIV(CLK_DOUT_CMU_RSP_CORE, "dout_clkcmu_rsp_core",
344
+
"mout_clkcmu_rsp_core", CLK_CON_DIV_CLKCMU_RSP_CORE, 0, 4),
345
+
DIV_F(CLK_DOUT_CMU_TRFM_CORE, "dout_clkcmu_trfm_core",
346
+
"mout_clkcmu_trfm_core", CLK_CON_DIV_CLKCMU_TRFM_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
347
+
DIV(CLK_DOUT_CMU_VCA_ACE, "dout_clkcmu_vca_ace",
348
+
"mout_clkcmu_vca_ace", CLK_CON_DIV_CLKCMU_VCA_ACE, 0, 4),
349
+
DIV(CLK_DOUT_CMU_VCA_OD, "dout_clkcmu_vca_od",
350
+
"mout_clkcmu_vca_od", CLK_CON_DIV_CLKCMU_VCA_OD, 0, 4),
351
+
DIV(CLK_DOUT_CMU_VIO_CORE, "dout_clkcmu_vio_core",
352
+
"mout_clkcmu_vio_core", CLK_CON_DIV_CLKCMU_VIO_CORE, 0, 4),
353
+
DIV(CLK_DOUT_CMU_VIO_AUDIO, "dout_clkcmu_vio_audio",
354
+
"mout_clkcmu_pll_audio", CLK_CON_DIV_CLKCMU_VIO_AUDIO, 0, 4),
355
+
DIV_F(CLK_DOUT_CMU_VIP0_CORE, "dout_clkcmu_vip0_core",
356
+
"mout_clkcmu_vip0_core", CLK_CON_DIV_CLKCMU_VIP0_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
357
+
DIV_F(CLK_DOUT_CMU_VIP1_CORE, "dout_clkcmu_vip1_core",
358
+
"mout_clkcmu_vip1_core", CLK_CON_DIV_CLKCMU_VIP1_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
359
+
DIV_F(CLK_DOUT_CMU_VPP_CORE, "dout_clkcmu_vpp_core",
360
+
"mout_clkcmu_vpp_core", CLK_CON_DIV_CLKCMU_VPP_CORE, 0, 4, CLK_SET_RATE_PARENT, 0),
361
+
};
362
+
363
+
static const struct samsung_cmu_info cmu_cmu_info __initconst = {
364
+
.pll_clks = cmu_cmu_pll_clks,
365
+
.nr_pll_clks = ARRAY_SIZE(cmu_cmu_pll_clks),
366
+
.fixed_factor_clks = cmu_fixed_factor_clks,
367
+
.nr_fixed_factor_clks = ARRAY_SIZE(cmu_fixed_factor_clks),
368
+
.mux_clks = cmu_cmu_mux_clks,
369
+
.nr_mux_clks = ARRAY_SIZE(cmu_cmu_mux_clks),
370
+
.div_clks = cmu_cmu_div_clks,
371
+
.nr_div_clks = ARRAY_SIZE(cmu_cmu_div_clks),
372
+
.nr_clk_ids = CMU_CMU_NR_CLK,
373
+
.clk_regs = cmu_cmu_clk_regs,
374
+
.nr_clk_regs = ARRAY_SIZE(cmu_cmu_clk_regs),
375
+
};
376
+
377
+
/* Register Offset definitions for CMU_BUS (0x12c10000) */
378
+
#define PLL_CON0_MUX_CLK_BUS_ACLK_USER 0x0100
379
+
#define PLL_CON0_MUX_CLK_BUS_DLP_USER 0x0120
380
+
#define CLK_CON_DIV_CLK_BUS_PCLK 0x1800
381
+
382
+
static const unsigned long cmu_bus_clk_regs[] __initconst = {
383
+
PLL_CON0_MUX_CLK_BUS_ACLK_USER,
384
+
PLL_CON0_MUX_CLK_BUS_DLP_USER,
385
+
CLK_CON_DIV_CLK_BUS_PCLK,
386
+
};
387
+
388
+
PNAME(mout_clk_bus_aclk_user_p) = { "fin_pll", "dout_clkcmu_bus" };
389
+
PNAME(mout_clk_bus_dlp_user_p) = { "fin_pll", "dout_clkcmu_bus_dlp" };
390
+
391
+
static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst = {
392
+
MUX(CLK_MOUT_BUS_ACLK_USER, "mout_clk_bus_aclk_user",
393
+
mout_clk_bus_aclk_user_p, PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1),
394
+
MUX(CLK_MOUT_BUS_DLP_USER, "mout_clk_bus_dlp_user",
395
+
mout_clk_bus_dlp_user_p, PLL_CON0_MUX_CLK_BUS_DLP_USER, 4, 1),
396
+
};
397
+
398
+
static const struct samsung_div_clock cmu_bus_div_clks[] __initconst = {
399
+
DIV(CLK_DOUT_BUS_PCLK, "dout_clk_bus_pclk", "mout_clk_bus_aclk_user",
400
+
CLK_CON_DIV_CLK_BUS_PCLK, 0, 4),
401
+
};
402
+
403
+
static const struct samsung_cmu_info cmu_bus_info __initconst = {
404
+
.mux_clks = cmu_bus_mux_clks,
405
+
.nr_mux_clks = ARRAY_SIZE(cmu_bus_mux_clks),
406
+
.div_clks = cmu_bus_div_clks,
407
+
.nr_div_clks = ARRAY_SIZE(cmu_bus_div_clks),
408
+
.nr_clk_ids = CMU_BUS_NR_CLK,
409
+
.clk_regs = cmu_bus_clk_regs,
410
+
.nr_clk_regs = ARRAY_SIZE(cmu_bus_clk_regs),
411
+
};
412
+
413
+
/* Register Offset definitions for CMU_CORE (0x12410000) */
414
+
#define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100
415
+
#define PLL_CON0_MUX_CLK_CORE_DLP_USER 0x0120
416
+
#define CLK_CON_DIV_CLK_CORE_PCLK 0x1800
417
+
418
+
static const unsigned long cmu_core_clk_regs[] __initconst = {
419
+
PLL_CON0_MUX_CLK_CORE_ACLK_USER,
420
+
PLL_CON0_MUX_CLK_CORE_DLP_USER,
421
+
CLK_CON_DIV_CLK_CORE_PCLK,
422
+
};
423
+
424
+
PNAME(mout_clk_core_aclk_user_p) = { "fin_pll", "dout_clkcmu_core_main" };
425
+
PNAME(mout_clk_core_dlp_user_p) = { "fin_pll", "dout_clkcmu_core_dlp" };
426
+
427
+
static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst = {
428
+
MUX(CLK_MOUT_CORE_ACLK_USER, "mout_clk_core_aclk_user",
429
+
mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1),
430
+
MUX(CLK_MOUT_CORE_DLP_USER, "mout_clk_core_dlp_user",
431
+
mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1),
432
+
};
433
+
434
+
static const struct samsung_div_clock cmu_core_div_clks[] __initconst = {
435
+
DIV(CLK_DOUT_CORE_PCLK, "dout_clk_core_pclk",
436
+
"mout_clk_core_aclk_user", CLK_CON_DIV_CLK_CORE_PCLK, 0, 4),
437
+
};
438
+
439
+
static const struct samsung_cmu_info cmu_core_info __initconst = {
440
+
.mux_clks = cmu_core_mux_clks,
441
+
.nr_mux_clks = ARRAY_SIZE(cmu_core_mux_clks),
442
+
.div_clks = cmu_core_div_clks,
443
+
.nr_div_clks = ARRAY_SIZE(cmu_core_div_clks),
444
+
.nr_clk_ids = CMU_CORE_NR_CLK,
445
+
.clk_regs = cmu_core_clk_regs,
446
+
.nr_clk_regs = ARRAY_SIZE(cmu_core_clk_regs),
447
+
};
448
+
449
+
/* Register Offset definitions for CMU_CPUCL (0x11410000) */
450
+
#define PLL_LOCKTIME_PLL_CPUCL 0x0000
451
+
#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER 0x0120
452
+
#define PLL_CON0_PLL_CPUCL 0x0140
453
+
#define CLK_CON_MUX_CLK_CPUCL_PLL 0x1000
454
+
#define CLK_CON_DIV_CLK_CLUSTER_ACLK 0x1800
455
+
#define CLK_CON_DIV_CLK_CLUSTER_CNTCLK 0x1804
456
+
#define CLK_CON_DIV_CLK_CLUSTER_PCLKDBG 0x1808
457
+
#define CLK_CON_DIV_CLK_CPUCL_CMUREF 0x180c
458
+
#define CLK_CON_DIV_CLK_CPUCL_PCLK 0x1814
459
+
#define CLK_CON_DIV_CLK_CLUSTER_ATCLK 0x1818
460
+
#define CLK_CON_DIV_CLK_CPUCL_DBG 0x181c
461
+
#define CLK_CON_DIV_CLK_CPUCL_PCLKDBG 0x1820
462
+
#define CLK_CON_GAT_CLK_CLUSTER_CPU 0x2008
463
+
#define CLK_CON_GAT_CLK_CPUCL_SHORTSTOP 0x200c
464
+
#define CLK_CON_DMYQCH_CON_CSSYS_QCH 0x3008
465
+
466
+
static const unsigned long cmu_cpucl_clk_regs[] __initconst = {
467
+
PLL_LOCKTIME_PLL_CPUCL,
468
+
PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER,
469
+
PLL_CON0_PLL_CPUCL,
470
+
CLK_CON_MUX_CLK_CPUCL_PLL,
471
+
CLK_CON_DIV_CLK_CLUSTER_ACLK,
472
+
CLK_CON_DIV_CLK_CLUSTER_CNTCLK,
473
+
CLK_CON_DIV_CLK_CLUSTER_PCLKDBG,
474
+
CLK_CON_DIV_CLK_CPUCL_CMUREF,
475
+
CLK_CON_DIV_CLK_CPUCL_PCLK,
476
+
CLK_CON_DIV_CLK_CLUSTER_ATCLK,
477
+
CLK_CON_DIV_CLK_CPUCL_DBG,
478
+
CLK_CON_DIV_CLK_CPUCL_PCLKDBG,
479
+
CLK_CON_GAT_CLK_CLUSTER_CPU,
480
+
CLK_CON_GAT_CLK_CPUCL_SHORTSTOP,
481
+
CLK_CON_DMYQCH_CON_CSSYS_QCH,
482
+
};
483
+
484
+
static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst = {
485
+
PLL(pll_1017x, CLK_FOUT_CPUCL_PLL, "fout_pll_cpucl", "fin_pll",
486
+
PLL_LOCKTIME_PLL_CPUCL, PLL_CON0_PLL_CPUCL, NULL),
487
+
};
488
+
489
+
PNAME(mout_clkcmu_cpucl_switch_user_p) = { "fin_pll", "dout_clkcmu_cpucl_switch" };
490
+
PNAME(mout_pll_cpucl_p) = { "fin_pll", "fout_pll_cpucl" };
491
+
PNAME(mout_clk_cpucl_pll_p) = { "mout_pll_cpucl", "mout_clkcmu_cpucl_switch_user" };
492
+
493
+
static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst = {
494
+
MUX_F(0, "mout_pll_cpucl", mout_pll_cpucl_p, PLL_CON0_PLL_CPUCL, 4, 1,
495
+
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
496
+
MUX(CLK_MOUT_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user",
497
+
mout_clkcmu_cpucl_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1),
498
+
MUX_F(CLK_MOUT_CPUCL_PLL, "mout_clk_cpucl_pll", mout_clk_cpucl_pll_p,
499
+
CLK_CON_MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
500
+
};
501
+
502
+
static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __initconst = {
503
+
FFACTOR(CLK_DOUT_CPUCL_CPU, "dout_clk_cpucl_cpu",
504
+
"mout_clk_cpucl_pll", 1, 1, CLK_SET_RATE_PARENT),
505
+
};
506
+
507
+
static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst = {
508
+
DIV(CLK_DOUT_CPUCL_CLUSTER_ACLK, "dout_clk_cluster_aclk",
509
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ACLK, 0, 4),
510
+
DIV(CLK_DOUT_CPUCL_CLUSTER_PCLKDBG, "dout_clk_cluster_pclkdbg",
511
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_PCLKDBG, 0, 4),
512
+
DIV(CLK_DOUT_CPUCL_CLUSTER_CNTCLK, "dout_clk_cluster_cntclk",
513
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_CNTCLK, 0, 4),
514
+
DIV(CLK_DOUT_CPUCL_CLUSTER_ATCLK, "dout_clk_cluster_atclk",
515
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CLUSTER_ATCLK, 0, 4),
516
+
DIV(CLK_DOUT_CPUCL_PCLK, "dout_clk_cpucl_pclk",
517
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_PCLK, 0, 4),
518
+
DIV(CLK_DOUT_CPUCL_CMUREF, "dout_clk_cpucl_cmuref",
519
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_CMUREF, 0, 3),
520
+
DIV(CLK_DOUT_CPUCL_DBG, "dout_clk_cpucl_dbg",
521
+
"dout_clk_cpucl_cpu", CLK_CON_DIV_CLK_CPUCL_DBG, 0, 4),
522
+
DIV(CLK_DOUT_CPUCL_PCLKDBG, "dout_clk_cpucl_pclkdbg",
523
+
"dout_clk_cpucl_dbg", CLK_CON_DIV_CLK_CPUCL_PCLKDBG, 0, 4),
524
+
};
525
+
526
+
static const struct samsung_gate_clock cmu_cpucl_gate_clks[] __initconst = {
527
+
GATE(CLK_GOUT_CPUCL_CLUSTER_CPU, "clk_con_gat_clk_cluster_cpu",
528
+
"clk_con_gat_clk_cpucl_shortstop", CLK_CON_GAT_CLK_CLUSTER_CPU, 21,
529
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
530
+
GATE(CLK_GOUT_CPUCL_SHORTSTOP, "clk_con_gat_clk_cpucl_shortstop",
531
+
"dout_clk_cpucl_cpu", CLK_CON_GAT_CLK_CPUCL_SHORTSTOP, 21,
532
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
533
+
GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG, "cssys_ipclkport_pclkdbg",
534
+
"dout_clk_cpucl_pclkdbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1,
535
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
536
+
GATE(CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK, "cssys_ipclkport_atclk",
537
+
"dout_clk_cpucl_dbg", CLK_CON_DMYQCH_CON_CSSYS_QCH, 1,
538
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
539
+
};
540
+
541
+
static const struct samsung_cmu_info cmu_cpucl_info __initconst = {
542
+
.pll_clks = cmu_cpucl_pll_clks,
543
+
.nr_pll_clks = ARRAY_SIZE(cmu_cpucl_pll_clks),
544
+
.fixed_factor_clks = cpucl_ffactor_clks,
545
+
.nr_fixed_factor_clks = ARRAY_SIZE(cpucl_ffactor_clks),
546
+
.mux_clks = cmu_cpucl_mux_clks,
547
+
.nr_mux_clks = ARRAY_SIZE(cmu_cpucl_mux_clks),
548
+
.div_clks = cmu_cpucl_div_clks,
549
+
.nr_div_clks = ARRAY_SIZE(cmu_cpucl_div_clks),
550
+
.gate_clks = cmu_cpucl_gate_clks,
551
+
.nr_gate_clks = ARRAY_SIZE(cmu_cpucl_gate_clks),
552
+
.nr_clk_ids = CMU_CPUCL_NR_CLK,
553
+
.clk_regs = cmu_cpucl_clk_regs,
554
+
.nr_clk_regs = ARRAY_SIZE(cmu_cpucl_clk_regs),
555
+
};
556
+
557
+
/* Register Offset definitions for CMU_FSYS (0x16c10000) */
558
+
#define PLL_LOCKTIME_PLL_FSYS 0x0004
559
+
#define PLL_CON0_MUX_CLK_FSYS_BUS_USER 0x0120
560
+
#define PLL_CON0_MUX_CLK_FSYS_MMC_USER 0x0140
561
+
#define PLL_CON0_MUX_CLK_FSYS_SCAN0_USER 0x0160
562
+
#define PLL_CON0_MUX_CLK_FSYS_SCAN1_USER 0x0180
563
+
#define PLL_CON0_PLL_FSYS 0x01c0
564
+
#define CLK_CON_DIV_CLK_FSYS_ADC 0x1804
565
+
#define CLK_CON_DIV_CLK_FSYS_BUS300 0x1808
566
+
#define CLK_CON_DIV_CLK_FSYS_BUS_QSPI 0x180c
567
+
#define CLK_CON_DIV_CLK_FSYS_EQOS_25 0x1810
568
+
#define CLK_CON_DIV_CLK_FSYS_EQOS_2P5 0x1814
569
+
#define CLK_CON_DIV_CLK_FSYS_EQOS_500 0x1818
570
+
#define CLK_CON_DIV_CLK_FSYS_EQOS_INT125 0x181c
571
+
#define CLK_CON_DIV_CLK_FSYS_MMC_CARD0 0x1820
572
+
#define CLK_CON_DIV_CLK_FSYS_MMC_CARD1 0x1824
573
+
#define CLK_CON_DIV_CLK_FSYS_OTP_MEM 0x1828
574
+
#define CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL 0x182c
575
+
#define CLK_CON_DIV_CLK_FSYS_QSPI 0x1830
576
+
#define CLK_CON_DIV_CLK_FSYS_SCLK_UART 0x1834
577
+
#define CLK_CON_DIV_CLK_FSYS_SFMC_NAND 0x1838
578
+
#define CLK_CON_DIV_SCAN_CLK_FSYS_125 0x183c
579
+
#define CLK_CON_DIV_SCAN_CLK_FSYS_MMC 0x1840
580
+
#define CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE 0x1844
581
+
#define CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK 0x2044
582
+
#define CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK 0x2048
583
+
#define CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK 0x204c
584
+
#define CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART 0x2050
585
+
#define CLK_CON_MMC0_IPCLKPORT_I_ACLK 0x2070
586
+
#define CLK_CON_MMC1_IPCLKPORT_I_ACLK 0x2078
587
+
#define CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x208c
588
+
#define CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2090
589
+
#define CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2094
590
+
#define CLK_CON_PWM_IPCLKPORT_I_PCLK_S0 0x20a0
591
+
#define CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 0x20bc
592
+
#define CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 0x20c0
593
+
#define CLK_CON_XHB_AHBBR_IPCLKPORT_CLK 0x20c4
594
+
#define CLK_CON_XHB_USB_IPCLKPORT_CLK 0x20cc
595
+
#define CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK 0x201c
596
+
#define CLK_CON_DMYQCH_CON_EQOS_TOP_QCH 0x3008
597
+
#define CLK_CON_DMYQCH_CON_MMC0_QCH 0x300c
598
+
#define CLK_CON_DMYQCH_CON_MMC1_QCH 0x3010
599
+
#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH 0x3018
600
+
#define CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF 0x301c
601
+
#define CLK_CON_DMYQCH_CON_QSPI_QCH 0x3020
602
+
#define CLK_CON_DMYQCH_CON_SFMC_QCH 0x3024
603
+
604
+
static const unsigned long cmu_fsys_clk_regs[] __initconst = {
605
+
PLL_LOCKTIME_PLL_FSYS,
606
+
PLL_CON0_MUX_CLK_FSYS_BUS_USER,
607
+
PLL_CON0_MUX_CLK_FSYS_MMC_USER,
608
+
PLL_CON0_MUX_CLK_FSYS_SCAN0_USER,
609
+
PLL_CON0_MUX_CLK_FSYS_SCAN1_USER,
610
+
PLL_CON0_PLL_FSYS,
611
+
CLK_CON_DIV_CLK_FSYS_ADC,
612
+
CLK_CON_DIV_CLK_FSYS_BUS300,
613
+
CLK_CON_DIV_CLK_FSYS_BUS_QSPI,
614
+
CLK_CON_DIV_CLK_FSYS_EQOS_25,
615
+
CLK_CON_DIV_CLK_FSYS_EQOS_2P5,
616
+
CLK_CON_DIV_CLK_FSYS_EQOS_500,
617
+
CLK_CON_DIV_CLK_FSYS_EQOS_INT125,
618
+
CLK_CON_DIV_CLK_FSYS_MMC_CARD0,
619
+
CLK_CON_DIV_CLK_FSYS_MMC_CARD1,
620
+
CLK_CON_DIV_CLK_FSYS_OTP_MEM,
621
+
CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL,
622
+
CLK_CON_DIV_CLK_FSYS_QSPI,
623
+
CLK_CON_DIV_CLK_FSYS_SCLK_UART,
624
+
CLK_CON_DIV_CLK_FSYS_SFMC_NAND,
625
+
CLK_CON_DIV_SCAN_CLK_FSYS_125,
626
+
CLK_CON_DIV_SCAN_CLK_FSYS_MMC,
627
+
CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE,
628
+
CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK,
629
+
CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK,
630
+
CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK,
631
+
CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART,
632
+
CLK_CON_MMC0_IPCLKPORT_I_ACLK,
633
+
CLK_CON_MMC1_IPCLKPORT_I_ACLK,
634
+
CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
635
+
CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
636
+
CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
637
+
CLK_CON_PWM_IPCLKPORT_I_PCLK_S0,
638
+
CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20,
639
+
CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY,
640
+
CLK_CON_XHB_AHBBR_IPCLKPORT_CLK,
641
+
CLK_CON_XHB_USB_IPCLKPORT_CLK,
642
+
CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK,
643
+
CLK_CON_DMYQCH_CON_EQOS_TOP_QCH,
644
+
CLK_CON_DMYQCH_CON_MMC0_QCH,
645
+
CLK_CON_DMYQCH_CON_MMC1_QCH,
646
+
CLK_CON_DMYQCH_CON_PCIE_TOP_QCH,
647
+
CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF,
648
+
CLK_CON_DMYQCH_CON_QSPI_QCH,
649
+
CLK_CON_DMYQCH_CON_SFMC_QCH,
650
+
};
651
+
652
+
static const struct samsung_pll_clock cmu_fsys_pll_clks[] __initconst = {
653
+
PLL(pll_1017x, CLK_FOUT_FSYS_PLL, "fout_pll_fsys", "fin_pll",
654
+
PLL_LOCKTIME_PLL_FSYS, PLL_CON0_PLL_FSYS, NULL),
655
+
};
656
+
657
+
PNAME(mout_fsys_scan0_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan0" };
658
+
PNAME(mout_fsys_scan1_user_p) = { "fin_pll", "dout_clkcmu_fsys_scan1" };
659
+
PNAME(mout_fsys_bus_user_p) = { "fin_pll", "dout_clkcmu_fsys_bus" };
660
+
PNAME(mout_fsys_mmc_user_p) = { "fin_pll", "dout_clkcmu_fsys_ip" };
661
+
PNAME(mout_fsys_pll_fsys_p) = { "fin_pll", "fout_pll_fsys" };
662
+
663
+
static const struct samsung_mux_clock cmu_fsys_mux_clks[] __initconst = {
664
+
MUX(0, "mout_clk_pll_fsys", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS, 4, 1),
665
+
MUX(CLK_MOUT_FSYS_SCAN0_USER, "mout_fsys_scan0_user",
666
+
mout_fsys_scan0_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, 4, 1),
667
+
MUX(CLK_MOUT_FSYS_SCAN1_USER, "mout_fsys_scan1_user",
668
+
mout_fsys_scan1_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, 4, 1),
669
+
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user",
670
+
mout_fsys_bus_user_p, PLL_CON0_MUX_CLK_FSYS_BUS_USER, 4, 1),
671
+
MUX(CLK_MOUT_FSYS_MMC_USER, "mout_fsys_mmc_user",
672
+
mout_fsys_mmc_user_p, PLL_CON0_MUX_CLK_FSYS_MMC_USER, 4, 1),
673
+
};
674
+
675
+
static const struct samsung_div_clock cmu_fsys_div_clks[] __initconst = {
676
+
DIV(CLK_DOUT_FSYS_PCIE_PIPE, "dout_fsys_pcie_pipe", "mout_clk_pll_fsys",
677
+
CLK_CON_DIV_SCAN_CLK_FSYS_PCIE_PIPE, 0, 4),
678
+
DIV(CLK_DOUT_FSYS_ADC, "dout_fsys_adc", "mout_clk_pll_fsys",
679
+
CLK_CON_DIV_CLK_FSYS_ADC, 0, 7),
680
+
DIV(CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL, "dout_fsys_pcie_phy_refclk_syspll",
681
+
"mout_clk_pll_fsys", CLK_CON_DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8),
682
+
DIV(CLK_DOUT_FSYS_QSPI, "dout_fsys_qspi", "mout_fsys_mmc_user",
683
+
CLK_CON_DIV_CLK_FSYS_QSPI, 0, 4),
684
+
DIV(CLK_DOUT_FSYS_EQOS_INT125, "dout_fsys_eqos_int125", "mout_clk_pll_fsys",
685
+
CLK_CON_DIV_CLK_FSYS_EQOS_INT125, 0, 4),
686
+
DIV(CLK_DOUT_FSYS_OTP_MEM, "dout_fsys_otp_mem", "fin_pll",
687
+
CLK_CON_DIV_CLK_FSYS_OTP_MEM, 0, 9),
688
+
DIV(CLK_DOUT_FSYS_SCLK_UART, "dout_fsys_sclk_uart", "mout_clk_pll_fsys",
689
+
CLK_CON_DIV_CLK_FSYS_SCLK_UART, 0, 10),
690
+
DIV(CLK_DOUT_FSYS_SFMC_NAND, "dout_fsys_sfmc_nand", "mout_fsys_mmc_user",
691
+
CLK_CON_DIV_CLK_FSYS_SFMC_NAND, 0, 4),
692
+
DIV(CLK_DOUT_SCAN_CLK_FSYS_125, "dout_scan_clk_fsys_125", "mout_clk_pll_fsys",
693
+
CLK_CON_DIV_SCAN_CLK_FSYS_125, 0, 4),
694
+
DIV(CLK_DOUT_FSYS_SCAN_CLK_MMC, "dout_scan_clk_fsys_mmc", "fout_pll_fsys",
695
+
CLK_CON_DIV_SCAN_CLK_FSYS_MMC, 0, 4),
696
+
DIV(CLK_DOUT_FSYS_EQOS_25, "dout_fsys_eqos_25", "dout_fsys_eqos_int125",
697
+
CLK_CON_DIV_CLK_FSYS_EQOS_25, 0, 4),
698
+
DIV_F(CLK_DOUT_FSYS_EQOS_2p5, "dout_fsys_eqos_2p5", "dout_fsys_eqos_25",
699
+
CLK_CON_DIV_CLK_FSYS_EQOS_2P5, 0, 4, CLK_SET_RATE_PARENT, 0),
700
+
DIV(0, "dout_fsys_eqos_500", "mout_clk_pll_fsys",
701
+
CLK_CON_DIV_CLK_FSYS_EQOS_500, 0, 4),
702
+
DIV(CLK_DOUT_FSYS_BUS300, "dout_fsys_bus300", "mout_fsys_bus_user",
703
+
CLK_CON_DIV_CLK_FSYS_BUS300, 0, 4),
704
+
DIV(CLK_DOUT_FSYS_BUS_QSPI, "dout_fsys_bus_qspi", "mout_fsys_mmc_user",
705
+
CLK_CON_DIV_CLK_FSYS_BUS_QSPI, 0, 4),
706
+
DIV(CLK_DOUT_FSYS_MMC_CARD0, "dout_fsys_mmc_card0", "mout_fsys_mmc_user",
707
+
CLK_CON_DIV_CLK_FSYS_MMC_CARD0, 0, 10),
708
+
DIV(CLK_DOUT_FSYS_MMC_CARD1, "dout_fsys_mmc_card1", "mout_fsys_mmc_user",
709
+
CLK_CON_DIV_CLK_FSYS_MMC_CARD1, 0, 10),
710
+
};
711
+
712
+
static const struct samsung_gate_clock cmu_fsys_gate_clks[] __initconst = {
713
+
GATE(CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN, "pcie_sub_ctrl_inst_0_phy_refclk_in",
714
+
"dout_fsys_pcie_phy_refclk_syspll", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH_REF, 1,
715
+
CLK_SET_RATE_PARENT, 0),
716
+
GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5,
717
+
"eqos_top_ipclkport_i_rgmii_txclk_2p5",
718
+
"dout_fsys_eqos_2p5", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
719
+
GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I, "eqos_top_ipclkport_aclk_i",
720
+
"dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
721
+
GATE(CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I, "eqos_top_ipclkport_clk_csr_i",
722
+
"dout_fsys_bus300", CLK_CON_DMYQCH_CON_EQOS_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
723
+
GATE(CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK, "pipe_pal_inst_0_i_apb_pclk",
724
+
"dout_fsys_bus300", CLK_CON_DMYQCH_CON_PCIE_TOP_QCH, 1, CLK_SET_RATE_PARENT, 0),
725
+
GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK, "qspi_ipclkport_hclk",
726
+
"dout_fsys_bus_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
727
+
GATE(CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK, "qspi_ipclkport_ssi_clk",
728
+
"dout_fsys_qspi", CLK_CON_DMYQCH_CON_QSPI_QCH, 1, CLK_SET_RATE_PARENT, 0),
729
+
GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN, "mmc0_ipclkport_sdclkin",
730
+
"dout_fsys_mmc_card0", CLK_CON_DMYQCH_CON_MMC0_QCH, 1, CLK_SET_RATE_PARENT, 0),
731
+
GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN, "mmc1_ipclkport_sdclkin",
732
+
"dout_fsys_mmc_card1", CLK_CON_DMYQCH_CON_MMC1_QCH, 1, CLK_SET_RATE_PARENT, 0),
733
+
GATE(CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND, "sfmc_ipclkport_i_aclk_nand",
734
+
"dout_fsys_sfmc_nand", CLK_CON_DMYQCH_CON_SFMC_QCH, 1, CLK_SET_RATE_PARENT, 0),
735
+
GATE(CLK_GOUT_FSYS_UART0_SCLK_UART, "uart0_sclk", "dout_fsys_sclk_uart",
736
+
CLK_CON_FSYS_UART0_IPCLKPORT_I_SCLK_UART, 21,
737
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
738
+
GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, "dwc_pcie_ctl_inst_0_mstr_aclk_ug",
739
+
"mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 21,
740
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
741
+
GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG, "dwc_pcie_ctl_inst_0_slv_aclk_ug",
742
+
"mout_fsys_bus_user", CLK_CON_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 21,
743
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
744
+
GATE(CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK, "fsys_i2c0_ipclkport_i_pclk", "dout_fsys_bus300",
745
+
CLK_CON_FSYS_I2C0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
746
+
GATE(CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK, "fsys_i2c1_ipclkport_i_pclk", "dout_fsys_bus300",
747
+
CLK_CON_FSYS_I2C1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
748
+
GATE(CLK_GOUT_FSYS_UART0_PCLK, "uart0_pclk", "dout_fsys_bus300",
749
+
CLK_CON_FSYS_UART0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
750
+
GATE(CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK, "mmc0_ipclkport_i_aclk", "dout_fsys_bus300",
751
+
CLK_CON_MMC0_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
752
+
GATE(CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK, "mmc1_ipclkport_i_aclk", "dout_fsys_bus300",
753
+
CLK_CON_MMC1_IPCLKPORT_I_ACLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
754
+
GATE(CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, "dwc_pcie_ctl_inst_0_dbi_aclk_ug",
755
+
"dout_fsys_bus300", CLK_CON_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 21,
756
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
757
+
GATE(CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0, "pwm_ipclkport_i_pclk_s0", "dout_fsys_bus300",
758
+
CLK_CON_PWM_IPCLKPORT_I_PCLK_S0, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
759
+
GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, "usb20drd_ipclkport_aclk_phyctrl_20",
760
+
"dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20, 21,
761
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
762
+
GATE(CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, "usb20drd_ipclkport_bus_clk_early",
763
+
"dout_fsys_bus300", CLK_CON_USB20DRD_IPCLKPORT_BUS_CLK_EARLY, 21,
764
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
765
+
GATE(CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK, "xhb_ahbbr_ipclkport_clk", "dout_fsys_bus300",
766
+
CLK_CON_XHB_AHBBR_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
767
+
GATE(CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK, "xhb_usb_ipclkport_clk", "dout_fsys_bus300",
768
+
CLK_CON_XHB_USB_IPCLKPORT_CLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
769
+
GATE(CLK_GOUT_FSYS_BUS_QSPI, "bus_p_fsys_ipclkport_qspiclk", "dout_fsys_bus_qspi",
770
+
CLK_CON_BUS_P_FSYS_IPCLKPORT_QSPICLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
771
+
};
772
+
773
+
static const struct samsung_cmu_info cmu_fsys_info __initconst = {
774
+
.pll_clks = cmu_fsys_pll_clks,
775
+
.nr_pll_clks = ARRAY_SIZE(cmu_fsys_pll_clks),
776
+
.mux_clks = cmu_fsys_mux_clks,
777
+
.nr_mux_clks = ARRAY_SIZE(cmu_fsys_mux_clks),
778
+
.div_clks = cmu_fsys_div_clks,
779
+
.nr_div_clks = ARRAY_SIZE(cmu_fsys_div_clks),
780
+
.gate_clks = cmu_fsys_gate_clks,
781
+
.nr_gate_clks = ARRAY_SIZE(cmu_fsys_gate_clks),
782
+
.nr_clk_ids = CMU_FSYS_NR_CLK,
783
+
.clk_regs = cmu_fsys_clk_regs,
784
+
.nr_clk_regs = ARRAY_SIZE(cmu_fsys_clk_regs),
785
+
};
786
+
787
+
/* Register Offset definitions for CMU_IMEM (0x10010000) */
788
+
#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100
789
+
#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120
790
+
#define CLK_CON_MUX_CLK_IMEM_GIC_CA53 0x1000
791
+
#define CLK_CON_MUX_CLK_IMEM_GIC_CA5 0x1008
792
+
#define CLK_CON_MCT_IPCLKPORT_PCLK 0x2038
793
+
#define CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK 0x2044
794
+
795
+
static const unsigned long cmu_imem_clk_regs[] __initconst = {
796
+
PLL_CON0_MUX_CLK_IMEM_ACLK_USER,
797
+
PLL_CON0_MUX_CLK_IMEM_JPEG_USER,
798
+
CLK_CON_MUX_CLK_IMEM_GIC_CA53,
799
+
CLK_CON_MUX_CLK_IMEM_GIC_CA5,
800
+
CLK_CON_MCT_IPCLKPORT_PCLK,
801
+
CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK,
802
+
};
803
+
804
+
PNAME(mout_imem_aclk_user_p) = { "fin_pll", "dout_clkcmu_imem_aclk" };
805
+
PNAME(mout_imem_gic_ca53_p) = { "mout_imem_aclk_user", "fin_pll" };
806
+
PNAME(mout_imem_gic_ca5_p) = { "mout_imem_aclk_user", "fin_pll" };
807
+
PNAME(mout_imem_jpeg_user_p) = { "fin_pll", "dout_clkcmu_imem_jpeg" };
808
+
809
+
static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst = {
810
+
MUX(CLK_MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user",
811
+
mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1),
812
+
MUX(CLK_MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53",
813
+
mout_imem_gic_ca53_p, CLK_CON_MUX_CLK_IMEM_GIC_CA53, 0, 1),
814
+
MUX(CLK_MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5",
815
+
mout_imem_gic_ca5_p, CLK_CON_MUX_CLK_IMEM_GIC_CA5, 0, 1),
816
+
MUX(CLK_MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user",
817
+
mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1),
818
+
};
819
+
820
+
static const struct samsung_gate_clock cmu_imem_gate_clks[] __initconst = {
821
+
GATE(CLK_GOUT_IMEM_MCT_PCLK, "mct_pclk", "mout_imem_aclk_user",
822
+
CLK_CON_MCT_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
823
+
GATE(CLK_GOUT_IMEM_PCLK_TMU0_APBIF, "sfrif_tmu_imem_ipclkport_pclk", "mout_imem_aclk_user",
824
+
CLK_CON_SFRIF_TMU_IMEM_IPCLKPORT_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
825
+
};
826
+
827
+
static const struct samsung_cmu_info cmu_imem_info __initconst = {
828
+
.mux_clks = cmu_imem_mux_clks,
829
+
.nr_mux_clks = ARRAY_SIZE(cmu_imem_mux_clks),
830
+
.gate_clks = cmu_imem_gate_clks,
831
+
.nr_gate_clks = ARRAY_SIZE(cmu_imem_gate_clks),
832
+
.nr_clk_ids = CMU_IMEM_NR_CLK,
833
+
.clk_regs = cmu_imem_clk_regs,
834
+
.nr_clk_regs = ARRAY_SIZE(cmu_imem_clk_regs),
835
+
};
836
+
837
+
static void __init artpec8_clk_cmu_imem_init(struct device_node *np)
838
+
{
839
+
samsung_cmu_register_one(np, &cmu_imem_info);
840
+
}
841
+
842
+
CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init);
843
+
844
+
/* Register Offset definitions for CMU_PERI (0x16410000) */
845
+
#define PLL_CON0_MUX_CLK_PERI_AUDIO_USER 0x0100
846
+
#define PLL_CON0_MUX_CLK_PERI_DISP_USER 0x0120
847
+
#define PLL_CON0_MUX_CLK_PERI_IP_USER 0x0140
848
+
#define CLK_CON_MUX_CLK_PERI_I2S0 0x1000
849
+
#define CLK_CON_MUX_CLK_PERI_I2S1 0x1004
850
+
#define CLK_CON_DIV_CLK_PERI_DSIM 0x1800
851
+
#define CLK_CON_DIV_CLK_PERI_I2S0 0x1804
852
+
#define CLK_CON_DIV_CLK_PERI_I2S1 0x1808
853
+
#define CLK_CON_DIV_CLK_PERI_PCLK 0x180c
854
+
#define CLK_CON_DIV_CLK_PERI_SPI 0x1810
855
+
#define CLK_CON_DIV_CLK_PERI_UART1 0x1814
856
+
#define CLK_CON_DIV_CLK_PERI_UART2 0x1818
857
+
#define CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 0x2004
858
+
#define CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK 0x2030
859
+
#define CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK 0x2034
860
+
#define CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK 0x2048
861
+
#define CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI 0x204c
862
+
#define CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK 0x2050
863
+
#define CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART 0x2054
864
+
#define CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK 0x2058
865
+
#define CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART 0x205c
866
+
#define CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH 0x3000
867
+
#define CLK_CON_DMYQCH_CON_DMA4DSIM_QCH 0x3004
868
+
#define CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH 0x3008
869
+
#define CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH 0x300c
870
+
871
+
static const unsigned long cmu_peri_clk_regs[] __initconst = {
872
+
PLL_CON0_MUX_CLK_PERI_AUDIO_USER,
873
+
PLL_CON0_MUX_CLK_PERI_DISP_USER,
874
+
PLL_CON0_MUX_CLK_PERI_IP_USER,
875
+
CLK_CON_MUX_CLK_PERI_I2S0,
876
+
CLK_CON_MUX_CLK_PERI_I2S1,
877
+
CLK_CON_DIV_CLK_PERI_DSIM,
878
+
CLK_CON_DIV_CLK_PERI_I2S0,
879
+
CLK_CON_DIV_CLK_PERI_I2S1,
880
+
CLK_CON_DIV_CLK_PERI_PCLK,
881
+
CLK_CON_DIV_CLK_PERI_SPI,
882
+
CLK_CON_DIV_CLK_PERI_UART1,
883
+
CLK_CON_DIV_CLK_PERI_UART2,
884
+
CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS,
885
+
CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK,
886
+
CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK,
887
+
CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK,
888
+
CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI,
889
+
CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK,
890
+
CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART,
891
+
CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK,
892
+
CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART,
893
+
CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH,
894
+
CLK_CON_DMYQCH_CON_DMA4DSIM_QCH,
895
+
CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH,
896
+
CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH,
897
+
};
898
+
899
+
static const struct samsung_fixed_rate_clock peri_fixed_clks[] __initconst = {
900
+
FRATE(0, "clk_peri_audio", NULL, 0, 100000000),
901
+
};
902
+
903
+
PNAME(mout_peri_ip_user_p) = { "fin_pll", "dout_clkcmu_peri_ip" };
904
+
PNAME(mout_peri_audio_user_p) = { "fin_pll", "dout_clkcmu_peri_audio" };
905
+
PNAME(mout_peri_disp_user_p) = { "fin_pll", "dout_clkcmu_peri_disp" };
906
+
PNAME(mout_peri_i2s0_p) = { "dout_peri_i2s0", "clk_peri_audio" };
907
+
PNAME(mout_peri_i2s1_p) = { "dout_peri_i2s1", "clk_peri_audio" };
908
+
909
+
static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst = {
910
+
MUX(CLK_MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p,
911
+
PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1),
912
+
MUX(CLK_MOUT_PERI_AUDIO_USER, "mout_peri_audio_user",
913
+
mout_peri_audio_user_p, PLL_CON0_MUX_CLK_PERI_AUDIO_USER, 4, 1),
914
+
MUX(CLK_MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p,
915
+
PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1),
916
+
MUX(CLK_MOUT_PERI_I2S0, "mout_peri_i2s0", mout_peri_i2s0_p,
917
+
CLK_CON_MUX_CLK_PERI_I2S0, 0, 1),
918
+
MUX(CLK_MOUT_PERI_I2S1, "mout_peri_i2s1", mout_peri_i2s1_p,
919
+
CLK_CON_MUX_CLK_PERI_I2S1, 0, 1),
920
+
};
921
+
922
+
static const struct samsung_div_clock cmu_peri_div_clks[] __initconst = {
923
+
DIV(CLK_DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user",
924
+
CLK_CON_DIV_CLK_PERI_SPI, 0, 10),
925
+
DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user",
926
+
CLK_CON_DIV_CLK_PERI_UART1, 0, 10),
927
+
DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user",
928
+
CLK_CON_DIV_CLK_PERI_UART2, 0, 10),
929
+
DIV(CLK_DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user",
930
+
CLK_CON_DIV_CLK_PERI_PCLK, 0, 4),
931
+
DIV(CLK_DOUT_PERI_I2S0, "dout_peri_i2s0", "mout_peri_audio_user",
932
+
CLK_CON_DIV_CLK_PERI_I2S0, 0, 4),
933
+
DIV(CLK_DOUT_PERI_I2S1, "dout_peri_i2s1", "mout_peri_audio_user",
934
+
CLK_CON_DIV_CLK_PERI_I2S1, 0, 4),
935
+
DIV(CLK_DOUT_PERI_DSIM, "dout_peri_dsim", "mout_peri_disp_user",
936
+
CLK_CON_DIV_CLK_PERI_DSIM, 0, 4),
937
+
};
938
+
939
+
static const struct samsung_gate_clock cmu_peri_gate_clks[] __initconst = {
940
+
GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK, "dma4dsim_ipclkport_clk_apb_clk",
941
+
"dout_peri_pclk", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
942
+
GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST, "i2ssc0_ipclkport_clk_hst", "dout_peri_pclk",
943
+
CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
944
+
GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST, "i2ssc1_ipclkport_clk_hst", "dout_peri_pclk",
945
+
CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
946
+
GATE(CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK, "audio_out_ipclkport_clk",
947
+
"mout_peri_audio_user", CLK_CON_DMYQCH_CON_AUDIO_OUT_QCH, 1, CLK_SET_RATE_PARENT, 0),
948
+
GATE(CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK, "peri_i2ssc0_ipclkport_clk", "mout_peri_i2s0",
949
+
CLK_CON_DMYQCH_CON_PERI_I2SSC0_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
950
+
GATE(CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK, "peri_i2ssc1_ipclkport_clk", "mout_peri_i2s1",
951
+
CLK_CON_DMYQCH_CON_PERI_I2SSC1_QCH, 1, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
952
+
GATE(CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK, "dma4dsim_ipclkport_clk_axi_clk",
953
+
"mout_peri_disp_user", CLK_CON_DMYQCH_CON_DMA4DSIM_QCH, 1, CLK_SET_RATE_PARENT, 0),
954
+
GATE(CLK_GOUT_PERI_SPI0_SCLK_SPI, "peri_spi0_ipclkport_i_sclk_spi", "dout_peri_spi",
955
+
CLK_CON_PERI_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
956
+
GATE(CLK_GOUT_PERI_UART1_SCLK_UART, "uart1_sclk", "dout_peri_uart1",
957
+
CLK_CON_PERI_UART1_IPCLKPORT_I_SCLK_UART, 21,
958
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
959
+
GATE(CLK_GOUT_PERI_UART2_SCLK_UART, "uart2_sclk", "dout_peri_uart2",
960
+
CLK_CON_PERI_UART2_IPCLKPORT_I_SCLK_UART, 21,
961
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
962
+
GATE(CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, "apb_async_dsim_ipclkport_pclks",
963
+
"dout_peri_pclk", CLK_CON_APB_ASYNC_DSIM_IPCLKPORT_PCLKS, 21,
964
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
965
+
GATE(CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK, "peri_i2c2_ipclkport_i_pclk", "dout_peri_pclk",
966
+
CLK_CON_PERI_I2C2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
967
+
GATE(CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK, "peri_i2c3_ipclkport_i_pclk", "dout_peri_pclk",
968
+
CLK_CON_PERI_I2C3_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
969
+
GATE(CLK_GOUT_PERI_SPI0_PCLK, "peri_spi0_ipclkport_i_pclk", "dout_peri_pclk",
970
+
CLK_CON_PERI_SPI0_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
971
+
GATE(CLK_GOUT_PERI_UART1_PCLK, "uart1_pclk", "dout_peri_pclk",
972
+
CLK_CON_PERI_UART1_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
973
+
GATE(CLK_GOUT_PERI_UART2_PCLK, "uart2_pclk", "dout_peri_pclk",
974
+
CLK_CON_PERI_UART2_IPCLKPORT_I_PCLK, 21, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
975
+
};
976
+
977
+
static const struct samsung_cmu_info cmu_peri_info __initconst = {
978
+
.mux_clks = cmu_peri_mux_clks,
979
+
.nr_mux_clks = ARRAY_SIZE(cmu_peri_mux_clks),
980
+
.div_clks = cmu_peri_div_clks,
981
+
.nr_div_clks = ARRAY_SIZE(cmu_peri_div_clks),
982
+
.gate_clks = cmu_peri_gate_clks,
983
+
.nr_gate_clks = ARRAY_SIZE(cmu_peri_gate_clks),
984
+
.fixed_clks = peri_fixed_clks,
985
+
.nr_fixed_clks = ARRAY_SIZE(peri_fixed_clks),
986
+
.nr_clk_ids = CMU_PERI_NR_CLK,
987
+
.clk_regs = cmu_peri_clk_regs,
988
+
.nr_clk_regs = ARRAY_SIZE(cmu_peri_clk_regs),
989
+
};
990
+
991
+
/**
992
+
* artpec8_cmu_probe - Probe function for ARTPEC platform clocks
993
+
* @pdev: Pointer to platform device
994
+
*
995
+
* Configure clock hierarchy for clock domains of ARTPEC platform
996
+
*/
997
+
static int __init artpec8_cmu_probe(struct platform_device *pdev)
998
+
{
999
+
const struct samsung_cmu_info *info;
1000
+
struct device *dev = &pdev->dev;
1001
+
1002
+
info = of_device_get_match_data(dev);
1003
+
exynos_arm64_register_cmu(dev, dev->of_node, info);
1004
+
1005
+
return 0;
1006
+
}
1007
+
1008
+
static const struct of_device_id artpec8_cmu_of_match[] = {
1009
+
{
1010
+
.compatible = "axis,artpec8-cmu-cmu",
1011
+
.data = &cmu_cmu_info,
1012
+
}, {
1013
+
.compatible = "axis,artpec8-cmu-bus",
1014
+
.data = &cmu_bus_info,
1015
+
}, {
1016
+
.compatible = "axis,artpec8-cmu-core",
1017
+
.data = &cmu_core_info,
1018
+
}, {
1019
+
.compatible = "axis,artpec8-cmu-cpucl",
1020
+
.data = &cmu_cpucl_info,
1021
+
}, {
1022
+
.compatible = "axis,artpec8-cmu-fsys",
1023
+
.data = &cmu_fsys_info,
1024
+
}, {
1025
+
.compatible = "axis,artpec8-cmu-peri",
1026
+
.data = &cmu_peri_info,
1027
+
}, {
1028
+
},
1029
+
};
1030
+
1031
+
static struct platform_driver artpec8_cmu_driver __refdata = {
1032
+
.driver = {
1033
+
.name = "artpec8-cmu",
1034
+
.of_match_table = artpec8_cmu_of_match,
1035
+
.suppress_bind_attrs = true,
1036
+
},
1037
+
.probe = artpec8_cmu_probe,
1038
+
};
1039
+
1040
+
static int __init artpec8_cmu_init(void)
1041
+
{
1042
+
return platform_driver_register(&artpec8_cmu_driver);
1043
+
}
1044
+
core_initcall(artpec8_cmu_init);
+7
-5
drivers/clk/samsung/clk-cpu.c
+7
-5
drivers/clk/samsung/clk-cpu.c
···
567
567
/* -------------------------------------------------------------------------- */
568
568
569
569
/* Common round rate callback usable for all types of CPU clocks */
570
-
static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
571
-
unsigned long *prate)
570
+
static int exynos_cpuclk_determine_rate(struct clk_hw *hw,
571
+
struct clk_rate_request *req)
572
572
{
573
573
struct clk_hw *parent = clk_hw_get_parent(hw);
574
-
*prate = clk_hw_round_rate(parent, drate);
575
-
return *prate;
574
+
req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
575
+
req->rate = req->best_parent_rate;
576
+
577
+
return 0;
576
578
}
577
579
578
580
/* Common recalc rate callback usable for all types of CPU clocks */
···
593
591
594
592
static const struct clk_ops exynos_cpuclk_clk_ops = {
595
593
.recalc_rate = exynos_cpuclk_recalc_rate,
596
-
.round_rate = exynos_cpuclk_round_rate,
594
+
.determine_rate = exynos_cpuclk_determine_rate,
597
595
};
598
596
599
597
/*
+1218
-22
drivers/clk/samsung/clk-exynos990.c
+1218
-22
drivers/clk/samsung/clk-exynos990.c
···
17
17
#include "clk-pll.h"
18
18
19
19
/* NOTE: Must be equal to the last clock ID increased by one */
20
-
#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
21
-
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
20
+
#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1)
21
+
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK + 1)
22
+
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PCLK + 1)
23
+
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_XIU_P_ACLK + 1)
22
24
#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
23
25
24
26
/* ---- CMU_TOP ------------------------------------------------------------- */
···
47
45
#define PLL_CON3_PLL_SHARED3 0x024c
48
46
#define PLL_CON0_PLL_SHARED4 0x0280
49
47
#define PLL_CON3_PLL_SHARED4 0x028c
48
+
#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000
50
49
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
51
50
#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
52
51
#define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
···
106
103
#define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
107
104
#define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
108
105
#define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
106
+
#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0
107
+
#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
109
108
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
110
109
#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
111
110
#define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
···
167
162
#define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
168
163
#define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
169
164
#define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
165
+
#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0
170
166
#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
171
167
#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
172
168
#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
···
245
239
PLL_LOCKTIME_PLL_SHARED2,
246
240
PLL_LOCKTIME_PLL_SHARED3,
247
241
PLL_LOCKTIME_PLL_SHARED4,
242
+
PLL_CON0_PLL_G3D,
248
243
PLL_CON3_PLL_G3D,
244
+
PLL_CON0_PLL_MMC,
249
245
PLL_CON3_PLL_MMC,
246
+
PLL_CON0_PLL_SHARED0,
250
247
PLL_CON3_PLL_SHARED0,
248
+
PLL_CON0_PLL_SHARED1,
251
249
PLL_CON3_PLL_SHARED1,
250
+
PLL_CON0_PLL_SHARED2,
252
251
PLL_CON3_PLL_SHARED2,
252
+
PLL_CON0_PLL_SHARED3,
253
253
PLL_CON3_PLL_SHARED3,
254
+
PLL_CON0_PLL_SHARED4,
254
255
PLL_CON3_PLL_SHARED4,
256
+
CLK_CON_MUX_CLKCMU_DPU_BUS,
255
257
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
256
258
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
257
259
CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
···
318
304
CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
319
305
CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
320
306
CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
307
+
CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
308
+
CLK_CON_MUX_MUX_CMU_CMUREF,
321
309
CLK_CON_DIV_CLKCMU_APM_BUS,
322
310
CLK_CON_DIV_CLKCMU_AUD_CPU,
323
311
CLK_CON_DIV_CLKCMU_BUS0_BUS,
···
379
363
CLK_CON_DIV_CLKCMU_VRA_BUS,
380
364
CLK_CON_DIV_DIV_CLKCMU_DPU,
381
365
CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
366
+
CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
382
367
CLK_CON_DIV_PLL_SHARED0_DIV2,
383
368
CLK_CON_DIV_PLL_SHARED0_DIV3,
384
369
CLK_CON_DIV_PLL_SHARED0_DIV4,
···
475
458
PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
476
459
PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
477
460
PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
461
+
PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
462
+
"dout_cmu_dpu_alt" };
478
463
PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
479
464
"dout_cmu_shared2_div2" };
480
465
PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
···
691
672
"dout_cmu_shared4_div2",
692
673
"dout_cmu_shared0_div4",
693
674
"dout_cmu_shared4_div3" };
675
+
PNAME(mout_cmu_cmuref_p) = { "oscclk",
676
+
"dout_cmu_clk_cmuref" };
677
+
PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4",
678
+
"dout_cmu_shared1_div4",
679
+
"dout_cmu_shared2_div2",
680
+
"oscclk" };
694
681
695
682
/*
696
683
* Register name to clock name mangling strategy used in this file
···
714
689
715
690
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
716
691
MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
717
-
PLL_CON3_PLL_SHARED0, 4, 1),
692
+
PLL_CON0_PLL_SHARED0, 4, 1),
718
693
MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
719
-
PLL_CON3_PLL_SHARED1, 4, 1),
694
+
PLL_CON0_PLL_SHARED1, 4, 1),
720
695
MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
721
-
PLL_CON3_PLL_SHARED2, 4, 1),
696
+
PLL_CON0_PLL_SHARED2, 4, 1),
722
697
MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
723
-
PLL_CON3_PLL_SHARED3, 4, 1),
698
+
PLL_CON0_PLL_SHARED3, 4, 1),
724
699
MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
725
700
PLL_CON0_PLL_SHARED4, 4, 1),
726
701
MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
727
702
PLL_CON0_PLL_MMC, 4, 1),
728
703
MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
729
704
PLL_CON0_PLL_G3D, 4, 1),
705
+
MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
706
+
mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
730
707
MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
731
708
mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
732
709
MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
···
786
759
MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt",
787
760
mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
788
761
MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus",
789
-
mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
762
+
mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3),
790
763
MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d",
791
764
mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
792
765
MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl",
793
-
mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1),
766
+
mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
794
767
MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm",
795
768
mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
796
769
MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus",
···
802
775
0, 2),
803
776
MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug",
804
777
mout_cmu_hsi0_usbdp_debug_p,
805
-
CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2),
778
+
CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1),
806
779
MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus",
807
780
mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
808
781
MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card",
···
815
788
0, 2),
816
789
MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd",
817
790
mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
818
-
0, 1),
791
+
0, 2),
819
792
MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus",
820
793
mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
821
794
MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie",
···
857
830
mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
858
831
MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
859
832
mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
833
+
MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
834
+
mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
835
+
MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
836
+
mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
860
837
};
861
838
862
839
static const struct samsung_div_clock top_div_clks[] __initconst = {
···
893
862
CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
894
863
895
864
DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
896
-
CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
865
+
CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
897
866
DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
898
867
CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
899
868
DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
···
918
887
CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
919
888
DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
920
889
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
921
-
DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug",
890
+
DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus",
922
891
"gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
923
-
0, 3),
892
+
0, 4),
924
893
DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
925
894
"gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
926
895
DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
···
955
924
CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
956
925
DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
957
926
"gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
958
-
DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
959
-
"gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
960
-
0, 4),
961
927
DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
962
928
CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
963
929
DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card",
964
930
"gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
965
931
0, 9),
966
-
DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
967
-
CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7),
968
932
DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card",
969
933
"gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
970
934
0, 3),
···
968
942
0, 3),
969
943
DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
970
944
CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
971
-
DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
972
-
CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7),
973
945
DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
974
946
CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
975
947
DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
···
1003
979
CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1004
980
DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
1005
981
CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
1006
-
DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu",
1007
-
CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4),
982
+
DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
983
+
CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
984
+
DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
985
+
CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
986
+
DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
987
+
CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
988
+
};
989
+
990
+
static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
991
+
FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie",
992
+
"gout_cmu_hsi1_pcie", 1, 8, 0),
993
+
FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
994
+
FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
995
+
"gout_cmu_hsi0_usbdp_debug", 1, 8, 0),
996
+
FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie",
997
+
"gout_cmu_hsi2_pcie", 1, 8, 0),
1008
998
};
1009
999
1010
1000
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
···
1164
1126
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1165
1127
.div_clks = top_div_clks,
1166
1128
.nr_div_clks = ARRAY_SIZE(top_div_clks),
1129
+
.fixed_factor_clks = cmu_top_ffactor,
1130
+
.nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
1167
1131
.gate_clks = top_gate_clks,
1168
1132
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1169
1133
.nr_clk_ids = CLKS_NR_TOP,
···
1226
1186
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1227
1187
CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1228
1188
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1189
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
1190
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
1229
1191
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1230
1192
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1231
1193
CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
···
1336
1294
"gout_hsi0_xiu_d_hsi0_aclk", "mout_hsi0_bus_user",
1337
1295
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1338
1296
21, CLK_IGNORE_UNUSED, 0),
1297
+
GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK,
1298
+
"gout_hsi0_lhs_acel_d_hsi0_clk", "mout_hsi0_bus_user",
1299
+
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
1300
+
21, CLK_IS_CRITICAL, 0),
1339
1301
};
1340
1302
1341
1303
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
···
1351
1305
.clk_regs = hsi0_clk_regs,
1352
1306
.nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1353
1307
.clk_name = "bus",
1308
+
};
1309
+
1310
+
/* ---- CMU_PERIC0 --------------------------------------------------------- */
1311
+
1312
+
/* Register Offset definitions for CMU_PERIC0 (0x10400000) */
1313
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1314
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
1315
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG 0x0610
1316
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG 0x0614
1317
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0620
1318
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0624
1319
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0630
1320
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0634
1321
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0640
1322
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0644
1323
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0650
1324
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0654
1325
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0660
1326
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0664
1327
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0670
1328
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0674
1329
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0680
1330
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0684
1331
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0690
1332
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0694
1333
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a0
1334
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a4
1335
+
#define PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b0
1336
+
#define PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b4
1337
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG 0x1800
1338
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1339
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1340
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1341
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1342
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1343
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1344
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI 0x181c
1345
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x1820
1346
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI 0x1824
1347
+
#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1348
+
#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
1349
+
#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
1350
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
1351
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2010
1352
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2014
1353
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2018
1354
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x201c
1355
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x2020
1356
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2024
1357
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2028
1358
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x202c
1359
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2030
1360
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2034
1361
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2038
1362
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x203c
1363
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2040
1364
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2044
1365
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2048
1366
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x204c
1367
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x2050
1368
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2054
1369
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2058
1370
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x205c
1371
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1372
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1373
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1374
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1375
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1376
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1377
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x2078
1378
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3 0x207c
1379
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4 0x2080
1380
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5 0x2084
1381
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6 0x2088
1382
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7 0x208c
1383
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8 0x2090
1384
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x2094
1385
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15 0x2098
1386
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3 0x209c
1387
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4 0x20a0
1388
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5 0x20a4
1389
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6 0x20a8
1390
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7 0x20ac
1391
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8 0x20b0
1392
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
1393
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK 0x20b8
1394
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK 0x20bc
1395
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK 0x20c0
1396
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK 0x20c4
1397
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK 0x20c8
1398
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK 0x20cc
1399
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK 0x20d0
1400
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK 0x20d4
1401
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20d8
1402
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK 0x20dc
1403
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK 0x20e0
1404
+
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e4
1405
+
1406
+
static const unsigned long peric0_clk_regs[] __initconst = {
1407
+
PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1408
+
PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
1409
+
PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
1410
+
PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG,
1411
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
1412
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER,
1413
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
1414
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER,
1415
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
1416
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER,
1417
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
1418
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER,
1419
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
1420
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER,
1421
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
1422
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER,
1423
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
1424
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER,
1425
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
1426
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
1427
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
1428
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER,
1429
+
PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
1430
+
PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER,
1431
+
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
1432
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1433
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1434
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1435
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1436
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1437
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1438
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
1439
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
1440
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
1441
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1442
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
1443
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
1444
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
1445
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
1446
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
1447
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1448
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1449
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
1450
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
1451
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
1452
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
1453
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1454
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1455
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1456
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1457
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1458
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1459
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1460
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1461
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
1462
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
1463
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
1464
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
1465
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1466
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1467
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1468
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1469
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1470
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1471
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
1472
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3,
1473
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4,
1474
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5,
1475
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6,
1476
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7,
1477
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8,
1478
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
1479
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15,
1480
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3,
1481
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4,
1482
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5,
1483
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6,
1484
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7,
1485
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8,
1486
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
1487
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
1488
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
1489
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
1490
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
1491
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
1492
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
1493
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
1494
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
1495
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
1496
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
1497
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
1498
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
1499
+
};
1500
+
1501
+
/* Parent clock list for CMU_PERIC0 muxes */
1502
+
PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
1503
+
PNAME(mout_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_peric0_ip" };
1504
+
PNAME(mout_peric0_usi00_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1505
+
PNAME(mout_peric0_usi01_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1506
+
PNAME(mout_peric0_usi02_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1507
+
PNAME(mout_peric0_usi03_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1508
+
PNAME(mout_peric0_usi04_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1509
+
PNAME(mout_peric0_usi05_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1510
+
PNAME(mout_peric0_usi13_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1511
+
PNAME(mout_peric0_usi14_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1512
+
PNAME(mout_peric0_usi15_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1513
+
PNAME(mout_peric0_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1514
+
1515
+
static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1516
+
MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1517
+
mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1518
+
4, 1),
1519
+
MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg",
1520
+
mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
1521
+
4, 1),
1522
+
MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user",
1523
+
mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
1524
+
4, 1),
1525
+
MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user",
1526
+
mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
1527
+
4, 1),
1528
+
MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user",
1529
+
mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
1530
+
4, 1),
1531
+
MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user",
1532
+
mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
1533
+
4, 1),
1534
+
MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user",
1535
+
mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
1536
+
4, 1),
1537
+
MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user",
1538
+
mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
1539
+
4, 1),
1540
+
MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user",
1541
+
mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
1542
+
4, 1),
1543
+
MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user",
1544
+
mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
1545
+
4, 1),
1546
+
MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user",
1547
+
mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
1548
+
4, 1),
1549
+
MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user",
1550
+
mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
1551
+
4, 1),
1552
+
};
1553
+
1554
+
static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1555
+
DIV(CLK_DOUT_PERIC0_UART_DBG, "dout_peric0_uart_dbg",
1556
+
"mout_peric0_uart_dbg",
1557
+
CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
1558
+
0, 4),
1559
+
DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1560
+
"mout_peric0_usi00_usi_user",
1561
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1562
+
0, 4),
1563
+
DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1564
+
"mout_peric0_usi01_usi_user",
1565
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1566
+
0, 4),
1567
+
DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1568
+
"mout_peric0_usi02_usi_user",
1569
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1570
+
0, 4),
1571
+
DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1572
+
"mout_peric0_usi03_usi_user",
1573
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1574
+
0, 4),
1575
+
DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1576
+
"mout_peric0_usi04_usi_user",
1577
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1578
+
0, 4),
1579
+
DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1580
+
"mout_peric0_usi05_usi_user",
1581
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1582
+
0, 4),
1583
+
DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi",
1584
+
"mout_peric0_usi13_usi_user",
1585
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
1586
+
0, 4),
1587
+
DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi",
1588
+
"mout_peric0_usi14_usi_user",
1589
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
1590
+
0, 4),
1591
+
DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi",
1592
+
"mout_peric0_usi15_usi_user",
1593
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
1594
+
0, 4),
1595
+
DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1596
+
"mout_peric0_usi_i2c_user",
1597
+
CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1598
+
0, 4),
1599
+
};
1600
+
1601
+
static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1602
+
GATE(CLK_GOUT_PERIC0_CMU_PCLK, "gout_peric0_cmu_pclk",
1603
+
"mout_peric0_bus_user",
1604
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
1605
+
21, CLK_IS_CRITICAL, 0),
1606
+
GATE(CLK_GOUT_PERIC0_OSCCLK_CLK, "gout_peric0_oscclk_clk",
1607
+
"oscclk",
1608
+
CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
1609
+
21, 0, 0),
1610
+
GATE(CLK_GOUT_PERIC0_D_TZPC_PCLK, "gout_peric0_d_tpzc_pclk",
1611
+
"mout_peric0_bus_user",
1612
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
1613
+
21, 0, 0),
1614
+
GATE(CLK_GOUT_PERIC0_GPIO_PCLK, "gout_peric0_gpio_pclk",
1615
+
"mout_peric0_bus_user",
1616
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
1617
+
21, CLK_IGNORE_UNUSED, 0),
1618
+
GATE(CLK_GOUT_PERIC0_LHM_AXI_P_CLK, "gout_peric0_lhm_axi_p_clk",
1619
+
"mout_peric0_bus_user",
1620
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
1621
+
21, CLK_IS_CRITICAL, 0),
1622
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_10, "gout_peric0_top0_ipclk_10",
1623
+
"dout_peric0_usi_i2c",
1624
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1625
+
21, 0, 0),
1626
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_11, "gout_peric0_top0_ipclk_11",
1627
+
"dout_peric0_usi03_usi",
1628
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1629
+
21, 0, 0),
1630
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_12, "gout_peric0_top0_ipclk_12",
1631
+
"dout_peric0_usi_i2c",
1632
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
1633
+
21, 0, 0),
1634
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_13, "gout_peric0_top0_ipclk_13",
1635
+
"dout_peric0_usi04_usi",
1636
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
1637
+
21, 0, 0),
1638
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_14, "gout_peric0_top0_ipclk_14",
1639
+
"dout_peric0_usi_i2c",
1640
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
1641
+
21, 0, 0),
1642
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_15, "gout_peric0_top0_ipclk_15",
1643
+
"dout_peric0_usi05_usi",
1644
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
1645
+
21, 0, 0),
1646
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_4, "gout_peric0_top0_ipclk_4",
1647
+
"dout_peric0_uart_dbg",
1648
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1649
+
21, 0, 0),
1650
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_5, "gout_peric0_top0_ipclk_5",
1651
+
"dout_peric0_usi00_usi",
1652
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1653
+
21, 0, 0),
1654
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_6, "gout_peric0_top0_ipclk_6",
1655
+
"dout_peric0_usi_i2c",
1656
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1657
+
21, 0, 0),
1658
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_7, "gout_peric0_top0_ipclk_7",
1659
+
"dout_peric0_usi01_usi",
1660
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1661
+
21, 0, 0),
1662
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_8, "gout_peric0_top0_ipclk_8",
1663
+
"dout_peric0_usi_i2c",
1664
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1665
+
21, 0, 0),
1666
+
GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_9, "gout_peric0_top0_ipclk_9",
1667
+
"dout_peric0_usi02_usi",
1668
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1669
+
21, 0, 0),
1670
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_10, "gout_peric0_top0_pclk_10",
1671
+
"mout_peric0_bus_user",
1672
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1673
+
21, 0, 0),
1674
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_11, "gout_peric0_top0_pclk_11",
1675
+
"mout_peric0_bus_user",
1676
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1677
+
21, 0, 0),
1678
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_12, "gout_peric0_top0_pclk_12",
1679
+
"mout_peric0_bus_user",
1680
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
1681
+
21, 0, 0),
1682
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_13, "gout_peric0_top0_pclk_13",
1683
+
"mout_peric0_bus_user",
1684
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
1685
+
21, 0, 0),
1686
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_14, "gout_peric0_top0_pclk_14",
1687
+
"mout_peric0_bus_user",
1688
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
1689
+
21, 0, 0),
1690
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_15, "gout_peric0_top0_pclk_15",
1691
+
"mout_peric0_bus_user",
1692
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
1693
+
21, 0, 0),
1694
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_4, "gout_peric0_top0_pclk_4",
1695
+
"mout_peric0_bus_user",
1696
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1697
+
21, 0, 0),
1698
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_5, "gout_peric0_top0_pclk_5",
1699
+
"mout_peric0_bus_user",
1700
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1701
+
21, 0, 0),
1702
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_6, "gout_peric0_top0_pclk_6",
1703
+
"mout_peric0_bus_user",
1704
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1705
+
21, 0, 0),
1706
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_7, "gout_peric0_top0_pclk_7",
1707
+
"mout_peric0_bus_user",
1708
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1709
+
21, 0, 0),
1710
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_8, "gout_peric0_top0_pclk_8",
1711
+
"mout_peric0_bus_user",
1712
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1713
+
21, 0, 0),
1714
+
GATE(CLK_GOUT_PERIC0_TOP0_PCLK_9, "gout_peric0_top0_pclk_9",
1715
+
"mout_peric0_bus_user",
1716
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1717
+
21, 0, 0),
1718
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_0, "gout_peric0_top1_ipclk_0",
1719
+
"dout_peric0_usi_i2c",
1720
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
1721
+
21, 0, 0),
1722
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_3, "gout_peric0_top1_ipclk_3",
1723
+
"dout_peric0_usi13_usi",
1724
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3,
1725
+
21, 0, 0),
1726
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_4, "gout_peric0_top1_ipclk_4",
1727
+
"dout_peric0_usi_i2c",
1728
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4,
1729
+
21, 0, 0),
1730
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_5, "gout_peric0_top1_ipclk_5",
1731
+
"dout_peric0_usi14_usi",
1732
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5,
1733
+
21, 0, 0),
1734
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_6, "gout_peric0_top1_ipclk_6",
1735
+
"dout_peric0_usi_i2c",
1736
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6,
1737
+
21, 0, 0),
1738
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_7, "gout_peric0_top1_ipclk_7",
1739
+
"dout_peric0_usi15_usi",
1740
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7,
1741
+
21, 0, 0),
1742
+
GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_8, "gout_peric0_top1_ipclk_8",
1743
+
"dout_peric0_usi_i2c",
1744
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8,
1745
+
21, 0, 0),
1746
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_0, "gout_peric0_top1_pclk_0",
1747
+
"mout_peric0_bus_user",
1748
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
1749
+
21, 0, 0),
1750
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_15, "gout_peric0_top1_pclk_15",
1751
+
"mout_peric0_bus_user",
1752
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15,
1753
+
21, 0, 0),
1754
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_3, "gout_peric0_top1_pclk_3",
1755
+
"mout_peric0_bus_user",
1756
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3,
1757
+
21, 0, 0),
1758
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_4, "gout_peric0_top1_pclk_4",
1759
+
"mout_peric0_bus_user",
1760
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4,
1761
+
21, 0, 0),
1762
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_5, "gout_peric0_top1_pclk_5",
1763
+
"mout_peric0_bus_user",
1764
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5,
1765
+
21, 0, 0),
1766
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_6, "gout_peric0_top1_pclk_6",
1767
+
"mout_peric0_bus_user",
1768
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6,
1769
+
21, 0, 0),
1770
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_7, "gout_peric0_top1_pclk_7",
1771
+
"mout_peric0_bus_user",
1772
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7,
1773
+
21, 0, 0),
1774
+
GATE(CLK_GOUT_PERIC0_TOP1_PCLK_8, "gout_peric0_top1_pclk_8",
1775
+
"mout_peric0_bus_user",
1776
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8,
1777
+
21, 0, 0),
1778
+
GATE(CLK_GOUT_PERIC0_BUSP_CLK, "gout_peric0_busp_clk",
1779
+
"mout_peric0_bus_user",
1780
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
1781
+
21, 0, 0),
1782
+
GATE(CLK_GOUT_PERIC0_UART_DBG_CLK, "gout_peric0_uart_dbg_clk",
1783
+
"dout_peric0_uart_dbg",
1784
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
1785
+
21, 0, 0),
1786
+
GATE(CLK_GOUT_PERIC0_USI00_USI_CLK, "gout_peric0_usi00_usi_clk",
1787
+
"dout_peric0_usi00_usi",
1788
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
1789
+
21, 0, 0),
1790
+
GATE(CLK_GOUT_PERIC0_USI01_USI_CLK, "gout_peric0_usi01_usi_clk",
1791
+
"dout_peric0_usi01_usi",
1792
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
1793
+
21, 0, 0),
1794
+
GATE(CLK_GOUT_PERIC0_USI02_USI_CLK, "gout_peric0_usi02_usi_clk",
1795
+
"dout_peric0_usi02_usi",
1796
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
1797
+
21, 0, 0),
1798
+
GATE(CLK_GOUT_PERIC0_USI03_USI_CLK, "gout_peric0_usi03_usi_clk",
1799
+
"dout_peric0_usi03_usi",
1800
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
1801
+
21, 0, 0),
1802
+
GATE(CLK_GOUT_PERIC0_USI04_USI_CLK, "gout_peric0_usi04_usi_clk",
1803
+
"dout_peric0_usi04_usi",
1804
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
1805
+
21, 0, 0),
1806
+
GATE(CLK_GOUT_PERIC0_USI05_USI_CLK, "gout_peric0_usi05_usi_clk",
1807
+
"dout_peric0_usi05_usi",
1808
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
1809
+
21, 0, 0),
1810
+
GATE(CLK_GOUT_PERIC0_USI13_USI_CLK, "gout_peric0_usi13_usi_clk",
1811
+
"dout_peric0_usi13_usi",
1812
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
1813
+
21, 0, 0),
1814
+
GATE(CLK_GOUT_PERIC0_USI14_USI_CLK, "gout_peric0_usi14_usi_clk",
1815
+
"dout_peric0_usi14_usi",
1816
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
1817
+
21, 0, 0),
1818
+
GATE(CLK_GOUT_PERIC0_USI15_USI_CLK, "gout_peric0_usi15_usi_clk",
1819
+
"dout_peric0_usi15_usi",
1820
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
1821
+
21, 0, 0),
1822
+
GATE(CLK_GOUT_PERIC0_USI_I2C_CLK, "gout_peric0_usi_i2c_clk",
1823
+
"dout_peric0_usi_i2c",
1824
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
1825
+
21, 0, 0),
1826
+
GATE(CLK_GOUT_PERIC0_SYSREG_PCLK, "gout_peric0_sysreg_pclk",
1827
+
"mout_peric0_bus_user",
1828
+
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
1829
+
21, 0, 0)
1830
+
};
1831
+
1832
+
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1833
+
.mux_clks = peric0_mux_clks,
1834
+
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1835
+
.div_clks = peric0_div_clks,
1836
+
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1837
+
.gate_clks = peric0_gate_clks,
1838
+
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1839
+
.nr_clk_ids = CLKS_NR_PERIC0,
1840
+
.clk_regs = peric0_clk_regs,
1841
+
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1842
+
.clk_name = "bus",
1843
+
};
1844
+
1845
+
/* ---- CMU_PERIC1 --------------------------------------------------------- */
1846
+
1847
+
/* Register Offset definitions for CMU_PERIC1 (0x10700000) */
1848
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1849
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
1850
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0610
1851
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0614
1852
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0620
1853
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0624
1854
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0630
1855
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0634
1856
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0640
1857
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0644
1858
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0650
1859
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0654
1860
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0660
1861
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0664
1862
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0670
1863
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0674
1864
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0680
1865
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0684
1866
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0690
1867
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0694
1868
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a0
1869
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a4
1870
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b0
1871
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b4
1872
+
#define PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c0
1873
+
#define PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c4
1874
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1800
1875
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1804
1876
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1808
1877
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x180c
1878
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1810
1879
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1814
1880
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1818
1881
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x181c
1882
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1883
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1884
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI 0x1828
1885
+
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x182c
1886
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
1887
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK 0x2008
1888
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x200c
1889
+
#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK 0x2010
1890
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2014
1891
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
1892
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK 0x201c
1893
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x2020
1894
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x2024
1895
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2028
1896
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12 0x202c
1897
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13 0x2030
1898
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14 0x2034
1899
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15 0x2038
1900
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x203c
1901
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x2040
1902
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2044
1903
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12 0x2048
1904
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13 0x204c
1905
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14 0x2050
1906
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2054
1907
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2058
1908
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0 0x205c
1909
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1 0x2060
1910
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10 0x2064
1911
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12 0x206c
1912
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13 0x2070
1913
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14 0x2074
1914
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15 0x2078
1915
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2 0x207c
1916
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3 0x2080
1917
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4 0x2084
1918
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5 0x2088
1919
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6 0x208c
1920
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7 0x2090
1921
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9 0x2098
1922
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0 0x209c
1923
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1 0x20a0
1924
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10 0x20a4
1925
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12 0x20ac
1926
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13 0x20b0
1927
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14 0x20b4
1928
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15 0x20b8
1929
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2 0x20bc
1930
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3 0x20c0
1931
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4 0x20c4
1932
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5 0x20c8
1933
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6 0x20cc
1934
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7 0x20d0
1935
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9 0x20d8
1936
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x20dc
1937
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x20e0
1938
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK 0x20e4
1939
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK 0x20e8
1940
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK 0x20ec
1941
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK 0x20f0
1942
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x20f4
1943
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x20f8
1944
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK 0x20fc
1945
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK 0x2100
1946
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK 0x2104
1947
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2108
1948
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK 0x210c
1949
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK 0x2110
1950
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK 0x2114
1951
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK 0x2118
1952
+
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x211c
1953
+
1954
+
static const unsigned long peric1_clk_regs[] __initconst = {
1955
+
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
1956
+
PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
1957
+
PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
1958
+
PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER,
1959
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
1960
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER,
1961
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
1962
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER,
1963
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
1964
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER,
1965
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
1966
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER,
1967
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
1968
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
1969
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
1970
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
1971
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
1972
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
1973
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
1974
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER,
1975
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
1976
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER,
1977
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
1978
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER,
1979
+
PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
1980
+
PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER,
1981
+
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
1982
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1983
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1984
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1985
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1986
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1987
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1988
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1989
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1990
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1991
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
1992
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1993
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
1994
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
1995
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
1996
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK,
1997
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
1998
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
1999
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
2000
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
2001
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
2002
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
2003
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12,
2004
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13,
2005
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14,
2006
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15,
2007
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
2008
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
2009
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
2010
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12,
2011
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13,
2012
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14,
2013
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
2014
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
2015
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0,
2016
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1,
2017
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10,
2018
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12,
2019
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13,
2020
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14,
2021
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15,
2022
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2,
2023
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3,
2024
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4,
2025
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5,
2026
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6,
2027
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7,
2028
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9,
2029
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0,
2030
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1,
2031
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10,
2032
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12,
2033
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13,
2034
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14,
2035
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15,
2036
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2,
2037
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3,
2038
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4,
2039
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5,
2040
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6,
2041
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7,
2042
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9,
2043
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
2044
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
2045
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
2046
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
2047
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
2048
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
2049
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
2050
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
2051
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
2052
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
2053
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
2054
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
2055
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
2056
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
2057
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK,
2058
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK,
2059
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
2060
+
};
2061
+
2062
+
/* Parent clock list for CMU_PERIC1 muxes */
2063
+
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
2064
+
PNAME(mout_peric1_uart_bt_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2065
+
PNAME(mout_peric1_usi06_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2066
+
PNAME(mout_peric1_usi07_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2067
+
PNAME(mout_peric1_usi08_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2068
+
PNAME(mout_peric1_usi09_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2069
+
PNAME(mout_peric1_usi10_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2070
+
PNAME(mout_peric1_usi11_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2071
+
PNAME(mout_peric1_usi12_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2072
+
PNAME(mout_peric1_usi18_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2073
+
PNAME(mout_peric1_usi16_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2074
+
PNAME(mout_peric1_usi17_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2075
+
PNAME(mout_peric1_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2076
+
2077
+
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
2078
+
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
2079
+
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
2080
+
4, 1),
2081
+
MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
2082
+
mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
2083
+
4, 1),
2084
+
MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user",
2085
+
mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
2086
+
4, 1),
2087
+
MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user",
2088
+
mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
2089
+
4, 1),
2090
+
MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user",
2091
+
mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
2092
+
4, 1),
2093
+
MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user",
2094
+
mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
2095
+
4, 1),
2096
+
MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user",
2097
+
mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
2098
+
4, 1),
2099
+
MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user",
2100
+
mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
2101
+
4, 1),
2102
+
MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user",
2103
+
mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
2104
+
4, 1),
2105
+
MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user",
2106
+
mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
2107
+
4, 1),
2108
+
MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user",
2109
+
mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
2110
+
4, 1),
2111
+
MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user",
2112
+
mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
2113
+
4, 1),
2114
+
MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user",
2115
+
mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
2116
+
4, 1),
2117
+
};
2118
+
2119
+
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
2120
+
DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt",
2121
+
"mout_peric1_uart_bt_user",
2122
+
CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
2123
+
0, 4),
2124
+
DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
2125
+
"mout_peric1_usi06_usi_user",
2126
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
2127
+
0, 4),
2128
+
DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
2129
+
"mout_peric1_usi07_usi_user",
2130
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
2131
+
0, 4),
2132
+
DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
2133
+
"mout_peric1_usi08_usi_user",
2134
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
2135
+
0, 4),
2136
+
DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi",
2137
+
"mout_peric1_usi18_usi_user",
2138
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
2139
+
0, 4),
2140
+
DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
2141
+
"mout_peric1_usi12_usi_user",
2142
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
2143
+
0, 4),
2144
+
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
2145
+
"mout_peric1_usi09_usi_user",
2146
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
2147
+
0, 4),
2148
+
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
2149
+
"mout_peric1_usi10_usi_user",
2150
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
2151
+
0, 4),
2152
+
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
2153
+
"mout_peric1_usi11_usi_user",
2154
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
2155
+
0, 4),
2156
+
DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
2157
+
"mout_peric1_usi16_usi_user",
2158
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
2159
+
0, 4),
2160
+
DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
2161
+
"mout_peric1_usi17_usi_user",
2162
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
2163
+
0, 4),
2164
+
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
2165
+
"mout_peric1_usi_i2c_user",
2166
+
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
2167
+
0, 4),
2168
+
};
2169
+
2170
+
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
2171
+
GATE(CLK_GOUT_PERIC1_CMU_PCLK, "gout_peric1_cmu_pclk",
2172
+
"mout_peric1_bus_user",
2173
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
2174
+
21, CLK_IS_CRITICAL, 0),
2175
+
GATE(CLK_GOUT_PERIC1_UART_BT_CLK, "gout_peric1_uart_bt_clk",
2176
+
"dout_peric1_uart_bt",
2177
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
2178
+
21, 0, 0),
2179
+
GATE(CLK_GOUT_PERIC1_USI12_USI_CLK, "gout_peric1_usi12_usi_clk",
2180
+
"dout_peric1_usi12_usi",
2181
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
2182
+
21, 0, 0),
2183
+
GATE(CLK_GOUT_PERIC1_USI18_USI_CLK, "gout_peric1_usi18_usi_clk",
2184
+
"dout_peric1_usi18_usi",
2185
+
CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK,
2186
+
21, 0, 0),
2187
+
GATE(CLK_GOUT_PERIC1_D_TZPC_PCLK, "gout_peric1_d_tzpc_pclk",
2188
+
"dout_peric1_bus_user",
2189
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
2190
+
21, 0, 0),
2191
+
GATE(CLK_GOUT_PERIC1_GPIO_PCLK, "gout_peric1_gpio_pclk",
2192
+
"mout_peric1_bus_user",
2193
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
2194
+
21, CLK_IGNORE_UNUSED, 0),
2195
+
GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK, "gout_peric1_lhm_axi_p_csis_clk",
2196
+
"mout_peric1_bus_user",
2197
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
2198
+
21, 0, 0),
2199
+
GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CLK, "gout_peric1_lhm_axi_p_clk",
2200
+
"mout_peric1_bus_user",
2201
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
2202
+
21, CLK_IS_CRITICAL, 0),
2203
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_10, "gout_peric1_top0_ipclk_10",
2204
+
"dout_peric1_usi06_usi",
2205
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
2206
+
21, 0, 0),
2207
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_11, "gout_peric1_top0_ipclk_11",
2208
+
"dout_peric1_usi_i2c",
2209
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
2210
+
21, 0, 0),
2211
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_12, "gout_peric1_top0_ipclk_12",
2212
+
"dout_peric1_usi07_usi",
2213
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12,
2214
+
21, 0, 0),
2215
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_13, "gout_peric1_top0_ipclk_13",
2216
+
"dout_peric1_usi_i2c",
2217
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13,
2218
+
21, 0, 0),
2219
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_14, "gout_peric1_top0_ipclk_14",
2220
+
"dout_peric1_usi08_usi",
2221
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14,
2222
+
21, 0, 0),
2223
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_15, "gout_peric1_top0_ipclk_15",
2224
+
"dout_peric1_usi_i2c",
2225
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15,
2226
+
21, 0, 0),
2227
+
GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_4, "gout_peric1_top0_ipclk_4",
2228
+
"dout_peric1_uart_bt",
2229
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
2230
+
21, 0, 0),
2231
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_10, "gout_peric1_top0_pclk_10",
2232
+
"mout_peric1_bus_user",
2233
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
2234
+
21, 0, 0),
2235
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_11, "gout_peric1_top0_pclk_11",
2236
+
"mout_peric1_bus_user",
2237
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
2238
+
21, 0, 0),
2239
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_12, "gout_peric1_top0_pclk_12",
2240
+
"mout_peric1_bus_user",
2241
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12,
2242
+
21, 0, 0),
2243
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_13, "gout_peric1_top0_pclk_13",
2244
+
"mout_peric1_bus_user",
2245
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13,
2246
+
21, 0, 0),
2247
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_14, "gout_peric1_top0_pclk_14",
2248
+
"mout_peric1_bus_user",
2249
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14,
2250
+
21, 0, 0),
2251
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_15, "gout_peric1_top0_pclk_15",
2252
+
"mout_peric1_bus_user",
2253
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
2254
+
21, 0, 0),
2255
+
GATE(CLK_GOUT_PERIC1_TOP0_PCLK_4, "gout_peric1_top0_pclk_4",
2256
+
"mout_peric1_bus_user",
2257
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
2258
+
21, 0, 0),
2259
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_0, "gout_peric1_top1_ipclk_0",
2260
+
"dout_peric1_usi09_usi",
2261
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0,
2262
+
21, 0, 0),
2263
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_1, "gout_peric1_top1_ipclk_1",
2264
+
"dout_peric1_usi_i2c",
2265
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1,
2266
+
21, 0, 0),
2267
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_10, "gout_peric1_top1_ipclk_10",
2268
+
"dout_peric1_usi_i2c",
2269
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10,
2270
+
21, 0, 0),
2271
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_12, "gout_peric1_top1_ipclk_12",
2272
+
"dout_peric1_usi12_usi",
2273
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12,
2274
+
21, 0, 0),
2275
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_13, "gout_peric1_top1_ipclk_13",
2276
+
"dout_peric1_usi_i2c",
2277
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13,
2278
+
21, 0, 0),
2279
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_14, "gout_peric1_top1_ipclk_14",
2280
+
"dout_peric1_usi18_usi",
2281
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14,
2282
+
21, 0, 0),
2283
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_15, "gout_peric1_top1_ipclk_15",
2284
+
"dout_peric1_usi_i2c",
2285
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15,
2286
+
21, 0, 0),
2287
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_2, "gout_peric1_top1_ipclk_2",
2288
+
"dout_peric1_usi10_usi",
2289
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2,
2290
+
21, 0, 0),
2291
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_3, "gout_peric1_top1_ipclk_3",
2292
+
"dout_peric1_usi_i2c",
2293
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3,
2294
+
21, 0, 0),
2295
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_4, "gout_peric1_top1_ipclk_4",
2296
+
"dout_peric1_usi11_usi",
2297
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4,
2298
+
21, 0, 0),
2299
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_5, "gout_peric1_top1_ipclk_5",
2300
+
"dout_peric1_usi_i2c",
2301
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5,
2302
+
21, 0, 0),
2303
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_6, "gout_peric1_top1_ipclk_6",
2304
+
"dout_peric1_usi16_usi",
2305
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6,
2306
+
21, 0, 0),
2307
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_7, "gout_peric1_top1_ipclk_7",
2308
+
"dout_peric1_usi_i2c",
2309
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7,
2310
+
21, 0, 0),
2311
+
GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_9, "gout_peric1_top1_ipclk_9",
2312
+
"dout_peric1_usi17_usi",
2313
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9,
2314
+
21, 0, 0),
2315
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_0, "gout_peric1_top1_pclk_0",
2316
+
"mout_peric1_bus_user",
2317
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0,
2318
+
21, 0, 0),
2319
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_1, "gout_peric1_top1_pclk_1",
2320
+
"mout_peric1_bus_user",
2321
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1,
2322
+
21, 0, 0),
2323
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_10, "gout_peric1_top1_pclk_10",
2324
+
"dout_peric1_bus_user",
2325
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10,
2326
+
21, 0, 0),
2327
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_12, "gout_peric1_top1_pclk_12",
2328
+
"dout_peric1_bus_user",
2329
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12,
2330
+
21, 0, 0),
2331
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_13, "gout_peric1_top1_pclk_13",
2332
+
"mout_peric1_bus_user",
2333
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13,
2334
+
21, 0, 0),
2335
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_14, "gout_peric1_top1_pclk_14",
2336
+
"mout_peric1_bus_user",
2337
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14,
2338
+
21, 0, 0),
2339
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_15, "gout_peric1_top1_pclk_15",
2340
+
"mout_peric1_bus_user",
2341
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15,
2342
+
21, 0, 0),
2343
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_2, "gout_peric1_top1_pclk_2",
2344
+
"mout_peric1_bus_user",
2345
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2,
2346
+
21, 0, 0),
2347
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_3, "gout_peric1_top1_pclk_3",
2348
+
"mout_peric1_bus_user",
2349
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3,
2350
+
21, 0, 0),
2351
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_4, "gout_peric1_top1_pclk_4",
2352
+
"mout_peric1_bus_user",
2353
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4,
2354
+
21, 0, 0),
2355
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_5, "gout_peric1_top1_pclk_5",
2356
+
"mout_peric1_bus_user",
2357
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5,
2358
+
21, 0, 0),
2359
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_6, "gout_peric1_top1_pclk_6",
2360
+
"mout_peric1_bus_user",
2361
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6,
2362
+
21, 0, 0),
2363
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_7, "gout_peric1_top1_pclk_7",
2364
+
"mout_peric1_bus_user",
2365
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7,
2366
+
21, 0, 0),
2367
+
GATE(CLK_GOUT_PERIC1_TOP1_PCLK_9, "gout_peric1_top1_pclk_9",
2368
+
"dout_peric1_bus_user",
2369
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9,
2370
+
21, 0, 0),
2371
+
GATE(CLK_GOUT_PERIC1_BUSP_CLK, "gout_peric1_busp_clk",
2372
+
"mout_peric1_bus_user",
2373
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
2374
+
21, 0, 0),
2375
+
GATE(CLK_GOUT_PERIC1_OSCCLK_CLK, "gout_peric1_oscclk_clk",
2376
+
"oscclk",
2377
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
2378
+
21, 0, 0),
2379
+
GATE(CLK_GOUT_PERIC1_USI06_USI_CLK, "gout_peric1_usi06_usi_clk",
2380
+
"dout_peric1_usi06_usi",
2381
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
2382
+
21, 0, 0),
2383
+
GATE(CLK_GOUT_PERIC1_USI07_USI_CLK, "gout_peric1_usi07_usi_clk",
2384
+
"dout_peric1_usi07_usi",
2385
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
2386
+
21, 0, 0),
2387
+
GATE(CLK_GOUT_PERIC1_USI08_USI_CLK, "gout_peric1_usi08_usi_clk",
2388
+
"dout_peric1_usi08_usi",
2389
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
2390
+
21, 0, 0),
2391
+
GATE(CLK_GOUT_PERIC1_USI09_USI_CLK, "gout_peric1_usi09_usi_clk",
2392
+
"dout_peric1_usi09_usi",
2393
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
2394
+
21, 0, 0),
2395
+
GATE(CLK_GOUT_PERIC1_USI10_USI_CLK, "gout_peric1_usi10_usi_clk",
2396
+
"dout_peric1_usi10_usi",
2397
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
2398
+
21, 0, 0),
2399
+
GATE(CLK_GOUT_PERIC1_USI11_USI_CLK, "gout_peric1_usi11_usi_clk",
2400
+
"dout_peric1_usi11_usi",
2401
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
2402
+
21, 0, 0),
2403
+
GATE(CLK_GOUT_PERIC1_USI16_USI_CLK, "gout_peric1_usi16_usi_clk",
2404
+
"dout_peric1_usi16_usi",
2405
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
2406
+
21, 0, 0),
2407
+
GATE(CLK_GOUT_PERIC1_USI17_USI_CLK, "gout_peric1_usi17_usi_clk",
2408
+
"dout_peric1_usi17_usi",
2409
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
2410
+
21, 0, 0),
2411
+
GATE(CLK_GOUT_PERIC1_USI_I2C_CLK, "gout_peric1_usi_i2c_clk",
2412
+
"dout_peric1_usi_i2c",
2413
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
2414
+
21, 0, 0),
2415
+
GATE(CLK_GOUT_PERIC1_SYSREG_PCLK, "gout_peric1_sysreg_pclk",
2416
+
"mout_peric1_bus_user",
2417
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
2418
+
21, 0, 0),
2419
+
GATE(CLK_GOUT_PERIC1_USI16_I3C_PCLK, "gout_peric1_usi16_i3c_pclk",
2420
+
"mout_peric1_bus_user",
2421
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
2422
+
21, 0, 0),
2423
+
GATE(CLK_GOUT_PERIC1_USI16_I3C_SCLK, "gout_peric1_usi16_i3c_sclk",
2424
+
"dout_peric1_usi_i2c",
2425
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
2426
+
21, 0, 0),
2427
+
GATE(CLK_GOUT_PERIC1_USI17_I3C_PCLK, "gout_peric1_usi17_i3c_pclk",
2428
+
"dout_peric1_bus_user",
2429
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK,
2430
+
21, 0, 0),
2431
+
GATE(CLK_GOUT_PERIC1_USI17_I3C_SCLK, "gout_peric1_usi17_i3c_sclk",
2432
+
"dout_peric1_usi_i2c",
2433
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK,
2434
+
21, 0, 0),
2435
+
GATE(CLK_GOUT_PERIC1_XIU_P_ACLK, "gout_peric1_xiu_p_aclk",
2436
+
"mout_peric1_bus_user",
2437
+
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
2438
+
21, CLK_IGNORE_UNUSED, 0),
2439
+
};
2440
+
2441
+
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
2442
+
.mux_clks = peric1_mux_clks,
2443
+
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
2444
+
.div_clks = peric1_div_clks,
2445
+
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
2446
+
.gate_clks = peric1_gate_clks,
2447
+
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
2448
+
.nr_clk_ids = CLKS_NR_PERIC1,
2449
+
.clk_regs = peric1_clk_regs,
2450
+
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
2451
+
.clk_name = "bus",
1354
2452
};
1355
2453
1356
2454
/* ---- CMU_PERIS ----------------------------------------------------------- */
···
2690
1500
{
2691
1501
.compatible = "samsung,exynos990-cmu-hsi0",
2692
1502
.data = &hsi0_cmu_info,
1503
+
}, {
1504
+
.compatible = "samsung,exynos990-cmu-peric0",
1505
+
.data = &peric0_cmu_info,
1506
+
}, {
1507
+
.compatible = "samsung,exynos990-cmu-peric1",
1508
+
.data = &peric1_cmu_info,
2693
1509
},
2694
1510
{ },
2695
1511
};
+14
-14
drivers/clk/samsung/clk-fsd.c
+14
-14
drivers/clk/samsung/clk-fsd.c
···
89
89
#define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)
90
90
#define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)
91
91
#define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1)
92
-
#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)
92
+
#define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_PCLK + 1)
93
93
94
94
static const unsigned long cmu_clk_regs[] __initconst = {
95
95
PLL_LOCKTIME_PLL_SHARED0,
···
1646
1646
};
1647
1647
1648
1648
static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
1649
-
PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
1649
+
PLL(pll_142xx, CAM_CSI_PLL, "fout_pll_cam_csi", "fin_pll",
1650
1650
PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
1651
1651
};
1652
1652
···
1682
1682
GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
1683
1683
GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1684
1684
GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1685
-
GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1685
+
GATE(CAM_CSI0_0_IPCLKPORT_I_PCLK, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1686
1686
GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1687
1687
GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1688
1688
GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1689
-
GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1689
+
GATE(CAM_CSI0_1_IPCLKPORT_I_PCLK, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1690
1690
GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1691
1691
GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1692
1692
GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1693
-
GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1693
+
GATE(CAM_CSI0_2_IPCLKPORT_I_PCLK, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1694
1694
GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1695
1695
GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
1696
1696
GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1697
-
GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1697
+
GATE(CAM_CSI0_3_IPCLKPORT_I_PCLK, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1698
1698
GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1699
1699
GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1700
1700
GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1701
-
GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1701
+
GATE(CAM_CSI1_0_IPCLKPORT_I_PCLK, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1702
1702
GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1703
1703
GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1704
1704
GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1705
-
GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1705
+
GATE(CAM_CSI1_1_IPCLKPORT_I_PCLK, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1706
1706
GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1707
1707
GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1708
1708
GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1709
-
GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1709
+
GATE(CAM_CSI1_2_IPCLKPORT_I_PCLK, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1710
1710
GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1711
1711
GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
1712
1712
GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1713
-
GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1713
+
GATE(CAM_CSI1_3_IPCLKPORT_I_PCLK, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1714
1714
GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1715
1715
GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1716
1716
GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1717
-
GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1717
+
GATE(CAM_CSI2_0_IPCLKPORT_I_PCLK, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
1718
1718
GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1719
1719
GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1720
1720
GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1721
-
GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1721
+
GATE(CAM_CSI2_1_IPCLKPORT_I_PCLK, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
1722
1722
GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1723
1723
GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1724
1724
GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1725
-
GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1725
+
GATE(CAM_CSI2_2_IPCLKPORT_I_PCLK, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
1726
1726
GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1727
1727
GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
1728
1728
GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
1729
-
GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1729
+
GATE(CAM_CSI2_3_IPCLKPORT_I_PCLK, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
1730
1730
GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1731
1731
GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
1732
1732
"dout_cam_csi_busd",
+146
-15
drivers/clk/samsung/clk-pll.c
+146
-15
drivers/clk/samsung/clk-pll.c
···
49
49
return NULL;
50
50
}
51
51
52
-
static long samsung_pll_round_rate(struct clk_hw *hw,
53
-
unsigned long drate, unsigned long *prate)
52
+
static int samsung_pll_determine_rate(struct clk_hw *hw,
53
+
struct clk_rate_request *req)
54
54
{
55
55
struct samsung_clk_pll *pll = to_clk_pll(hw);
56
56
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
···
58
58
59
59
/* Assuming rate_table is in descending order */
60
60
for (i = 0; i < pll->rate_count; i++) {
61
-
if (drate >= rate_table[i].rate)
62
-
return rate_table[i].rate;
61
+
if (req->rate >= rate_table[i].rate) {
62
+
req->rate = rate_table[i].rate;
63
+
64
+
return 0;
65
+
}
63
66
}
64
67
65
68
/* return minimum supported value */
66
-
return rate_table[i - 1].rate;
69
+
req->rate = rate_table[i - 1].rate;
70
+
71
+
return 0;
67
72
}
68
73
69
74
static bool pll_early_timeout = true;
···
278
273
}
279
274
280
275
/* Set PLL lock time. */
281
-
if (pll->type == pll_142xx)
276
+
if (pll->type == pll_142xx || pll->type == pll_1017x)
282
277
writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
283
278
pll->lock_reg);
284
279
else
···
303
298
304
299
static const struct clk_ops samsung_pll35xx_clk_ops = {
305
300
.recalc_rate = samsung_pll35xx_recalc_rate,
306
-
.round_rate = samsung_pll_round_rate,
301
+
.determine_rate = samsung_pll_determine_rate,
307
302
.set_rate = samsung_pll35xx_set_rate,
308
303
.enable = samsung_pll3xxx_enable,
309
304
.disable = samsung_pll3xxx_disable,
···
416
411
static const struct clk_ops samsung_pll36xx_clk_ops = {
417
412
.recalc_rate = samsung_pll36xx_recalc_rate,
418
413
.set_rate = samsung_pll36xx_set_rate,
419
-
.round_rate = samsung_pll_round_rate,
414
+
.determine_rate = samsung_pll_determine_rate,
420
415
.enable = samsung_pll3xxx_enable,
421
416
.disable = samsung_pll3xxx_disable,
422
417
};
···
519
514
520
515
static const struct clk_ops samsung_pll0822x_clk_ops = {
521
516
.recalc_rate = samsung_pll0822x_recalc_rate,
522
-
.round_rate = samsung_pll_round_rate,
517
+
.determine_rate = samsung_pll_determine_rate,
523
518
.set_rate = samsung_pll0822x_set_rate,
524
519
.enable = samsung_pll3xxx_enable,
525
520
.disable = samsung_pll3xxx_disable,
···
617
612
static const struct clk_ops samsung_pll0831x_clk_ops = {
618
613
.recalc_rate = samsung_pll0831x_recalc_rate,
619
614
.set_rate = samsung_pll0831x_set_rate,
620
-
.round_rate = samsung_pll_round_rate,
615
+
.determine_rate = samsung_pll_determine_rate,
621
616
.enable = samsung_pll3xxx_enable,
622
617
.disable = samsung_pll3xxx_disable,
623
618
};
···
740
735
741
736
static const struct clk_ops samsung_pll45xx_clk_ops = {
742
737
.recalc_rate = samsung_pll45xx_recalc_rate,
743
-
.round_rate = samsung_pll_round_rate,
738
+
.determine_rate = samsung_pll_determine_rate,
744
739
.set_rate = samsung_pll45xx_set_rate,
745
740
};
746
741
···
885
880
886
881
static const struct clk_ops samsung_pll46xx_clk_ops = {
887
882
.recalc_rate = samsung_pll46xx_recalc_rate,
888
-
.round_rate = samsung_pll_round_rate,
883
+
.determine_rate = samsung_pll_determine_rate,
889
884
.set_rate = samsung_pll46xx_set_rate,
890
885
};
891
886
···
1098
1093
1099
1094
static const struct clk_ops samsung_pll2550xx_clk_ops = {
1100
1095
.recalc_rate = samsung_pll2550xx_recalc_rate,
1101
-
.round_rate = samsung_pll_round_rate,
1096
+
.determine_rate = samsung_pll_determine_rate,
1102
1097
.set_rate = samsung_pll2550xx_set_rate,
1103
1098
};
1104
1099
···
1190
1185
1191
1186
static const struct clk_ops samsung_pll2650x_clk_ops = {
1192
1187
.recalc_rate = samsung_pll2650x_recalc_rate,
1193
-
.round_rate = samsung_pll_round_rate,
1188
+
.determine_rate = samsung_pll_determine_rate,
1194
1189
.set_rate = samsung_pll2650x_set_rate,
1195
1190
};
1196
1191
···
1282
1277
static const struct clk_ops samsung_pll2650xx_clk_ops = {
1283
1278
.recalc_rate = samsung_pll2650xx_recalc_rate,
1284
1279
.set_rate = samsung_pll2650xx_set_rate,
1285
-
.round_rate = samsung_pll_round_rate,
1280
+
.determine_rate = samsung_pll_determine_rate,
1286
1281
};
1287
1282
1288
1283
static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
···
1328
1323
1329
1324
static const struct clk_ops samsung_pll531x_clk_ops = {
1330
1325
.recalc_rate = samsung_pll531x_recalc_rate,
1326
+
};
1327
+
1328
+
/*
1329
+
* PLL1031x Clock Type
1330
+
*/
1331
+
#define PLL1031X_LOCK_FACTOR (500)
1332
+
1333
+
#define PLL1031X_MDIV_MASK (0x3ff)
1334
+
#define PLL1031X_PDIV_MASK (0x3f)
1335
+
#define PLL1031X_SDIV_MASK (0x7)
1336
+
#define PLL1031X_MDIV_SHIFT (16)
1337
+
#define PLL1031X_PDIV_SHIFT (8)
1338
+
#define PLL1031X_SDIV_SHIFT (0)
1339
+
1340
+
#define PLL1031X_KDIV_MASK (0xffff)
1341
+
#define PLL1031X_KDIV_SHIFT (0)
1342
+
#define PLL1031X_MFR_MASK (0x3f)
1343
+
#define PLL1031X_MRR_MASK (0x1f)
1344
+
#define PLL1031X_MFR_SHIFT (16)
1345
+
#define PLL1031X_MRR_SHIFT (24)
1346
+
1347
+
static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw,
1348
+
unsigned long parent_rate)
1349
+
{
1350
+
struct samsung_clk_pll *pll = to_clk_pll(hw);
1351
+
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3;
1352
+
u64 fvco = parent_rate;
1353
+
1354
+
pll_con0 = readl_relaxed(pll->con_reg);
1355
+
pll_con3 = readl_relaxed(pll->con_reg + 0xc);
1356
+
mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
1357
+
pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
1358
+
sdiv = (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK;
1359
+
kdiv = (pll_con3 & PLL1031X_KDIV_MASK);
1360
+
1361
+
fvco *= (mdiv << PLL1031X_MDIV_SHIFT) + kdiv;
1362
+
do_div(fvco, (pdiv << sdiv));
1363
+
fvco >>= PLL1031X_MDIV_SHIFT;
1364
+
1365
+
return (unsigned long)fvco;
1366
+
}
1367
+
1368
+
static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3,
1369
+
const struct samsung_pll_rate_table *rate)
1370
+
{
1371
+
u32 old_mdiv, old_pdiv, old_kdiv;
1372
+
1373
+
old_mdiv = (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK;
1374
+
old_pdiv = (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK;
1375
+
old_kdiv = (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK;
1376
+
1377
+
return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv ||
1378
+
old_kdiv != rate->kdiv);
1379
+
}
1380
+
1381
+
static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drate,
1382
+
unsigned long prate)
1383
+
{
1384
+
struct samsung_clk_pll *pll = to_clk_pll(hw);
1385
+
const struct samsung_pll_rate_table *rate;
1386
+
u32 con0, con3;
1387
+
1388
+
/* Get required rate settings from table */
1389
+
rate = samsung_get_pll_settings(pll, drate);
1390
+
if (!rate) {
1391
+
pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1392
+
drate, clk_hw_get_name(hw));
1393
+
return -EINVAL;
1394
+
}
1395
+
1396
+
con0 = readl_relaxed(pll->con_reg);
1397
+
con3 = readl_relaxed(pll->con_reg + 0xc);
1398
+
1399
+
if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) {
1400
+
/* If only s change, change just s value only */
1401
+
con0 &= ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT);
1402
+
con0 |= rate->sdiv << PLL1031X_SDIV_SHIFT;
1403
+
writel_relaxed(con0, pll->con_reg);
1404
+
1405
+
return 0;
1406
+
}
1407
+
1408
+
/* Set PLL lock time. */
1409
+
writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg);
1410
+
1411
+
/* Set PLL M, P, and S values. */
1412
+
con0 &= ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) |
1413
+
(PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) |
1414
+
(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT));
1415
+
1416
+
con0 |= (rate->mdiv << PLL1031X_MDIV_SHIFT) |
1417
+
(rate->pdiv << PLL1031X_PDIV_SHIFT) |
1418
+
(rate->sdiv << PLL1031X_SDIV_SHIFT);
1419
+
1420
+
/* Set PLL K, MFR and MRR values. */
1421
+
con3 = readl_relaxed(pll->con_reg + 0xc);
1422
+
con3 &= ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) |
1423
+
(PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) |
1424
+
(PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT));
1425
+
con3 |= (rate->kdiv << PLL1031X_KDIV_SHIFT) |
1426
+
(rate->mfr << PLL1031X_MFR_SHIFT) |
1427
+
(rate->mrr << PLL1031X_MRR_SHIFT);
1428
+
1429
+
/* Write configuration to PLL */
1430
+
writel_relaxed(con0, pll->con_reg);
1431
+
writel_relaxed(con3, pll->con_reg + 0xc);
1432
+
1433
+
/* Wait for PLL lock if the PLL is enabled */
1434
+
return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
1435
+
}
1436
+
1437
+
static const struct clk_ops samsung_pll1031x_clk_ops = {
1438
+
.recalc_rate = samsung_pll1031x_recalc_rate,
1439
+
.determine_rate = samsung_pll_determine_rate,
1440
+
.set_rate = samsung_pll1031x_set_rate,
1441
+
};
1442
+
1443
+
static const struct clk_ops samsung_pll1031x_clk_min_ops = {
1444
+
.recalc_rate = samsung_pll1031x_recalc_rate,
1331
1445
};
1332
1446
1333
1447
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
···
1497
1373
case pll_1451x:
1498
1374
case pll_1452x:
1499
1375
case pll_142xx:
1376
+
case pll_1017x:
1500
1377
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
1501
1378
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
1502
1379
if (!pll->rate_table)
···
1592
1467
case pll_531x:
1593
1468
case pll_4311:
1594
1469
init.ops = &samsung_pll531x_clk_ops;
1470
+
break;
1471
+
case pll_1031x:
1472
+
if (!pll->rate_table)
1473
+
init.ops = &samsung_pll1031x_clk_min_ops;
1474
+
else
1475
+
init.ops = &samsung_pll1031x_clk_ops;
1595
1476
break;
1596
1477
default:
1597
1478
pr_warn("%s: Unknown pll type for pll clk %s\n",
+2
drivers/clk/samsung/clk-pll.h
+2
drivers/clk/samsung/clk-pll.h
+1
-1
drivers/clk/tegra/Kconfig
+1
-1
drivers/clk/tegra/Kconfig
+26
-4
drivers/clk/tegra/clk-tegra114.c
+26
-4
drivers/clk/tegra/clk-tegra114.c
···
11
11
#include <linux/export.h>
12
12
#include <linux/clk/tegra.h>
13
13
#include <dt-bindings/clock/tegra114-car.h>
14
+
#include <dt-bindings/reset/nvidia,tegra114-car.h>
14
15
15
16
#include "clk.h"
16
17
#include "clk-id.h"
···
1273
1272
*
1274
1273
* Assert the reset line of the DFLL's DVCO. No return value.
1275
1274
*/
1276
-
void tegra114_clock_assert_dfll_dvco_reset(void)
1275
+
static void tegra114_clock_assert_dfll_dvco_reset(void)
1277
1276
{
1278
1277
u32 v;
1279
1278
···
1282
1281
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1283
1282
tegra114_car_barrier();
1284
1283
}
1285
-
EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1286
1284
1287
1285
/**
1288
1286
* tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
···
1289
1289
* Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1290
1290
* operate. No return value.
1291
1291
*/
1292
-
void tegra114_clock_deassert_dfll_dvco_reset(void)
1292
+
static void tegra114_clock_deassert_dfll_dvco_reset(void)
1293
1293
{
1294
1294
u32 v;
1295
1295
···
1298
1298
writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1299
1299
tegra114_car_barrier();
1300
1300
}
1301
-
EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1301
+
1302
+
static int tegra114_reset_assert(unsigned long id)
1303
+
{
1304
+
if (id == TEGRA114_RST_DFLL_DVCO)
1305
+
tegra114_clock_assert_dfll_dvco_reset();
1306
+
else
1307
+
return -EINVAL;
1308
+
1309
+
return 0;
1310
+
}
1311
+
1312
+
static int tegra114_reset_deassert(unsigned long id)
1313
+
{
1314
+
if (id == TEGRA114_RST_DFLL_DVCO)
1315
+
tegra114_clock_deassert_dfll_dvco_reset();
1316
+
else
1317
+
return -EINVAL;
1318
+
1319
+
return 0;
1320
+
}
1302
1321
1303
1322
static void __init tegra114_clock_init(struct device_node *np)
1304
1323
{
···
1362
1343
ARRAY_SIZE(tegra114_audio_plls), 24000000);
1363
1344
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1364
1345
&pll_x_params);
1346
+
1347
+
tegra_init_special_resets(1, tegra114_reset_assert,
1348
+
tegra114_reset_deassert);
1365
1349
1366
1350
tegra_add_of_provider(np, of_clk_src_onecell_get);
1367
1351
tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
+131
-27
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+131
-27
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
···
29
29
};
30
30
31
31
/* Maximum CPU frequency, indexed by CPU speedo id */
32
+
static const unsigned long tegra114_cpu_max_freq_table[] = {
33
+
[0] = 2040000000UL,
34
+
[1] = 1810500000UL,
35
+
[2] = 1912500000UL,
36
+
[3] = 1810500000UL,
37
+
};
38
+
39
+
#define T114_CPU_CVB_TABLE \
40
+
.min_millivolts = 1000, \
41
+
.max_millivolts = 1320, \
42
+
.speedo_scale = 100, \
43
+
.voltage_scale = 1000, \
44
+
.entries = { \
45
+
{ 306000000UL, { 2190643, -141851, 3576 } }, \
46
+
{ 408000000UL, { 2250968, -144331, 3576 } }, \
47
+
{ 510000000UL, { 2313333, -146811, 3576 } }, \
48
+
{ 612000000UL, { 2377738, -149291, 3576 } }, \
49
+
{ 714000000UL, { 2444183, -151771, 3576 } }, \
50
+
{ 816000000UL, { 2512669, -154251, 3576 } }, \
51
+
{ 918000000UL, { 2583194, -156731, 3576 } }, \
52
+
{ 1020000000UL, { 2655759, -159211, 3576 } }, \
53
+
{ 1122000000UL, { 2730365, -161691, 3576 } }, \
54
+
{ 1224000000UL, { 2807010, -164171, 3576 } }, \
55
+
{ 1326000000UL, { 2885696, -166651, 3576 } }, \
56
+
{ 1428000000UL, { 2966422, -169131, 3576 } }, \
57
+
{ 1530000000UL, { 3049183, -171601, 3576 } }, \
58
+
{ 1606500000UL, { 3112179, -173451, 3576 } }, \
59
+
{ 1708500000UL, { 3198504, -175931, 3576 } }, \
60
+
{ 1810500000UL, { 3304747, -179126, 3576 } }, \
61
+
{ 1912500000UL, { 3395401, -181606, 3576 } }, \
62
+
{ 0UL, { 0, 0, 0 } }, \
63
+
}, \
64
+
.cpu_dfll_data = { \
65
+
.tune0_low = 0x00b0039d, \
66
+
.tune0_high = 0x00b0009d, \
67
+
.tune1 = 0x0000001f, \
68
+
.tune_high_min_millivolts = 1050, \
69
+
}
70
+
71
+
static const struct cvb_table tegra114_cpu_cvb_tables[] = {
72
+
{
73
+
.speedo_id = 0,
74
+
.process_id = -1,
75
+
.min_millivolts = 1000,
76
+
.max_millivolts = 1250,
77
+
.speedo_scale = 100,
78
+
.voltage_scale = 100,
79
+
.entries = {
80
+
{ 306000000UL, { 107330, -1569, 0 } },
81
+
{ 408000000UL, { 111250, -1666, 0 } },
82
+
{ 510000000UL, { 110000, -1460, 0 } },
83
+
{ 612000000UL, { 117290, -1745, 0 } },
84
+
{ 714000000UL, { 122700, -1910, 0 } },
85
+
{ 816000000UL, { 125620, -1945, 0 } },
86
+
{ 918000000UL, { 130560, -2076, 0 } },
87
+
{ 1020000000UL, { 137280, -2303, 0 } },
88
+
{ 1122000000UL, { 146440, -2660, 0 } },
89
+
{ 1224000000UL, { 152190, -2825, 0 } },
90
+
{ 1326000000UL, { 157520, -2953, 0 } },
91
+
{ 1428000000UL, { 166100, -3261, 0 } },
92
+
{ 1530000000UL, { 176410, -3647, 0 } },
93
+
{ 1632000000UL, { 189620, -4186, 0 } },
94
+
{ 1734000000UL, { 203190, -4725, 0 } },
95
+
{ 1836000000UL, { 222670, -5573, 0 } },
96
+
{ 1938000000UL, { 256210, -7165, 0 } },
97
+
{ 2040000000UL, { 250050, -6544, 0 } },
98
+
{ 0UL, { 0, 0, 0 } },
99
+
},
100
+
.cpu_dfll_data = {
101
+
.tune0_low = 0x00b0019d,
102
+
.tune0_high = 0x00b0019d,
103
+
.tune1 = 0x0000001f,
104
+
.tune_high_min_millivolts = 1000,
105
+
}
106
+
},
107
+
{
108
+
.speedo_id = 1,
109
+
.process_id = -1,
110
+
T114_CPU_CVB_TABLE
111
+
},
112
+
{
113
+
.speedo_id = 2,
114
+
.process_id = -1,
115
+
T114_CPU_CVB_TABLE
116
+
},
117
+
{
118
+
.speedo_id = 3,
119
+
.process_id = -1,
120
+
T114_CPU_CVB_TABLE
121
+
},
122
+
};
123
+
124
+
/* Maximum CPU frequency, indexed by CPU speedo id */
32
125
static const unsigned long tegra124_cpu_max_freq_table[] = {
33
126
[0] = 2014500000UL,
34
127
[1] = 2320500000UL,
···
186
93
[10] = 1504500000UL,
187
94
};
188
95
189
-
#define CPU_CVB_TABLE \
96
+
#define TEGRA210_CPU_CVB_TABLE \
190
97
.speedo_scale = 100, \
191
98
.voltage_scale = 1000, \
192
99
.entries = { \
···
213
120
{ 0UL, { 0, 0, 0 } }, \
214
121
}
215
122
216
-
#define CPU_CVB_TABLE_XA \
123
+
#define TEGRA210_CPU_CVB_TABLE_XA \
217
124
.speedo_scale = 100, \
218
125
.voltage_scale = 1000, \
219
126
.entries = { \
···
236
143
{ 0UL, { 0, 0, 0 } }, \
237
144
}
238
145
239
-
#define CPU_CVB_TABLE_EUCM1 \
146
+
#define TEGRA210_CPU_CVB_TABLE_EUCM1 \
240
147
.speedo_scale = 100, \
241
148
.voltage_scale = 1000, \
242
149
.entries = { \
···
259
166
{ 0UL, { 0, 0, 0 } }, \
260
167
}
261
168
262
-
#define CPU_CVB_TABLE_EUCM2 \
169
+
#define TEGRA210_CPU_CVB_TABLE_EUCM2 \
263
170
.speedo_scale = 100, \
264
171
.voltage_scale = 1000, \
265
172
.entries = { \
···
281
188
{ 0UL, { 0, 0, 0 } }, \
282
189
}
283
190
284
-
#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
191
+
#define TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
285
192
.speedo_scale = 100, \
286
193
.voltage_scale = 1000, \
287
194
.entries = { \
···
302
209
{ 0UL, { 0, 0, 0 } }, \
303
210
}
304
211
305
-
#define CPU_CVB_TABLE_ODN \
212
+
#define TEGRA210_CPU_CVB_TABLE_ODN \
306
213
.speedo_scale = 100, \
307
214
.voltage_scale = 1000, \
308
215
.entries = { \
···
331
238
.process_id = 0,
332
239
.min_millivolts = 840,
333
240
.max_millivolts = 1120,
334
-
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
241
+
TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
335
242
.cpu_dfll_data = {
336
243
.tune0_low = 0xffead0ff,
337
244
.tune0_high = 0xffead0ff,
···
344
251
.process_id = 1,
345
252
.min_millivolts = 840,
346
253
.max_millivolts = 1120,
347
-
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
254
+
TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
348
255
.cpu_dfll_data = {
349
256
.tune0_low = 0xffead0ff,
350
257
.tune0_high = 0xffead0ff,
···
357
264
.process_id = 0,
358
265
.min_millivolts = 900,
359
266
.max_millivolts = 1162,
360
-
CPU_CVB_TABLE_EUCM2,
267
+
TEGRA210_CPU_CVB_TABLE_EUCM2,
361
268
.cpu_dfll_data = {
362
269
.tune0_low = 0xffead0ff,
363
270
.tune0_high = 0xffead0ff,
···
369
276
.process_id = 1,
370
277
.min_millivolts = 900,
371
278
.max_millivolts = 1162,
372
-
CPU_CVB_TABLE_EUCM2,
279
+
TEGRA210_CPU_CVB_TABLE_EUCM2,
373
280
.cpu_dfll_data = {
374
281
.tune0_low = 0xffead0ff,
375
282
.tune0_high = 0xffead0ff,
···
381
288
.process_id = 0,
382
289
.min_millivolts = 900,
383
290
.max_millivolts = 1195,
384
-
CPU_CVB_TABLE_EUCM2,
291
+
TEGRA210_CPU_CVB_TABLE_EUCM2,
385
292
.cpu_dfll_data = {
386
293
.tune0_low = 0xffead0ff,
387
294
.tune0_high = 0xffead0ff,
···
393
300
.process_id = 1,
394
301
.min_millivolts = 900,
395
302
.max_millivolts = 1195,
396
-
CPU_CVB_TABLE_EUCM2,
303
+
TEGRA210_CPU_CVB_TABLE_EUCM2,
397
304
.cpu_dfll_data = {
398
305
.tune0_low = 0xffead0ff,
399
306
.tune0_high = 0xffead0ff,
···
405
312
.process_id = 0,
406
313
.min_millivolts = 841,
407
314
.max_millivolts = 1227,
408
-
CPU_CVB_TABLE_EUCM1,
315
+
TEGRA210_CPU_CVB_TABLE_EUCM1,
409
316
.cpu_dfll_data = {
410
317
.tune0_low = 0xffead0ff,
411
318
.tune0_high = 0xffead0ff,
···
418
325
.process_id = 1,
419
326
.min_millivolts = 841,
420
327
.max_millivolts = 1227,
421
-
CPU_CVB_TABLE_EUCM1,
328
+
TEGRA210_CPU_CVB_TABLE_EUCM1,
422
329
.cpu_dfll_data = {
423
330
.tune0_low = 0xffead0ff,
424
331
.tune0_high = 0xffead0ff,
···
431
338
.process_id = 0,
432
339
.min_millivolts = 870,
433
340
.max_millivolts = 1150,
434
-
CPU_CVB_TABLE,
341
+
TEGRA210_CPU_CVB_TABLE,
435
342
.cpu_dfll_data = {
436
343
.tune0_low = 0xffead0ff,
437
344
.tune1 = 0x20091d9,
···
442
349
.process_id = 1,
443
350
.min_millivolts = 870,
444
351
.max_millivolts = 1150,
445
-
CPU_CVB_TABLE,
352
+
TEGRA210_CPU_CVB_TABLE,
446
353
.cpu_dfll_data = {
447
354
.tune0_low = 0xffead0ff,
448
355
.tune1 = 0x25501d0,
···
453
360
.process_id = 0,
454
361
.min_millivolts = 818,
455
362
.max_millivolts = 1227,
456
-
CPU_CVB_TABLE,
363
+
TEGRA210_CPU_CVB_TABLE,
457
364
.cpu_dfll_data = {
458
365
.tune0_low = 0xffead0ff,
459
366
.tune0_high = 0xffead0ff,
···
466
373
.process_id = 1,
467
374
.min_millivolts = 818,
468
375
.max_millivolts = 1227,
469
-
CPU_CVB_TABLE,
376
+
TEGRA210_CPU_CVB_TABLE,
470
377
.cpu_dfll_data = {
471
378
.tune0_low = 0xffead0ff,
472
379
.tune0_high = 0xffead0ff,
···
479
386
.process_id = -1,
480
387
.min_millivolts = 918,
481
388
.max_millivolts = 1113,
482
-
CPU_CVB_TABLE_XA,
389
+
TEGRA210_CPU_CVB_TABLE_XA,
483
390
.cpu_dfll_data = {
484
391
.tune0_low = 0xffead0ff,
485
392
.tune1 = 0x17711BD,
···
490
397
.process_id = 0,
491
398
.min_millivolts = 825,
492
399
.max_millivolts = 1227,
493
-
CPU_CVB_TABLE_ODN,
400
+
TEGRA210_CPU_CVB_TABLE_ODN,
494
401
.cpu_dfll_data = {
495
402
.tune0_low = 0xffead0ff,
496
403
.tune0_high = 0xffead0ff,
···
503
410
.process_id = 1,
504
411
.min_millivolts = 825,
505
412
.max_millivolts = 1227,
506
-
CPU_CVB_TABLE_ODN,
413
+
TEGRA210_CPU_CVB_TABLE_ODN,
507
414
.cpu_dfll_data = {
508
415
.tune0_low = 0xffead0ff,
509
416
.tune0_high = 0xffead0ff,
···
516
423
.process_id = 0,
517
424
.min_millivolts = 870,
518
425
.max_millivolts = 1227,
519
-
CPU_CVB_TABLE,
426
+
TEGRA210_CPU_CVB_TABLE,
520
427
.cpu_dfll_data = {
521
428
.tune0_low = 0xffead0ff,
522
429
.tune1 = 0x20091d9,
···
527
434
.process_id = 1,
528
435
.min_millivolts = 870,
529
436
.max_millivolts = 1227,
530
-
CPU_CVB_TABLE,
437
+
TEGRA210_CPU_CVB_TABLE,
531
438
.cpu_dfll_data = {
532
439
.tune0_low = 0xffead0ff,
533
440
.tune1 = 0x25501d0,
···
538
445
.process_id = 0,
539
446
.min_millivolts = 837,
540
447
.max_millivolts = 1227,
541
-
CPU_CVB_TABLE,
448
+
TEGRA210_CPU_CVB_TABLE,
542
449
.cpu_dfll_data = {
543
450
.tune0_low = 0xffead0ff,
544
451
.tune0_high = 0xffead0ff,
···
551
458
.process_id = 1,
552
459
.min_millivolts = 837,
553
460
.max_millivolts = 1227,
554
-
CPU_CVB_TABLE,
461
+
TEGRA210_CPU_CVB_TABLE,
555
462
.cpu_dfll_data = {
556
463
.tune0_low = 0xffead0ff,
557
464
.tune0_high = 0xffead0ff,
···
564
471
.process_id = 0,
565
472
.min_millivolts = 850,
566
473
.max_millivolts = 1170,
567
-
CPU_CVB_TABLE,
474
+
TEGRA210_CPU_CVB_TABLE,
568
475
.cpu_dfll_data = {
569
476
.tune0_low = 0xffead0ff,
570
477
.tune0_high = 0xffead0ff,
···
577
484
.process_id = 1,
578
485
.min_millivolts = 850,
579
486
.max_millivolts = 1170,
580
-
CPU_CVB_TABLE,
487
+
TEGRA210_CPU_CVB_TABLE,
581
488
.cpu_dfll_data = {
582
489
.tune0_low = 0xffead0ff,
583
490
.tune0_high = 0xffead0ff,
···
585
492
.tune_high_min_millivolts = 864,
586
493
}
587
494
},
495
+
};
496
+
497
+
static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = {
498
+
.cpu_max_freq_table = tegra114_cpu_max_freq_table,
499
+
.cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table),
500
+
.cpu_cvb_tables = tegra114_cpu_cvb_tables,
501
+
.cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables)
588
502
};
589
503
590
504
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
···
609
509
};
610
510
611
511
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
512
+
{
513
+
.compatible = "nvidia,tegra114-dfll",
514
+
.data = &tegra114_dfll_fcpu_data,
515
+
},
612
516
{
613
517
.compatible = "nvidia,tegra124-dfll",
614
518
.data = &tegra124_dfll_fcpu_data,
+1
drivers/clk/tegra/clk-tegra30.c
+1
drivers/clk/tegra/clk-tegra30.c
-2
drivers/clk/tegra/clk.h
-2
drivers/clk/tegra/clk.h
···
897
897
void tegra114_clock_tune_cpu_trimmers_high(void);
898
898
void tegra114_clock_tune_cpu_trimmers_low(void);
899
899
void tegra114_clock_tune_cpu_trimmers_init(void);
900
-
void tegra114_clock_assert_dfll_dvco_reset(void);
901
-
void tegra114_clock_deassert_dfll_dvco_reset(void);
902
900
903
901
typedef void (*tegra_clk_apply_init_table_func)(void);
904
902
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+169
include/dt-bindings/clock/axis,artpec8-clk.h
+169
include/dt-bindings/clock/axis,artpec8-clk.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
4
+
* https://www.samsung.com
5
+
* Copyright (c) 2025 Axis Communications AB.
6
+
* https://www.axis.com
7
+
*
8
+
* Device Tree binding constants for ARTPEC-8 clock controller.
9
+
*/
10
+
11
+
#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
12
+
#define _DT_BINDINGS_CLOCK_ARTPEC8_H
13
+
14
+
/* CMU_CMU */
15
+
#define CLK_FOUT_SHARED0_PLL 1
16
+
#define CLK_DOUT_SHARED0_DIV2 2
17
+
#define CLK_DOUT_SHARED0_DIV3 3
18
+
#define CLK_DOUT_SHARED0_DIV4 4
19
+
#define CLK_FOUT_SHARED1_PLL 5
20
+
#define CLK_DOUT_SHARED1_DIV2 6
21
+
#define CLK_DOUT_SHARED1_DIV3 7
22
+
#define CLK_DOUT_SHARED1_DIV4 8
23
+
#define CLK_FOUT_AUDIO_PLL 9
24
+
#define CLK_DOUT_CMU_BUS 10
25
+
#define CLK_DOUT_CMU_BUS_DLP 11
26
+
#define CLK_DOUT_CMU_CDC_CORE 12
27
+
#define CLK_DOUT_CMU_OTP 13
28
+
#define CLK_DOUT_CMU_CORE_MAIN 14
29
+
#define CLK_DOUT_CMU_CORE_DLP 15
30
+
#define CLK_DOUT_CMU_CPUCL_SWITCH 16
31
+
#define CLK_DOUT_CMU_DLP_CORE 17
32
+
#define CLK_DOUT_CMU_FSYS_BUS 18
33
+
#define CLK_DOUT_CMU_FSYS_IP 19
34
+
#define CLK_DOUT_CMU_FSYS_SCAN0 20
35
+
#define CLK_DOUT_CMU_FSYS_SCAN1 21
36
+
#define CLK_DOUT_CMU_GPU_3D 22
37
+
#define CLK_DOUT_CMU_GPU_2D 23
38
+
#define CLK_DOUT_CMU_IMEM_ACLK 24
39
+
#define CLK_DOUT_CMU_IMEM_JPEG 25
40
+
#define CLK_DOUT_CMU_MIF_SWITCH 26
41
+
#define CLK_DOUT_CMU_MIF_BUSP 27
42
+
#define CLK_DOUT_CMU_PERI_DISP 28
43
+
#define CLK_DOUT_CMU_PERI_IP 29
44
+
#define CLK_DOUT_CMU_PERI_AUDIO 30
45
+
#define CLK_DOUT_CMU_RSP_CORE 31
46
+
#define CLK_DOUT_CMU_TRFM_CORE 32
47
+
#define CLK_DOUT_CMU_VCA_ACE 33
48
+
#define CLK_DOUT_CMU_VCA_OD 34
49
+
#define CLK_DOUT_CMU_VIO_CORE 35
50
+
#define CLK_DOUT_CMU_VIO_AUDIO 36
51
+
#define CLK_DOUT_CMU_VIP0_CORE 37
52
+
#define CLK_DOUT_CMU_VIP1_CORE 38
53
+
#define CLK_DOUT_CMU_VPP_CORE 39
54
+
55
+
/* CMU_BUS */
56
+
#define CLK_MOUT_BUS_ACLK_USER 1
57
+
#define CLK_MOUT_BUS_DLP_USER 2
58
+
#define CLK_DOUT_BUS_PCLK 3
59
+
60
+
/* CMU_CORE */
61
+
#define CLK_MOUT_CORE_ACLK_USER 1
62
+
#define CLK_MOUT_CORE_DLP_USER 2
63
+
#define CLK_DOUT_CORE_PCLK 3
64
+
65
+
/* CMU_CPUCL */
66
+
#define CLK_FOUT_CPUCL_PLL 1
67
+
#define CLK_MOUT_CPUCL_PLL 2
68
+
#define CLK_MOUT_CPUCL_SWITCH_USER 3
69
+
#define CLK_DOUT_CPUCL_CPU 4
70
+
#define CLK_DOUT_CPUCL_CLUSTER_ACLK 5
71
+
#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG 6
72
+
#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK 7
73
+
#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 8
74
+
#define CLK_DOUT_CPUCL_PCLK 9
75
+
#define CLK_DOUT_CPUCL_CMUREF 10
76
+
#define CLK_DOUT_CPUCL_DBG 11
77
+
#define CLK_DOUT_CPUCL_PCLKDBG 12
78
+
#define CLK_GOUT_CPUCL_CLUSTER_CPU 13
79
+
#define CLK_GOUT_CPUCL_SHORTSTOP 14
80
+
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 15
81
+
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 16
82
+
83
+
/* CMU_FSYS */
84
+
#define CLK_FOUT_FSYS_PLL 1
85
+
#define CLK_MOUT_FSYS_SCAN0_USER 2
86
+
#define CLK_MOUT_FSYS_SCAN1_USER 3
87
+
#define CLK_MOUT_FSYS_BUS_USER 4
88
+
#define CLK_MOUT_FSYS_MMC_USER 5
89
+
#define CLK_DOUT_FSYS_PCIE_PIPE 6
90
+
#define CLK_DOUT_FSYS_ADC 7
91
+
#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8
92
+
#define CLK_DOUT_FSYS_EQOS_INT125 9
93
+
#define CLK_DOUT_FSYS_OTP_MEM 10
94
+
#define CLK_DOUT_FSYS_SCLK_UART 11
95
+
#define CLK_DOUT_FSYS_EQOS_25 12
96
+
#define CLK_DOUT_FSYS_EQOS_2p5 13
97
+
#define CLK_DOUT_FSYS_BUS300 14
98
+
#define CLK_DOUT_FSYS_BUS_QSPI 15
99
+
#define CLK_DOUT_FSYS_MMC_CARD0 16
100
+
#define CLK_DOUT_FSYS_MMC_CARD1 17
101
+
#define CLK_DOUT_SCAN_CLK_FSYS_125 18
102
+
#define CLK_DOUT_FSYS_QSPI 19
103
+
#define CLK_DOUT_FSYS_SFMC_NAND 20
104
+
#define CLK_DOUT_FSYS_SCAN_CLK_MMC 21
105
+
#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 22
106
+
#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 23
107
+
#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK 24
108
+
#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK 25
109
+
#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK 26
110
+
#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK 27
111
+
#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0 28
112
+
#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 29
113
+
#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG 30
114
+
#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 31
115
+
#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK 32
116
+
#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I 33
117
+
#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I 34
118
+
#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5 35
119
+
#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND 36
120
+
#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN 37
121
+
#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK 38
122
+
#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN 39
123
+
#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK 40
124
+
#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN 41
125
+
#define CLK_GOUT_FSYS_UART0_PCLK 42
126
+
#define CLK_GOUT_FSYS_UART0_SCLK_UART 43
127
+
#define CLK_GOUT_FSYS_BUS_QSPI 44
128
+
#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK 45
129
+
#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK 46
130
+
131
+
/* CMU_IMEM */
132
+
#define CLK_MOUT_IMEM_ACLK_USER 1
133
+
#define CLK_MOUT_IMEM_GIC_CA53 2
134
+
#define CLK_MOUT_IMEM_GIC_CA5 3
135
+
#define CLK_MOUT_IMEM_JPEG_USER 4
136
+
#define CLK_GOUT_IMEM_MCT_PCLK 5
137
+
#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 6
138
+
139
+
/* CMU_PERI */
140
+
#define CLK_MOUT_PERI_IP_USER 1
141
+
#define CLK_MOUT_PERI_AUDIO_USER 2
142
+
#define CLK_MOUT_PERI_I2S0 3
143
+
#define CLK_MOUT_PERI_I2S1 4
144
+
#define CLK_MOUT_PERI_DISP_USER 5
145
+
#define CLK_DOUT_PERI_SPI 6
146
+
#define CLK_DOUT_PERI_UART1 7
147
+
#define CLK_DOUT_PERI_UART2 8
148
+
#define CLK_DOUT_PERI_PCLK 9
149
+
#define CLK_DOUT_PERI_I2S0 10
150
+
#define CLK_DOUT_PERI_I2S1 11
151
+
#define CLK_DOUT_PERI_DSIM 12
152
+
#define CLK_GOUT_PERI_UART1_PCLK 13
153
+
#define CLK_GOUT_PERI_UART1_SCLK_UART 14
154
+
#define CLK_GOUT_PERI_UART2_PCLK 15
155
+
#define CLK_GOUT_PERI_UART2_SCLK_UART 16
156
+
#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 17
157
+
#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 18
158
+
#define CLK_GOUT_PERI_SPI0_PCLK 19
159
+
#define CLK_GOUT_PERI_SPI0_SCLK_SPI 20
160
+
#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 21
161
+
#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST 22
162
+
#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST 23
163
+
#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK 24
164
+
#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK 25
165
+
#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK 26
166
+
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 27
167
+
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 28
168
+
169
+
#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */
+13
include/dt-bindings/clock/fsd-clk.h
+13
include/dt-bindings/clock/fsd-clk.h
···
139
139
#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
140
140
#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
141
141
#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
142
+
#define CAM_CSI_PLL 13
143
+
#define CAM_CSI0_0_IPCLKPORT_I_PCLK 14
144
+
#define CAM_CSI0_1_IPCLKPORT_I_PCLK 15
145
+
#define CAM_CSI0_2_IPCLKPORT_I_PCLK 16
146
+
#define CAM_CSI0_3_IPCLKPORT_I_PCLK 17
147
+
#define CAM_CSI1_0_IPCLKPORT_I_PCLK 18
148
+
#define CAM_CSI1_1_IPCLKPORT_I_PCLK 19
149
+
#define CAM_CSI1_2_IPCLKPORT_I_PCLK 20
150
+
#define CAM_CSI1_3_IPCLKPORT_I_PCLK 21
151
+
#define CAM_CSI2_0_IPCLKPORT_I_PCLK 22
152
+
#define CAM_CSI2_1_IPCLKPORT_I_PCLK 23
153
+
#define CAM_CSI2_2_IPCLKPORT_I_PCLK 24
154
+
#define CAM_CSI2_3_IPCLKPORT_I_PCLK 25
142
155
143
156
#endif /*_DT_BINDINGS_CLOCK_FSD_H */
+181
include/dt-bindings/clock/samsung,exynos990.h
+181
include/dt-bindings/clock/samsung,exynos990.h
···
208
208
#define CLK_GOUT_CMU_SSP_BUS 197
209
209
#define CLK_GOUT_CMU_TNR_BUS 198
210
210
#define CLK_GOUT_CMU_VRA_BUS 199
211
+
#define CLK_MOUT_CMU_CMUREF 200
212
+
#define CLK_MOUT_CMU_DPU_BUS 201
213
+
#define CLK_MOUT_CMU_CLK_CMUREF 202
214
+
#define CLK_DOUT_CMU_CLK_CMUREF 203
211
215
212
216
/* CMU_HSI0 */
213
217
#define CLK_MOUT_HSI0_BUS_USER 1
···
236
232
#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20
237
233
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
238
234
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
235
+
#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23
236
+
237
+
/* CMU_PERIC0 */
238
+
#define CLK_MOUT_PERIC0_BUS_USER 1
239
+
#define CLK_MOUT_PERIC0_UART_DBG 2
240
+
#define CLK_MOUT_PERIC0_USI00_USI_USER 3
241
+
#define CLK_MOUT_PERIC0_USI01_USI_USER 4
242
+
#define CLK_MOUT_PERIC0_USI02_USI_USER 5
243
+
#define CLK_MOUT_PERIC0_USI03_USI_USER 6
244
+
#define CLK_MOUT_PERIC0_USI04_USI_USER 7
245
+
#define CLK_MOUT_PERIC0_USI05_USI_USER 8
246
+
#define CLK_MOUT_PERIC0_USI13_USI_USER 9
247
+
#define CLK_MOUT_PERIC0_USI14_USI_USER 10
248
+
#define CLK_MOUT_PERIC0_USI15_USI_USER 11
249
+
#define CLK_MOUT_PERIC0_USI_I2C_USER 12
250
+
#define CLK_DOUT_PERIC0_UART_DBG 13
251
+
#define CLK_DOUT_PERIC0_USI00_USI 14
252
+
#define CLK_DOUT_PERIC0_USI01_USI 15
253
+
#define CLK_DOUT_PERIC0_USI02_USI 16
254
+
#define CLK_DOUT_PERIC0_USI03_USI 17
255
+
#define CLK_DOUT_PERIC0_USI04_USI 18
256
+
#define CLK_DOUT_PERIC0_USI05_USI 19
257
+
#define CLK_DOUT_PERIC0_USI13_USI 20
258
+
#define CLK_DOUT_PERIC0_USI14_USI 21
259
+
#define CLK_DOUT_PERIC0_USI15_USI 22
260
+
#define CLK_DOUT_PERIC0_USI_I2C 23
261
+
#define CLK_GOUT_PERIC0_CMU_PCLK 24
262
+
#define CLK_GOUT_PERIC0_OSCCLK_CLK 25
263
+
#define CLK_GOUT_PERIC0_D_TZPC_PCLK 26
264
+
#define CLK_GOUT_PERIC0_GPIO_PCLK 27
265
+
#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28
266
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29
267
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30
268
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31
269
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32
270
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33
271
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34
272
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35
273
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36
274
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37
275
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38
276
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39
277
+
#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40
278
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_10 41
279
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_11 42
280
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_12 43
281
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_13 44
282
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_14 45
283
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_15 46
284
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_4 47
285
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_5 48
286
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_6 49
287
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_7 50
288
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_8 51
289
+
#define CLK_GOUT_PERIC0_TOP0_PCLK_9 52
290
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53
291
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54
292
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55
293
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56
294
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57
295
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58
296
+
#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59
297
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_0 60
298
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_15 61
299
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_3 62
300
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_4 63
301
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_5 64
302
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_6 65
303
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_7 66
304
+
#define CLK_GOUT_PERIC0_TOP1_PCLK_8 67
305
+
#define CLK_GOUT_PERIC0_BUSP_CLK 68
306
+
#define CLK_GOUT_PERIC0_UART_DBG_CLK 69
307
+
#define CLK_GOUT_PERIC0_USI00_USI_CLK 70
308
+
#define CLK_GOUT_PERIC0_USI01_USI_CLK 71
309
+
#define CLK_GOUT_PERIC0_USI02_USI_CLK 72
310
+
#define CLK_GOUT_PERIC0_USI03_USI_CLK 73
311
+
#define CLK_GOUT_PERIC0_USI04_USI_CLK 74
312
+
#define CLK_GOUT_PERIC0_USI05_USI_CLK 75
313
+
#define CLK_GOUT_PERIC0_USI13_USI_CLK 76
314
+
#define CLK_GOUT_PERIC0_USI14_USI_CLK 77
315
+
#define CLK_GOUT_PERIC0_USI15_USI_CLK 78
316
+
#define CLK_GOUT_PERIC0_USI_I2C_CLK 79
317
+
#define CLK_GOUT_PERIC0_SYSREG_PCLK 80
318
+
319
+
/* CMU_PERIC1 */
320
+
#define CLK_MOUT_PERIC1_BUS_USER 1
321
+
#define CLK_MOUT_PERIC1_UART_BT_USER 2
322
+
#define CLK_MOUT_PERIC1_USI06_USI_USER 3
323
+
#define CLK_MOUT_PERIC1_USI07_USI_USER 4
324
+
#define CLK_MOUT_PERIC1_USI08_USI_USER 5
325
+
#define CLK_MOUT_PERIC1_USI09_USI_USER 6
326
+
#define CLK_MOUT_PERIC1_USI10_USI_USER 7
327
+
#define CLK_MOUT_PERIC1_USI11_USI_USER 8
328
+
#define CLK_MOUT_PERIC1_USI12_USI_USER 9
329
+
#define CLK_MOUT_PERIC1_USI18_USI_USER 10
330
+
#define CLK_MOUT_PERIC1_USI16_USI_USER 11
331
+
#define CLK_MOUT_PERIC1_USI17_USI_USER 12
332
+
#define CLK_MOUT_PERIC1_USI_I2C_USER 13
333
+
#define CLK_DOUT_PERIC1_UART_BT 14
334
+
#define CLK_DOUT_PERIC1_USI06_USI 15
335
+
#define CLK_DOUT_PERIC1_USI07_USI 16
336
+
#define CLK_DOUT_PERIC1_USI08_USI 17
337
+
#define CLK_DOUT_PERIC1_USI18_USI 18
338
+
#define CLK_DOUT_PERIC1_USI12_USI 19
339
+
#define CLK_DOUT_PERIC1_USI09_USI 20
340
+
#define CLK_DOUT_PERIC1_USI10_USI 21
341
+
#define CLK_DOUT_PERIC1_USI11_USI 22
342
+
#define CLK_DOUT_PERIC1_USI16_USI 23
343
+
#define CLK_DOUT_PERIC1_USI17_USI 24
344
+
#define CLK_DOUT_PERIC1_USI_I2C 25
345
+
#define CLK_GOUT_PERIC1_CMU_PCLK 26
346
+
#define CLK_GOUT_PERIC1_UART_BT_CLK 27
347
+
#define CLK_GOUT_PERIC1_USI12_USI_CLK 28
348
+
#define CLK_GOUT_PERIC1_USI18_USI_CLK 29
349
+
#define CLK_GOUT_PERIC1_D_TZPC_PCLK 30
350
+
#define CLK_GOUT_PERIC1_GPIO_PCLK 31
351
+
#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32
352
+
#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33
353
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34
354
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35
355
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36
356
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37
357
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38
358
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39
359
+
#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40
360
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_10 41
361
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_11 42
362
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_12 43
363
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_13 44
364
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_14 45
365
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_15 46
366
+
#define CLK_GOUT_PERIC1_TOP0_PCLK_4 47
367
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48
368
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49
369
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50
370
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51
371
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52
372
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53
373
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54
374
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55
375
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56
376
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57
377
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58
378
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59
379
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60
380
+
#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61
381
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_0 62
382
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_1 63
383
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_10 64
384
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_12 65
385
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_13 66
386
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_14 67
387
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_15 68
388
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_2 69
389
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_3 70
390
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_4 71
391
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_5 72
392
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_6 73
393
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_7 74
394
+
#define CLK_GOUT_PERIC1_TOP1_PCLK_9 75
395
+
#define CLK_GOUT_PERIC1_BUSP_CLK 76
396
+
#define CLK_GOUT_PERIC1_OSCCLK_CLK 77
397
+
#define CLK_GOUT_PERIC1_USI06_USI_CLK 78
398
+
#define CLK_GOUT_PERIC1_USI07_USI_CLK 79
399
+
#define CLK_GOUT_PERIC1_USI08_USI_CLK 80
400
+
#define CLK_GOUT_PERIC1_USI09_USI_CLK 81
401
+
#define CLK_GOUT_PERIC1_USI10_USI_CLK 82
402
+
#define CLK_GOUT_PERIC1_USI11_USI_CLK 83
403
+
#define CLK_GOUT_PERIC1_USI16_USI_CLK 84
404
+
#define CLK_GOUT_PERIC1_USI17_USI_CLK 85
405
+
#define CLK_GOUT_PERIC1_USI_I2C_CLK 86
406
+
#define CLK_GOUT_PERIC1_SYSREG_PCLK 87
407
+
#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88
408
+
#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89
409
+
#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90
410
+
#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91
411
+
#define CLK_GOUT_PERIC1_XIU_P_ACLK 92
239
412
240
413
/* CMU_PERIS */
241
414
#define CLK_MOUT_PERIS_BUS_USER 1
+2
-1
include/dt-bindings/clock/tegra30-car.h
+2
-1
include/dt-bindings/clock/tegra30-car.h
···
271
271
#define TEGRA30_CLK_AUDIO3_MUX 306
272
272
#define TEGRA30_CLK_AUDIO4_MUX 307
273
273
#define TEGRA30_CLK_SPDIF_MUX 308
274
-
#define TEGRA30_CLK_CLK_MAX 309
274
+
#define TEGRA30_CLK_CSIA_PAD 309
275
+
#define TEGRA30_CLK_CSIB_PAD 310
275
276
276
277
#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
+13
include/dt-bindings/reset/nvidia,tegra114-car.h
+13
include/dt-bindings/reset/nvidia,tegra114-car.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* This header provides Tegra114-specific constants for binding
4
+
* nvidia,tegra114-car.
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H
8
+
#define _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H
9
+
10
+
#define TEGRA114_RESET(x) (5 * 32 + (x))
11
+
#define TEGRA114_RST_DFLL_DVCO TEGRA114_RESET(0)
12
+
13
+
#endif /* _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H */