tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'qcom-dts-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM32 DeviceTree updates for v6.6

GCC and LCC clock controller parent clocks are introduced on MDM9615.

The newly introduced RPM representation is introduced across multiple
platforms.

Voltage ADC channel names are corrected across multiple platforms.

APQ8064 gains a definition for GSBI4.

The XO clock for SDHCI is corrected, as is the USB node name, on
IPQ4019. USB node name is also corrected for SDX55.

The correct PMIC is included on SDX65 MTP.

The incorrect spi-max-frequency property is removed from controllers on
IPQ8064 and MSM8960.

OCMEM and the display subsystem are added to MSM8226.

Reset line is added to the PM8941 and the APQ8074 Dragonboard, while a
few properties of the Sony Xperia Z2 Tablet touchscreen are corrected.

* tag 'qcom-dts-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: apq8064: add support to gsbi4 uart
ARM: dts: qcom: sdx65-mtp: Update the pmic used in sdx65
ARM: dts: qcom: ipq4019: correct SDHCI XO clock
ARM: dts: qcom: Use labels with generic node names for ADC channels
ARM: dts: qcom-mdm9615: specify gcc clocks
ARM: dts: qcom-mdm9615: specify clocks for the lcc device
ARM: dts: qcom: msm8974pro-castor: correct touchscreen syna,nosleep-mode
ARM: dts: qcom: msm8974pro-castor: correct touchscreen function names
ARM: dts: qcom: msm8974pro-castor: correct inverted X of touchscreen
ARM: dts: qcom: apq8064: Drop redundant /smd node
ARM: dts: qcom: Add rpm-proc node for SMD platforms
ARM: dts: qcom: apq8074-dragonboard: add resin
ARM: dts: qcom-pm8941: add resin support
ARM: dts: qcom: minor whitespace cleanup around '='
ARM: dts: qcom: msm8960: drop spi-max-frequency from controller
ARM: dts: qcom: ipq8064: drop spi-max-frequency from controller
ARM: dts: qcom: sdx55: use generic node names for USB
ARM: dts: qcom: ipq4019: use generic node names for USB
ARM: dts: qcom: msm8226: Add ocmem
ARM: dts: qcom: msm8226: Add mdss nodes

Link: https://lore.kernel.org/r/20230818024928.2485173-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 3b6d013c 59486969

+313 -146
+16
arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi
··· 233 233 }; 234 234 }; 235 235 236 + gsbi4_uart_pin_a: gsbi4-uart-pin-active-state { 237 + rx-pins { 238 + pins = "gpio11"; 239 + function = "gsbi4"; 240 + drive-strength = <2>; 241 + bias-disable; 242 + }; 243 + 244 + tx-pins { 245 + pins = "gpio10"; 246 + function = "gsbi4"; 247 + drive-strength = <4>; 248 + bias-disable; 249 + }; 250 + }; 251 + 236 252 gsbi6_uart_2pins: gsbi6_uart_2pins { 237 253 mux { 238 254 pins = "gpio14", "gpio15";
+12 -40
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
··· 226 226 hwlocks = <&sfpb_mutex 3>; 227 227 }; 228 228 229 - smd { 230 - compatible = "qcom,smd"; 231 - 232 - modem-edge { 233 - interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; 234 - 235 - qcom,ipc = <&l2cc 8 3>; 236 - qcom,smd-edge = <0>; 237 - 238 - status = "disabled"; 239 - }; 240 - 241 - q6-edge { 242 - interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; 243 - 244 - qcom,ipc = <&l2cc 8 15>; 245 - qcom,smd-edge = <1>; 246 - 247 - status = "disabled"; 248 - }; 249 - 250 - dsps-edge { 251 - interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; 252 - 253 - qcom,ipc = <&sps_sic_non_secure 0x4080 0>; 254 - qcom,smd-edge = <3>; 255 - 256 - status = "disabled"; 257 - }; 258 - 259 - riva-edge { 260 - interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; 261 - 262 - qcom,ipc = <&l2cc 8 25>; 263 - qcom,smd-edge = <6>; 264 - 265 - status = "disabled"; 266 - }; 267 - }; 268 - 269 229 smsm { 270 230 compatible = "qcom,smsm"; 271 231 ··· 514 554 #address-cells = <1>; 515 555 #size-cells = <1>; 516 556 ranges; 557 + 558 + gsbi4_serial: serial@16340000 { 559 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 560 + reg = <0x16340000 0x100>, 561 + <0x16300000 0x3>; 562 + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 563 + pinctrl-0 = <&gsbi4_uart_pin_a>; 564 + pinctrl-names = "default"; 565 + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 566 + clock-names = "core", "iface"; 567 + status = "disabled"; 568 + }; 517 569 518 570 gsbi4_i2c: i2c@16380000 { 519 571 compatible = "qcom,i2c-qup-v1.1.1";
+5
arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts
··· 156 156 }; 157 157 }; 158 158 159 + &pm8941_resin { 160 + linux,code = <KEY_VOLUMEDOWN>; 161 + status = "okay"; 162 + }; 163 + 159 164 &pm8941_wled { 160 165 qcom,cs-out; 161 166 qcom,switching-freq = <3200>;
+3 -3
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
··· 784 784 }; 785 785 }; 786 786 787 - smd { 788 - compatible = "qcom,smd"; 787 + rpm: remoteproc { 788 + compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc"; 789 789 790 - rpm { 790 + smd-edge { 791 791 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 792 792 qcom,ipc = <&apcs 8 0>; 793 793 qcom,smd-edge = <15>;
+4 -3
arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
··· 262 262 &usb3 { 263 263 status = "okay"; 264 264 265 - dwc3@8a00000 { 266 - phys = <&usb3_hs_phy>; 267 - phy-names = "usb2-phy"; 268 265 }; 266 + 267 + &usb3_dwc { 268 + phys = <&usb3_hs_phy>; 269 + phy-names = "usb2-phy"; 269 270 }; 270 271 271 272 &usb2_hs_phy {
+23 -20
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
··· 230 230 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 231 231 interrupt-names = "hc_irq", "pwr_irq"; 232 232 bus-width = <8>; 233 - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, 234 - <&gcc GCC_DCD_XO_CLK>; 235 - clock-names = "iface", "core", "xo"; 233 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 234 + <&gcc GCC_SDCC1_APPS_CLK>, 235 + <&xo>; 236 + clock-names = "iface", 237 + "core", 238 + "xo"; 236 239 status = "disabled"; 237 240 }; 238 241 ··· 419 416 420 417 pcie0: pci@40000000 { 421 418 compatible = "qcom,pcie-ipq4019"; 422 - reg = <0x40000000 0xf1d 423 - 0x40000f20 0xa8 424 - 0x80000 0x2000 425 - 0x40100000 0x1000>; 419 + reg = <0x40000000 0xf1d>, 420 + <0x40000f20 0xa8>, 421 + <0x80000 0x2000>, 422 + <0x40100000 0x1000>; 426 423 reg-names = "dbi", "elbi", "parf", "config"; 427 424 device_type = "pci"; 428 425 linux,pci-domain = <0>; ··· 546 543 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 547 544 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 548 545 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 549 - interrupt-names = "msi0", "msi1", "msi2", "msi3", 550 - "msi4", "msi5", "msi6", "msi7", 551 - "msi8", "msi9", "msi10", "msi11", 546 + interrupt-names = "msi0", "msi1", "msi2", "msi3", 547 + "msi4", "msi5", "msi6", "msi7", 548 + "msi8", "msi9", "msi10", "msi11", 552 549 "msi12", "msi13", "msi14", "msi15", 553 550 "legacy"; 554 551 status = "disabled"; ··· 588 585 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 589 586 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 590 587 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 591 - interrupt-names = "msi0", "msi1", "msi2", "msi3", 592 - "msi4", "msi5", "msi6", "msi7", 593 - "msi8", "msi9", "msi10", "msi11", 588 + interrupt-names = "msi0", "msi1", "msi2", "msi3", 589 + "msi4", "msi5", "msi6", "msi7", 590 + "msi8", "msi9", "msi10", "msi11", 594 591 "msi12", "msi13", "msi14", "msi15", 595 592 "legacy"; 596 593 status = "disabled"; ··· 624 621 }; 625 622 }; 626 623 627 - usb3_ss_phy: ssphy@9a000 { 624 + usb3_ss_phy: usb-phy@9a000 { 628 625 compatible = "qcom,usb-ss-ipq4019-phy"; 629 626 #phy-cells = <0>; 630 627 reg = <0x9a000 0x800>; ··· 634 631 status = "disabled"; 635 632 }; 636 633 637 - usb3_hs_phy: hsphy@a6000 { 634 + usb3_hs_phy: usb-phy@a6000 { 638 635 compatible = "qcom,usb-hs-ipq4019-phy"; 639 636 #phy-cells = <0>; 640 637 reg = <0xa6000 0x40>; ··· 644 641 status = "disabled"; 645 642 }; 646 643 647 - usb3: usb3@8af8800 { 644 + usb3: usb@8af8800 { 648 645 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 649 646 reg = <0x8af8800 0x100>; 650 647 #address-cells = <1>; ··· 656 653 ranges; 657 654 status = "disabled"; 658 655 659 - dwc3@8a00000 { 656 + usb3_dwc: usb@8a00000 { 660 657 compatible = "snps,dwc3"; 661 658 reg = <0x8a00000 0xf8000>; 662 659 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; ··· 666 663 }; 667 664 }; 668 665 669 - usb2_hs_phy: hsphy@a8000 { 666 + usb2_hs_phy: usb-phy@a8000 { 670 667 compatible = "qcom,usb-hs-ipq4019-phy"; 671 668 #phy-cells = <0>; 672 669 reg = <0xa8000 0x40>; ··· 676 673 status = "disabled"; 677 674 }; 678 675 679 - usb2: usb2@60f8800 { 676 + usb2: usb@60f8800 { 680 677 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; 681 678 reg = <0x60f8800 0x100>; 682 679 #address-cells = <1>; ··· 688 685 ranges; 689 686 status = "disabled"; 690 687 691 - dwc3@6000000 { 688 + usb@6000000 { 692 689 compatible = "snps,dwc3"; 693 690 reg = <0x6000000 0xf8000>; 694 691 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-1
arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts
··· 282 282 283 283 spi4: spi@1a280000 { 284 284 status = "okay"; 285 - spi-max-frequency = <50000000>; 286 285 287 286 pinctrl-0 = <&spi_pins>; 288 287 pinctrl-names = "default";
-1
arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi
··· 30 30 31 31 spi4: spi@1a280000 { 32 32 status = "okay"; 33 - spi-max-frequency = <50000000>; 34 33 35 34 pinctrl-0 = <&spi_pins>; 36 35 pinctrl-names = "default";
+18 -1
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
··· 10 10 11 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13 + #include <dt-bindings/clock/qcom,lcc-msm8960.h> 13 14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h> 14 15 #include <dt-bindings/mfd/qcom-rpm.h> 15 16 #include <dt-bindings/soc/qcom,gsbi.h> ··· 40 39 }; 41 40 42 41 clocks { 43 - cxo_board { 42 + cxo_board: cxo_board { 44 43 compatible = "fixed-clock"; 45 44 #clock-cells = <0>; 46 45 clock-frequency = <19200000>; ··· 107 106 #power-domain-cells = <1>; 108 107 #reset-cells = <1>; 109 108 reg = <0x900000 0x4000>; 109 + clocks = <&cxo_board>, 110 + <&lcc PLL4>; 110 111 }; 111 112 112 113 lcc: clock-controller@28000000 { ··· 116 113 reg = <0x28000000 0x1000>; 117 114 #clock-cells = <1>; 118 115 #reset-cells = <1>; 116 + clocks = <&cxo_board>, 117 + <&gcc PLL4_VOTE>, 118 + <0>, 119 + <0>, <0>, 120 + <0>, <0>, 121 + <0>; 122 + clock-names = "cxo", 123 + "pll4_vote", 124 + "mi2s_codec_clk", 125 + "codec_i2s_mic_codec_clk", 126 + "spare_i2s_mic_codec_clk", 127 + "codec_i2s_spkr_codec_clk", 128 + "spare_i2s_spkr_codec_clk", 129 + "pcm_codec_clk"; 119 130 }; 120 131 121 132 l2cc: clock-controller@2011000 {
+163 -19
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
··· 53 53 IRQ_TYPE_LEVEL_HIGH)>; 54 54 }; 55 55 56 - reserved-memory { 57 - #address-cells = <1>; 58 - #size-cells = <1>; 59 - ranges; 56 + rpm: remoteproc { 57 + compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 60 58 61 - smem_region: smem@3000000 { 62 - reg = <0x3000000 0x100000>; 63 - no-map; 64 - }; 65 - 66 - adsp_region: adsp@dc00000 { 67 - reg = <0x0dc00000 0x1900000>; 68 - no-map; 69 - }; 70 - }; 71 - 72 - smd { 73 - compatible = "qcom,smd"; 74 - 75 - rpm { 59 + smd-edge { 76 60 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 77 61 qcom,ipc = <&apcs 8 0>; 78 62 qcom,smd-edge = <15>; ··· 101 117 }; 102 118 }; 103 119 }; 120 + }; 121 + }; 122 + 123 + reserved-memory { 124 + #address-cells = <1>; 125 + #size-cells = <1>; 126 + ranges; 127 + 128 + smem_region: smem@3000000 { 129 + reg = <0x3000000 0x100000>; 130 + no-map; 131 + }; 132 + 133 + adsp_region: adsp@dc00000 { 134 + reg = <0x0dc00000 0x1900000>; 135 + no-map; 104 136 }; 105 137 }; 106 138 ··· 784 784 }; 785 785 }; 786 786 787 + sram@fdd00000 { 788 + compatible = "qcom,msm8226-ocmem"; 789 + reg = <0xfdd00000 0x2000>, 790 + <0xfec00000 0x20000>; 791 + reg-names = "ctrl", "mem"; 792 + ranges = <0 0xfec00000 0x20000>; 793 + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 794 + clock-names = "core"; 795 + 796 + #address-cells = <1>; 797 + #size-cells = <1>; 798 + 799 + gmu_sram: gmu-sram@0 { 800 + reg = <0x0 0x20000>; 801 + }; 802 + }; 803 + 787 804 sram@fe805000 { 788 805 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 789 806 reg = <0xfe805000 0x1000>; ··· 812 795 mode-bootloader = <0x77665500>; 813 796 mode-normal = <0x77665501>; 814 797 mode-recovery = <0x77665502>; 798 + }; 799 + }; 800 + 801 + mdss: display-subsystem@fd900000 { 802 + compatible = "qcom,mdss"; 803 + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 804 + reg-names = "mdss_phys", "vbif_phys"; 805 + 806 + power-domains = <&mmcc MDSS_GDSC>; 807 + 808 + clocks = <&mmcc MDSS_AHB_CLK>, 809 + <&mmcc MDSS_AXI_CLK>, 810 + <&mmcc MDSS_VSYNC_CLK>; 811 + clock-names = "iface", 812 + "bus", 813 + "vsync"; 814 + 815 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 816 + 817 + interrupt-controller; 818 + #interrupt-cells = <1>; 819 + 820 + #address-cells = <1>; 821 + #size-cells = <1>; 822 + ranges; 823 + 824 + status = "disabled"; 825 + 826 + mdss_mdp: display-controller@fd900000 { 827 + compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 828 + reg = <0xfd900100 0x22000>; 829 + reg-names = "mdp_phys"; 830 + 831 + interrupt-parent = <&mdss>; 832 + interrupts = <0>; 833 + 834 + clocks = <&mmcc MDSS_AHB_CLK>, 835 + <&mmcc MDSS_AXI_CLK>, 836 + <&mmcc MDSS_MDP_CLK>, 837 + <&mmcc MDSS_VSYNC_CLK>; 838 + clock-names = "iface", 839 + "bus", 840 + "core", 841 + "vsync"; 842 + 843 + ports { 844 + #address-cells = <1>; 845 + #size-cells = <0>; 846 + 847 + port@0 { 848 + reg = <0>; 849 + mdss_mdp_intf1_out: endpoint { 850 + remote-endpoint = <&mdss_dsi0_in>; 851 + }; 852 + }; 853 + }; 854 + }; 855 + 856 + mdss_dsi0: dsi@fd922800 { 857 + compatible = "qcom,msm8226-dsi-ctrl", 858 + "qcom,mdss-dsi-ctrl"; 859 + reg = <0xfd922800 0x1f8>; 860 + reg-names = "dsi_ctrl"; 861 + 862 + interrupt-parent = <&mdss>; 863 + interrupts = <4>; 864 + 865 + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 866 + <&mmcc PCLK0_CLK_SRC>; 867 + assigned-clock-parents = <&mdss_dsi0_phy 0>, 868 + <&mdss_dsi0_phy 1>; 869 + 870 + clocks = <&mmcc MDSS_MDP_CLK>, 871 + <&mmcc MDSS_AHB_CLK>, 872 + <&mmcc MDSS_AXI_CLK>, 873 + <&mmcc MDSS_BYTE0_CLK>, 874 + <&mmcc MDSS_PCLK0_CLK>, 875 + <&mmcc MDSS_ESC0_CLK>, 876 + <&mmcc MMSS_MISC_AHB_CLK>; 877 + clock-names = "mdp_core", 878 + "iface", 879 + "bus", 880 + "byte", 881 + "pixel", 882 + "core", 883 + "core_mmss"; 884 + 885 + phys = <&mdss_dsi0_phy>; 886 + 887 + #address-cells = <1>; 888 + #size-cells = <0>; 889 + 890 + ports { 891 + #address-cells = <1>; 892 + #size-cells = <0>; 893 + 894 + port@0 { 895 + reg = <0>; 896 + mdss_dsi0_in: endpoint { 897 + remote-endpoint = <&mdss_mdp_intf1_out>; 898 + }; 899 + }; 900 + 901 + port@1 { 902 + reg = <1>; 903 + mdss_dsi0_out: endpoint { 904 + }; 905 + }; 906 + }; 907 + }; 908 + 909 + mdss_dsi0_phy: phy@fd922a00 { 910 + compatible = "qcom,dsi-phy-28nm-8226"; 911 + reg = <0xfd922a00 0xd4>, 912 + <0xfd922b00 0x280>, 913 + <0xfd922d80 0x30>; 914 + reg-names = "dsi_pll", 915 + "dsi_phy", 916 + "dsi_phy_regulator"; 917 + 918 + #clock-cells = <1>; 919 + #phy-cells = <0>; 920 + 921 + clocks = <&mmcc MDSS_AHB_CLK>, 922 + <&rpmcc RPM_SMD_XO_CLK_SRC>; 923 + clock-names = "iface", 924 + "ref"; 815 925 }; 816 926 }; 817 927 };
-1
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
··· 364 364 #size-cells = <0>; 365 365 reg = <0x16080000 0x1000>; 366 366 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 367 - spi-max-frequency = <24000000>; 368 367 cs-gpios = <&msmgpio 8 0>; 369 368 370 369 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+22 -22
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
··· 113 113 interrupts = <GIC_PPI 7 0xf04>; 114 114 }; 115 115 116 + rpm: remoteproc { 117 + compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; 118 + 119 + smd-edge { 120 + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 121 + qcom,ipc = <&apcs 8 0>; 122 + qcom,smd-edge = <15>; 123 + 124 + rpm_requests: rpm-requests { 125 + compatible = "qcom,rpm-msm8974"; 126 + qcom,smd-channels = "rpm_requests"; 127 + 128 + rpmcc: clock-controller { 129 + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 130 + #clock-cells = <1>; 131 + clocks = <&xo_board>; 132 + clock-names = "xo"; 133 + }; 134 + }; 135 + }; 136 + }; 137 + 116 138 reserved-memory { 117 139 #address-cells = <1>; 118 140 #size-cells = <1>; ··· 312 290 313 291 interrupt-controller; 314 292 #interrupt-cells = <2>; 315 - }; 316 - }; 317 - 318 - smd { 319 - compatible = "qcom,smd"; 320 - 321 - rpm { 322 - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 323 - qcom,ipc = <&apcs 8 0>; 324 - qcom,smd-edge = <15>; 325 - 326 - rpm_requests: rpm-requests { 327 - compatible = "qcom,rpm-msm8974"; 328 - qcom,smd-channels = "rpm_requests"; 329 - 330 - rpmcc: clock-controller { 331 - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 332 - #clock-cells = <1>; 333 - clocks = <&xo_board>; 334 - clock-names = "xo"; 335 - }; 336 - }; 337 293 }; 338 294 }; 339 295
+1 -1
arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts
··· 414 414 415 415 wcnss_pin_a: wcnss-pin-active-state { 416 416 wlan-pins { 417 - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; 417 + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; 418 418 function = "wlan"; 419 419 420 420 drive-strength = <6>;
+4 -4
arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts
··· 125 125 126 126 syna,startup-delay-ms = <100>; 127 127 128 - rmi-f01@1 { 128 + rmi4-f01@1 { 129 129 reg = <0x1>; 130 - syna,nosleep = <1>; 130 + syna,nosleep-mode = <1>; 131 131 }; 132 132 133 - rmi-f11@11 { 133 + rmi4-f11@11 { 134 134 reg = <0x11>; 135 - syna,f11-flip-x = <1>; 136 135 syna,sensor-type = <1>; 136 + touchscreen-inverted-x; 137 137 }; 138 138 }; 139 139 };
+6 -6
arch/arm/boot/dts/qcom/qcom-pm8226.dtsi
··· 102 102 #size-cells = <0>; 103 103 #io-channel-cells = <1>; 104 104 105 - adc-chan@7 { 105 + channel@7 { 106 106 reg = <VADC_VSYS>; 107 107 qcom,pre-scaling = <1 3>; 108 108 label = "vph_pwr"; 109 109 }; 110 - adc-chan@8 { 110 + channel@8 { 111 111 reg = <VADC_DIE_TEMP>; 112 112 label = "die_temp"; 113 113 }; 114 - adc-chan@9 { 114 + channel@9 { 115 115 reg = <VADC_REF_625MV>; 116 116 label = "ref_625mv"; 117 117 }; 118 - adc-chan@a { 118 + channel@a { 119 119 reg = <VADC_REF_1250MV>; 120 120 label = "ref_1250mv"; 121 121 }; 122 - adc-chan@e { 122 + channel@e { 123 123 reg = <VADC_GND_REF>; 124 124 }; 125 - adc-chan@f { 125 + channel@f { 126 126 reg = <VADC_VDD_VADC>; 127 127 }; 128 128 };
+24 -12
arch/arm/boot/dts/qcom/qcom-pm8941.dtsi
··· 50 50 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; 51 51 }; 52 52 53 - pwrkey@800 { 54 - compatible = "qcom,pm8941-pwrkey"; 53 + pon@800 { 54 + compatible = "qcom,pm8941-pon"; 55 55 reg = <0x800>; 56 - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; 57 - debounce = <15625>; 58 - bias-pull-up; 56 + 57 + pwrkey { 58 + compatible = "qcom,pm8941-pwrkey"; 59 + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; 60 + debounce = <15625>; 61 + bias-pull-up; 62 + }; 63 + 64 + pm8941_resin: resin { 65 + compatible = "qcom,pm8941-resin"; 66 + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; 67 + debounce = <15625>; 68 + bias-pull-up; 69 + status = "disabled"; 70 + }; 59 71 }; 60 72 61 73 usb_id: usb-detect@900 { ··· 145 133 #io-channel-cells = <1>; 146 134 147 135 148 - adc-chan@6 { 136 + channel@6 { 149 137 reg = <VADC_VBAT_SNS>; 150 138 }; 151 139 152 - adc-chan@8 { 140 + channel@8 { 153 141 reg = <VADC_DIE_TEMP>; 154 142 }; 155 143 156 - adc-chan@9 { 144 + channel@9 { 157 145 reg = <VADC_REF_625MV>; 158 146 }; 159 147 160 - adc-chan@a { 148 + channel@a { 161 149 reg = <VADC_REF_1250MV>; 162 150 }; 163 151 164 - adc-chan@e { 152 + channel@e { 165 153 reg = <VADC_GND_REF>; 166 154 }; 167 155 168 - adc-chan@f { 156 + channel@f { 169 157 reg = <VADC_VDD_VADC>; 170 158 }; 171 159 172 - adc-chan@30 { 160 + channel@30 { 173 161 reg = <VADC_LR_MUX1_BAT_THERM>; 174 162 }; 175 163 };
+6 -6
arch/arm/boot/dts/qcom/qcom-pma8084.dtsi
··· 64 64 #size-cells = <0>; 65 65 #io-channel-cells = <1>; 66 66 67 - adc-chan@8 { 67 + channel@8 { 68 68 reg = <VADC_DIE_TEMP>; 69 69 }; 70 70 71 - adc-chan@9 { 71 + channel@9 { 72 72 reg = <VADC_REF_625MV>; 73 73 }; 74 74 75 - adc-chan@a { 75 + channel@a { 76 76 reg = <VADC_REF_1250MV>; 77 77 }; 78 78 79 - adc-chan@c { 79 + channel@c { 80 80 reg = <VADC_SPARE1>; 81 81 }; 82 82 83 - adc-chan@e { 83 + channel@e { 84 84 reg = <VADC_GND_REF>; 85 85 }; 86 86 87 - adc-chan@f { 87 + channel@f { 88 88 reg = <VADC_VDD_VADC>; 89 89 }; 90 90 };
+4 -4
arch/arm/boot/dts/qcom/qcom-pmx55.dtsi
··· 40 40 #io-channel-cells = <1>; 41 41 interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; 42 42 43 - ref-gnd@0 { 43 + channel@0 { 44 44 reg = <ADC5_REF_GND>; 45 45 qcom,pre-scaling = <1 1>; 46 46 label = "ref_gnd"; 47 47 }; 48 48 49 - vref-1p25@1 { 49 + channel@1 { 50 50 reg = <ADC5_1P25VREF>; 51 51 qcom,pre-scaling = <1 1>; 52 52 label = "vref_1p25"; 53 53 }; 54 54 55 - die-temp@6 { 55 + channel@6 { 56 56 reg = <ADC5_DIE_TEMP>; 57 57 qcom,pre-scaling = <1 1>; 58 58 label = "die_temp"; 59 59 }; 60 60 61 - chg-temp@9 { 61 + channel@9 { 62 62 reg = <ADC5_CHG_TEMP>; 63 63 qcom,pre-scaling = <1 1>; 64 64 label = "chg_temp";
+1 -1
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
··· 603 603 604 604 resets = <&gcc GCC_USB30_BCR>; 605 605 606 - usb_dwc3: dwc3@a600000 { 606 + usb_dwc3: usb@a600000 { 607 607 compatible = "snps,dwc3"; 608 608 reg = <0x0a600000 0xcd00>; 609 609 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+1 -1
arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts
··· 7 7 #include "qcom-sdx65.dtsi" 8 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 9 9 #include <arm64/qcom/pmk8350.dtsi> 10 - #include <arm64/qcom/pm8150b.dtsi> 10 + #include <arm64/qcom/pm7250b.dtsi> 11 11 #include "qcom-pmx65.dtsi" 12 12 13 13 / {