Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v6.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
Basic graphics support for rv1126, some more new peripherals for it as well
and some improvements for the edgeble-neu2 board based on this soc.
* tag 'v6.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Add rv1126 VOP_LITE support
ARM: dts: rockchip: Add rv1126 PD_VO entry
ARM: dts: rockchip: Add 12V main supply for edgeble-neu2
ARM: dts: rockchip: Add 3V3_SYS regulator for edgeble-neu2
ARM: dts: rockchip: Enable SFC for edgeble-neu2
ARM: dts: rockchip: Drop EMMC_RSTN for edgeble-neu2
ARM: dts: rockchip: Add rv1126 uart5m2_xfer pins
ARM: dts: rockchip: Add rv1126 FSPI pins
ARM: dts: rockchip: Add SFC node to rv1126
Link: https://lore.kernel.org/r/6299163.hdfAi7Kttb@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+165
-10
+29
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
+29
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts
···
20
20
chosen {
21
21
stdout-path = "serial2:1500000n8";
22
22
};
23
+
24
+
vcc12v_dcin: vcc12v-dcin-regulator {
25
+
compatible = "regulator-fixed";
26
+
regulator-name = "vcc12v_dcin";
27
+
regulator-always-on;
28
+
regulator-boot-on;
29
+
regulator-min-microvolt = <12000000>;
30
+
regulator-max-microvolt = <12000000>;
31
+
};
32
+
33
+
vcc5v0_sys: vcc5v0-sys-regulator {
34
+
compatible = "regulator-fixed";
35
+
regulator-name = "vcc5v0_sys";
36
+
regulator-always-on;
37
+
regulator-boot-on;
38
+
regulator-min-microvolt = <5000000>;
39
+
regulator-max-microvolt = <5000000>;
40
+
vin-supply = <&vcc12v_dcin>;
41
+
};
42
+
43
+
v3v3_sys: v3v3-sys-regulator {
44
+
compatible = "regulator-fixed";
45
+
regulator-name = "v3v3_sys";
46
+
regulator-always-on;
47
+
regulator-boot-on;
48
+
regulator-min-microvolt = <3300000>;
49
+
regulator-max-microvolt = <3300000>;
50
+
vin-supply = <&vcc5v0_sys>;
51
+
};
23
52
};
24
53
25
54
&gmac {
+17
-10
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi
+17
-10
arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi
···
11
11
mmc0 = &emmc;
12
12
};
13
13
14
-
vcc5v0_sys: vcc5v0-sys-regulator {
15
-
compatible = "regulator-fixed";
16
-
regulator-name = "vcc5v0_sys";
17
-
regulator-always-on;
18
-
regulator-boot-on;
19
-
regulator-min-microvolt = <5000000>;
20
-
regulator-max-microvolt = <5000000>;
21
-
};
22
-
23
14
vccio_flash: vccio-flash-regulator {
24
15
compatible = "regulator-fixed";
25
16
enable-active-high;
···
43
52
bus-width = <8>;
44
53
non-removable;
45
54
pinctrl-names = "default";
46
-
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
55
+
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
47
56
rockchip,default-sample-phase = <90>;
48
57
vmmc-supply = <&vcc_3v3>;
49
58
vqmmc-supply = <&vccio_flash>;
···
290
299
&saradc {
291
300
vref-supply = <&vcc_1v8>;
292
301
status = "okay";
302
+
};
303
+
304
+
&sfc {
305
+
pinctrl-names = "default";
306
+
pinctrl-0 = <&fspi_pins>;
307
+
#address-cells = <1>;
308
+
#size-cells = <0>;
309
+
status = "okay";
310
+
311
+
flash@0 {
312
+
compatible = "jedec,spi-nor";
313
+
reg = <0>;
314
+
spi-max-frequency = <50000000>;
315
+
spi-rx-bus-width = <4>;
316
+
spi-tx-bus-width = <1>;
317
+
};
293
318
};
294
319
295
320
&sdio {
+26
arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
+26
arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi
···
59
59
<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
60
60
};
61
61
};
62
+
fspi {
63
+
/omit-if-no-ref/
64
+
fspi_pins: fspi-pins {
65
+
rockchip,pins =
66
+
/* fspi_clk */
67
+
<1 RK_PA3 3 &pcfg_pull_down>,
68
+
/* fspi_cs0n */
69
+
<0 RK_PD4 3 &pcfg_pull_up>,
70
+
/* fspi_d0 */
71
+
<1 RK_PA0 3 &pcfg_pull_up>,
72
+
/* fspi_d1 */
73
+
<1 RK_PA1 3 &pcfg_pull_up>,
74
+
/* fspi_d2 */
75
+
<0 RK_PD6 3 &pcfg_pull_up>,
76
+
/* fspi_d3 */
77
+
<1 RK_PA2 3 &pcfg_pull_up>;
78
+
};
79
+
};
62
80
i2c0 {
63
81
/omit-if-no-ref/
64
82
i2c0_xfer: i2c0-xfer {
···
266
248
<3 RK_PA7 4 &pcfg_pull_up>,
267
249
/* uart5_tx_m0 */
268
250
<3 RK_PA6 4 &pcfg_pull_up>;
251
+
};
252
+
/omit-if-no-ref/
253
+
uart5m2_xfer: uart5m2-xfer {
254
+
rockchip,pins =
255
+
/* uart5_rx_m2 */
256
+
<2 RK_PA1 3 &pcfg_pull_up>,
257
+
/* uart5_tx_m2 */
258
+
<2 RK_PA0 3 &pcfg_pull_up>;
269
259
};
270
260
};
271
261
};
+93
arch/arm/boot/dts/rockchip/rv1126.dtsi
+93
arch/arm/boot/dts/rockchip/rv1126.dtsi
···
83
83
clock-frequency = <24000000>;
84
84
};
85
85
86
+
display_subsystem {
87
+
compatible = "rockchip,display-subsystem";
88
+
ports = <&vop_out>;
89
+
};
90
+
86
91
xin24m: oscillator {
87
92
compatible = "fixed-clock";
88
93
clock-frequency = <24000000>;
···
128
123
qos_sdio: qos@fe86c000 {
129
124
compatible = "rockchip,rv1126-qos", "syscon";
130
125
reg = <0xfe86c000 0x20>;
126
+
};
127
+
128
+
qos_iep: qos@fe8a0000 {
129
+
compatible = "rockchip,rv1126-qos", "syscon";
130
+
reg = <0xfe8a0000 0x20>;
131
+
};
132
+
133
+
qos_rga_rd: qos@fe8a0080 {
134
+
compatible = "rockchip,rv1126-qos", "syscon";
135
+
reg = <0xfe8a0080 0x20>;
136
+
};
137
+
138
+
qos_rga_wr: qos@fe8a0100 {
139
+
compatible = "rockchip,rv1126-qos", "syscon";
140
+
reg = <0xfe8a0100 0x20>;
141
+
};
142
+
143
+
qos_vop: qos@fe8a0180 {
144
+
compatible = "rockchip,rv1126-qos", "syscon";
145
+
reg = <0xfe8a0180 0x20>;
131
146
};
132
147
133
148
gic: interrupt-controller@feff0000 {
···
193
168
clocks = <&cru HCLK_SDIO>,
194
169
<&cru CLK_SDIO>;
195
170
pm_qos = <&qos_sdio>;
171
+
#power-domain-cells = <0>;
172
+
};
173
+
174
+
power-domain@RV1126_PD_VO {
175
+
reg = <RV1126_PD_VO>;
176
+
clocks = <&cru ACLK_RGA>,
177
+
<&cru HCLK_RGA>,
178
+
<&cru CLK_RGA_CORE>,
179
+
<&cru ACLK_VOP>,
180
+
<&cru HCLK_VOP>,
181
+
<&cru DCLK_VOP>,
182
+
<&cru PCLK_DSIHOST>,
183
+
<&cru ACLK_IEP>,
184
+
<&cru HCLK_IEP>,
185
+
<&cru CLK_IEP_CORE>;
186
+
pm_qos = <&qos_rga_rd>,
187
+
<&qos_rga_wr>,
188
+
<&qos_vop>,
189
+
<&qos_iep>;
196
190
#power-domain-cells = <0>;
197
191
};
198
192
};
···
376
332
clock-names = "pclk", "timer";
377
333
};
378
334
335
+
vop: vop@ffb00000 {
336
+
compatible = "rockchip,rv1126-vop";
337
+
reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
338
+
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
339
+
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
340
+
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
341
+
reset-names = "axi", "ahb", "dclk";
342
+
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
343
+
iommus = <&vop_mmu>;
344
+
power-domains = <&power RV1126_PD_VO>;
345
+
status = "disabled";
346
+
347
+
vop_out: port {
348
+
#address-cells = <1>;
349
+
#size-cells = <0>;
350
+
351
+
vop_out_rgb: endpoint@0 {
352
+
reg = <0>;
353
+
};
354
+
355
+
vop_out_dsi: endpoint@1 {
356
+
reg = <1>;
357
+
};
358
+
};
359
+
};
360
+
361
+
vop_mmu: iommu@ffb00f00 {
362
+
compatible = "rockchip,iommu";
363
+
reg = <0xffb00f00 0x100>;
364
+
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
365
+
clock-names = "aclk", "iface";
366
+
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
367
+
#iommu-cells = <0>;
368
+
power-domains = <&power RV1126_PD_VO>;
369
+
status = "disabled";
370
+
};
371
+
379
372
gmac: ethernet@ffc40000 {
380
373
compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
381
374
reg = <0xffc40000 0x4000>;
···
497
416
fifo-depth = <0x100>;
498
417
max-frequency = <200000000>;
499
418
power-domains = <&power RV1126_PD_SDIO>;
419
+
status = "disabled";
420
+
};
421
+
422
+
sfc: spi@ffc90000 {
423
+
compatible = "rockchip,sfc";
424
+
reg = <0xffc90000 0x4000>;
425
+
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
426
+
assigned-clocks = <&cru SCLK_SFC>;
427
+
assigned-clock-rates = <80000000>;
428
+
clock-names = "clk_sfc", "hclk_sfc";
429
+
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
430
+
power-domains = <&power RV1126_PD_NVM>;
500
431
status = "disabled";
501
432
};
502
433