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phy: ti: phy-j721e-wiz: split wiz_clock_init() function

The wiz_clock_init() function mixes probe and hardware configuration.
Rename the wiz_clock_init() to wiz_clock_probe() and move the hardware
configuration part in a new function named wiz_clock_init().

This hardware configuration sequence must be called during the resume
stage of the driver.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-2-f15815833974@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Thomas Richard and committed by
Vinod Koul 3c4e13cf 5aa4733b

+37 -29
+37 -29
drivers/phy/ti/phy-j721e-wiz.c
··· 1076 1076 return ret; 1077 1077 } 1078 1078 1079 - static int wiz_clock_init(struct wiz *wiz, struct device_node *node) 1079 + static void wiz_clock_init(struct wiz *wiz) 1080 1080 { 1081 - const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1082 - struct device *dev = wiz->dev; 1083 - struct device_node *clk_node; 1084 - const char *node_name; 1085 1081 unsigned long rate; 1086 - struct clk *clk; 1087 - int ret; 1088 - int i; 1089 1082 1090 - clk = devm_clk_get(dev, "core_ref_clk"); 1091 - if (IS_ERR(clk)) 1092 - return dev_err_probe(dev, PTR_ERR(clk), 1093 - "core_ref_clk clock not found\n"); 1094 - 1095 - wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1096 - 1097 - rate = clk_get_rate(clk); 1098 - if (rate >= 100000000) 1083 + rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]); 1084 + if (rate >= REF_CLK_100MHZ) 1099 1085 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); 1100 1086 else 1101 1087 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); ··· 1105 1119 break; 1106 1120 } 1107 1121 1122 + if (wiz->input_clks[WIZ_CORE_REFCLK1]) { 1123 + rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]); 1124 + if (rate >= REF_CLK_100MHZ) 1125 + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1126 + else 1127 + regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1128 + } 1129 + 1130 + rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]); 1131 + if (rate >= REF_CLK_100MHZ) 1132 + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1133 + else 1134 + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1135 + } 1136 + 1137 + static int wiz_clock_probe(struct wiz *wiz, struct device_node *node) 1138 + { 1139 + const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; 1140 + struct device *dev = wiz->dev; 1141 + struct device_node *clk_node; 1142 + const char *node_name; 1143 + struct clk *clk; 1144 + int ret; 1145 + int i; 1146 + 1147 + clk = devm_clk_get(dev, "core_ref_clk"); 1148 + if (IS_ERR(clk)) 1149 + return dev_err_probe(dev, PTR_ERR(clk), 1150 + "core_ref_clk clock not found\n"); 1151 + 1152 + wiz->input_clks[WIZ_CORE_REFCLK] = clk; 1153 + 1108 1154 if (wiz->data->pma_cmn_refclk1_int_mode) { 1109 1155 clk = devm_clk_get(dev, "core_ref1_clk"); 1110 1156 if (IS_ERR(clk)) ··· 1144 1126 "core_ref1_clk clock not found\n"); 1145 1127 1146 1128 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; 1147 - 1148 - rate = clk_get_rate(clk); 1149 - if (rate >= 100000000) 1150 - regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1); 1151 - else 1152 - regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3); 1153 1129 } 1154 1130 1155 1131 clk = devm_clk_get(dev, "ext_ref_clk"); ··· 1153 1141 1154 1142 wiz->input_clks[WIZ_EXT_REFCLK] = clk; 1155 1143 1156 - rate = clk_get_rate(clk); 1157 - if (rate >= 100000000) 1158 - regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); 1159 - else 1160 - regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); 1144 + wiz_clock_init(wiz); 1161 1145 1162 1146 switch (wiz->type) { 1163 1147 case AM64_WIZ_10G: ··· 1597 1589 goto err_get_sync; 1598 1590 } 1599 1591 1600 - ret = wiz_clock_init(wiz, node); 1592 + ret = wiz_clock_probe(wiz, node); 1601 1593 if (ret < 0) { 1602 1594 dev_warn(dev, "Failed to initialize clocks\n"); 1603 1595 goto err_get_sync;