Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Update ROQ size in coredump
Since RoQ size differs between generations, calculate dynamically the
RoQ size while capturing coredump.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/515610/
Link: https://lore.kernel.org/r/20221221203925.v2.4.I07f22966395eb045f6b312710f53890d5d7e69d4@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org>
authored by
Akhil P Oommen
and committed by
Rob Clark
3cba4a2c
1e05bba5
+20
-8
+10
-1
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+10
-1
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
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dumper);
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}
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+
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
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{
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/* The value at [16:31] is in 4dword units. Convert it to dwords */
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return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;
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}
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+
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/* Read a block of data from an indexed register pair */
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static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
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struct a6xx_gpu_state *a6xx_state,
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-
const struct a6xx_indexed_registers *indexed,
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struct a6xx_indexed_registers *indexed,
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struct a6xx_gpu_state_obj *obj)
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{
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int i;
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obj->handle = (const void *) indexed;
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if (indexed->count_fn)
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indexed->count = indexed->count_fn(gpu);
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+
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obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32));
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if (!obj->data)
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return;
+10
-7
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+10
-7
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
···
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REGS(a6xx_gmu_gx_registers, 0, 0),
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};
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-
static const struct a6xx_indexed_registers {
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static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
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static struct a6xx_indexed_registers {
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const char *name;
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u32 addr;
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u32 data;
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u32 count;
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u32 (*count_fn)(struct msm_gpu *gpu);
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} a6xx_indexed_reglist[] = {
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{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
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-
REG_A6XX_CP_SQE_STAT_DATA, 0x33 },
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REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
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{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
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-
REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },
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+
REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
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{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
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-
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x6000 },
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REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
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{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
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-
REG_A6XX_CP_ROQ_DBG_DATA, 0x400 },
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REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
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};
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-
static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
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static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
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"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
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-
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060,
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REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
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};
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#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }