tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Fixes for a few clk drivers and bindings:

- Add a missing property to the Mediatek MT8188 clk binding to
keep binding checks happy

- Avoid an OOB by setting the correct number of parents in
dispmix_csr_clk_dev_data

- Allocate clk_hw structs early in probe to avoid an ordering
issue where clk_parent_data points to an unallocated clk_hw
when the child clk is registered before the parent clk in the
SCMI clk driver

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
clk: scmi: Handle case where child clocks are initialized before their parents

Linus Torvalds 3cd75219 5d5d6229

+22 -13
+3
Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
··· 52 52 '#clock-cells': 53 53 const: 1 54 54 55 + '#reset-cells': 56 + const: 1 57 + 55 58 required: 56 59 - compatible 57 60 - reg
+11 -9
drivers/clk/clk-scmi.c
··· 404 404 const struct scmi_handle *handle = sdev->handle; 405 405 struct scmi_protocol_handle *ph; 406 406 const struct clk_ops *scmi_clk_ops_db[SCMI_MAX_CLK_OPS] = {}; 407 + struct scmi_clk *sclks; 407 408 408 409 if (!handle) 409 410 return -ENODEV; ··· 431 430 transport_is_atomic = handle->is_transport_atomic(handle, 432 431 &atomic_threshold_us); 433 432 434 - for (idx = 0; idx < count; idx++) { 435 - struct scmi_clk *sclk; 436 - const struct clk_ops *scmi_ops; 433 + sclks = devm_kcalloc(dev, count, sizeof(*sclks), GFP_KERNEL); 434 + if (!sclks) 435 + return -ENOMEM; 437 436 438 - sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); 439 - if (!sclk) 440 - return -ENOMEM; 437 + for (idx = 0; idx < count; idx++) 438 + hws[idx] = &sclks[idx].hw; 439 + 440 + for (idx = 0; idx < count; idx++) { 441 + struct scmi_clk *sclk = &sclks[idx]; 442 + const struct clk_ops *scmi_ops; 441 443 442 444 sclk->info = scmi_proto_clk_ops->info_get(ph, idx); 443 445 if (!sclk->info) { 444 446 dev_dbg(dev, "invalid clock info for idx %d\n", idx); 445 - devm_kfree(dev, sclk); 447 + hws[idx] = NULL; 446 448 continue; 447 449 } 448 450 ··· 483 479 if (err) { 484 480 dev_err(dev, "failed to register clock %d\n", idx); 485 481 devm_kfree(dev, sclk->parent_data); 486 - devm_kfree(dev, sclk); 487 482 hws[idx] = NULL; 488 483 } else { 489 484 dev_dbg(dev, "Registered clock:%s%s\n", 490 485 sclk->info->name, 491 486 scmi_ops->enable ? " (atomic ops)" : ""); 492 - hws[idx] = &sclk->hw; 493 487 } 494 488 } 495 489
+8 -4
drivers/clk/imx/clk-imx95-blk-ctl.c
··· 219 219 .clk_reg_offset = 0, 220 220 }; 221 221 222 + static const char * const disp_engine_parents[] = { 223 + "videopll1", "dsi_pll", "ldb_pll_div7" 224 + }; 225 + 222 226 static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = { 223 227 [IMX95_CLK_DISPMIX_ENG0_SEL] = { 224 228 .name = "disp_engine0_sel", 225 - .parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", }, 226 - .num_parents = 4, 229 + .parent_names = disp_engine_parents, 230 + .num_parents = ARRAY_SIZE(disp_engine_parents), 227 231 .reg = 0, 228 232 .bit_idx = 0, 229 233 .bit_width = 2, ··· 236 232 }, 237 233 [IMX95_CLK_DISPMIX_ENG1_SEL] = { 238 234 .name = "disp_engine1_sel", 239 - .parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", }, 240 - .num_parents = 4, 235 + .parent_names = disp_engine_parents, 236 + .num_parents = ARRAY_SIZE(disp_engine_parents), 241 237 .reg = 0, 242 238 .bit_idx = 2, 243 239 .bit_width = 2,