Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-10-24' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Simona Vetter:
"Very quiet, all just small stuff and nothing scary pending to my
knowledge:
- drm_panic: bunch of size calculation fixes
- pantor: fix kernel panic on partial gpu va unmap
- rockchip: hdmi hotplug setup fix
- amdgpu: dp mst, dc/display fixes
- i915: fix panic structure leak
- xe: madvise uapi fix, wq alloc error, vma flag handling fix"
* tag 'drm-fixes-2025-10-24' of https://gitlab.freedesktop.org/drm/kernel:
drm/xe: Check return value of GGTT workqueue allocation
drm/amd/display: use GFP_NOWAIT for allocation in interrupt handler
drm/amd/display: increase max link count and fix link->enc NULL pointer access
drm/amd/display: Fix NULL pointer dereference
drm/panic: Fix 24bit pixel crossing page boundaries
drm/panic: Fix divide by 0 if the screen width < font width
drm/panic: Fix kmsg text drawing rectangle
drm/panic: Fix qr_code, ensure vmargin is positive
drm/panic: Fix overlap between qr code and logo
drm/panic: Fix drawing the logo on a small narrow screen
drm/xe/uapi: Hide the madvise autoreset behind a VM_BIND flag
drm/xe: Retain vma flags when recreating and splitting vmas for madvise
drm/i915/panic: fix panic structure allocation memory leak
drm/panthor: Fix kernel panic on partial unmap of a GPU VA region
drm/rockchip: dw_hdmi: use correct SCLIN mask for RK3228
+153
-95
+2
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+2
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
551
551
struct dc_stream_state *stream,
552
552
struct dc_crtc_timing_adjust *adjust)
553
553
{
554
-
struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_KERNEL);
554
+
struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_NOWAIT);
555
555
if (!offload_work) {
556
556
drm_dbg_driver(adev_to_drm(adev), "Failed to allocate vupdate_offload_work\n");
557
557
return;
558
558
}
559
559
560
-
struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_KERNEL);
560
+
struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_NOWAIT);
561
561
if (!adjust_copy) {
562
562
drm_dbg_driver(adev_to_drm(adev), "Failed to allocate adjust_copy\n");
563
563
kfree(offload_work);
+3
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+3
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+2
-1
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+2
-1
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
···
78
78
struct audio_output audio_output[MAX_PIPES];
79
79
struct dc_stream_state *streams_on_link[MAX_PIPES];
80
80
int num_streams_on_link = 0;
81
+
struct dc *dc = (struct dc *)link->dc;
81
82
82
83
needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) !=
83
84
link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings));
···
151
150
if (streams_on_link[i] && streams_on_link[i]->link && streams_on_link[i]->link == link) {
152
151
stream_update.stream = streams_on_link[i];
153
152
stream_update.dpms_off = &dpms_off;
154
-
dc_update_planes_and_stream(state->clk_mgr->ctx->dc, NULL, 0, streams_on_link[i], &stream_update);
153
+
dc_update_planes_and_stream(dc, NULL, 0, streams_on_link[i], &stream_update);
155
154
}
156
155
}
157
156
}
+54
-6
drivers/gpu/drm/drm_panic.c
+54
-6
drivers/gpu/drm/drm_panic.c
···
174
174
*p = color & 0xff;
175
175
}
176
176
177
+
/*
178
+
* Special case if the pixel crosses page boundaries
179
+
*/
180
+
static void drm_panic_write_pixel24_xpage(void *vaddr, struct page *next_page,
181
+
unsigned int offset, u32 color)
182
+
{
183
+
u8 *vaddr2;
184
+
u8 *p = vaddr + offset;
185
+
186
+
vaddr2 = kmap_local_page_try_from_panic(next_page);
187
+
188
+
*p++ = color & 0xff;
189
+
color >>= 8;
190
+
191
+
if (offset == PAGE_SIZE - 1)
192
+
p = vaddr2;
193
+
194
+
*p++ = color & 0xff;
195
+
color >>= 8;
196
+
197
+
if (offset == PAGE_SIZE - 2)
198
+
p = vaddr2;
199
+
200
+
*p = color & 0xff;
201
+
kunmap_local(vaddr2);
202
+
}
203
+
177
204
static void drm_panic_write_pixel32(void *vaddr, unsigned int offset, u32 color)
178
205
{
179
206
u32 *p = vaddr + offset;
···
258
231
page = new_page;
259
232
vaddr = kmap_local_page_try_from_panic(pages[page]);
260
233
}
261
-
if (vaddr)
234
+
if (!vaddr)
235
+
continue;
236
+
237
+
// Special case for 24bit, as a pixel might cross page boundaries
238
+
if (cpp == 3 && offset + 3 > PAGE_SIZE)
239
+
drm_panic_write_pixel24_xpage(vaddr, pages[page + 1],
240
+
offset, fg32);
241
+
else
262
242
drm_panic_write_pixel(vaddr, offset, fg32, cpp);
263
243
}
264
244
}
···
355
321
page = new_page;
356
322
vaddr = kmap_local_page_try_from_panic(pages[page]);
357
323
}
358
-
drm_panic_write_pixel(vaddr, offset, color, cpp);
324
+
if (!vaddr)
325
+
continue;
326
+
327
+
// Special case for 24bit, as a pixel might cross page boundaries
328
+
if (cpp == 3 && offset + 3 > PAGE_SIZE)
329
+
drm_panic_write_pixel24_xpage(vaddr, pages[page + 1],
330
+
offset, color);
331
+
else
332
+
drm_panic_write_pixel(vaddr, offset, color, cpp);
359
333
}
360
334
}
361
335
if (vaddr)
···
471
429
static void drm_panic_logo_draw(struct drm_scanout_buffer *sb, struct drm_rect *rect,
472
430
const struct font_desc *font, u32 fg_color)
473
431
{
432
+
if (rect->x2 > sb->width || rect->y2 > sb->height)
433
+
return;
434
+
474
435
if (logo_mono)
475
436
drm_panic_blit(sb, rect, logo_mono->data,
476
437
DIV_ROUND_UP(drm_rect_width(rect), 8), 1, fg_color);
···
522
477
struct drm_panic_line *line, int yoffset, u32 fg_color)
523
478
{
524
479
int chars_per_row = sb->width / font->width;
525
-
struct drm_rect r_txt = DRM_RECT_INIT(0, yoffset, sb->width, sb->height);
480
+
struct drm_rect r_txt = DRM_RECT_INIT(0, yoffset, sb->width, font->height);
526
481
struct drm_panic_line line_wrap;
527
482
528
483
if (line->len > chars_per_row) {
···
565
520
struct drm_panic_line line;
566
521
int yoffset;
567
522
568
-
if (!font)
523
+
if (!font || font->width > sb->width)
569
524
return;
570
525
571
526
yoffset = sb->height - font->height - (sb->height % font->height) / 2;
···
778
733
pr_debug("QR width %d and scale %d\n", qr_width, scale);
779
734
r_qr_canvas = DRM_RECT_INIT(0, 0, qr_canvas_width * scale, qr_canvas_width * scale);
780
735
781
-
v_margin = (sb->height - drm_rect_height(&r_qr_canvas) - drm_rect_height(&r_msg)) / 5;
736
+
v_margin = sb->height - drm_rect_height(&r_qr_canvas) - drm_rect_height(&r_msg);
737
+
if (v_margin < 0)
738
+
return -ENOSPC;
739
+
v_margin /= 5;
782
740
783
741
drm_rect_translate(&r_qr_canvas, (sb->width - r_qr_canvas.x2) / 2, 2 * v_margin);
784
742
r_qr = DRM_RECT_INIT(r_qr_canvas.x1 + QR_MARGIN * scale, r_qr_canvas.y1 + QR_MARGIN * scale,
···
794
746
/* Fill with the background color, and draw text on top */
795
747
drm_panic_fill(sb, &r_screen, bg_color);
796
748
797
-
if (!drm_rect_overlap(&r_logo, &r_msg) && !drm_rect_overlap(&r_logo, &r_qr))
749
+
if (!drm_rect_overlap(&r_logo, &r_msg) && !drm_rect_overlap(&r_logo, &r_qr_canvas))
798
750
drm_panic_logo_draw(sb, &r_logo, font, fg_color);
799
751
800
752
draw_txt_rectangle(sb, font, panic_msg, panic_msg_lines, true, &r_msg, fg_color);
+13
-12
drivers/gpu/drm/i915/display/intel_fb.c
+13
-12
drivers/gpu/drm/i915/display/intel_fb.c
···
2117
2117
2118
2118
intel_frontbuffer_put(intel_fb->frontbuffer);
2119
2119
2120
+
kfree(intel_fb->panic);
2120
2121
kfree(intel_fb);
2121
2122
}
2122
2123
···
2216
2215
struct intel_display *display = to_intel_display(obj->dev);
2217
2216
struct drm_framebuffer *fb = &intel_fb->base;
2218
2217
u32 max_stride;
2219
-
int ret = -EINVAL;
2218
+
int ret;
2220
2219
int i;
2220
+
2221
+
intel_fb->panic = intel_panic_alloc();
2222
+
if (!intel_fb->panic)
2223
+
return -ENOMEM;
2221
2224
2222
2225
/*
2223
2226
* intel_frontbuffer_get() must be done before
2224
2227
* intel_fb_bo_framebuffer_init() to avoid set_tiling vs. addfb race.
2225
2228
*/
2226
2229
intel_fb->frontbuffer = intel_frontbuffer_get(obj);
2227
-
if (!intel_fb->frontbuffer)
2228
-
return -ENOMEM;
2230
+
if (!intel_fb->frontbuffer) {
2231
+
ret = -ENOMEM;
2232
+
goto err_free_panic;
2233
+
}
2229
2234
2230
2235
ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd);
2231
2236
if (ret)
···
2330
2323
intel_fb_bo_framebuffer_fini(obj);
2331
2324
err_frontbuffer_put:
2332
2325
intel_frontbuffer_put(intel_fb->frontbuffer);
2326
+
err_free_panic:
2327
+
kfree(intel_fb->panic);
2328
+
2333
2329
return ret;
2334
2330
}
2335
2331
···
2359
2349
struct intel_framebuffer *intel_framebuffer_alloc(void)
2360
2350
{
2361
2351
struct intel_framebuffer *intel_fb;
2362
-
struct intel_panic *panic;
2363
2352
2364
2353
intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2365
2354
if (!intel_fb)
2366
2355
return NULL;
2367
-
2368
-
panic = intel_panic_alloc();
2369
-
if (!panic) {
2370
-
kfree(intel_fb);
2371
-
return NULL;
2372
-
}
2373
-
2374
-
intel_fb->panic = panic;
2375
2356
2376
2357
return intel_fb;
2377
2358
}
+7
-3
drivers/gpu/drm/panthor/panthor_mmu.c
+7
-3
drivers/gpu/drm/panthor/panthor_mmu.c
···
1175
1175
break;
1176
1176
1177
1177
case DRM_PANTHOR_VM_BIND_OP_TYPE_UNMAP:
1178
-
/* Partial unmaps might trigger a remap with either a prev or a next VA,
1179
-
* but not both.
1178
+
/* Two VMAs can be needed for an unmap, as an unmap can happen
1179
+
* in the middle of a drm_gpuva, requiring a remap with both
1180
+
* prev & next VA. Or an unmap can span more than one drm_gpuva
1181
+
* where the first and last ones are covered partially, requring
1182
+
* a remap for the first with a prev VA and remap for the last
1183
+
* with a next VA.
1180
1184
*/
1181
-
vma_count = 1;
1185
+
vma_count = 2;
1182
1186
break;
1183
1187
1184
1188
default:
+1
-1
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+1
-1
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+3
drivers/gpu/drm/xe/xe_ggtt.c
+3
drivers/gpu/drm/xe/xe_ggtt.c
···
292
292
ggtt->pt_ops = &xelp_pt_ops;
293
293
294
294
ggtt->wq = alloc_workqueue("xe-ggtt-wq", 0, WQ_MEM_RECLAIM);
295
+
if (!ggtt->wq)
296
+
return -ENOMEM;
297
+
295
298
__xe_ggtt_init_early(ggtt, xe_wopcm_size(xe));
296
299
297
300
err = drmm_add_action_or_reset(&xe->drm, ggtt_fini_early, ggtt);
+2
-2
drivers/gpu/drm/xe/xe_pt.c
+2
-2
drivers/gpu/drm/xe/xe_pt.c
···
2022
2022
case DRM_GPUVA_OP_MAP:
2023
2023
if ((!op->map.immediate && xe_vm_in_fault_mode(vm) &&
2024
2024
!op->map.invalidate_on_bind) ||
2025
-
op->map.is_cpu_addr_mirror)
2025
+
(op->map.vma_flags & XE_VMA_SYSTEM_ALLOCATOR))
2026
2026
break;
2027
2027
2028
2028
err = bind_op_prepare(vm, tile, pt_update_ops, op->map.vma,
···
2252
2252
switch (op->base.op) {
2253
2253
case DRM_GPUVA_OP_MAP:
2254
2254
if ((!op->map.immediate && xe_vm_in_fault_mode(vm)) ||
2255
-
op->map.is_cpu_addr_mirror)
2255
+
(op->map.vma_flags & XE_VMA_SYSTEM_ALLOCATOR))
2256
2256
break;
2257
2257
2258
2258
bind_op_commit(vm, tile, pt_update_ops, op->map.vma, fence,
+5
drivers/gpu/drm/xe/xe_svm.c
+5
drivers/gpu/drm/xe/xe_svm.c
+37
-59
drivers/gpu/drm/xe/xe_vm.c
+37
-59
drivers/gpu/drm/xe/xe_vm.c
···
616
616
vops->pt_update_ops[i].num_ops += inc_val;
617
617
}
618
618
619
+
#define XE_VMA_CREATE_MASK ( \
620
+
XE_VMA_READ_ONLY | \
621
+
XE_VMA_DUMPABLE | \
622
+
XE_VMA_SYSTEM_ALLOCATOR | \
623
+
DRM_GPUVA_SPARSE | \
624
+
XE_VMA_MADV_AUTORESET)
625
+
619
626
static void xe_vm_populate_rebind(struct xe_vma_op *op, struct xe_vma *vma,
620
627
u8 tile_mask)
621
628
{
···
635
628
op->base.map.gem.offset = vma->gpuva.gem.offset;
636
629
op->map.vma = vma;
637
630
op->map.immediate = true;
638
-
op->map.dumpable = vma->gpuva.flags & XE_VMA_DUMPABLE;
639
-
op->map.is_null = xe_vma_is_null(vma);
631
+
op->map.vma_flags = vma->gpuva.flags & XE_VMA_CREATE_MASK;
640
632
}
641
633
642
634
static int xe_vm_ops_add_rebind(struct xe_vma_ops *vops, struct xe_vma *vma,
···
938
932
kfree(vma);
939
933
}
940
934
941
-
#define VMA_CREATE_FLAG_READ_ONLY BIT(0)
942
-
#define VMA_CREATE_FLAG_IS_NULL BIT(1)
943
-
#define VMA_CREATE_FLAG_DUMPABLE BIT(2)
944
-
#define VMA_CREATE_FLAG_IS_SYSTEM_ALLOCATOR BIT(3)
945
-
946
935
static struct xe_vma *xe_vma_create(struct xe_vm *vm,
947
936
struct xe_bo *bo,
948
937
u64 bo_offset_or_userptr,
···
948
947
struct xe_vma *vma;
949
948
struct xe_tile *tile;
950
949
u8 id;
951
-
bool read_only = (flags & VMA_CREATE_FLAG_READ_ONLY);
952
-
bool is_null = (flags & VMA_CREATE_FLAG_IS_NULL);
953
-
bool dumpable = (flags & VMA_CREATE_FLAG_DUMPABLE);
954
-
bool is_cpu_addr_mirror =
955
-
(flags & VMA_CREATE_FLAG_IS_SYSTEM_ALLOCATOR);
950
+
bool is_null = (flags & DRM_GPUVA_SPARSE);
951
+
bool is_cpu_addr_mirror = (flags & XE_VMA_SYSTEM_ALLOCATOR);
956
952
957
953
xe_assert(vm->xe, start < end);
958
954
xe_assert(vm->xe, end < vm->size);
···
970
972
if (!vma)
971
973
return ERR_PTR(-ENOMEM);
972
974
973
-
if (is_cpu_addr_mirror)
974
-
vma->gpuva.flags |= XE_VMA_SYSTEM_ALLOCATOR;
975
-
if (is_null)
976
-
vma->gpuva.flags |= DRM_GPUVA_SPARSE;
977
975
if (bo)
978
976
vma->gpuva.gem.obj = &bo->ttm.base;
979
977
}
···
980
986
vma->gpuva.vm = &vm->gpuvm;
981
987
vma->gpuva.va.addr = start;
982
988
vma->gpuva.va.range = end - start + 1;
983
-
if (read_only)
984
-
vma->gpuva.flags |= XE_VMA_READ_ONLY;
985
-
if (dumpable)
986
-
vma->gpuva.flags |= XE_VMA_DUMPABLE;
989
+
vma->gpuva.flags = flags;
987
990
988
991
for_each_tile(tile, vm->xe, id)
989
992
vma->tile_mask |= 0x1 << id;
···
2263
2272
if (__op->op == DRM_GPUVA_OP_MAP) {
2264
2273
op->map.immediate =
2265
2274
flags & DRM_XE_VM_BIND_FLAG_IMMEDIATE;
2266
-
op->map.read_only =
2267
-
flags & DRM_XE_VM_BIND_FLAG_READONLY;
2268
-
op->map.is_null = flags & DRM_XE_VM_BIND_FLAG_NULL;
2269
-
op->map.is_cpu_addr_mirror = flags &
2270
-
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR;
2271
-
op->map.dumpable = flags & DRM_XE_VM_BIND_FLAG_DUMPABLE;
2275
+
if (flags & DRM_XE_VM_BIND_FLAG_READONLY)
2276
+
op->map.vma_flags |= XE_VMA_READ_ONLY;
2277
+
if (flags & DRM_XE_VM_BIND_FLAG_NULL)
2278
+
op->map.vma_flags |= DRM_GPUVA_SPARSE;
2279
+
if (flags & DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR)
2280
+
op->map.vma_flags |= XE_VMA_SYSTEM_ALLOCATOR;
2281
+
if (flags & DRM_XE_VM_BIND_FLAG_DUMPABLE)
2282
+
op->map.vma_flags |= XE_VMA_DUMPABLE;
2283
+
if (flags & DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET)
2284
+
op->map.vma_flags |= XE_VMA_MADV_AUTORESET;
2272
2285
op->map.pat_index = pat_index;
2273
2286
op->map.invalidate_on_bind =
2274
2287
__xe_vm_needs_clear_scratch_pages(vm, flags);
···
2585
2590
.pat_index = op->map.pat_index,
2586
2591
};
2587
2592
2588
-
flags |= op->map.read_only ?
2589
-
VMA_CREATE_FLAG_READ_ONLY : 0;
2590
-
flags |= op->map.is_null ?
2591
-
VMA_CREATE_FLAG_IS_NULL : 0;
2592
-
flags |= op->map.dumpable ?
2593
-
VMA_CREATE_FLAG_DUMPABLE : 0;
2594
-
flags |= op->map.is_cpu_addr_mirror ?
2595
-
VMA_CREATE_FLAG_IS_SYSTEM_ALLOCATOR : 0;
2593
+
flags |= op->map.vma_flags & XE_VMA_CREATE_MASK;
2596
2594
2597
2595
vma = new_vma(vm, &op->base.map, &default_attr,
2598
2596
flags);
···
2594
2606
2595
2607
op->map.vma = vma;
2596
2608
if (((op->map.immediate || !xe_vm_in_fault_mode(vm)) &&
2597
-
!op->map.is_cpu_addr_mirror) ||
2609
+
!(op->map.vma_flags & XE_VMA_SYSTEM_ALLOCATOR)) ||
2598
2610
op->map.invalidate_on_bind)
2599
2611
xe_vma_ops_incr_pt_update_ops(vops,
2600
2612
op->tile_mask, 1);
···
2625
2637
op->remap.start = xe_vma_start(old);
2626
2638
op->remap.range = xe_vma_size(old);
2627
2639
2628
-
flags |= op->base.remap.unmap->va->flags &
2629
-
XE_VMA_READ_ONLY ?
2630
-
VMA_CREATE_FLAG_READ_ONLY : 0;
2631
-
flags |= op->base.remap.unmap->va->flags &
2632
-
DRM_GPUVA_SPARSE ?
2633
-
VMA_CREATE_FLAG_IS_NULL : 0;
2634
-
flags |= op->base.remap.unmap->va->flags &
2635
-
XE_VMA_DUMPABLE ?
2636
-
VMA_CREATE_FLAG_DUMPABLE : 0;
2637
-
flags |= xe_vma_is_cpu_addr_mirror(old) ?
2638
-
VMA_CREATE_FLAG_IS_SYSTEM_ALLOCATOR : 0;
2639
-
2640
+
flags |= op->base.remap.unmap->va->flags & XE_VMA_CREATE_MASK;
2640
2641
if (op->base.remap.prev) {
2641
2642
vma = new_vma(vm, op->base.remap.prev,
2642
2643
&old->attr, flags);
···
3256
3279
DRM_XE_VM_BIND_FLAG_NULL | \
3257
3280
DRM_XE_VM_BIND_FLAG_DUMPABLE | \
3258
3281
DRM_XE_VM_BIND_FLAG_CHECK_PXP | \
3259
-
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR)
3282
+
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR | \
3283
+
DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET)
3260
3284
3261
3285
#ifdef TEST_VM_OPS_ERROR
3262
3286
#define SUPPORTED_FLAGS (SUPPORTED_FLAGS_STUB | FORCE_OP_ERROR)
···
3372
3394
XE_IOCTL_DBG(xe, (prefetch_region != DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC &&
3373
3395
!(BIT(prefetch_region) & xe->info.mem_region_mask))) ||
3374
3396
XE_IOCTL_DBG(xe, obj &&
3375
-
op == DRM_XE_VM_BIND_OP_UNMAP)) {
3397
+
op == DRM_XE_VM_BIND_OP_UNMAP) ||
3398
+
XE_IOCTL_DBG(xe, (flags & DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET) &&
3399
+
(!is_cpu_addr_mirror || op != DRM_XE_VM_BIND_OP_MAP))) {
3376
3400
err = -EINVAL;
3377
3401
goto free_bind_ops;
3378
3402
}
···
4192
4212
struct xe_vma_ops vops;
4193
4213
struct drm_gpuva_ops *ops = NULL;
4194
4214
struct drm_gpuva_op *__op;
4195
-
bool is_cpu_addr_mirror = false;
4215
+
unsigned int vma_flags = 0;
4196
4216
bool remap_op = false;
4197
4217
struct xe_vma_mem_attr tmp_attr;
4198
4218
u16 default_pat;
···
4222
4242
vma = gpuva_to_vma(op->base.unmap.va);
4223
4243
XE_WARN_ON(!xe_vma_has_default_mem_attrs(vma));
4224
4244
default_pat = vma->attr.default_pat_index;
4245
+
vma_flags = vma->gpuva.flags;
4225
4246
}
4226
4247
4227
4248
if (__op->op == DRM_GPUVA_OP_REMAP) {
4228
4249
vma = gpuva_to_vma(op->base.remap.unmap->va);
4229
4250
default_pat = vma->attr.default_pat_index;
4251
+
vma_flags = vma->gpuva.flags;
4230
4252
}
4231
4253
4232
4254
if (__op->op == DRM_GPUVA_OP_MAP) {
4233
-
op->map.is_cpu_addr_mirror = true;
4255
+
op->map.vma_flags |= vma_flags & XE_VMA_CREATE_MASK;
4234
4256
op->map.pat_index = default_pat;
4235
4257
}
4236
4258
} else {
···
4241
4259
xe_assert(vm->xe, !remap_op);
4242
4260
xe_assert(vm->xe, xe_vma_has_no_bo(vma));
4243
4261
remap_op = true;
4244
-
4245
-
if (xe_vma_is_cpu_addr_mirror(vma))
4246
-
is_cpu_addr_mirror = true;
4247
-
else
4248
-
is_cpu_addr_mirror = false;
4262
+
vma_flags = vma->gpuva.flags;
4249
4263
}
4250
4264
4251
4265
if (__op->op == DRM_GPUVA_OP_MAP) {
···
4250
4272
/*
4251
4273
* In case of madvise ops DRM_GPUVA_OP_MAP is
4252
4274
* always after DRM_GPUVA_OP_REMAP, so ensure
4253
-
* we assign op->map.is_cpu_addr_mirror true
4254
-
* if REMAP is for xe_vma_is_cpu_addr_mirror vma
4275
+
* to propagate the flags from the vma we're
4276
+
* unmapping.
4255
4277
*/
4256
-
op->map.is_cpu_addr_mirror = is_cpu_addr_mirror;
4278
+
op->map.vma_flags |= vma_flags & XE_VMA_CREATE_MASK;
4257
4279
}
4258
4280
}
4259
4281
print_op(vm->xe, __op);
+2
-8
drivers/gpu/drm/xe/xe_vm_types.h
+2
-8
drivers/gpu/drm/xe/xe_vm_types.h
···
46
46
#define XE_VMA_PTE_COMPACT (DRM_GPUVA_USERBITS << 7)
47
47
#define XE_VMA_DUMPABLE (DRM_GPUVA_USERBITS << 8)
48
48
#define XE_VMA_SYSTEM_ALLOCATOR (DRM_GPUVA_USERBITS << 9)
49
+
#define XE_VMA_MADV_AUTORESET (DRM_GPUVA_USERBITS << 10)
49
50
50
51
/**
51
52
* struct xe_vma_mem_attr - memory attributes associated with vma
···
346
345
struct xe_vma_op_map {
347
346
/** @vma: VMA to map */
348
347
struct xe_vma *vma;
348
+
unsigned int vma_flags;
349
349
/** @immediate: Immediate bind */
350
350
bool immediate;
351
351
/** @read_only: Read only */
352
-
bool read_only;
353
-
/** @is_null: is NULL binding */
354
-
bool is_null;
355
-
/** @is_cpu_addr_mirror: is CPU address mirror binding */
356
-
bool is_cpu_addr_mirror;
357
-
/** @dumpable: whether BO is dumped on GPU hang */
358
-
bool dumpable;
359
-
/** @invalidate: invalidate the VMA before bind */
360
352
bool invalidate_on_bind;
361
353
/** @pat_index: The pat index to use for this operation. */
362
354
u16 pat_index;
+15
include/uapi/drm/xe_drm.h
+15
include/uapi/drm/xe_drm.h
···
1013
1013
* valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
1014
1014
* mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
1015
1015
* handle MBZ, and the BO offset MBZ.
1016
+
* - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
1017
+
* %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
1018
+
* CPU address space range is unmapped (typically with munmap(2) or brk(2)).
1019
+
* The madvise values set with &DRM_IOCTL_XE_MADVISE are reset to the values
1020
+
* that were present immediately after the &DRM_IOCTL_XE_VM_BIND.
1021
+
* The reset GPU virtual address range is the intersection of the range bound
1022
+
* using &DRM_IOCTL_XE_VM_BIND and the virtual CPU address space range
1023
+
* unmapped.
1024
+
* This functionality is present to mimic the behaviour of CPU address space
1025
+
* madvises set using madvise(2), which are typically reset on unmap.
1026
+
* Note: free(3) may or may not call munmap(2) and/or brk(2), and may thus
1027
+
* not invoke autoreset. Neither will stack variables going out of scope.
1028
+
* Therefore it's recommended to always explicitly reset the madvises when
1029
+
* freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
1016
1030
*
1017
1031
* The @prefetch_mem_region_instance for %DRM_XE_VM_BIND_OP_PREFETCH can also be:
1018
1032
* - %DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC, which ensures prefetching occurs in
···
1133
1119
#define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3)
1134
1120
#define DRM_XE_VM_BIND_FLAG_CHECK_PXP (1 << 4)
1135
1121
#define DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR (1 << 5)
1122
+
#define DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET (1 << 6)
1136
1123
/** @flags: Bind flags */
1137
1124
__u32 flags;
1138
1125