tjh.dev / kernel
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register

In a subsequent patch, the registration callback will need more parameters
from cpg_mssr_priv (like another base address with clock controllers
with double register block, and also, notifiers and rmw_lock).
Instead of adding more parameters, move the needed parameters to a public
sub-struct.
Instead moving clks to this structure, which would have implied to add
an allocation (and cleanup) for it, keep the way the allocation is done
and just have a copy of the pointer in the public structure.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Link: https://lore.kernel.org/20250515141828.43444-5-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Thierry Bultel and committed by
Geert Uytterhoeven 3d37ca14 a68ea80f

+88 -71
+4 -3
drivers/clk/renesas/r7s9210-cpg-mssr.c
··· 159 159 160 160 static struct clk * __init rza2_cpg_clk_register(struct device *dev, 161 161 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 162 - struct clk **clks, void __iomem *base, 163 - struct raw_notifier_head *notifiers) 162 + struct cpg_mssr_pub *pub) 164 163 { 165 - struct clk *parent; 164 + void __iomem *base = pub->base0; 165 + struct clk **clks = pub->clks; 166 166 unsigned int mult = 1; 167 167 unsigned int div = 1; 168 + struct clk *parent; 168 169 169 170 parent = clks[core->parent]; 170 171 if (IS_ERR(parent))
+4 -4
drivers/clk/renesas/r8a77970-cpg-mssr.c
··· 219 219 220 220 static struct clk * __init r8a77970_cpg_clk_register(struct device *dev, 221 221 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 222 - struct clk **clks, void __iomem *base, 223 - struct raw_notifier_head *notifiers) 222 + struct cpg_mssr_pub *pub) 224 223 { 225 224 const struct clk_div_table *table; 225 + void __iomem *base = pub->base0; 226 + struct clk **clks = pub->clks; 226 227 const struct clk *parent; 227 228 unsigned int shift; 228 229 ··· 237 236 shift = 4; 238 237 break; 239 238 default: 240 - return rcar_gen3_cpg_clk_register(dev, core, info, clks, base, 241 - notifiers); 239 + return rcar_gen3_cpg_clk_register(dev, core, info, pub); 242 240 } 243 241 244 242 parent = clks[core->parent];
+3 -2
drivers/clk/renesas/rcar-gen2-cpg.c
··· 274 274 275 275 struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, 276 276 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 277 - struct clk **clks, void __iomem *base, 278 - struct raw_notifier_head *notifiers) 277 + struct cpg_mssr_pub *pub) 279 278 { 280 279 const struct clk_div_table *table = NULL; 280 + void __iomem *base = pub->base0; 281 + struct clk **clks = pub->clks; 281 282 const struct clk *parent; 282 283 const char *parent_name; 283 284 unsigned int mult = 1;
+1 -2
drivers/clk/renesas/rcar-gen2-cpg.h
··· 32 32 33 33 struct clk *rcar_gen2_cpg_clk_register(struct device *dev, 34 34 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 35 - struct clk **clks, void __iomem *base, 36 - struct raw_notifier_head *notifiers); 35 + struct cpg_mssr_pub *pub); 37 36 int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, 38 37 unsigned int pll0_div, u32 mode); 39 38
+4 -2
drivers/clk/renesas/rcar-gen3-cpg.c
··· 345 345 346 346 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 347 347 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 348 - struct clk **clks, void __iomem *base, 349 - struct raw_notifier_head *notifiers) 348 + struct cpg_mssr_pub *pub) 350 349 { 350 + struct raw_notifier_head *notifiers = &pub->notifiers; 351 + void __iomem *base = pub->base0; 352 + struct clk **clks = pub->clks; 351 353 const struct clk *parent; 352 354 unsigned int mult = 1; 353 355 unsigned int div = 1;
+1 -2
drivers/clk/renesas/rcar-gen3-cpg.h
··· 81 81 82 82 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 83 83 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 84 - struct clk **clks, void __iomem *base, 85 - struct raw_notifier_head *notifiers); 84 + struct cpg_mssr_pub *pub); 86 85 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 87 86 unsigned int clk_extalr, u32 mode); 88 87
+4 -2
drivers/clk/renesas/rcar-gen4-cpg.c
··· 418 418 419 419 struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev, 420 420 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 421 - struct clk **clks, void __iomem *base, 422 - struct raw_notifier_head *notifiers) 421 + struct cpg_mssr_pub *pub) 423 422 { 423 + struct raw_notifier_head *notifiers = &pub->notifiers; 424 + void __iomem *base = pub->base0; 425 + struct clk **clks = pub->clks; 424 426 const struct clk *parent; 425 427 unsigned int mult = 1; 426 428 unsigned int div = 1;
+1 -2
drivers/clk/renesas/rcar-gen4-cpg.h
··· 78 78 79 79 struct clk *rcar_gen4_cpg_clk_register(struct device *dev, 80 80 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 81 - struct clk **clks, void __iomem *base, 82 - struct raw_notifier_head *notifiers); 81 + struct cpg_mssr_pub *pub); 83 82 int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config, 84 83 unsigned int clk_extalr, u32 mode); 85 84
+48 -50
drivers/clk/renesas/renesas-cpg-mssr.c
··· 126 126 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby 127 127 * and Software Reset Private Data 128 128 * 129 + * @pub: Data passed to clock registration callback 129 130 * @rcdev: Optional reset controller entity 130 131 * @dev: CPG/MSSR device 131 - * @base: CPG/MSSR register block base address 132 132 * @reg_layout: CPG/MSSR register layout 133 - * @rmw_lock: protects RMW register accesses 134 133 * @np: Device node in DT for this CPG/MSSR module 135 134 * @num_core_clks: Number of Core Clocks in clks[] 136 135 * @num_mod_clks: Number of Module Clocks in clks[] 137 136 * @last_dt_core_clk: ID of the last Core Clock exported to DT 138 - * @notifiers: Notifier chain to save/restore clock state for system resume 139 137 * @status_regs: Pointer to status registers array 140 138 * @control_regs: Pointer to control registers array 141 139 * @reset_regs: Pointer to reset registers array ··· 145 147 * @clks: Array containing all Core and Module Clocks 146 148 */ 147 149 struct cpg_mssr_priv { 150 + struct cpg_mssr_pub pub; 148 151 #ifdef CONFIG_RESET_CONTROLLER 149 152 struct reset_controller_dev rcdev; 150 153 #endif 151 154 struct device *dev; 152 - void __iomem *base; 153 155 enum clk_reg_layout reg_layout; 154 - spinlock_t rmw_lock; 155 156 struct device_node *np; 156 157 157 158 unsigned int num_core_clks; 158 159 unsigned int num_mod_clks; 159 160 unsigned int last_dt_core_clk; 160 161 161 - struct raw_notifier_head notifiers; 162 162 const u16 *status_regs; 163 163 const u16 *control_regs; 164 164 const u16 *reset_regs; ··· 202 206 203 207 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 204 208 str_on_off(enable)); 205 - spin_lock_irqsave(&priv->rmw_lock, flags); 209 + spin_lock_irqsave(&priv->pub.rmw_lock, flags); 206 210 207 211 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 208 - value = readb(priv->base + priv->control_regs[reg]); 212 + value = readb(priv->pub.base0 + priv->control_regs[reg]); 209 213 if (enable) 210 214 value &= ~bitmask; 211 215 else 212 216 value |= bitmask; 213 - writeb(value, priv->base + priv->control_regs[reg]); 217 + writeb(value, priv->pub.base0 + priv->control_regs[reg]); 214 218 215 219 /* dummy read to ensure write has completed */ 216 - readb(priv->base + priv->control_regs[reg]); 217 - barrier_data(priv->base + priv->control_regs[reg]); 220 + readb(priv->pub.base0 + priv->control_regs[reg]); 221 + barrier_data(priv->pub.base0 + priv->control_regs[reg]); 222 + 218 223 } else { 219 - value = readl(priv->base + priv->control_regs[reg]); 224 + value = readl(priv->pub.base0 + priv->control_regs[reg]); 220 225 if (enable) 221 226 value &= ~bitmask; 222 227 else 223 228 value |= bitmask; 224 - writel(value, priv->base + priv->control_regs[reg]); 229 + writel(value, priv->pub.base0 + priv->control_regs[reg]); 225 230 } 226 231 227 - spin_unlock_irqrestore(&priv->rmw_lock, flags); 232 + spin_unlock_irqrestore(&priv->pub.rmw_lock, flags); 228 233 229 234 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 230 235 return 0; 231 236 232 - error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 237 + error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], 233 238 value, !(value & bitmask), 0, 10); 234 239 if (error) 235 240 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 236 - priv->base + priv->control_regs[reg], bit); 241 + priv->pub.base0 + priv->control_regs[reg], bit); 237 242 238 243 return error; 239 244 } ··· 253 256 { 254 257 struct mstp_clock *clock = to_mstp_clock(hw); 255 258 struct cpg_mssr_priv *priv = clock->priv; 259 + unsigned int reg = clock->index / 32; 256 260 u32 value; 257 261 258 262 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 259 - value = readb(priv->base + priv->control_regs[clock->index / 32]); 263 + value = readb(priv->pub.base0 + priv->control_regs[reg]); 260 264 else 261 - value = readl(priv->base + priv->status_regs[clock->index / 32]); 265 + value = readl(priv->pub.base0 + priv->status_regs[reg]); 262 266 263 267 return !(value & BIT(clock->index % 32)); 264 268 } ··· 346 348 case CLK_TYPE_DIV6P1: 347 349 case CLK_TYPE_DIV6_RO: 348 350 WARN_DEBUG(core->parent >= priv->num_core_clks); 349 - parent = priv->clks[core->parent]; 351 + parent = priv->pub.clks[core->parent]; 350 352 if (IS_ERR(parent)) { 351 353 clk = parent; 352 354 goto fail; ··· 356 358 357 359 if (core->type == CLK_TYPE_DIV6_RO) 358 360 /* Multiply with the DIV6 register value */ 359 - div *= (readl(priv->base + core->offset) & 0x3f) + 1; 361 + div *= (readl(priv->pub.base0 + core->offset) & 0x3f) + 1; 360 362 361 363 if (core->type == CLK_TYPE_DIV6P1) { 362 364 clk = cpg_div6_register(core->name, 1, &parent_name, 363 - priv->base + core->offset, 364 - &priv->notifiers); 365 + priv->pub.base0 + core->offset, 366 + &priv->pub.notifiers); 365 367 } else { 366 368 clk = clk_register_fixed_factor(NULL, core->name, 367 369 parent_name, 0, ··· 377 379 default: 378 380 if (info->cpg_clk_register) 379 381 clk = info->cpg_clk_register(dev, core, info, 380 - priv->clks, priv->base, 381 - &priv->notifiers); 382 + &priv->pub); 382 383 else 383 384 dev_err(dev, "%s has unsupported core clock type %u\n", 384 385 core->name, core->type); ··· 388 391 goto fail; 389 392 390 393 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 391 - priv->clks[id] = clk; 394 + priv->pub.clks[id] = clk; 392 395 return; 393 396 394 397 fail: ··· 411 414 WARN_DEBUG(id < priv->num_core_clks); 412 415 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 413 416 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 414 - WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 417 + WARN_DEBUG(PTR_ERR(priv->pub.clks[id]) != -ENOENT); 415 418 416 419 if (!mod->name) { 417 420 /* Skip NULLified clock */ 418 421 return; 419 422 } 420 423 421 - parent = priv->clks[mod->parent]; 424 + parent = priv->pub.clks[mod->parent]; 422 425 if (IS_ERR(parent)) { 423 426 clk = parent; 424 427 goto fail; ··· 620 623 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 621 624 622 625 /* Reset module */ 623 - writel(bitmask, priv->base + priv->reset_regs[reg]); 626 + writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]); 624 627 625 628 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 626 629 udelay(35); 627 630 628 631 /* Release module from reset state */ 629 - writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 632 + writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]); 630 633 631 634 return 0; 632 635 } ··· 640 643 641 644 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 642 645 643 - writel(bitmask, priv->base + priv->reset_regs[reg]); 646 + writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]); 644 647 return 0; 645 648 } 646 649 ··· 654 657 655 658 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 656 659 657 - writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 660 + writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]); 658 661 return 0; 659 662 } 660 663 ··· 666 669 unsigned int bit = id % 32; 667 670 u32 bitmask = BIT(bit); 668 671 669 - return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); 672 + return !!(readl(priv->pub.base0 + priv->reset_regs[reg]) & bitmask); 670 673 } 671 674 672 675 static const struct reset_control_ops cpg_mssr_reset_ops = { ··· 892 895 if (priv->smstpcr_saved[reg].mask) 893 896 priv->smstpcr_saved[reg].val = 894 897 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? 895 - readb(priv->base + priv->control_regs[reg]) : 896 - readl(priv->base + priv->control_regs[reg]); 898 + readb(priv->pub.base0 + priv->control_regs[reg]) : 899 + readl(priv->pub.base0 + priv->control_regs[reg]); 897 900 } 898 901 899 902 /* Save core clocks */ 900 - raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 903 + raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_SUSPEND, NULL); 901 904 902 905 return 0; 903 906 } ··· 914 917 return 0; 915 918 916 919 /* Restore core clocks */ 917 - raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 920 + raw_notifier_call_chain(&priv->pub.notifiers, PM_EVENT_RESUME, NULL); 918 921 919 922 /* Restore module clocks */ 920 923 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { ··· 923 926 continue; 924 927 925 928 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 926 - oldval = readb(priv->base + priv->control_regs[reg]); 929 + oldval = readb(priv->pub.base0 + priv->control_regs[reg]); 927 930 else 928 - oldval = readl(priv->base + priv->control_regs[reg]); 931 + oldval = readl(priv->pub.base0 + priv->control_regs[reg]); 929 932 newval = oldval & ~mask; 930 933 newval |= priv->smstpcr_saved[reg].val & mask; 931 934 if (newval == oldval) 932 935 continue; 933 936 934 937 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 935 - writeb(newval, priv->base + priv->control_regs[reg]); 938 + writeb(newval, priv->pub.base0 + priv->control_regs[reg]); 936 939 /* dummy read to ensure write has completed */ 937 - readb(priv->base + priv->control_regs[reg]); 938 - barrier_data(priv->base + priv->control_regs[reg]); 940 + readb(priv->pub.base0 + priv->control_regs[reg]); 941 + barrier_data(priv->pub.base0 + priv->control_regs[reg]); 939 942 continue; 940 943 } else 941 - writel(newval, priv->base + priv->control_regs[reg]); 944 + writel(newval, priv->pub.base0 + priv->control_regs[reg]); 942 945 943 946 /* Wait until enabled clocks are really enabled */ 944 947 mask &= ~priv->smstpcr_saved[reg].val; 945 948 if (!mask) 946 949 continue; 947 950 948 - error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 951 + error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg], 949 952 oldval, !(oldval & mask), 0, 10); 950 953 if (error) 951 954 dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg, ··· 1055 1058 if (!priv) 1056 1059 return -ENOMEM; 1057 1060 1061 + priv->pub.clks = priv->clks; 1058 1062 priv->np = np; 1059 1063 priv->dev = dev; 1060 - spin_lock_init(&priv->rmw_lock); 1064 + spin_lock_init(&priv->pub.rmw_lock); 1061 1065 1062 - priv->base = of_iomap(np, 0); 1063 - if (!priv->base) { 1066 + priv->pub.base0 = of_iomap(np, 0); 1067 + if (!priv->pub.base0) { 1064 1068 error = -ENOMEM; 1065 1069 goto out_err; 1066 1070 } ··· 1069 1071 priv->num_core_clks = info->num_total_core_clks; 1070 1072 priv->num_mod_clks = info->num_hw_mod_clks; 1071 1073 priv->last_dt_core_clk = info->last_dt_core_clk; 1072 - RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 1074 + RAW_INIT_NOTIFIER_HEAD(&priv->pub.notifiers); 1073 1075 priv->reg_layout = info->reg_layout; 1074 1076 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { 1075 1077 priv->status_regs = mstpsr; ··· 1089 1091 } 1090 1092 1091 1093 for (i = 0; i < nclks; i++) 1092 - priv->clks[i] = ERR_PTR(-ENOENT); 1094 + priv->pub.clks[i] = ERR_PTR(-ENOENT); 1093 1095 1094 1096 error = cpg_mssr_reserved_init(priv, info); 1095 1097 if (error) ··· 1106 1108 reserve_err: 1107 1109 cpg_mssr_reserved_exit(priv); 1108 1110 out_err: 1109 - if (priv->base) 1110 - iounmap(priv->base); 1111 + if (priv->pub.base0) 1112 + iounmap(priv->pub.base0); 1111 1113 kfree(priv); 1112 1114 1113 1115 return error;
+18 -2
drivers/clk/renesas/renesas-cpg-mssr.h
··· 8 8 #ifndef __CLK_RENESAS_CPG_MSSR_H__ 9 9 #define __CLK_RENESAS_CPG_MSSR_H__ 10 10 11 + #include <linux/notifier.h> 12 + 11 13 /* 12 14 * Definitions of CPG Core Clocks 13 15 * ··· 29 27 unsigned int div; 30 28 unsigned int mult; 31 29 unsigned int offset; 30 + }; 31 + 32 + /** 33 + * struct cpg_mssr_pub - data shared with device-specific clk registration code 34 + * 35 + * @base0: CPG/MSSR register block base0 address 36 + * @notifiers: Notifier chain to save/restore clock state for system resume 37 + * @rmw_lock: protects RMW register accesses 38 + * @clks: pointer to clocks 39 + */ 40 + struct cpg_mssr_pub { 41 + void __iomem *base0; 42 + struct raw_notifier_head notifiers; 43 + spinlock_t rmw_lock; 44 + struct clk **clks; 32 45 }; 33 46 34 47 enum clk_types { ··· 170 153 struct clk *(*cpg_clk_register)(struct device *dev, 171 154 const struct cpg_core_clk *core, 172 155 const struct cpg_mssr_info *info, 173 - struct clk **clks, void __iomem *base, 174 - struct raw_notifier_head *notifiers); 156 + struct cpg_mssr_pub *pub); 175 157 }; 176 158 177 159 extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;