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clk: renesas: rzg2l: Move pointers after hw member

Reorder the pointer members in struct mstp_clock so they appear immediately
after the hw member. This helps avoid potential padding and eliminates the
need for any calculations in the to_mod_clock() macro. As struct clk_hw
currently contains only pointers, placing it first also avoids padding.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250514090415.4098534-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Claudiu Beznea and committed by
Geert Uytterhoeven a68ea80f 2f96afdf

+4 -4
+4 -4
drivers/clk/renesas/rzg2l-cpg.c
··· 1185 1185 * struct mstp_clock - MSTP gating clock 1186 1186 * 1187 1187 * @hw: handle between common and hardware-specific interfaces 1188 + * @priv: CPG/MSTP private data 1189 + * @sibling: pointer to the other coupled clock 1188 1190 * @off: register offset 1189 1191 * @bit: ON/MON bit 1190 1192 * @enabled: soft state of the clock, if it is coupled with another clock 1191 - * @priv: CPG/MSTP private data 1192 - * @sibling: pointer to the other coupled clock 1193 1193 */ 1194 1194 struct mstp_clock { 1195 1195 struct clk_hw hw; 1196 + struct rzg2l_cpg_priv *priv; 1197 + struct mstp_clock *sibling; 1196 1198 u16 off; 1197 1199 u8 bit; 1198 1200 bool enabled; 1199 - struct rzg2l_cpg_priv *priv; 1200 - struct mstp_clock *sibling; 1201 1201 }; 1202 1202 1203 1203 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)