Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mips: pci-mt7620: fix bridge register access
Host bridge registers and PCI RC control registers have different
memory base. pcie_m32() is used to write the RC control registers
instead of bridge registers. This patch introduces bridge_m32()
and use it to operate bridge registers to fix the access issue.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
authored by
Shiji Yang
and committed by
Thomas Bogendoerfer
3dbb0827
c7dd395d
+12
-3
+12
-3
arch/mips/pci/pci-mt7620.c
+12
-3
arch/mips/pci/pci-mt7620.c
···
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return ioread32(bridge_base + reg);
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}
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+
static inline void bridge_m32(u32 clr, u32 set, unsigned reg)
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+
{
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u32 val = bridge_r32(reg);
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+
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val &= ~clr;
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val |= set;
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bridge_w32(val, reg);
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}
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+
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static inline void pcie_w32(u32 val, unsigned reg)
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{
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iowrite32(val, pcie_base + reg);
···
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pcie_phy(0x68, 0xB4);
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/* put core into reset */
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-
pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
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+
bridge_m32(PCIRST, PCIRST, RALINK_PCI_PCICFG_ADDR);
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reset_control_assert(rstpcie0);
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/* disable power and all clocks */
···
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mdelay(50);
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/* enable write access */
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-
pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
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+
bridge_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
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mdelay(100);
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/* check if there is a card present */
···
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pcie_w32(0x06040001, RALINK_PCI0_CLASS);
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/* enable interrupts */
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-
pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
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+
bridge_m32(PCIINT2, PCIINT2, RALINK_PCI_PCIENA);
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/* voodoo from the SDK driver */
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pci_config_read(NULL, 0, 4, 4, &val);