phy: qcom-qmp-ufs: cleanup the driver · tjh.dev/kernel@3e1865b

+12 -281

1 changed file

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drivers

phy

qualcomm

phy-qcom-qmp-ufs.c

+12 -281

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

··· 599 599 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 600 600 const struct qmp_phy_init_tbl *serdes_tbl; 601 601 int serdes_tbl_num; 602 - const struct qmp_phy_init_tbl *serdes_tbl_sec; 603 - int serdes_tbl_num_sec; 604 602 const struct qmp_phy_init_tbl *tx_tbl; 605 603 int tx_tbl_num; 606 - const struct qmp_phy_init_tbl *tx_tbl_sec; 607 - int tx_tbl_num_sec; 608 604 const struct qmp_phy_init_tbl *rx_tbl; 609 605 int rx_tbl_num; 610 - const struct qmp_phy_init_tbl *rx_tbl_sec; 611 - int rx_tbl_num_sec; 612 606 const struct qmp_phy_init_tbl *pcs_tbl; 613 607 int pcs_tbl_num; 614 - const struct qmp_phy_init_tbl *pcs_tbl_sec; 615 - int pcs_tbl_num_sec; 616 - const struct qmp_phy_init_tbl *pcs_misc_tbl; 617 - int pcs_misc_tbl_num; 618 - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 619 - int pcs_misc_tbl_num_sec; 620 - 621 - /* Init sequence for DP PHY block link rates */ 622 - const struct qmp_phy_init_tbl *serdes_tbl_rbr; 623 - int serdes_tbl_rbr_num; 624 - const struct qmp_phy_init_tbl *serdes_tbl_hbr; 625 - int serdes_tbl_hbr_num; 626 - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 627 - int serdes_tbl_hbr2_num; 628 - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 629 - int serdes_tbl_hbr3_num; 630 - 631 - /* DP PHY callbacks */ 632 - int (*configure_dp_phy)(struct qmp_phy *qphy); 633 - void (*configure_dp_tx)(struct qmp_phy *qphy); 634 - int (*calibrate_dp_phy)(struct qmp_phy *qphy); 635 - void (*dp_aux_init)(struct qmp_phy *qphy); 636 608 637 609 /* clock ids to be requested */ 638 610 const char * const *clk_list; 639 611 int num_clks; 640 - /* resets to be requested */ 641 - const char * const *reset_list; 642 - int num_resets; 643 612 /* regulators to be requested */ 644 613 const char * const *vreg_list; 645 614 int num_vregs; ··· 618 649 619 650 unsigned int start_ctrl; 620 651 unsigned int pwrdn_ctrl; 621 - unsigned int mask_com_pcs_ready; 622 652 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 623 653 unsigned int phy_status; 624 654 625 - /* true, if PHY has a separate PHY_COM control block */ 626 - bool has_phy_com_ctrl; 627 - /* true, if PHY has a reset for individual lanes */ 628 - bool has_lane_rst; 629 - /* true, if PHY needs delay after POWER_DOWN */ 630 - bool has_pwrdn_delay; 631 - /* power_down delay in usec */ 632 - int pwrdn_delay_min; 633 - int pwrdn_delay_max; 634 - 635 - /* true, if PHY has a separate DP_COM control block */ 636 - bool has_phy_dp_com_ctrl; 637 655 /* true, if PHY has secondary tx/rx lanes to be configured */ 638 656 bool is_dual_lane_phy; 639 657 640 658 /* true, if PCS block has no separate SW_RESET register */ 641 659 bool no_pcs_sw_reset; 642 - }; 643 - 644 - struct qmp_phy_combo_cfg { 645 - const struct qmp_phy_cfg *usb_cfg; 646 - const struct qmp_phy_cfg *dp_cfg; 647 660 }; 648 661 649 662 /** ··· 640 689 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 641 690 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 642 691 * @pcs_misc: iomapped memory space for lane's pcs_misc 643 - * @pipe_clk: pipe clock 644 692 * @index: lane index 645 693 * @qmp: QMP phy to which this lane belongs 646 - * @lane_rst: lane's reset controller 647 694 * @mode: current PHY mode 648 - * @dp_aux_cfg: Display port aux config 649 - * @dp_opts: Display port optional config 650 - * @dp_clks: Display port clocks 651 695 */ 652 696 struct qmp_phy { 653 697 struct phy *phy; ··· 654 708 void __iomem *tx2; 655 709 void __iomem *rx2; 656 710 void __iomem *pcs_misc; 657 - struct clk *pipe_clk; 658 711 unsigned int index; 659 712 struct qcom_qmp *qmp; 660 - struct reset_control *lane_rst; 661 713 enum phy_mode mode; 662 - unsigned int dp_aux_cfg; 663 - struct phy_configure_opts_dp dp_opts; 664 - struct qmp_phy_dp_clks *dp_clks; 665 - }; 666 - 667 - struct qmp_phy_dp_clks { 668 - struct qmp_phy *qphy; 669 - struct clk_hw dp_link_hw; 670 - struct clk_hw dp_pixel_hw; 671 714 }; 672 715 673 716 /** 674 717 * struct qcom_qmp - structure holding QMP phy block attributes 675 718 * 676 719 * @dev: device 677 - * @dp_com: iomapped memory space for phy's dp_com control block 678 720 * 679 721 * @clks: array of clocks required by phy 680 722 * @resets: array of resets required by phy ··· 675 741 */ 676 742 struct qcom_qmp { 677 743 struct device *dev; 678 - void __iomem *dp_com; 679 744 680 745 struct clk_bulk_data *clks; 681 - struct reset_control **resets; 682 746 struct regulator_bulk_data *vregs; 683 747 684 748 struct qmp_phy **phys; ··· 803 871 .start_ctrl = SERDES_START, 804 872 .pwrdn_ctrl = SW_PWRDN, 805 873 806 - .is_dual_lane_phy = false, 807 874 .no_pcs_sw_reset = true, 808 875 }; 809 876 ··· 914 983 915 984 static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy) 916 985 { 917 - struct qcom_qmp *qmp = qphy->qmp; 918 986 const struct qmp_phy_cfg *cfg = qphy->cfg; 919 987 void __iomem *serdes = qphy->serdes; 920 988 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 921 989 int serdes_tbl_num = cfg->serdes_tbl_num; 922 - int ret; 923 990 924 991 qcom_qmp_phy_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 925 - if (cfg->serdes_tbl_sec) 926 - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 927 - cfg->serdes_tbl_num_sec); 928 - 929 - if (cfg->has_phy_com_ctrl) { 930 - void __iomem *status; 931 - unsigned int mask, val; 932 - 933 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 934 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 935 - SERDES_START | PCS_START); 936 - 937 - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 938 - mask = cfg->mask_com_pcs_ready; 939 - 940 - ret = readl_poll_timeout(status, val, (val & mask), 10, 941 - PHY_INIT_COMPLETE_TIMEOUT); 942 - if (ret) { 943 - dev_err(qmp->dev, 944 - "phy common block init timed-out\n"); 945 - return ret; 946 - } 947 - } 948 992 949 993 return 0; 950 994 } ··· 928 1022 { 929 1023 struct qcom_qmp *qmp = qphy->qmp; 930 1024 const struct qmp_phy_cfg *cfg = qphy->cfg; 931 - void __iomem *serdes = qphy->serdes; 932 1025 void __iomem *pcs = qphy->pcs; 933 - void __iomem *dp_com = qmp->dp_com; 934 - int ret, i; 1026 + int ret; 935 1027 936 1028 mutex_lock(&qmp->phy_mutex); 937 1029 if (qmp->init_count++) { ··· 944 1040 goto err_unlock; 945 1041 } 946 1042 947 - for (i = 0; i < cfg->num_resets; i++) { 948 - ret = reset_control_assert(qmp->resets[i]); 949 - if (ret) { 950 - dev_err(qmp->dev, "%s reset assert failed\n", 951 - cfg->reset_list[i]); 952 - goto err_disable_regulators; 953 - } 954 - } 955 - 956 - for (i = cfg->num_resets - 1; i >= 0; i--) { 957 - ret = reset_control_deassert(qmp->resets[i]); 958 - if (ret) { 959 - dev_err(qmp->dev, "%s reset deassert failed\n", 960 - qphy->cfg->reset_list[i]); 961 - goto err_assert_reset; 962 - } 963 - } 964 - 965 1043 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 966 1044 if (ret) 967 - goto err_assert_reset; 1045 + goto err_disable_regulators; 968 1046 969 - if (cfg->has_phy_dp_com_ctrl) { 970 - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 971 - SW_PWRDN); 972 - /* override hardware control for reset of qmp phy */ 973 - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 974 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 975 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 976 - 977 - /* Default type-c orientation, i.e CC1 */ 978 - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 979 - 980 - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 981 - USB3_MODE | DP_MODE); 982 - 983 - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 984 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 985 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 986 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 987 - 988 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 989 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 990 - } 991 - 992 - if (cfg->has_phy_com_ctrl) { 993 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 994 - SW_PWRDN); 995 - } else { 996 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 997 - qphy_setbits(pcs, 998 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 999 - cfg->pwrdn_ctrl); 1000 - else 1001 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1002 - cfg->pwrdn_ctrl); 1003 - } 1047 + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1048 + qphy_setbits(pcs, 1049 + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1050 + cfg->pwrdn_ctrl); 1051 + else 1052 + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1053 + cfg->pwrdn_ctrl); 1004 1054 1005 1055 mutex_unlock(&qmp->phy_mutex); 1006 1056 1007 1057 return 0; 1008 1058 1009 - err_assert_reset: 1010 - while (++i < cfg->num_resets) 1011 - reset_control_assert(qmp->resets[i]); 1012 1059 err_disable_regulators: 1013 1060 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1014 1061 err_unlock: ··· 972 1117 { 973 1118 struct qcom_qmp *qmp = qphy->qmp; 974 1119 const struct qmp_phy_cfg *cfg = qphy->cfg; 975 - void __iomem *serdes = qphy->serdes; 976 - int i = cfg->num_resets; 977 1120 978 1121 mutex_lock(&qmp->phy_mutex); 979 1122 if (--qmp->init_count) { ··· 980 1127 } 981 1128 982 1129 reset_control_assert(qmp->ufs_reset); 983 - if (cfg->has_phy_com_ctrl) { 984 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 985 - SERDES_START | PCS_START); 986 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 987 - SW_RESET); 988 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 989 - SW_PWRDN); 990 - } 991 - 992 - while (--i >= 0) 993 - reset_control_assert(qmp->resets[i]); 994 1130 995 1131 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 996 1132 ··· 1040 1198 void __iomem *tx = qphy->tx; 1041 1199 void __iomem *rx = qphy->rx; 1042 1200 void __iomem *pcs = qphy->pcs; 1043 - void __iomem *pcs_misc = qphy->pcs_misc; 1044 1201 void __iomem *status; 1045 1202 unsigned int mask, val, ready; 1046 1203 int ret; 1047 1204 1048 1205 qcom_qmp_phy_ufs_serdes_init(qphy); 1049 1206 1050 - if (cfg->has_lane_rst) { 1051 - ret = reset_control_deassert(qphy->lane_rst); 1052 - if (ret) { 1053 - dev_err(qmp->dev, "lane%d reset deassert failed\n", 1054 - qphy->index); 1055 - return ret; 1056 - } 1057 - } 1058 - 1059 - ret = clk_prepare_enable(qphy->pipe_clk); 1060 - if (ret) { 1061 - dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1062 - goto err_reset_lane; 1063 - } 1064 - 1065 1207 /* Tx, Rx, and PCS configurations */ 1066 1208 qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, 1067 1209 cfg->tx_tbl, cfg->tx_tbl_num, 1); 1068 - if (cfg->tx_tbl_sec) 1069 - qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 1070 - cfg->tx_tbl_num_sec, 1); 1071 1210 1072 1211 /* Configuration for other LANE for USB-DP combo PHY */ 1073 1212 if (cfg->is_dual_lane_phy) { 1074 1213 qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, 1075 1214 cfg->tx_tbl, cfg->tx_tbl_num, 2); 1076 - if (cfg->tx_tbl_sec) 1077 - qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs, 1078 - cfg->tx_tbl_sec, 1079 - cfg->tx_tbl_num_sec, 2); 1080 1215 } 1081 1216 1082 1217 qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, 1083 1218 cfg->rx_tbl, cfg->rx_tbl_num, 1); 1084 - if (cfg->rx_tbl_sec) 1085 - qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, 1086 - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 1087 1219 1088 1220 if (cfg->is_dual_lane_phy) { 1089 1221 qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, 1090 1222 cfg->rx_tbl, cfg->rx_tbl_num, 2); 1091 - if (cfg->rx_tbl_sec) 1092 - qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs, 1093 - cfg->rx_tbl_sec, 1094 - cfg->rx_tbl_num_sec, 2); 1095 1223 } 1096 1224 1097 1225 qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1098 - if (cfg->pcs_tbl_sec) 1099 - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 1100 - cfg->pcs_tbl_num_sec); 1101 1226 1102 1227 ret = reset_control_deassert(qmp->ufs_reset); 1103 1228 if (ret) 1104 - goto err_disable_pipe_clk; 1105 - 1106 - qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 1107 - cfg->pcs_misc_tbl_num); 1108 - if (cfg->pcs_misc_tbl_sec) 1109 - qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 1110 - cfg->pcs_misc_tbl_num_sec); 1111 - 1112 - if (cfg->has_pwrdn_delay) 1113 - usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1229 + return ret; 1114 1230 1115 1231 /* Pull PHY out of reset state */ 1116 1232 if (!cfg->no_pcs_sw_reset) ··· 1084 1284 PHY_INIT_COMPLETE_TIMEOUT); 1085 1285 if (ret) { 1086 1286 dev_err(qmp->dev, "phy initialization timed-out\n"); 1087 - goto err_disable_pipe_clk; 1287 + return ret; 1088 1288 } 1289 + 1089 1290 return 0; 1090 - 1091 - err_disable_pipe_clk: 1092 - clk_disable_unprepare(qphy->pipe_clk); 1093 - err_reset_lane: 1094 - if (cfg->has_lane_rst) 1095 - reset_control_assert(qphy->lane_rst); 1096 - 1097 - return ret; 1098 1291 } 1099 1292 1100 1293 static int qcom_qmp_phy_ufs_power_off(struct phy *phy) 1101 1294 { 1102 1295 struct qmp_phy *qphy = phy_get_drvdata(phy); 1103 1296 const struct qmp_phy_cfg *cfg = qphy->cfg; 1104 - 1105 - clk_disable_unprepare(qphy->pipe_clk); 1106 1297 1107 1298 /* PHY reset */ 1108 1299 if (!cfg->no_pcs_sw_reset) ··· 1117 1326 static int qcom_qmp_phy_ufs_exit(struct phy *phy) 1118 1327 { 1119 1328 struct qmp_phy *qphy = phy_get_drvdata(phy); 1120 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1121 - 1122 - if (cfg->has_lane_rst) 1123 - reset_control_assert(qphy->lane_rst); 1124 1329 1125 1330 qcom_qmp_phy_ufs_com_exit(qphy); 1126 1331 ··· 1174 1387 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1175 1388 } 1176 1389 1177 - static int qcom_qmp_phy_ufs_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 1178 - { 1179 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 1180 - int i; 1181 - 1182 - qmp->resets = devm_kcalloc(dev, cfg->num_resets, 1183 - sizeof(*qmp->resets), GFP_KERNEL); 1184 - if (!qmp->resets) 1185 - return -ENOMEM; 1186 - 1187 - for (i = 0; i < cfg->num_resets; i++) { 1188 - struct reset_control *rst; 1189 - const char *name = cfg->reset_list[i]; 1190 - 1191 - rst = devm_reset_control_get_exclusive(dev, name); 1192 - if (IS_ERR(rst)) { 1193 - dev_err(dev, "failed to get %s reset\n", name); 1194 - return PTR_ERR(rst); 1195 - } 1196 - qmp->resets[i] = rst; 1197 - } 1198 - 1199 - return 0; 1200 - } 1201 - 1202 1390 static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 1203 1391 { 1204 1392 struct qcom_qmp *qmp = dev_get_drvdata(dev); ··· 1197 1435 .owner = THIS_MODULE, 1198 1436 }; 1199 1437 1200 - static void qcom_qmp_reset_control_put(void *data) 1201 - { 1202 - reset_control_put(data); 1203 - } 1204 - 1205 1438 static 1206 1439 int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id, 1207 1440 void __iomem *serdes, const struct qmp_phy_cfg *cfg) ··· 1204 1447 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1205 1448 struct phy *generic_phy; 1206 1449 struct qmp_phy *qphy; 1207 - char prop_name[MAX_PROP_NAME]; 1208 1450 int ret; 1209 1451 1210 1452 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); ··· 1258 1502 1259 1503 if (!qphy->pcs_misc) 1260 1504 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1261 - 1262 - /* Get lane reset, if any */ 1263 - if (cfg->has_lane_rst) { 1264 - snprintf(prop_name, sizeof(prop_name), "lane%d", id); 1265 - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 1266 - if (IS_ERR(qphy->lane_rst)) { 1267 - dev_err(dev, "failed to get lane%d reset\n", id); 1268 - return PTR_ERR(qphy->lane_rst); 1269 - } 1270 - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 1271 - qphy->lane_rst); 1272 - if (ret) 1273 - return ret; 1274 - } 1275 1505 1276 1506 generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); 1277 1507 if (IS_ERR(generic_phy)) { ··· 1342 1600 if (IS_ERR(serdes)) 1343 1601 return PTR_ERR(serdes); 1344 1602 1345 - /* per PHY dp_com; if PHY has dp_com control block */ 1346 - if (cfg->has_phy_dp_com_ctrl) { 1347 - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 1348 - if (IS_ERR(qmp->dp_com)) 1349 - return PTR_ERR(qmp->dp_com); 1350 - } 1351 - 1352 1603 expected_phys = cfg->nlanes; 1353 1604 1354 1605 mutex_init(&qmp->phy_mutex); 1355 1606 1356 1607 ret = qcom_qmp_phy_ufs_clk_init(dev, cfg); 1357 - if (ret) 1358 - return ret; 1359 - 1360 - ret = qcom_qmp_phy_ufs_reset_init(dev, cfg); 1361 1608 if (ret) 1362 1609 return ret; 1363 1610

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