phy: qcom-qmp-pcie-msm8996: cleanup the driver

+41 -227

1 changed file

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drivers

phy

qualcomm

phy-qcom-qmp-pcie-msm8996.c

+41 -227

drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c

··· 266 266 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 267 267 int pcs_misc_tbl_num_sec; 268 268 269 - /* Init sequence for DP PHY block link rates */ 270 - const struct qmp_phy_init_tbl *serdes_tbl_rbr; 271 - int serdes_tbl_rbr_num; 272 - const struct qmp_phy_init_tbl *serdes_tbl_hbr; 273 - int serdes_tbl_hbr_num; 274 - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 275 - int serdes_tbl_hbr2_num; 276 - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 277 - int serdes_tbl_hbr3_num; 278 - 279 - /* DP PHY callbacks */ 280 - int (*configure_dp_phy)(struct qmp_phy *qphy); 281 - void (*configure_dp_tx)(struct qmp_phy *qphy); 282 - int (*calibrate_dp_phy)(struct qmp_phy *qphy); 283 - void (*dp_aux_init)(struct qmp_phy *qphy); 284 - 285 269 /* clock ids to be requested */ 286 270 const char * const *clk_list; 287 271 int num_clks; ··· 285 301 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 286 302 unsigned int phy_status; 287 303 288 - /* true, if PHY has a separate PHY_COM control block */ 289 - bool has_phy_com_ctrl; 290 - /* true, if PHY has a reset for individual lanes */ 291 - bool has_lane_rst; 292 304 /* true, if PHY needs delay after POWER_DOWN */ 293 305 bool has_pwrdn_delay; 294 306 /* power_down delay in usec */ 295 307 int pwrdn_delay_min; 296 308 int pwrdn_delay_max; 297 - 298 - /* true, if PHY has a separate DP_COM control block */ 299 - bool has_phy_dp_com_ctrl; 300 - /* true, if PHY has secondary tx/rx lanes to be configured */ 301 - bool is_dual_lane_phy; 302 - 303 - /* true, if PCS block has no separate SW_RESET register */ 304 - bool no_pcs_sw_reset; 305 - }; 306 - 307 - struct qmp_phy_combo_cfg { 308 - const struct qmp_phy_cfg *usb_cfg; 309 - const struct qmp_phy_cfg *dp_cfg; 310 309 }; 311 310 312 311 /** ··· 301 334 * @tx: iomapped memory space for lane's tx 302 335 * @rx: iomapped memory space for lane's rx 303 336 * @pcs: iomapped memory space for lane's pcs 304 - * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 305 - * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 306 337 * @pcs_misc: iomapped memory space for lane's pcs_misc 307 338 * @pipe_clk: pipe clock 308 339 * @index: lane index 309 340 * @qmp: QMP phy to which this lane belongs 310 341 * @lane_rst: lane's reset controller 311 342 * @mode: current PHY mode 312 - * @dp_aux_cfg: Display port aux config 313 - * @dp_opts: Display port optional config 314 - * @dp_clks: Display port clocks 315 343 */ 316 344 struct qmp_phy { 317 345 struct phy *phy; ··· 315 353 void __iomem *tx; 316 354 void __iomem *rx; 317 355 void __iomem *pcs; 318 - void __iomem *tx2; 319 - void __iomem *rx2; 320 356 void __iomem *pcs_misc; 321 357 struct clk *pipe_clk; 322 358 unsigned int index; 323 359 struct qcom_qmp *qmp; 324 360 struct reset_control *lane_rst; 325 361 enum phy_mode mode; 326 - unsigned int dp_aux_cfg; 327 - struct phy_configure_opts_dp dp_opts; 328 - struct qmp_phy_dp_clks *dp_clks; 329 - }; 330 - 331 - struct qmp_phy_dp_clks { 332 - struct qmp_phy *qphy; 333 - struct clk_hw dp_link_hw; 334 - struct clk_hw dp_pixel_hw; 335 362 }; 336 363 337 364 /** 338 365 * struct qcom_qmp - structure holding QMP phy block attributes 339 366 * 340 367 * @dev: device 341 - * @dp_com: iomapped memory space for phy's dp_com control block 342 368 * 343 369 * @clks: array of clocks required by phy 344 370 * @resets: array of resets required by phy ··· 335 385 * @phys: array of per-lane phy descriptors 336 386 * @phy_mutex: mutex lock for PHY common block initialization 337 387 * @init_count: phy common block initialization count 338 - * @ufs_reset: optional UFS PHY reset handle 339 388 */ 340 389 struct qcom_qmp { 341 390 struct device *dev; 342 - void __iomem *dp_com; 343 391 344 392 struct clk_bulk_data *clks; 345 393 struct reset_control **resets; ··· 347 399 348 400 struct mutex phy_mutex; 349 401 int init_count; 350 - 351 - struct reset_control *ufs_reset; 352 402 }; 353 403 354 404 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 413 467 .mask_com_pcs_ready = PCS_READY, 414 468 .phy_status = PHYSTATUS, 415 469 416 - .has_phy_com_ctrl = true, 417 - .has_lane_rst = true, 418 470 .has_pwrdn_delay = true, 419 471 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 420 472 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, ··· 456 512 void __iomem *serdes = qphy->serdes; 457 513 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 458 514 int serdes_tbl_num = cfg->serdes_tbl_num; 515 + void __iomem *status; 516 + unsigned int mask, val; 459 517 int ret; 460 518 461 519 qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); ··· 465 519 qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 466 520 cfg->serdes_tbl_num_sec); 467 521 468 - if (cfg->has_phy_com_ctrl) { 469 - void __iomem *status; 470 - unsigned int mask, val; 471 522 472 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 473 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 474 - SERDES_START | PCS_START); 523 + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 524 + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 525 + SERDES_START | PCS_START); 475 526 476 - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 477 - mask = cfg->mask_com_pcs_ready; 527 + status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 528 + mask = cfg->mask_com_pcs_ready; 478 529 479 - ret = readl_poll_timeout(status, val, (val & mask), 10, 480 - PHY_INIT_COMPLETE_TIMEOUT); 481 - if (ret) { 482 - dev_err(qmp->dev, 483 - "phy common block init timed-out\n"); 484 - return ret; 485 - } 530 + ret = readl_poll_timeout(status, val, (val & mask), 10, 531 + PHY_INIT_COMPLETE_TIMEOUT); 532 + if (ret) { 533 + dev_err(qmp->dev, 534 + "phy common block init timed-out\n"); 535 + return ret; 486 536 } 487 537 488 538 return 0; ··· 489 547 struct qcom_qmp *qmp = qphy->qmp; 490 548 const struct qmp_phy_cfg *cfg = qphy->cfg; 491 549 void __iomem *serdes = qphy->serdes; 492 - void __iomem *pcs = qphy->pcs; 493 - void __iomem *dp_com = qmp->dp_com; 494 550 int ret, i; 495 551 496 552 mutex_lock(&qmp->phy_mutex); ··· 526 586 if (ret) 527 587 goto err_assert_reset; 528 588 529 - if (cfg->has_phy_dp_com_ctrl) { 530 - qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 531 - SW_PWRDN); 532 - /* override hardware control for reset of qmp phy */ 533 - qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 534 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 535 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 536 - 537 - /* Default type-c orientation, i.e CC1 */ 538 - qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 539 - 540 - qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 541 - USB3_MODE | DP_MODE); 542 - 543 - /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 544 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 545 - SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 546 - SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 547 - 548 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 549 - qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 550 - } 551 - 552 - if (cfg->has_phy_com_ctrl) { 553 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 554 - SW_PWRDN); 555 - } else { 556 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 557 - qphy_setbits(pcs, 558 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 559 - cfg->pwrdn_ctrl); 560 - else 561 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 562 - cfg->pwrdn_ctrl); 563 - } 589 + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 590 + SW_PWRDN); 564 591 565 592 mutex_unlock(&qmp->phy_mutex); 566 593 ··· 557 650 return 0; 558 651 } 559 652 560 - reset_control_assert(qmp->ufs_reset); 561 - if (cfg->has_phy_com_ctrl) { 562 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 563 - SERDES_START | PCS_START); 564 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 565 - SW_RESET); 566 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 567 - SW_PWRDN); 568 - } 653 + qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 654 + SERDES_START | PCS_START); 655 + qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 656 + SW_RESET); 657 + qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 658 + SW_PWRDN); 569 659 570 660 while (--i >= 0) 571 661 reset_control_assert(qmp->resets[i]); ··· 580 676 { 581 677 struct qmp_phy *qphy = phy_get_drvdata(phy); 582 678 struct qcom_qmp *qmp = qphy->qmp; 583 - const struct qmp_phy_cfg *cfg = qphy->cfg; 584 679 int ret; 585 680 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 586 - 587 - if (cfg->no_pcs_sw_reset) { 588 - /* 589 - * Get UFS reset, which is delayed until now to avoid a 590 - * circular dependency where UFS needs its PHY, but the PHY 591 - * needs this UFS reset. 592 - */ 593 - if (!qmp->ufs_reset) { 594 - qmp->ufs_reset = 595 - devm_reset_control_get_exclusive(qmp->dev, 596 - "ufsphy"); 597 - 598 - if (IS_ERR(qmp->ufs_reset)) { 599 - ret = PTR_ERR(qmp->ufs_reset); 600 - dev_err(qmp->dev, 601 - "failed to get UFS reset: %d\n", 602 - ret); 603 - 604 - qmp->ufs_reset = NULL; 605 - return ret; 606 - } 607 - } 608 - 609 - ret = reset_control_assert(qmp->ufs_reset); 610 - if (ret) 611 - return ret; 612 - } 613 681 614 682 ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy); 615 683 if (ret) ··· 605 729 606 730 qcom_qmp_phy_pcie_msm8996_serdes_init(qphy); 607 731 608 - if (cfg->has_lane_rst) { 609 - ret = reset_control_deassert(qphy->lane_rst); 610 - if (ret) { 611 - dev_err(qmp->dev, "lane%d reset deassert failed\n", 612 - qphy->index); 613 - return ret; 614 - } 732 + ret = reset_control_deassert(qphy->lane_rst); 733 + if (ret) { 734 + dev_err(qmp->dev, "lane%d reset deassert failed\n", 735 + qphy->index); 736 + return ret; 615 737 } 616 738 617 739 ret = clk_prepare_enable(qphy->pipe_clk); ··· 625 751 qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 626 752 cfg->tx_tbl_num_sec, 1); 627 753 628 - /* Configuration for other LANE for USB-DP combo PHY */ 629 - if (cfg->is_dual_lane_phy) { 630 - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, 631 - cfg->tx_tbl, cfg->tx_tbl_num, 2); 632 - if (cfg->tx_tbl_sec) 633 - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs, 634 - cfg->tx_tbl_sec, 635 - cfg->tx_tbl_num_sec, 2); 636 - } 637 - 638 754 qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, 639 755 cfg->rx_tbl, cfg->rx_tbl_num, 1); 640 756 if (cfg->rx_tbl_sec) 641 757 qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs, 642 758 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 643 759 644 - if (cfg->is_dual_lane_phy) { 645 - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, 646 - cfg->rx_tbl, cfg->rx_tbl_num, 2); 647 - if (cfg->rx_tbl_sec) 648 - qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs, 649 - cfg->rx_tbl_sec, 650 - cfg->rx_tbl_num_sec, 2); 651 - } 652 - 653 760 qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 654 761 if (cfg->pcs_tbl_sec) 655 762 qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 656 763 cfg->pcs_tbl_num_sec); 657 - 658 - ret = reset_control_deassert(qmp->ufs_reset); 659 - if (ret) 660 - goto err_disable_pipe_clk; 661 764 662 765 qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 663 766 cfg->pcs_misc_tbl_num); ··· 652 801 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 653 802 654 803 /* Pull PHY out of reset state */ 655 - if (!cfg->no_pcs_sw_reset) 656 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 804 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 805 + 657 806 /* start SerDes and Phy-Coding-Sublayer */ 658 807 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 659 808 ··· 673 822 err_disable_pipe_clk: 674 823 clk_disable_unprepare(qphy->pipe_clk); 675 824 err_reset_lane: 676 - if (cfg->has_lane_rst) 677 - reset_control_assert(qphy->lane_rst); 825 + reset_control_assert(qphy->lane_rst); 678 826 679 827 return ret; 680 828 } ··· 686 836 clk_disable_unprepare(qphy->pipe_clk); 687 837 688 838 /* PHY reset */ 689 - if (!cfg->no_pcs_sw_reset) 690 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 839 + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 691 840 692 841 /* stop SerDes and Phy-Coding-Sublayer */ 693 842 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ··· 706 857 static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy) 707 858 { 708 859 struct qmp_phy *qphy = phy_get_drvdata(phy); 709 - const struct qmp_phy_cfg *cfg = qphy->cfg; 710 860 711 - if (cfg->has_lane_rst) 712 - reset_control_assert(qphy->lane_rst); 861 + reset_control_assert(qphy->lane_rst); 713 862 714 863 qcom_qmp_phy_pcie_msm8996_com_exit(qphy); 715 864 ··· 912 1065 if (!qphy->pcs) 913 1066 return -ENOMEM; 914 1067 915 - /* 916 - * If this is a dual-lane PHY, then there should be registers for the 917 - * second lane. Some old device trees did not specify this, so fall 918 - * back to old legacy behavior of assuming they can be reached at an 919 - * offset from the first lane. 920 - */ 921 - if (cfg->is_dual_lane_phy) { 922 - qphy->tx2 = of_iomap(np, 3); 923 - qphy->rx2 = of_iomap(np, 4); 924 - if (!qphy->tx2 || !qphy->rx2) { 925 - dev_warn(dev, 926 - "Underspecified device tree, falling back to legacy register regions\n"); 927 - 928 - /* In the old version, pcs_misc is at index 3. */ 929 - qphy->pcs_misc = qphy->tx2; 930 - qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; 931 - qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; 932 - 933 - } else { 934 - qphy->pcs_misc = of_iomap(np, 5); 935 - } 936 - 937 - } else { 938 - qphy->pcs_misc = of_iomap(np, 3); 939 - } 1068 + qphy->pcs_misc = of_iomap(np, 3); 940 1069 941 1070 if (!qphy->pcs_misc) 942 1071 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); ··· 940 1117 } 941 1118 942 1119 /* Get lane reset, if any */ 943 - if (cfg->has_lane_rst) { 944 - snprintf(prop_name, sizeof(prop_name), "lane%d", id); 945 - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 946 - if (IS_ERR(qphy->lane_rst)) { 947 - dev_err(dev, "failed to get lane%d reset\n", id); 948 - return PTR_ERR(qphy->lane_rst); 949 - } 950 - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 951 - qphy->lane_rst); 952 - if (ret) 953 - return ret; 1120 + snprintf(prop_name, sizeof(prop_name), "lane%d", id); 1121 + qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 1122 + if (IS_ERR(qphy->lane_rst)) { 1123 + dev_err(dev, "failed to get lane%d reset\n", id); 1124 + return PTR_ERR(qphy->lane_rst); 954 1125 } 1126 + ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 1127 + qphy->lane_rst); 1128 + if (ret) 1129 + return ret; 955 1130 956 1131 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops); 957 1132 if (IS_ERR(generic_phy)) { ··· 1003 1182 serdes = devm_platform_ioremap_resource(pdev, 0); 1004 1183 if (IS_ERR(serdes)) 1005 1184 return PTR_ERR(serdes); 1006 - 1007 - /* per PHY dp_com; if PHY has dp_com control block */ 1008 - if (cfg->has_phy_dp_com_ctrl) { 1009 - qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 1010 - if (IS_ERR(qmp->dp_com)) 1011 - return PTR_ERR(qmp->dp_com); 1012 - } 1013 1185 1014 1186 expected_phys = cfg->nlanes; 1015 1187

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