tjh.dev / kernel
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drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL

Continue migration to the MDSS-revision based checks and replace
DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655407/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-25-3b2085a07884@oss.qualcomm.com

Dmitry Baryshkov 3e6d0543 ca4f289e

+17 -23
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
··· 318 318 { 319 319 .name = "wb_2", .id = WB_2, 320 320 .base = 0x65000, .len = 0x2c8, 321 - .features = WB_SM8250_MASK, 321 + .features = WB_SDM845_MASK, 322 322 .format_list = wb2_formats_rgb_yuv, 323 323 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 324 324 .xin_id = 6,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 275 275 { 276 276 .name = "wb_2", .id = WB_2, 277 277 .base = 0x65000, .len = 0x2c8, 278 - .features = WB_SM8250_MASK, 278 + .features = WB_SDM845_MASK, 279 279 .format_list = wb2_formats_rgb_yuv, 280 280 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 281 281 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 281 281 { 282 282 .name = "wb_2", .id = WB_2, 283 283 .base = 0x65000, .len = 0x2c8, 284 - .features = WB_SM8250_MASK, 284 + .features = WB_SDM845_MASK, 285 285 .format_list = wb2_formats_rgb_yuv, 286 286 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 287 287 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
··· 241 241 { 242 242 .name = "wb_2", .id = WB_2, 243 243 .base = 0x65000, .len = 0x2c8, 244 - .features = WB_SM8250_MASK, 244 + .features = WB_SDM845_MASK, 245 245 .format_list = wb2_formats_rgb_yuv, 246 246 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 247 247 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
··· 154 154 { 155 155 .name = "wb_2", .id = WB_2, 156 156 .base = 0x65000, .len = 0x2c8, 157 - .features = WB_SM8250_MASK, 157 + .features = WB_SDM845_MASK, 158 158 .format_list = wb2_formats_rgb_yuv, 159 159 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 160 160 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
··· 133 133 { 134 134 .name = "wb_2", .id = WB_2, 135 135 .base = 0x65000, .len = 0x2c8, 136 - .features = WB_SM8250_MASK, 136 + .features = WB_SDM845_MASK, 137 137 .format_list = wb2_formats_rgb_yuv, 138 138 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 139 139 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 312 312 { 313 313 .name = "wb_2", .id = WB_2, 314 314 .base = 0x65000, .len = 0x2c8, 315 - .features = WB_SM8250_MASK, 315 + .features = WB_SDM845_MASK, 316 316 .format_list = wb2_formats_rgb_yuv, 317 317 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 318 318 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
··· 148 148 { 149 149 .name = "wb_2", .id = WB_2, 150 150 .base = 0x65000, .len = 0x2c8, 151 - .features = WB_SM8250_MASK, 151 + .features = WB_SDM845_MASK, 152 152 .format_list = wb2_formats_rgb_yuv, 153 153 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 154 154 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
··· 142 142 { 143 143 .name = "wb_2", .id = WB_2, 144 144 .base = 0x65000, .len = 0x2c8, 145 - .features = WB_SM8250_MASK, 145 + .features = WB_SDM845_MASK, 146 146 .format_list = wb2_formats_rgb_yuv, 147 147 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 148 148 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
··· 285 285 { 286 286 .name = "wb_2", .id = WB_2, 287 287 .base = 0x65000, .len = 0x2c8, 288 - .features = WB_SM8250_MASK, 288 + .features = WB_SDM845_MASK, 289 289 .format_list = wb2_formats_rgb_yuv, 290 290 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 291 291 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
··· 159 159 { 160 160 .name = "wb_2", .id = WB_2, 161 161 .base = 0x65000, .len = 0x2c8, 162 - .features = WB_SM8250_MASK, 162 + .features = WB_SDM845_MASK, 163 163 .format_list = wb2_formats_rgb_yuv, 164 164 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 165 165 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
··· 298 298 { 299 299 .name = "wb_2", .id = WB_2, 300 300 .base = 0x65000, .len = 0x2c8, 301 - .features = WB_SM8250_MASK, 301 + .features = WB_SDM845_MASK, 302 302 .format_list = wb2_formats_rgb_yuv, 303 303 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 304 304 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
··· 305 305 { 306 306 .name = "wb_2", .id = WB_2, 307 307 .base = 0x65000, .len = 0x2c8, 308 - .features = WB_SM8250_MASK, 308 + .features = WB_SDM845_MASK, 309 309 .format_list = wb2_formats_rgb_yuv, 310 310 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 311 311 .clk_ctrl = DPU_CLK_CTRL_WB2,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
··· 294 294 { 295 295 .name = "wb_2", .id = WB_2, 296 296 .base = 0x65000, .len = 0x2c8, 297 - .features = WB_SM8250_MASK, 297 + .features = WB_SDM845_MASK, 298 298 .format_list = wb2_formats_rgb_yuv, 299 299 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 300 300 .xin_id = 6,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
··· 294 294 { 295 295 .name = "wb_2", .id = WB_2, 296 296 .base = 0x65000, .len = 0x2c8, 297 - .features = WB_SM8250_MASK, 297 + .features = WB_SDM845_MASK, 298 298 .format_list = wb2_formats_rgb_yuv, 299 299 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 300 300 .xin_id = 6,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
··· 294 294 { 295 295 .name = "wb_2", .id = WB_2, 296 296 .base = 0x65000, .len = 0x2c8, 297 - .features = WB_SM8250_MASK, 297 + .features = WB_SDM845_MASK, 298 298 .format_list = wb2_formats_rgb_yuv, 299 299 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 300 300 .xin_id = 6,
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 98 98 BIT(DPU_WB_QOS_8LVL) | \ 99 99 BIT(DPU_WB_CDP)) 100 100 101 - #define WB_SM8250_MASK (WB_SDM845_MASK | \ 102 - BIT(DPU_WB_INPUT_CTRL)) 103 - 104 101 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 105 102 #define DEFAULT_DPU_LINE_WIDTH 2048 106 103 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 140 140 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 141 141 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 142 142 * @DPU_WB_CDP Writeback supports client driven prefetch 143 - * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 144 - * data arrives. 145 143 * @DPU_WB_CROP CWB supports cropping 146 144 * @DPU_WB_MAX maximum value 147 145 */ ··· 153 155 DPU_WB_QOS, 154 156 DPU_WB_QOS_8LVL, 155 157 DPU_WB_CDP, 156 - DPU_WB_INPUT_CTRL, 157 158 DPU_WB_CROP, 158 159 DPU_WB_MAX 159 160 };
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
··· 208 208 if (test_bit(DPU_WB_CDP, &features)) 209 209 ops->setup_cdp = dpu_hw_wb_setup_cdp; 210 210 211 - if (test_bit(DPU_WB_INPUT_CTRL, &features)) 211 + if (mdss_rev->core_major_ver >= 5) 212 212 ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk; 213 213 214 214 if (mdss_rev->core_major_ver >= 9)