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drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL

Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655404/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-24-3b2085a07884@oss.qualcomm.com

authored by

Dmitry Baryshkov and committed by
Dmitry Baryshkov ca4f289e de723462

+8 -26
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 259 259 { 260 260 .name = "dsc_0", .id = DSC_0, 261 261 .base = 0x80000, .len = 0x140, 262 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 263 262 }, { 264 263 .name = "dsc_1", .id = DSC_1, 265 264 .base = 0x80400, .len = 0x140, 266 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 267 265 }, { 268 266 .name = "dsc_2", .id = DSC_2, 269 267 .base = 0x80800, .len = 0x140, 270 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 271 268 }, { 272 269 .name = "dsc_3", .id = DSC_3, 273 270 .base = 0x80c00, .len = 0x140, 274 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 275 271 }, 276 272 }; 277 273
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 259 259 { 260 260 .name = "dsc_0", .id = DSC_0, 261 261 .base = 0x80000, .len = 0x140, 262 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 263 262 }, { 264 263 .name = "dsc_1", .id = DSC_1, 265 264 .base = 0x80400, .len = 0x140, 266 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 267 265 }, { 268 266 .name = "dsc_2", .id = DSC_2, 269 267 .base = 0x80800, .len = 0x140, 270 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 271 268 }, { 272 269 .name = "dsc_3", .id = DSC_3, 273 270 .base = 0x80c00, .len = 0x140, 274 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 275 271 }, { 276 272 .name = "dsc_4", .id = DSC_4, 277 273 .base = 0x81000, .len = 0x140, 278 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 279 274 }, { 280 275 .name = "dsc_5", .id = DSC_5, 281 276 .base = 0x81400, .len = 0x140, 282 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 283 277 }, 284 278 }; 285 279
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
··· 193 193 { 194 194 .name = "dsc_0", .id = DSC_0, 195 195 .base = 0x80000, .len = 0x140, 196 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 197 196 }, { 198 197 .name = "dsc_1", .id = DSC_1, 199 198 .base = 0x80400, .len = 0x140, 200 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 201 199 }, 202 200 }; 203 201
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 258 258 { 259 259 .name = "dsc_0", .id = DSC_0, 260 260 .base = 0x80000, .len = 0x140, 261 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 262 261 }, { 263 262 .name = "dsc_1", .id = DSC_1, 264 263 .base = 0x80400, .len = 0x140, 265 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 266 264 }, { 267 265 .name = "dsc_2", .id = DSC_2, 268 266 .base = 0x80800, .len = 0x140, 269 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 270 267 }, { 271 268 .name = "dsc_3", .id = DSC_3, 272 269 .base = 0x80c00, .len = 0x140, 273 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 274 270 }, 275 271 }; 276 272
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
··· 135 135 { 136 136 .name = "dsc_0", .id = DSC_0, 137 137 .base = 0x80000, .len = 0x140, 138 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 139 138 }, 140 139 }; 141 140
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
··· 87 87 { 88 88 .name = "dsc_0", .id = DSC_0, 89 89 .base = 0x80000, .len = 0x140, 90 - .features = BIT(DPU_DSC_OUTPUT_CTRL), 91 90 }, 92 91 }; 93 92
+1 -4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 174 174 175 175 /** 176 176 * DSC sub-blocks/features 177 - * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets 178 - * the pixel output from this DSC. 179 177 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding 180 178 * @DPU_DSC_MAX 181 179 */ 182 180 enum { 183 - DPU_DSC_OUTPUT_CTRL = 0x1, 184 - DPU_DSC_NATIVE_42x_EN, 181 + DPU_DSC_NATIVE_42x_EN = 0x1, 185 182 DPU_DSC_MAX 186 183 }; 187 184
+4 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
··· 186 186 * @dev: Corresponding device for devres management 187 187 * @cfg: DSC catalog entry for which driver object is required 188 188 * @addr: Mapped register io address of MDP 189 + * @mdss_ver: dpu core's major and minor versions 189 190 * Return: Error code or allocated dpu_hw_dsc context 190 191 */ 191 192 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 192 193 const struct dpu_dsc_cfg *cfg, 193 - void __iomem *addr) 194 + void __iomem *addr, 195 + const struct dpu_mdss_version *mdss_ver) 194 196 { 195 197 struct dpu_hw_dsc *c; 196 198 ··· 209 207 c->ops.dsc_disable = dpu_hw_dsc_disable; 210 208 c->ops.dsc_config = dpu_hw_dsc_config; 211 209 c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh; 212 - if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL)) 210 + if (mdss_ver->core_major_ver >= 5) 213 211 c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; 214 212 215 213 return c;
+2 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
··· 64 64 65 65 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 66 66 const struct dpu_dsc_cfg *cfg, 67 - void __iomem *addr); 67 + void __iomem *addr, 68 + const struct dpu_mdss_version *mdss_ver); 68 69 69 70 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, 70 71 const struct dpu_dsc_cfg *cfg,
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
··· 171 171 if (cat->mdss_ver->core_major_ver >= 7) 172 172 hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio); 173 173 else 174 - hw = dpu_hw_dsc_init(dev, dsc, mmio); 174 + hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); 175 175 176 176 if (IS_ERR(hw)) { 177 177 rc = PTR_ERR(hw);