Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20230112204446.30236-2-quic_molvera@quicinc.com' into arm64-for-6.3
Merge DT binding in order to get GCC clock defines.
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Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
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Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
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maintainers:
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- Melody Olvera <quic_molvera@quicinc.com>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on QDU1000 and QRU1000
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See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
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properties:
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compatible:
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const: qcom,qdu1000-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: PCIE 0 Pipe clock source
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- description: PCIE 0 Phy Auxiliary clock source
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- description: USB3 Phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,qdu1000-gcc";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
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<&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>,
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<&usb3_phy_wrapper_pipe_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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include/dt-bindings/clock/qcom,qdu1000-gcc.h
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include/dt-bindings/clock/qcom,qdu1000-gcc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
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/* GCC clocks */
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#define GCC_GPLL0 0
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#define GCC_GPLL0_OUT_EVEN 1
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#define GCC_GPLL1 2
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#define GCC_GPLL2 3
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#define GCC_GPLL2_OUT_EVEN 4
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#define GCC_GPLL3 5
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#define GCC_GPLL4 6
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#define GCC_GPLL5 7
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#define GCC_GPLL5_OUT_EVEN 8
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#define GCC_GPLL6 9
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#define GCC_GPLL7 10
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#define GCC_GPLL8 11
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#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12
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#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13
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#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14
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#define GCC_BOOT_ROM_AHB_CLK 15
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#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
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#define GCC_DDRSS_ECPRI_DMA_CLK 18
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#define GCC_ECPRI_AHB_CLK 19
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#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20
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#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21
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#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22
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#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23
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#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24
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#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25
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#define GCC_ECPRI_XO_CLK 26
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#define GCC_ETH_DBG_SNOC_AXI_CLK 27
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#define GCC_GEMNOC_PCIE_QX_CLK 28
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#define GCC_GP1_CLK 29
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#define GCC_GP1_CLK_SRC 30
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#define GCC_GP2_CLK 31
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#define GCC_GP2_CLK_SRC 32
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#define GCC_GP3_CLK 33
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#define GCC_GP3_CLK_SRC 34
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#define GCC_PCIE_0_AUX_CLK 35
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#define GCC_PCIE_0_AUX_CLK_SRC 36
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#define GCC_PCIE_0_CFG_AHB_CLK 37
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#define GCC_PCIE_0_CLKREF_EN 38
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#define GCC_PCIE_0_MSTR_AXI_CLK 39
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#define GCC_PCIE_0_PHY_AUX_CLK 40
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#define GCC_PCIE_0_PHY_RCHNG_CLK 41
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42
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#define GCC_PCIE_0_PIPE_CLK 43
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#define GCC_PCIE_0_SLV_AXI_CLK 44
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
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#define GCC_PDM2_CLK 46
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#define GCC_PDM2_CLK_SRC 47
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#define GCC_PDM_AHB_CLK 48
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#define GCC_PDM_XO4_CLK 49
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#define GCC_QMIP_ANOC_PCIE_CLK 50
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#define GCC_QMIP_ECPRI_DMA0_CLK 51
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#define GCC_QMIP_ECPRI_DMA1_CLK 52
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#define GCC_QMIP_ECPRI_GSI_CLK 53
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54
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#define GCC_QUPV3_WRAP0_CORE_CLK 55
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#define GCC_QUPV3_WRAP0_S0_CLK 56
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57
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#define GCC_QUPV3_WRAP0_S1_CLK 58
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59
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#define GCC_QUPV3_WRAP0_S2_CLK 60
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61
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#define GCC_QUPV3_WRAP0_S3_CLK 62
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63
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#define GCC_QUPV3_WRAP0_S4_CLK 64
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65
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#define GCC_QUPV3_WRAP0_S5_CLK 66
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67
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#define GCC_QUPV3_WRAP0_S6_CLK 68
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69
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#define GCC_QUPV3_WRAP0_S7_CLK 70
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72
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#define GCC_QUPV3_WRAP1_CORE_CLK 73
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#define GCC_QUPV3_WRAP1_S0_CLK 74
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75
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#define GCC_QUPV3_WRAP1_S1_CLK 76
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77
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#define GCC_QUPV3_WRAP1_S2_CLK 78
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79
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#define GCC_QUPV3_WRAP1_S3_CLK 80
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81
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#define GCC_QUPV3_WRAP1_S4_CLK 82
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83
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#define GCC_QUPV3_WRAP1_S5_CLK 84
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85
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#define GCC_QUPV3_WRAP1_S6_CLK 86
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87
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#define GCC_QUPV3_WRAP1_S7_CLK 88
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93
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#define GCC_SDCC5_AHB_CLK 94
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#define GCC_SDCC5_APPS_CLK 95
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#define GCC_SDCC5_APPS_CLK_SRC 96
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#define GCC_SDCC5_ICE_CORE_CLK 97
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#define GCC_SDCC5_ICE_CORE_CLK_SRC 98
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#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99
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#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100
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#define GCC_SNOC_CNOC_PCIE_QX_CLK 101
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#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102
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#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103
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#define GCC_TSC_CFG_AHB_CLK 104
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#define GCC_TSC_CLK_SRC 105
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#define GCC_TSC_CNTR_CLK 106
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#define GCC_TSC_ETU_CLK 107
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#define GCC_USB2_CLKREF_EN 108
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#define GCC_USB30_PRIM_MASTER_CLK 109
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113
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#define GCC_USB30_PRIM_SLEEP_CLK 114
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#define GCC_USB3_PRIM_PHY_AUX_CLK 115
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
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#define GCC_SM_BUS_AHB_CLK 119
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#define GCC_SM_BUS_XO_CLK 120
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#define GCC_SM_BUS_XO_CLK_SRC 121
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122
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#define GCC_ETH_100G_C2C_HM_APB_CLK 123
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#define GCC_ETH_100G_FH_HM_APB_0_CLK 124
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#define GCC_ETH_100G_FH_HM_APB_1_CLK 125
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#define GCC_ETH_100G_FH_HM_APB_2_CLK 126
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#define GCC_ETH_DBG_C2C_HM_APB_CLK 127
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#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128
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#define GCC_PCIE_0_PIPE_CLK_SRC 129
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#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130
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/* GCC resets */
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#define GCC_ECPRI_CC_BCR 0
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#define GCC_ECPRI_SS_BCR 1
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#define GCC_ETH_WRAPPER_BCR 2
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#define GCC_PCIE_0_BCR 3
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#define GCC_PCIE_0_LINK_DOWN_BCR 4
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
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#define GCC_PCIE_0_PHY_BCR 6
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
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#define GCC_PCIE_PHY_CFG_AHB_BCR 8
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#define GCC_PCIE_PHY_COM_BCR 9
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#define GCC_PDM_BCR 10
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#define GCC_QUPV3_WRAPPER_0_BCR 11
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#define GCC_QUPV3_WRAPPER_1_BCR 12
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#define GCC_QUSB2PHY_PRIM_BCR 13
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#define GCC_QUSB2PHY_SEC_BCR 14
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#define GCC_SDCC5_BCR 15
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#define GCC_TCSR_PCIE_BCR 16
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#define GCC_TSC_BCR 17
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#define GCC_USB30_PRIM_BCR 18
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#define GCC_USB3_DP_PHY_PRIM_BCR 19
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#define GCC_USB3_DP_PHY_SEC_BCR 20
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#define GCC_USB3_PHY_PRIM_BCR 21
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#define GCC_USB3_PHY_SEC_BCR 22
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#define GCC_USB3PHY_PHY_PRIM_BCR 23
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#define GCC_USB3PHY_PHY_SEC_BCR 24
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25
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/* GCC power domains */
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#define PCIE_0_GDSC 0
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#define PCIE_0_PHY_GDSC 1
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#define USB30_PRIM_GDSC 2
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#endif