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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: spacemit: k3: adjust drive strength and schmitter trigger
K3 SoC expand drive strength to 4 bits which support even larger
settings table comparing to old SoC generation. Also schmitter trigger
setting is changed to 1 bit.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
authored by
Yixun Lan
and committed by
Linus Walleij
3f20bdf7
7412311c
+116
-47
+116
-47
drivers/pinctrl/spacemit/pinctrl-k1.c
+116
-47
drivers/pinctrl/spacemit/pinctrl-k1.c
···
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#include "pinctrl-k1.h"
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/*
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-
* +---------+----------+-----------+--------+--------+----------+--------+
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-
* | pull | drive | schmitter | slew | edge | strong | mux |
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* | up/down | strength | trigger | rate | detect | pull | mode |
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-
* +---------+----------+-----------+--------+--------+----------+--------+
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-
* 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits
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+
* | pull | drive | schmitter | slew | edge | strong | mux |
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* SoC | up/down | strength | trigger | rate | detect | pull | mode |
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*-----+---------+----------+-----------+-------+--------+--------+--------+
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* K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits |
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*-----+---------+----------+-----------+-------+--------+--------+--------+
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* K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits |
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*/
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#define PAD_MUX GENMASK(2, 0)
···
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#define PAD_EDGE_CLEAR BIT(6)
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#define PAD_SLEW_RATE GENMASK(12, 11)
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#define PAD_SLEW_RATE_EN BIT(7)
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#define PAD_SCHMITT GENMASK(9, 8)
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#define PAD_DRIVE GENMASK(12, 10)
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#define PAD_SCHMITT_K1 GENMASK(9, 8)
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#define PAD_DRIVE_K1 GENMASK(12, 10)
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#define PAD_SCHMITT_K3 BIT(8)
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#define PAD_DRIVE_K3 GENMASK(12, 9)
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#define PAD_PULLDOWN BIT(13)
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#define PAD_PULLUP BIT(14)
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#define PAD_PULL_EN BIT(15)
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+
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struct spacemit_pin_drv_strength {
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u8 val;
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u32 mA;
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+
};
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+
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struct spacemit_pinctrl_dconf {
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u64 schmitt_mask;
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u64 drive_mask;
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+
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struct spacemit_pin_drv_strength *ds_1v8_tbl;
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size_t ds_1v8_tbl_num;
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struct spacemit_pin_drv_strength *ds_3v3_tbl;
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size_t ds_3v3_tbl_num;
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};
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struct spacemit_pin {
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u16 pin;
···
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const struct spacemit_pin *data;
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u16 npins;
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unsigned int (*pin_to_offset)(unsigned int pin);
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const struct spacemit_pinctrl_dconf *dconf;
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};
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struct spacemit_pin_mux_config {
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const struct spacemit_pin *pin;
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u32 config;
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};
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struct spacemit_pin_drv_strength {
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u8 val;
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u32 mA;
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};
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/* map pin id to pinctrl register offset, refer MFPR definition */
···
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seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value);
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}
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/* use IO high level output current as the table */
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static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
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{ 0, 11 },
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{ 2, 21 },
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{ 4, 32 },
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{ 6, 42 },
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static const struct spacemit_pinctrl_dconf k1_drive_conf = {
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.drive_mask = PAD_DRIVE_K1,
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.schmitt_mask = PAD_SCHMITT_K1,
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.ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
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{ 0, 11 },
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{ 2, 21 },
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{ 4, 32 },
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{ 6, 42 },
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},
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.ds_1v8_tbl_num = 4,
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.ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
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{ 0, 7 },
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{ 2, 10 },
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{ 4, 13 },
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{ 6, 16 },
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{ 1, 19 },
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{ 3, 23 },
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{ 5, 26 },
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{ 7, 29 },
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},
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.ds_3v3_tbl_num = 8,
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};
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static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = {
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{ 0, 7 },
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{ 2, 10 },
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{ 4, 13 },
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{ 6, 16 },
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{ 1, 19 },
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{ 3, 23 },
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{ 5, 26 },
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{ 7, 29 },
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static const struct spacemit_pinctrl_dconf k3_drive_conf = {
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.drive_mask = PAD_DRIVE_K3,
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.schmitt_mask = PAD_SCHMITT_K3,
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.ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
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{ 0, 2 },
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{ 1, 4 },
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{ 2, 6 },
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{ 3, 7 },
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{ 4, 9 },
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{ 5, 11 },
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{ 6, 13 },
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{ 7, 14 },
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{ 8, 21 },
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{ 9, 23 },
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{ 10, 25 },
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{ 11, 26 },
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{ 12, 28 },
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{ 13, 30 },
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{ 14, 31 },
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{ 15, 33 },
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},
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.ds_1v8_tbl_num = 16,
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.ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
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{ 0, 3 },
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{ 1, 5 },
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{ 2, 7 },
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{ 3, 9 },
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{ 4, 11 },
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{ 5, 13 },
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{ 6, 15 },
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{ 7, 17 },
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{ 8, 25 },
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{ 9, 27 },
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{ 10, 29 },
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{ 11, 31 },
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{ 12, 33 },
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{ 13, 35 },
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{ 14, 37 },
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{ 15, 38 },
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},
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.ds_3v3_tbl_num = 16,
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};
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static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
···
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}
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static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type,
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const struct spacemit_pinctrl_dconf *dconf,
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u32 mA)
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{
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switch (type) {
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case IO_TYPE_1V8:
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return spacemit_get_ds_value(spacemit_ds_1v8_tbl,
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ARRAY_SIZE(spacemit_ds_1v8_tbl),
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return spacemit_get_ds_value(dconf->ds_1v8_tbl,
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dconf->ds_1v8_tbl_num,
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mA);
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case IO_TYPE_3V3:
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return spacemit_get_ds_value(spacemit_ds_3v3_tbl,
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ARRAY_SIZE(spacemit_ds_3v3_tbl),
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return spacemit_get_ds_value(dconf->ds_3v3_tbl,
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dconf->ds_3v3_tbl_num,
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mA);
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default:
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return 0;
···
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}
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static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type,
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const struct spacemit_pinctrl_dconf *dconf,
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u32 value)
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{
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switch (type) {
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case IO_TYPE_1V8:
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return spacemit_get_ds_mA(spacemit_ds_1v8_tbl,
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ARRAY_SIZE(spacemit_ds_1v8_tbl),
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value & 0x6);
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return spacemit_get_ds_mA(dconf->ds_1v8_tbl,
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dconf->ds_1v8_tbl_num,
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value);
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case IO_TYPE_3V3:
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return spacemit_get_ds_mA(spacemit_ds_3v3_tbl,
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ARRAY_SIZE(spacemit_ds_3v3_tbl),
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return spacemit_get_ds_mA(dconf->ds_3v3_tbl,
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dconf->ds_3v3_tbl_num,
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value);
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default:
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return 0;
···
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#define ENABLE_DRV_STRENGTH BIT(1)
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#define ENABLE_SLEW_RATE BIT(2)
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static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
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const struct spacemit_pinctrl_dconf *dconf,
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unsigned long *configs,
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unsigned int num_configs,
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u32 *value)
···
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drv_strength = arg;
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break;
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case PIN_CONFIG_INPUT_SCHMITT:
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v &= ~PAD_SCHMITT;
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v |= FIELD_PREP(PAD_SCHMITT, arg);
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v &= ~dconf->schmitt_mask;
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v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask;
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break;
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case PIN_CONFIG_POWER_SOURCE:
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voltage = arg;
···
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}
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}
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val = spacemit_get_driver_strength(type, drv_strength);
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val = spacemit_get_driver_strength(type, dconf, drv_strength);
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v &= ~PAD_DRIVE;
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v |= FIELD_PREP(PAD_DRIVE, val);
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v &= ~dconf->drive_mask;
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v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask;
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}
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if (flag & ENABLE_SLEW_RATE) {
···
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const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
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u32 value;
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if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
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if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf,
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configs, num_configs, &value))
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return -EINVAL;
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return spacemit_pin_set_config(pctrl, pin, value);
···
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return -EINVAL;
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spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
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if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
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if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf,
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configs, num_configs, &value))
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return -EINVAL;
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for (i = 0; i < group->grp.npins; i++)
···
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struct seq_file *seq, unsigned int pin)
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{
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struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf;
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const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
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enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
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void __iomem *reg = spacemit_pin_to_reg(pctrl, pin);
···
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seq_printf(seq, ", io type (%s)", io_type_desc[type]);
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tmp = FIELD_GET(PAD_DRIVE, value);
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tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask);
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if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) {
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mA = spacemit_get_drive_strength_mA(type, tmp);
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mA = spacemit_get_drive_strength_mA(type, dconf, tmp);
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seq_printf(seq, ", drive strength (%d mA)", mA);
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}
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/* drive strength depend on power source, so show all values */
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if (type == IO_TYPE_EXTERNAL)
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seq_printf(seq, ", drive strength (%d or %d mA)",
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spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp),
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spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp));
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spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp),
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spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp));
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seq_printf(seq, ", register (0x%04x)", value);
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}
···
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.data = k1_pin_data,
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.npins = ARRAY_SIZE(k1_pin_desc),
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.pin_to_offset = spacemit_k1_pin_to_offset,
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.dconf = &k1_drive_conf,
1121
1055
};
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static const struct pinctrl_pin_desc k3_pin_desc[] = {
···
1455
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.data = k3_pin_data,
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.npins = ARRAY_SIZE(k3_pin_desc),
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.pin_to_offset = spacemit_k3_pin_to_offset,
1390
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.dconf = &k3_drive_conf,
1458
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};
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static const struct of_device_id k1_pinctrl_ids[] = {