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drm/amd/powerplay: enable ulv feature by default for vega10.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
4022e4f2 301654a4

+28 -5
+28 -5
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
··· 126 126 data->registry_data.clock_stretcher_support = 127 127 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? false : true; 128 128 129 + data->registry_data.ulv_support = 130 + hwmgr->feature_mask & PP_ULV_MASK ? true : false; 131 + 129 132 data->registry_data.disable_water_mark = 0; 130 133 131 134 data->registry_data.fan_control_support = 1; ··· 2583 2580 return 0; 2584 2581 } 2585 2582 2583 + static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) 2584 + { 2585 + struct vega10_hwmgr *data = 2586 + (struct vega10_hwmgr *)(hwmgr->backend); 2587 + 2588 + if (data->registry_data.ulv_support) { 2589 + PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, 2590 + false, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2591 + "disable ULV Feature Failed!", 2592 + return -EINVAL); 2593 + data->smu_features[GNLD_ULV].enabled = false; 2594 + } 2595 + 2596 + return 0; 2597 + } 2598 + 2586 2599 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2587 2600 { 2588 2601 struct vega10_hwmgr *data = ··· 2766 2747 "Failed to enable VR hot feature!", 2767 2748 result = tmp_result); 2768 2749 2769 - tmp_result = vega10_enable_ulv(hwmgr); 2770 - PP_ASSERT_WITH_CODE(!tmp_result, 2771 - "Failed to enable ULV!", 2772 - result = tmp_result); 2773 - 2774 2750 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); 2775 2751 PP_ASSERT_WITH_CODE(!tmp_result, 2776 2752 "Failed to enable deep sleep master switch!", ··· 2783 2769 tmp_result = vega10_power_control_set_level(hwmgr); 2784 2770 PP_ASSERT_WITH_CODE(!tmp_result, 2785 2771 "Failed to power control set level!", 2772 + result = tmp_result); 2773 + 2774 + tmp_result = vega10_enable_ulv(hwmgr); 2775 + PP_ASSERT_WITH_CODE(!tmp_result, 2776 + "Failed to enable ULV!", 2786 2777 result = tmp_result); 2787 2778 2788 2779 return result; ··· 4550 4531 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); 4551 4532 PP_ASSERT_WITH_CODE((tmp_result == 0), 4552 4533 "Failed to stop DPM!", result = tmp_result); 4534 + 4535 + tmp_result = vega10_disable_ulv(hwmgr); 4536 + PP_ASSERT_WITH_CODE((tmp_result == 0), 4537 + "Failed to disable ulv!", result = tmp_result); 4553 4538 4554 4539 return result; 4555 4540 }