Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/a6xx: Set GMU CGC properties on a6xx too
This was apparently never done before.. Program the expected values.
This also gets rid of sneakily setting that register through the HWCG
reg list on A690.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611098/
Signed-off-by: Rob Clark <robdclark@chromium.org>
authored by
Konrad Dybcio
and committed by
Rob Clark
40c297eb
51682bc4
+17
-10
-1
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
-1
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
···
448
448
{REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
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{REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
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{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
451
-
{REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
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{REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
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{REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
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{}
+10
-8
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+10
-8
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
···
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struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
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const struct adreno_reglist *reg;
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unsigned int i;
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+
u32 cgc_delay, cgc_hyst;
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u32 val, clock_cntl_on;
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if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
···
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else
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clock_cntl_on = 0x8aa8aa82;
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-
if (adreno_is_a7xx(adreno_gpu)) {
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-
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
422
-
state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
423
-
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
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-
state ? 0x10111 : 0);
425
-
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
426
-
state ? 0x5555 : 0);
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-
}
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+
cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
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+
cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
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+
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+
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
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+
state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
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+
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
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+
state ? cgc_delay : 0);
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+
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
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+
state ? cgc_hyst : 0);
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if (!adreno_gpu->info->a6xx->hwcg) {
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gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
+7
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
+7
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.h
···
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return adreno_is_a610(gpu) || adreno_is_a702(gpu);
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}
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-
/* check for a615, a616, a618, a619 or any a630 derivatives */
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+
/* TODO: 615/616 */
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+
static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
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+
{
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+
return adreno_is_a618(gpu) ||
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+
adreno_is_a619(gpu);
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+
}
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+
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static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
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{
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if (WARN_ON_ONCE(!gpu->info))