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drm/msm/a6xx: Use the per-GPU value for gmu_cgc_mode

This register's magic value differs wildly between different GPUs, use
the hardcoded data instead of trying to make some logic out of it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611096/
Signed-off-by: Rob Clark <robdclark@chromium.org>

authored by

Konrad Dybcio and committed by
Rob Clark
51682bc4 d50a8363

+2 -4
+2 -4
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 402 402 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 403 403 const struct adreno_reglist *reg; 404 404 unsigned int i; 405 - u32 val, clock_cntl_on, cgc_mode; 405 + u32 val, clock_cntl_on; 406 406 407 407 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu))) 408 408 return; ··· 417 417 clock_cntl_on = 0x8aa8aa82; 418 418 419 419 if (adreno_is_a7xx(adreno_gpu)) { 420 - cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000; 421 - 422 420 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 423 - state ? cgc_mode : 0); 421 + state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); 424 422 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 425 423 state ? 0x10111 : 0); 426 424 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,