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dt-bindings: tegra: Update headers for Tegra234

Update the device-tree clock, memory, power and reset headers for
Tegra234 by adding the definitions for all the various devices.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

authored by

Jon Hunter and committed by
Thierry Reding 41155b6f 0e2b014e

+1167 -31
+628 -7
include/dt-bindings/clock/tegra234-clock.h
··· 9 9 * @defgroup bpmp_clock_ids Clock ID's 10 10 * @{ 11 11 */ 12 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */ 13 + #define TEGRA234_CLK_ACTMON 1U 14 + /** @brief output of gate CLK_ENB_ADSP */ 15 + #define TEGRA234_CLK_ADSP 2U 16 + /** @brief output of gate CLK_ENB_ADSPNEON */ 17 + #define TEGRA234_CLK_ADSPNEON 3U 12 18 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 13 19 #define TEGRA234_CLK_AHUB 4U 14 20 /** @brief output of gate CLK_ENB_APB2APE */ ··· 23 17 #define TEGRA234_CLK_APE 6U 24 18 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 25 19 #define TEGRA234_CLK_AUD_MCLK 7U 20 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ 21 + #define TEGRA234_CLK_AXI_CBB 8U 22 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ 23 + #define TEGRA234_CLK_CAN1 9U 24 + /** @brief output of gate CLK_ENB_CAN1_HOST */ 25 + #define TEGRA234_CLK_CAN1_HOST 10U 26 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ 27 + #define TEGRA234_CLK_CAN2 11U 28 + /** @brief output of gate CLK_ENB_CAN2_HOST */ 29 + #define TEGRA234_CLK_CAN2_HOST 12U 30 + /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ 31 + #define TEGRA234_CLK_CLK_M 14U 26 32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 27 33 #define TEGRA234_CLK_DMIC1 15U 28 34 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ ··· 43 25 #define TEGRA234_CLK_DMIC3 17U 44 26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 45 27 #define TEGRA234_CLK_DMIC4 18U 28 + /** @brief output of gate CLK_ENB_DPAUX */ 29 + #define TEGRA234_CLK_DPAUX 19U 30 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */ 31 + #define TEGRA234_CLK_NVJPG1 20U 32 + /** 33 + * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY 34 + * divided by the divider controlled by ACLK_CLK_DIVISOR in 35 + * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER 36 + */ 37 + #define TEGRA234_CLK_ACLK 21U 38 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */ 39 + #define TEGRA234_CLK_MSS_ENCRYPT 22U 40 + /** @brief clock recovered from EAVB input */ 41 + #define TEGRA234_CLK_EQOS_RX_INPUT 23U 42 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */ 43 + #define TEGRA234_CLK_AON_APB 25U 44 + /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */ 45 + #define TEGRA234_CLK_AON_NIC 26U 46 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */ 47 + #define TEGRA234_CLK_AON_CPU_NIC 27U 48 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ 49 + #define TEGRA234_CLK_PLLA1 28U 46 50 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 47 51 #define TEGRA234_CLK_DSPK1 29U 48 52 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ ··· 78 38 * throughput and memory controller power. 79 39 */ 80 40 #define TEGRA234_CLK_EMC 31U 81 - /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 82 - #define TEGRA234_CLK_HOST1X 46U 41 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */ 42 + #define TEGRA234_CLK_EQOS_AXI 32U 43 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */ 44 + #define TEGRA234_CLK_EQOS_PTP_REF 33U 45 + /** @brief output of gate CLK_ENB_EQOS_RX */ 46 + #define TEGRA234_CLK_EQOS_RX 34U 47 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */ 48 + #define TEGRA234_CLK_EQOS_TX 35U 49 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ 50 + #define TEGRA234_CLK_EXTPERIPH1 36U 51 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ 52 + #define TEGRA234_CLK_EXTPERIPH2 37U 53 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ 54 + #define TEGRA234_CLK_EXTPERIPH3 38U 55 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ 56 + #define TEGRA234_CLK_EXTPERIPH4 39U 83 57 /** @brief output of gate CLK_ENB_FUSE */ 84 58 #define TEGRA234_CLK_FUSE 40U 59 + /** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */ 60 + #define TEGRA234_CLK_GPC0CLK 41U 61 + /** @brief TODO */ 62 + #define TEGRA234_CLK_GPU_PWR 42U 63 + /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ 64 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 65 + #define TEGRA234_CLK_HOST1X 46U 66 + /** @brief xusb_hs_hsicp_clk */ 67 + #define TEGRA234_CLK_XUSB_HS_HSICP 47U 85 68 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 86 69 #define TEGRA234_CLK_I2C1 48U 87 70 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ ··· 145 82 #define TEGRA234_CLK_I2S6 66U 146 83 /** @brief clock recovered from I2S6 input */ 147 84 #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 85 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ 86 + #define TEGRA234_CLK_ISP 69U 87 + /** @brief Monitored branch of EQOS_RX clock */ 88 + #define TEGRA234_CLK_EQOS_RX_M 70U 89 + /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */ 90 + #define TEGRA234_CLK_MAUD 71U 91 + /** @brief output of gate CLK_ENB_MIPI_CAL */ 92 + #define TEGRA234_CLK_MIPI_CAL 72U 93 + /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ 94 + #define TEGRA234_CLK_MPHY_CORE_PLL_FIXED 73U 95 + /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ 96 + #define TEGRA234_CLK_MPHY_L0_RX_ANA 74U 97 + /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ 98 + #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT 75U 99 + /** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */ 100 + #define TEGRA234_CLK_MPHY_L0_RX_SYMB 76U 101 + /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ 102 + #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT 77U 103 + /** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */ 104 + #define TEGRA234_CLK_MPHY_L0_TX_SYMB 78U 105 + /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ 106 + #define TEGRA234_CLK_MPHY_L1_RX_ANA 79U 107 + /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ 108 + #define TEGRA234_CLK_MPHY_TX_1MHZ_REF 80U 109 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ 110 + #define TEGRA234_CLK_NVCSI 81U 111 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ 112 + #define TEGRA234_CLK_NVCSILP 82U 148 113 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 149 114 #define TEGRA234_CLK_NVDEC 83U 115 + /** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */ 116 + #define TEGRA234_CLK_HUB 84U 117 + /** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */ 118 + #define TEGRA234_CLK_DISP 85U 119 + /** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */ 120 + #define TEGRA234_CLK_NVDISPLAY_P0 86U 121 + /** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */ 122 + #define TEGRA234_CLK_NVDISPLAY_P1 87U 123 + /** @brief DSC_CLK (DISPCLK ÷ 3) */ 124 + #define TEGRA234_CLK_DSC 88U 125 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ 126 + #define TEGRA234_CLK_NVENC 89U 127 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ 128 + #define TEGRA234_CLK_NVJPG 90U 129 + /** @brief input from Tegra's XTAL_IN */ 130 + #define TEGRA234_CLK_OSC 91U 131 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */ 132 + #define TEGRA234_CLK_AON_TOUCH 92U 150 133 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 151 134 #define TEGRA234_CLK_PLLA 93U 135 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ 136 + #define TEGRA234_CLK_PLLAON 94U 137 + /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ 138 + #define TEGRA234_CLK_PLLE 100U 139 + /** @brief PLLP vco output */ 140 + #define TEGRA234_CLK_PLLP 101U 152 141 /** @brief PLLP clk output */ 153 142 #define TEGRA234_CLK_PLLP_OUT0 102U 143 + /** Fixed frequency 960MHz PLL for USB and EAVB */ 144 + #define TEGRA234_CLK_UTMIP_PLL 103U 154 145 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 155 146 #define TEGRA234_CLK_PLLA_OUT0 104U 156 147 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ ··· 223 106 #define TEGRA234_CLK_PWM7 111U 224 107 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 225 108 #define TEGRA234_CLK_PWM8 112U 109 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */ 110 + #define TEGRA234_CLK_RCE_CPU_NIC 113U 111 + /** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */ 112 + #define TEGRA234_CLK_RCE_NIC 114U 113 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */ 114 + #define TEGRA234_CLK_AON_I2C_SLOW 117U 115 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ 116 + #define TEGRA234_CLK_SCE_CPU_NIC 118U 117 + /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ 118 + #define TEGRA234_CLK_SCE_NIC 119U 119 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ 120 + #define TEGRA234_CLK_SDMMC1 120U 121 + /** @brief Logical clk for setting the UPHY PLL3 rate */ 122 + #define TEGRA234_CLK_UPHY_PLL3 121U 226 123 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 227 124 #define TEGRA234_CLK_SDMMC4 123U 125 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */ 126 + #define TEGRA234_CLK_SE 124U 127 + /** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */ 128 + #define TEGRA234_CLK_SOR0_PLL_REF 125U 129 + /** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */ 130 + #define TEGRA234_CLK_SOR0_REF 126U 131 + /** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */ 132 + #define TEGRA234_CLK_SOR1_PLL_REF 127U 133 + /** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */ 134 + #define TEGRA234_CLK_PRE_SOR0_REF 128U 135 + /** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */ 136 + #define TEGRA234_CLK_SOR1_REF 129U 137 + /** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */ 138 + #define TEGRA234_CLK_PRE_SOR1_REF 130U 139 + /** @brief output of gate CLK_ENB_SOR_SAFE */ 140 + #define TEGRA234_CLK_SOR_SAFE 131U 141 + /** @brief SOR_CLK_CTRL__0_DIV divider output */ 142 + #define TEGRA234_CLK_SOR0_DIV 132U 143 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ 144 + #define TEGRA234_CLK_DMIC5 134U 145 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ 146 + #define TEGRA234_CLK_SPI1 135U 147 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ 148 + #define TEGRA234_CLK_SPI2 136U 149 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */ 150 + #define TEGRA234_CLK_SPI3 137U 151 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ 152 + #define TEGRA234_CLK_I2C_SLOW 138U 228 153 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 229 154 #define TEGRA234_CLK_SYNC_DMIC1 139U 230 155 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ ··· 291 132 #define TEGRA234_CLK_SYNC_I2S5 149U 292 133 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 293 134 #define TEGRA234_CLK_SYNC_I2S6 150U 135 + /** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */ 136 + #define TEGRA234_CLK_MPHY_FORCE_LS_MODE 151U 137 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */ 138 + #define TEGRA234_CLK_TACH0 152U 139 + /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ 140 + #define TEGRA234_CLK_TSEC 153U 294 141 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ 295 142 #define TEGRA234_CLK_TSEC_PKA 154U 296 143 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 297 144 #define TEGRA234_CLK_UARTA 155U 145 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ 146 + #define TEGRA234_CLK_UARTB 156U 147 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ 148 + #define TEGRA234_CLK_UARTC 157U 149 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ 150 + #define TEGRA234_CLK_UARTD 158U 151 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ 152 + #define TEGRA234_CLK_UARTE 159U 153 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ 154 + #define TEGRA234_CLK_UARTF 160U 298 155 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 299 156 #define TEGRA234_CLK_PEX1_C6_CORE 161U 157 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ 158 + #define TEGRA234_CLK_UART_FST_MIPI_CAL 162U 159 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ 160 + #define TEGRA234_CLK_UFSDEV_REF 163U 161 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ 162 + #define TEGRA234_CLK_UFSHC 164U 163 + /** @brief output of gate CLK_ENB_USB2_TRK */ 164 + #define TEGRA234_CLK_USB2_TRK 165U 165 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ 166 + #define TEGRA234_CLK_VI 166U 300 167 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 301 - #define TEGRA234_CLK_VIC 167U 168 + #define TEGRA234_CLK_VIC 167U 169 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */ 170 + #define TEGRA234_CLK_CSITE 168U 171 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */ 172 + #define TEGRA234_CLK_IST 169U 173 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */ 174 + #define TEGRA234_CLK_JTAG_INTFC_PRE_CG 170U 302 175 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 303 176 #define TEGRA234_CLK_PEX2_C7_CORE 171U 304 177 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ 305 178 #define TEGRA234_CLK_PEX2_C8_CORE 172U 306 179 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ 307 180 #define TEGRA234_CLK_PEX2_C9_CORE 173U 181 + /** @brief dla0_falcon_clk */ 182 + #define TEGRA234_CLK_DLA0_FALCON 174U 183 + /** @brief dla0_core_clk */ 184 + #define TEGRA234_CLK_DLA0_CORE 175U 185 + /** @brief dla1_falcon_clk */ 186 + #define TEGRA234_CLK_DLA1_FALCON 176U 187 + /** @brief dla1_core_clk */ 188 + #define TEGRA234_CLK_DLA1_CORE 177U 189 + /** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */ 190 + #define TEGRA234_CLK_SOR0 178U 191 + /** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */ 192 + #define TEGRA234_CLK_SOR1 179U 193 + /** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */ 194 + #define TEGRA234_CLK_SOR_PAD_INPUT 180U 195 + /** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */ 196 + #define TEGRA234_CLK_PRE_SF0 181U 197 + /** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */ 198 + #define TEGRA234_CLK_SF0 182U 199 + /** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */ 200 + #define TEGRA234_CLK_SF1 183U 201 + /** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */ 202 + #define TEGRA234_CLK_DSI_PAD_INPUT 184U 308 203 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ 309 204 #define TEGRA234_CLK_PEX2_C10_CORE 187U 310 - /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ 205 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */ 206 + #define TEGRA234_CLK_UARTI 188U 207 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */ 208 + #define TEGRA234_CLK_UARTJ 189U 209 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */ 210 + #define TEGRA234_CLK_UARTH 190U 211 + /** @brief ungated version of fuse clk */ 212 + #define TEGRA234_CLK_FUSE_SERIAL 191U 213 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */ 311 214 #define TEGRA234_CLK_QSPI0_2X_PM 192U 312 - /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ 215 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */ 313 216 #define TEGRA234_CLK_QSPI1_2X_PM 193U 314 - /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ 217 + /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm_clk) */ 315 218 #define TEGRA234_CLK_QSPI0_PM 194U 316 - /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ 219 + /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm_clk) */ 317 220 #define TEGRA234_CLK_QSPI1_PM 195U 221 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */ 222 + #define TEGRA234_CLK_VI_CONST 196U 223 + /** @brief NAFLL clock source for BPMP */ 224 + #define TEGRA234_CLK_NAFLL_BPMP 197U 225 + /** @brief NAFLL clock source for SCE */ 226 + #define TEGRA234_CLK_NAFLL_SCE 198U 227 + /** @brief NAFLL clock source for NVDEC */ 228 + #define TEGRA234_CLK_NAFLL_NVDEC 199U 229 + /** @brief NAFLL clock source for NVJPG */ 230 + #define TEGRA234_CLK_NAFLL_NVJPG 200U 231 + /** @brief NAFLL clock source for TSEC */ 232 + #define TEGRA234_CLK_NAFLL_TSEC 201U 233 + /** @brief NAFLL clock source for VI */ 234 + #define TEGRA234_CLK_NAFLL_VI 203U 235 + /** @brief NAFLL clock source for SE */ 236 + #define TEGRA234_CLK_NAFLL_SE 204U 237 + /** @brief NAFLL clock source for NVENC */ 238 + #define TEGRA234_CLK_NAFLL_NVENC 205U 239 + /** @brief NAFLL clock source for ISP */ 240 + #define TEGRA234_CLK_NAFLL_ISP 206U 241 + /** @brief NAFLL clock source for VIC */ 242 + #define TEGRA234_CLK_NAFLL_VIC 207U 243 + /** @brief NAFLL clock source for AXICBB */ 244 + #define TEGRA234_CLK_NAFLL_AXICBB 209U 245 + /** @brief NAFLL clock source for NVJPG1 */ 246 + #define TEGRA234_CLK_NAFLL_NVJPG1 210U 247 + /** @brief NAFLL clock source for PVA core */ 248 + #define TEGRA234_CLK_NAFLL_PVA0_CORE 211U 249 + /** @brief NAFLL clock source for PVA VPS */ 250 + #define TEGRA234_CLK_NAFLL_PVA0_VPS 212U 251 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */ 252 + #define TEGRA234_CLK_DBGAPB 213U 253 + /** @brief NAFLL clock source for RCE */ 254 + #define TEGRA234_CLK_NAFLL_RCE 214U 255 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */ 256 + #define TEGRA234_CLK_LA 215U 257 + /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */ 258 + #define TEGRA234_CLK_PLLP_OUT_JTAG 216U 259 + /** @brief AXI_CBB branch sharing gate control with SDMMC4 */ 260 + #define TEGRA234_CLK_SDMMC4_AXICIF 217U 318 261 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 319 262 #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 320 263 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ ··· 431 170 #define TEGRA234_CLK_PEX0_C4_CORE 224U 432 171 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ 433 172 #define TEGRA234_CLK_PEX1_C5_CORE 225U 173 + /** @brief Monitored branch of PEX0_C0_CORE clock */ 174 + #define TEGRA234_CLK_PEX0_C0_CORE_M 229U 175 + /** @brief Monitored branch of PEX0_C1_CORE clock */ 176 + #define TEGRA234_CLK_PEX0_C1_CORE_M 230U 177 + /** @brief Monitored branch of PEX0_C2_CORE clock */ 178 + #define TEGRA234_CLK_PEX0_C2_CORE_M 231U 179 + /** @brief Monitored branch of PEX0_C3_CORE clock */ 180 + #define TEGRA234_CLK_PEX0_C3_CORE_M 232U 181 + /** @brief Monitored branch of PEX0_C4_CORE clock */ 182 + #define TEGRA234_CLK_PEX0_C4_CORE_M 233U 183 + /** @brief Monitored branch of PEX1_C5_CORE clock */ 184 + #define TEGRA234_CLK_PEX1_C5_CORE_M 234U 185 + /** @brief Monitored branch of PEX1_C6_CORE clock */ 186 + #define TEGRA234_CLK_PEX1_C6_CORE_M 235U 187 + /** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */ 188 + #define TEGRA234_CLK_GPC1CLK 236U 434 189 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 435 190 #define TEGRA234_CLK_PLLC4 237U 191 + /** @brief PLLC4 VCO followed by DIV3 path */ 192 + #define TEGRA234_CLK_PLLC4_OUT1 239U 193 + /** @brief PLLC4 VCO followed by DIV5 path */ 194 + #define TEGRA234_CLK_PLLC4_OUT2 240U 195 + /** @brief output of the mux controlled by PLLC4_CLK_SEL */ 196 + #define TEGRA234_CLK_PLLC4_MUXED 241U 197 + /** @brief PLLC4 VCO followed by DIV2 path */ 198 + #define TEGRA234_CLK_PLLC4_VCO_DIV2 242U 199 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */ 200 + #define TEGRA234_CLK_PLLNVHS 243U 201 + /** @brief Monitored branch of PEX2_C7_CORE clock */ 202 + #define TEGRA234_CLK_PEX2_C7_CORE_M 244U 203 + /** @brief Monitored branch of PEX2_C8_CORE clock */ 204 + #define TEGRA234_CLK_PEX2_C8_CORE_M 245U 205 + /** @brief Monitored branch of PEX2_C9_CORE clock */ 206 + #define TEGRA234_CLK_PEX2_C9_CORE_M 246U 207 + /** @brief Monitored branch of PEX2_C10_CORE clock */ 208 + #define TEGRA234_CLK_PEX2_C10_CORE_M 247U 436 209 /** @brief RX clock recovered from MGBE0 lane input */ 437 210 #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 438 211 /** @brief RX clock recovered from MGBE1 lane input */ ··· 475 180 #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 476 181 /** @brief RX clock recovered from MGBE3 lane input */ 477 182 #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 183 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */ 184 + #define TEGRA234_CLK_PEX_SATA_USB_RX_BYP 254U 185 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */ 186 + #define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT 255U 187 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */ 188 + #define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT 256U 189 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */ 190 + #define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT 257U 191 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */ 192 + #define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT 258U 193 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */ 194 + #define TEGRA234_CLK_NVHS_RX_BYP_REF 263U 195 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */ 196 + #define TEGRA234_CLK_NVHS_PLL0_MGMT 264U 197 + /** @brief xusb_core_dev_clk */ 198 + #define TEGRA234_CLK_XUSB_CORE_DEV 265U 199 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output */ 200 + #define TEGRA234_CLK_XUSB_CORE_MUX 266U 201 + /** @brief xusb_core_host_clk */ 202 + #define TEGRA234_CLK_XUSB_CORE_HOST 267U 203 + /** @brief xusb_core_superspeed_clk */ 204 + #define TEGRA234_CLK_XUSB_CORE_SS 268U 205 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */ 206 + #define TEGRA234_CLK_XUSB_FALCON 269U 207 + /** @brief xusb_falcon_host_clk */ 208 + #define TEGRA234_CLK_XUSB_FALCON_HOST 270U 209 + /** @brief xusb_falcon_superspeed_clk */ 210 + #define TEGRA234_CLK_XUSB_FALCON_SS 271U 211 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */ 212 + #define TEGRA234_CLK_XUSB_FS 272U 213 + /** @brief xusb_fs_host_clk */ 214 + #define TEGRA234_CLK_XUSB_FS_HOST 273U 215 + /** @brief xusb_fs_dev_clk */ 216 + #define TEGRA234_CLK_XUSB_FS_DEV 274U 217 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */ 218 + #define TEGRA234_CLK_XUSB_SS 275U 219 + /** @brief xusb_ss_dev_clk */ 220 + #define TEGRA234_CLK_XUSB_SS_DEV 276U 221 + /** @brief xusb_ss_superspeed_clk */ 222 + #define TEGRA234_CLK_XUSB_SS_SUPERSPEED 277U 223 + /** @brief NAFLL clock source for CPU cluster 0 */ 224 + #define TEGRA234_CLK_NAFLL_CLUSTER0 280U /* TODO: remove */ 225 + #define TEGRA234_CLK_NAFLL_CLUSTER0_CORE 280U 226 + /** @brief NAFLL clock source for CPU cluster 1 */ 227 + #define TEGRA234_CLK_NAFLL_CLUSTER1 281U /* TODO: remove */ 228 + #define TEGRA234_CLK_NAFLL_CLUSTER1_CORE 281U 229 + /** @brief NAFLL clock source for CPU cluster 2 */ 230 + #define TEGRA234_CLK_NAFLL_CLUSTER2 282U /* TODO: remove */ 231 + #define TEGRA234_CLK_NAFLL_CLUSTER2_CORE 282U 232 + /** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */ 233 + #define TEGRA234_CLK_CAN1_CORE 284U 234 + /** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */ 235 + #define TEGRA234_CLK_CAN2_CORE 285U 236 + /** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */ 237 + #define TEGRA234_CLK_PLLA1_OUT1 286U 238 + /** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */ 239 + #define TEGRA234_CLK_PLLNVHS_HPS 287U 240 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */ 241 + #define TEGRA234_CLK_PLLREFE_VCOOUT 288U 478 242 /** @brief 32K input clock provided by PMIC */ 479 243 #define TEGRA234_CLK_CLK_32K 289U 244 + /** @brief Fixed 48MHz clock divided down from utmipll */ 245 + #define TEGRA234_CLK_UTMIPLL_CLKOUT48 291U 246 + /** @brief Fixed 480MHz clock divided down from utmipll */ 247 + #define TEGRA234_CLK_UTMIPLL_CLKOUT480 292U 248 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ 249 + #define TEGRA234_CLK_PLLNVCSI 294U 250 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */ 251 + #define TEGRA234_CLK_PVA0_CPU_AXI 295U 252 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */ 253 + #define TEGRA234_CLK_PVA0_VPS 297U 254 + /** @brief DLA0_CORE_NAFLL */ 255 + #define TEGRA234_CLK_NAFLL_DLA0_CORE 299U 256 + /** @brief DLA0_FALCON_NAFLL */ 257 + #define TEGRA234_CLK_NAFLL_DLA0_FALCON 300U 258 + /** @brief DLA1_CORE_NAFLL */ 259 + #define TEGRA234_CLK_NAFLL_DLA1_CORE 301U 260 + /** @brief DLA1_FALCON_NAFLL */ 261 + #define TEGRA234_CLK_NAFLL_DLA1_FALCON 302U 262 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ 263 + #define TEGRA234_CLK_AON_UART_FST_MIPI_CAL 303U 264 + /** @brief GPU system clock */ 265 + #define TEGRA234_CLK_GPUSYS 304U 266 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */ 267 + #define TEGRA234_CLK_I2C5 305U 268 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */ 269 + #define TEGRA234_CLK_FR_SE 306U 270 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */ 271 + #define TEGRA234_CLK_BPMP_CPU_NIC 307U 272 + /** @brief output of gate CLK_ENB_BPMP_CPU */ 273 + #define TEGRA234_CLK_BPMP_CPU 308U 274 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */ 275 + #define TEGRA234_CLK_TSC 309U 276 + /** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */ 277 + #define TEGRA234_CLK_EMCSA_MPLL 310U 278 + /** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */ 279 + #define TEGRA234_CLK_EMCSB_MPLL 311U 280 + /** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */ 281 + #define TEGRA234_CLK_EMCSC_MPLL 312U 282 + /** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */ 283 + #define TEGRA234_CLK_EMCSD_MPLL 313U 284 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ 285 + #define TEGRA234_CLK_PLLC 314U 286 + /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ 287 + #define TEGRA234_CLK_PLLC2 315U 288 + /** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */ 289 + #define TEGRA234_CLK_TSC_REF 317U 290 + /** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */ 291 + #define TEGRA234_CLK_FUSE_BURN 318U 292 + /** @brief GBE PLL */ 293 + #define TEGRA234_CLK_PLLGBE 319U 294 + /** @brief GBE PLL hardware power sequencer */ 295 + #define TEGRA234_CLK_PLLGBE_HPS 320U 296 + /** @brief output of EMC CDB side A fixed (DIV4) divider */ 297 + #define TEGRA234_CLK_EMCSA_EMC 321U 298 + /** @brief output of EMC CDB side B fixed (DIV4) divider */ 299 + #define TEGRA234_CLK_EMCSB_EMC 322U 300 + /** @brief output of EMC CDB side C fixed (DIV4) divider */ 301 + #define TEGRA234_CLK_EMCSC_EMC 323U 302 + /** @brief output of EMC CDB side D fixed (DIV4) divider */ 303 + #define TEGRA234_CLK_EMCSD_EMC 324U 304 + /** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */ 305 + #define TEGRA234_CLK_PLLE_HPS 326U 306 + /** @brief CLK_ENB_PLLREFE_OUT gate output */ 307 + #define TEGRA234_CLK_PLLREFE_VCOOUT_GATED 327U 308 + /** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */ 309 + #define TEGRA234_CLK_PLLP_DIV17 328U 310 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */ 311 + #define TEGRA234_CLK_SOC_THERM 329U 312 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */ 313 + #define TEGRA234_CLK_TSENSE 330U 314 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */ 315 + #define TEGRA234_CLK_FR_SEU1 331U 316 + /** @brief NAFLL clock source for OFA */ 317 + #define TEGRA234_CLK_NAFLL_OFA 333U 318 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */ 319 + #define TEGRA234_CLK_OFA 334U 320 + /** @brief NAFLL clock source for SEU1 */ 321 + #define TEGRA234_CLK_NAFLL_SEU1 335U 322 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */ 323 + #define TEGRA234_CLK_SEU1 336U 324 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ 325 + #define TEGRA234_CLK_SPI4 337U 326 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */ 327 + #define TEGRA234_CLK_SPI5 338U 328 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */ 329 + #define TEGRA234_CLK_DCE_CPU_NIC 339U 330 + /** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */ 331 + #define TEGRA234_CLK_DCE_NIC 340U 332 + /** @brief NAFLL clock source for DCE */ 333 + #define TEGRA234_CLK_NAFLL_DCE 341U 334 + /** @brief Monitored branch of MPHY_L0_RX_ANA clock */ 335 + #define TEGRA234_CLK_MPHY_L0_RX_ANA_M 342U 336 + /** @brief Monitored branch of MPHY_L1_RX_ANA clock */ 337 + #define TEGRA234_CLK_MPHY_L1_RX_ANA_M 343U 338 + /** @brief ungated version of TX symbol clock after fixed 1/2 divider */ 339 + #define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB 344U 340 + /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ 341 + #define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV 345U 342 + /** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */ 343 + #define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB 346U 344 + /** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ 345 + #define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV 347U 346 + /** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ 347 + #define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV 348U 348 + /** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */ 349 + #define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV 349U 350 + /** @brief Monitored branch of MPHY_L0_TX_SYMB clock */ 351 + #define TEGRA234_CLK_MPHY_L0_TX_SYMB_M 350U 352 + /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ 353 + #define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV 351U 354 + /** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ 355 + #define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV 352U 356 + /** @brief output of SW_MPHY_L0_RX_LS_BIT divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ 357 + #define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV 353U 358 + /** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */ 359 + #define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV 354U 360 + /** @brief Monitored branch of MPHY_L0_RX_SYMB clock */ 361 + #define TEGRA234_CLK_MPHY_L0_RX_SYMB_M 355U 480 362 /** @brief Monitored branch of MBGE0 RX input clock */ 481 363 #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 482 364 /** @brief Monitored branch of MBGE1 RX input clock */ ··· 670 198 #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 671 199 /** @brief Monitored branch of MGBE3 RX PCS mux output */ 672 200 #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 201 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */ 202 + #define TEGRA234_CLK_TACH1 365U 203 + /** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */ 204 + #define TEGRA234_CLK_MGBES_APP 366U 205 + /** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */ 206 + #define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF 367U 207 + /** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */ 208 + #define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG 368U 673 209 /** @brief RX PCS clock recovered from MGBE0 lane input */ 674 210 #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 675 211 /** @brief RX PCS clock recovered from MGBE1 lane input */ ··· 714 234 #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 715 235 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 716 236 #define TEGRA234_CLK_MGBE1_MAC 386U 237 + /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */ 238 + #define TEGRA234_CLK_MGBE1_MACSEC 387U 717 239 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 718 240 #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 719 241 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ ··· 732 250 #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 733 251 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 734 252 #define TEGRA234_CLK_MGBE2_MAC 395U 253 + /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */ 254 + #define TEGRA234_CLK_MGBE2_MACSEC 396U 735 255 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 736 256 #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 737 257 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ ··· 758 274 #define TEGRA234_CLK_MGBE3_APP 407U 759 275 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 760 276 #define TEGRA234_CLK_MGBE3_PTP_REF 408U 277 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */ 278 + #define TEGRA234_CLK_GBE_RX_BYP_REF 409U 279 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */ 280 + #define TEGRA234_CLK_GBE_PLL0_MGMT 410U 281 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */ 282 + #define TEGRA234_CLK_GBE_PLL1_MGMT 411U 283 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */ 284 + #define TEGRA234_CLK_GBE_PLL2_MGMT 412U 285 + /** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */ 286 + #define TEGRA234_CLK_EQOS_MACSEC_RX 413U 287 + /** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */ 288 + #define TEGRA234_CLK_EQOS_MACSEC_TX 414U 289 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */ 290 + #define TEGRA234_CLK_EQOS_TX_DIVIDER 415U 291 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */ 292 + #define TEGRA234_CLK_NVHS_PLL1_MGMT 416U 293 + /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */ 294 + #define TEGRA234_CLK_EMCHUB 417U 295 + /** @brief clock recovered from I2S7 input */ 296 + #define TEGRA234_CLK_I2S7_SYNC_INPUT 418U 297 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */ 298 + #define TEGRA234_CLK_SYNC_I2S7 419U 299 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */ 300 + #define TEGRA234_CLK_I2S7 420U 301 + /** @brief Monitored output of I2S7 pad macro mux */ 302 + #define TEGRA234_CLK_I2S7_PAD_M 421U 303 + /** @brief clock recovered from I2S8 input */ 304 + #define TEGRA234_CLK_I2S8_SYNC_INPUT 422U 305 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */ 306 + #define TEGRA234_CLK_SYNC_I2S8 423U 307 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */ 308 + #define TEGRA234_CLK_I2S8 424U 309 + /** @brief Monitored output of I2S8 pad macro mux */ 310 + #define TEGRA234_CLK_I2S8_PAD_M 425U 311 + /** @brief NAFLL clock source for GPU GPC0 */ 312 + #define TEGRA234_CLK_NAFLL_GPC0 426U 313 + /** @brief NAFLL clock source for GPU GPC1 */ 314 + #define TEGRA234_CLK_NAFLL_GPC1 427U 315 + /** @brief NAFLL clock source for GPU SYSCLK */ 316 + #define TEGRA234_CLK_NAFLL_GPUSYS 428U 317 + /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */ 318 + #define TEGRA234_CLK_NAFLL_DSU0 429U /* TODO: remove */ 319 + #define TEGRA234_CLK_NAFLL_CLUSTER0_DSU 429U 320 + /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */ 321 + #define TEGRA234_CLK_NAFLL_DSU1 430U /* TODO: remove */ 322 + #define TEGRA234_CLK_NAFLL_CLUSTER1_DSU 430U 323 + /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */ 324 + #define TEGRA234_CLK_NAFLL_DSU2 431U /* TODO: remove */ 325 + #define TEGRA234_CLK_NAFLL_CLUSTER2_DSU 431U 326 + /** @brief output of gate CLK_ENB_SCE_CPU */ 327 + #define TEGRA234_CLK_SCE_CPU 432U 328 + /** @brief output of gate CLK_ENB_RCE_CPU */ 329 + #define TEGRA234_CLK_RCE_CPU 433U 330 + /** @brief output of gate CLK_ENB_DCE_CPU */ 331 + #define TEGRA234_CLK_DCE_CPU 434U 332 + /** @brief DSIPLL VCO output */ 333 + #define TEGRA234_CLK_DSIPLL_VCO 435U 334 + /** @brief DSIPLL SYNC_CLKOUTP/N differential output */ 335 + #define TEGRA234_CLK_DSIPLL_CLKOUTPN 436U 336 + /** @brief DSIPLL SYNC_CLKOUTA output */ 337 + #define TEGRA234_CLK_DSIPLL_CLKOUTA 437U 338 + /** @brief SPPLL0 VCO output */ 339 + #define TEGRA234_CLK_SPPLL0_VCO 438U 340 + /** @brief SPPLL0 SYNC_CLKOUTP/N differential output */ 341 + #define TEGRA234_CLK_SPPLL0_CLKOUTPN 439U 342 + /** @brief SPPLL0 SYNC_CLKOUTA output */ 343 + #define TEGRA234_CLK_SPPLL0_CLKOUTA 440U 344 + /** @brief SPPLL0 SYNC_CLKOUTB output */ 345 + #define TEGRA234_CLK_SPPLL0_CLKOUTB 441U 346 + /** @brief SPPLL0 CLKOUT_DIVBY10 output */ 347 + #define TEGRA234_CLK_SPPLL0_DIV10 442U 348 + /** @brief SPPLL0 CLKOUT_DIVBY25 output */ 349 + #define TEGRA234_CLK_SPPLL0_DIV25 443U 350 + /** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */ 351 + #define TEGRA234_CLK_SPPLL0_DIV27PN 444U 352 + /** @brief SPPLL1 VCO output */ 353 + #define TEGRA234_CLK_SPPLL1_VCO 445U 354 + /** @brief SPPLL1 SYNC_CLKOUTP/N differential output */ 355 + #define TEGRA234_CLK_SPPLL1_CLKOUTPN 446U 356 + /** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */ 357 + #define TEGRA234_CLK_SPPLL1_DIV27PN 447U 358 + /** @brief VPLL0 reference clock */ 359 + #define TEGRA234_CLK_VPLL0_REF 448U 360 + /** @brief VPLL0 */ 361 + #define TEGRA234_CLK_VPLL0 449U 362 + /** @brief VPLL1 */ 363 + #define TEGRA234_CLK_VPLL1 450U 364 + /** @brief NVDISPLAY_P0_CLK reference select */ 365 + #define TEGRA234_CLK_NVDISPLAY_P0_REF 451U 366 + /** @brief RG0_PCLK */ 367 + #define TEGRA234_CLK_RG0 452U 368 + /** @brief RG1_PCLK */ 369 + #define TEGRA234_CLK_RG1 453U 370 + /** @brief DISPPLL output */ 371 + #define TEGRA234_CLK_DISPPLL 454U 372 + /** @brief DISPHUBPLL output */ 373 + #define TEGRA234_CLK_DISPHUBPLL 455U 374 + /** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */ 375 + #define TEGRA234_CLK_DSI_LP 456U 761 376 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 762 377 #define TEGRA234_CLK_AZA_2XBIT 457U 763 378 /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 764 379 #define TEGRA234_CLK_AZA_BIT 458U 380 + /** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */ 381 + #define TEGRA234_CLK_DSI_CORE 459U 382 + /** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */ 383 + #define TEGRA234_CLK_DSI_PIXEL 460U 384 + /** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */ 385 + #define TEGRA234_CLK_PRE_SOR0 461U 386 + /** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */ 387 + #define TEGRA234_CLK_PRE_SOR1 462U 388 + /** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */ 389 + #define TEGRA234_CLK_DP_LINK_REF 463U 390 + /** @brief Link clock input from DP macro brick PLL */ 391 + #define TEGRA234_CLK_SOR_LINKA_INPUT 464U 392 + /** @brief SOR AFIFO clock outut */ 393 + #define TEGRA234_CLK_SOR_LINKA_AFIFO 465U 394 + /** @brief Monitored branch of linka_afifo_clk */ 395 + #define TEGRA234_CLK_SOR_LINKA_AFIFO_M 466U 396 + /** @brief Monitored branch of rg0_pclk */ 397 + #define TEGRA234_CLK_RG0_M 467U 398 + /** @brief Monitored branch of rg1_pclk */ 399 + #define TEGRA234_CLK_RG1_M 468U 400 + /** @brief Monitored branch of sor0_clk */ 401 + #define TEGRA234_CLK_SOR0_M 469U 402 + /** @brief Monitored branch of sor1_clk */ 403 + #define TEGRA234_CLK_SOR1_M 470U 404 + /** @brief EMC PLLHUB output */ 405 + #define TEGRA234_CLK_PLLHUB 471U 406 + /** @brief output of fixed (DIV2) MC HUB divider */ 407 + #define TEGRA234_CLK_MCHUB 472U 408 + /** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */ 409 + #define TEGRA234_CLK_EMCSA_MC 473U 410 + /** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */ 411 + #define TEGRA234_CLK_EMCSB_MC 474U 412 + /** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */ 413 + #define TEGRA234_CLK_EMCSC_MC 475U 414 + /** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */ 415 + #define TEGRA234_CLK_EMCSD_MC 476U 416 + 417 + /** @} */ 765 418 766 419 #endif
+416 -23
include/dt-bindings/memory/tegra234-mc.h
··· 8 8 #define TEGRA234_SID_INVALID 0x00 9 9 #define TEGRA234_SID_PASSTHROUGH 0x7f 10 10 11 + /* ISO stream IDs */ 12 + #define TEGRA234_SID_ISO_NVDISPLAY 0x01 13 + #define TEGRA234_SID_ISO_VI 0x02 14 + #define TEGRA234_SID_ISO_VIFALC 0x03 15 + #define TEGRA234_SID_ISO_VI2 0x04 16 + #define TEGRA234_SID_ISO_VI2FALC 0x05 17 + #define TEGRA234_SID_ISO_VI_VM2 0x06 18 + #define TEGRA234_SID_ISO_VI2_VM2 0x07 19 + 11 20 /* NISO0 stream IDs */ 12 - #define TEGRA234_SID_APE 0x02 13 - #define TEGRA234_SID_HDA 0x03 14 - #define TEGRA234_SID_GPCDMA 0x04 15 - #define TEGRA234_SID_MGBE 0x06 16 - #define TEGRA234_SID_PCIE0 0x12 17 - #define TEGRA234_SID_PCIE4 0x13 18 - #define TEGRA234_SID_PCIE5 0x14 19 - #define TEGRA234_SID_PCIE6 0x15 20 - #define TEGRA234_SID_PCIE9 0x1f 21 - #define TEGRA234_SID_MGBE_VF1 0x49 22 - #define TEGRA234_SID_MGBE_VF2 0x4a 23 - #define TEGRA234_SID_MGBE_VF3 0x4b 21 + #define TEGRA234_SID_AON 0x01 22 + #define TEGRA234_SID_APE 0x02 23 + #define TEGRA234_SID_HDA 0x03 24 + #define TEGRA234_SID_GPCDMA 0x04 25 + #define TEGRA234_SID_ETR 0x05 26 + #define TEGRA234_SID_MGBE 0x06 27 + #define TEGRA234_SID_NVDISPLAY 0x07 28 + #define TEGRA234_SID_DCE 0x08 29 + #define TEGRA234_SID_PSC 0x09 30 + #define TEGRA234_SID_RCE 0x0a 31 + #define TEGRA234_SID_SCE 0x0b 32 + #define TEGRA234_SID_UFSHC 0x0c 33 + #define TEGRA234_SID_APE_1 0x0d 34 + #define TEGRA234_SID_GPCDMA_1 0x0e 35 + #define TEGRA234_SID_GPCDMA_2 0x0f 36 + #define TEGRA234_SID_GPCDMA_3 0x10 37 + #define TEGRA234_SID_GPCDMA_4 0x11 38 + #define TEGRA234_SID_PCIE0 0x12 39 + #define TEGRA234_SID_PCIE4 0x13 40 + #define TEGRA234_SID_PCIE5 0x14 41 + #define TEGRA234_SID_PCIE6 0x15 42 + #define TEGRA234_SID_RCE_VM2 0x16 43 + #define TEGRA234_SID_RCE_SERVER 0x17 44 + #define TEGRA234_SID_SMMU_TEST 0x18 45 + #define TEGRA234_SID_UFS_1 0x19 46 + #define TEGRA234_SID_UFS_2 0x1a 47 + #define TEGRA234_SID_UFS_3 0x1b 48 + #define TEGRA234_SID_UFS_4 0x1c 49 + #define TEGRA234_SID_UFS_5 0x1d 50 + #define TEGRA234_SID_UFS_6 0x1e 51 + #define TEGRA234_SID_PCIE9 0x1f 52 + #define TEGRA234_SID_VSE_GPCDMA_VM0 0x20 53 + #define TEGRA234_SID_VSE_GPCDMA_VM1 0x21 54 + #define TEGRA234_SID_VSE_GPCDMA_VM2 0x22 55 + #define TEGRA234_SID_NVDLA1 0x23 56 + #define TEGRA234_SID_NVENC 0x24 57 + #define TEGRA234_SID_NVJPG1 0x25 58 + #define TEGRA234_SID_OFA 0x26 59 + #define TEGRA234_SID_MGBE_VF1 0x49 60 + #define TEGRA234_SID_MGBE_VF2 0x4a 61 + #define TEGRA234_SID_MGBE_VF3 0x4b 62 + #define TEGRA234_SID_MGBE_VF4 0x4c 63 + #define TEGRA234_SID_MGBE_VF5 0x4d 64 + #define TEGRA234_SID_MGBE_VF6 0x4e 65 + #define TEGRA234_SID_MGBE_VF7 0x4f 66 + #define TEGRA234_SID_MGBE_VF8 0x50 67 + #define TEGRA234_SID_MGBE_VF9 0x51 68 + #define TEGRA234_SID_MGBE_VF10 0x52 69 + #define TEGRA234_SID_MGBE_VF11 0x53 70 + #define TEGRA234_SID_MGBE_VF12 0x54 71 + #define TEGRA234_SID_MGBE_VF13 0x55 72 + #define TEGRA234_SID_MGBE_VF14 0x56 73 + #define TEGRA234_SID_MGBE_VF15 0x57 74 + #define TEGRA234_SID_MGBE_VF16 0x58 75 + #define TEGRA234_SID_MGBE_VF17 0x59 76 + #define TEGRA234_SID_MGBE_VF18 0x5a 77 + #define TEGRA234_SID_MGBE_VF19 0x5b 78 + #define TEGRA234_SID_MGBE_VF20 0x5c 79 + #define TEGRA234_SID_APE_2 0x5e 80 + #define TEGRA234_SID_APE_3 0x5f 81 + #define TEGRA234_SID_UFS_7 0x60 82 + #define TEGRA234_SID_UFS_8 0x61 83 + #define TEGRA234_SID_UFS_9 0x62 84 + #define TEGRA234_SID_UFS_10 0x63 85 + #define TEGRA234_SID_UFS_11 0x64 86 + #define TEGRA234_SID_UFS_12 0x65 87 + #define TEGRA234_SID_UFS_13 0x66 88 + #define TEGRA234_SID_UFS_14 0x67 89 + #define TEGRA234_SID_UFS_15 0x68 90 + #define TEGRA234_SID_UFS_16 0x69 91 + #define TEGRA234_SID_UFS_17 0x6a 92 + #define TEGRA234_SID_UFS_18 0x6b 93 + #define TEGRA234_SID_UFS_19 0x6c 94 + #define TEGRA234_SID_UFS_20 0x6d 95 + #define TEGRA234_SID_GPCDMA_5 0x6e 96 + #define TEGRA234_SID_GPCDMA_6 0x6f 97 + #define TEGRA234_SID_GPCDMA_7 0x70 98 + #define TEGRA234_SID_GPCDMA_8 0x71 99 + #define TEGRA234_SID_GPCDMA_9 0x72 24 100 25 101 /* NISO1 stream IDs */ 26 - #define TEGRA234_SID_SDMMC4 0x02 27 - #define TEGRA234_SID_PCIE1 0x05 28 - #define TEGRA234_SID_PCIE2 0x06 29 - #define TEGRA234_SID_PCIE3 0x07 30 - #define TEGRA234_SID_PCIE7 0x08 31 - #define TEGRA234_SID_PCIE8 0x09 32 - #define TEGRA234_SID_PCIE10 0x0b 33 - #define TEGRA234_SID_BPMP 0x10 34 - #define TEGRA234_SID_HOST1X 0x27 35 - #define TEGRA234_SID_NVDEC 0x29 36 - #define TEGRA234_SID_VIC 0x34 102 + #define TEGRA234_SID_SDMMC1A 0x01 103 + #define TEGRA234_SID_SDMMC4 0x02 104 + #define TEGRA234_SID_EQOS 0x03 105 + #define TEGRA234_SID_HWMP_PMA 0x04 106 + #define TEGRA234_SID_PCIE1 0x05 107 + #define TEGRA234_SID_PCIE2 0x06 108 + #define TEGRA234_SID_PCIE3 0x07 109 + #define TEGRA234_SID_PCIE7 0x08 110 + #define TEGRA234_SID_PCIE8 0x09 111 + #define TEGRA234_SID_PCIE10 0x0b 112 + #define TEGRA234_SID_QSPI0 0x0c 113 + #define TEGRA234_SID_QSPI1 0x0d 114 + #define TEGRA234_SID_XUSB_HOST 0x0e 115 + #define TEGRA234_SID_XUSB_DEV 0x0f 116 + #define TEGRA234_SID_BPMP 0x10 117 + #define TEGRA234_SID_FSI 0x11 118 + #define TEGRA234_SID_PVA0_VM0 0x12 119 + #define TEGRA234_SID_PVA0_VM1 0x13 120 + #define TEGRA234_SID_PVA0_VM2 0x14 121 + #define TEGRA234_SID_PVA0_VM3 0x15 122 + #define TEGRA234_SID_PVA0_VM4 0x16 123 + #define TEGRA234_SID_PVA0_VM5 0x17 124 + #define TEGRA234_SID_PVA0_VM6 0x18 125 + #define TEGRA234_SID_PVA0_VM7 0x19 126 + #define TEGRA234_SID_XUSB_VF0 0x1a 127 + #define TEGRA234_SID_XUSB_VF1 0x1b 128 + #define TEGRA234_SID_XUSB_VF2 0x1c 129 + #define TEGRA234_SID_XUSB_VF3 0x1d 130 + #define TEGRA234_SID_EQOS_VF1 0x1e 131 + #define TEGRA234_SID_EQOS_VF2 0x1f 132 + #define TEGRA234_SID_EQOS_VF3 0x20 133 + #define TEGRA234_SID_EQOS_VF4 0x21 134 + #define TEGRA234_SID_ISP_VM2 0x22 135 + #define TEGRA234_SID_HOST1X 0x27 136 + #define TEGRA234_SID_ISP 0x28 137 + #define TEGRA234_SID_NVDEC 0x29 138 + #define TEGRA234_SID_NVJPG 0x2a 139 + #define TEGRA234_SID_NVDLA0 0x2b 140 + #define TEGRA234_SID_PVA0 0x2c 141 + #define TEGRA234_SID_SES_SE0 0x2d 142 + #define TEGRA234_SID_SES_SE1 0x2e 143 + #define TEGRA234_SID_SES_SE2 0x2f 144 + #define TEGRA234_SID_SEU1_SE0 0x30 145 + #define TEGRA234_SID_SEU1_SE1 0x31 146 + #define TEGRA234_SID_SEU1_SE2 0x32 147 + #define TEGRA234_SID_TSEC 0x33 148 + #define TEGRA234_SID_VIC 0x34 149 + #define TEGRA234_SID_HC_VM0 0x3d 150 + #define TEGRA234_SID_HC_VM1 0x3e 151 + #define TEGRA234_SID_HC_VM2 0x3f 152 + #define TEGRA234_SID_HC_VM3 0x40 153 + #define TEGRA234_SID_HC_VM4 0x41 154 + #define TEGRA234_SID_HC_VM5 0x42 155 + #define TEGRA234_SID_HC_VM6 0x43 156 + #define TEGRA234_SID_HC_VM7 0x44 157 + #define TEGRA234_SID_SE_VM0 0x45 158 + #define TEGRA234_SID_SE_VM1 0x46 159 + #define TEGRA234_SID_SE_VM2 0x47 160 + #define TEGRA234_SID_ISPFALC 0x48 161 + #define TEGRA234_SID_NISO1_SMMU_TEST 0x49 162 + #define TEGRA234_SID_TSEC_VM0 0x4a 37 163 38 164 /* Shared stream IDs */ 39 165 #define TEGRA234_SID_HOST1X_CTX0 0x35 ··· 175 49 * memory client IDs 176 50 */ 177 51 52 + /* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */ 53 + #define TEGRA234_MEMORY_CLIENT_PTCR 0x00 54 + /* MSS internal memqual MIU7 read clients */ 55 + #define TEGRA234_MEMORY_CLIENT_MIU7R 0x01 56 + /* MSS internal memqual MIU7 write clients */ 57 + #define TEGRA234_MEMORY_CLIENT_MIU7W 0x02 58 + /* MSS internal memqual MIU8 read clients */ 59 + #define TEGRA234_MEMORY_CLIENT_MIU8R 0x03 60 + /* MSS internal memqual MIU8 write clients */ 61 + #define TEGRA234_MEMORY_CLIENT_MIU8W 0x04 62 + /* MSS internal memqual MIU9 read clients */ 63 + #define TEGRA234_MEMORY_CLIENT_MIU9R 0x05 64 + /* MSS internal memqual MIU9 write clients */ 65 + #define TEGRA234_MEMORY_CLIENT_MIU9W 0x06 66 + /* MSS internal memqual MIU10 read clients */ 67 + #define TEGRA234_MEMORY_CLIENT_MIU10R 0x07 68 + /* MSS internal memqual MIU10 write clients */ 69 + #define TEGRA234_MEMORY_CLIENT_MIU10W 0x08 70 + /* MSS internal memqual MIU11 read clients */ 71 + #define TEGRA234_MEMORY_CLIENT_MIU11R 0x09 72 + /* MSS internal memqual MIU11 write clients */ 73 + #define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a 74 + /* MSS internal memqual MIU12 read clients */ 75 + #define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b 76 + /* MSS internal memqual MIU12 write clients */ 77 + #define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c 78 + /* MSS internal memqual MIU13 read clients */ 79 + #define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d 80 + /* MSS internal memqual MIU13 write clients */ 81 + #define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e 82 + #define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13 83 + #define TEGRA234_MEMORY_CLIENT_NVL5R 0x14 178 84 /* High-definition audio (HDA) read clients */ 179 85 #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 86 + /* Host channel data read clients */ 180 87 #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 88 + #define TEGRA234_MEMORY_CLIENT_NVL5W 0x17 89 + #define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18 90 + #define TEGRA234_MEMORY_CLIENT_NVL6R 0x19 91 + #define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a 92 + #define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b 93 + #define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c 94 + #define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d 95 + #define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e 96 + #define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20 97 + #define TEGRA234_MEMORY_CLIENT_NVL8R 0x21 98 + #define TEGRA234_MEMORY_CLIENT_NVL8W 0x22 99 + #define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23 100 + #define TEGRA234_MEMORY_CLIENT_NVL9R 0x24 101 + #define TEGRA234_MEMORY_CLIENT_NVL9W 0x25 181 102 /* PCIE6 read clients */ 182 103 #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 183 104 /* PCIE6 write clients */ 184 105 #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 185 106 /* PCIE7 read clients */ 186 107 #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a 108 + #define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b 109 + /* DLA0ARDB read clients */ 110 + #define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c 111 + /* DLA0ARDB1 read clients */ 112 + #define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d 113 + /* DLA0 writes */ 114 + #define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e 115 + /* DLA1ARDB read clients */ 116 + #define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f 187 117 /* PCIE7 write clients */ 188 118 #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 189 119 /* PCIE8 read clients */ 190 120 #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 191 121 /* High-definition audio (HDA) write clients */ 192 122 #define TEGRA234_MEMORY_CLIENT_HDAW 0x35 123 + /* Writes from Cortex-A9 4 CPU cores via the L2 cache */ 124 + #define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39 125 + /* OFAA client */ 126 + #define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a 193 127 /* PCIE8 write clients */ 194 128 #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b 195 129 /* PCIE9 read clients */ ··· 262 76 #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f 263 77 /* PCIE10 write clients */ 264 78 #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 79 + /* ISP read client for Crossbar A */ 80 + #define TEGRA234_MEMORY_CLIENT_ISPRA 0x44 81 + /* ISP read client 1 for Crossbar A */ 82 + #define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45 83 + /* ISP Write client for Crossbar A */ 84 + #define TEGRA234_MEMORY_CLIENT_ISPWA 0x46 85 + /* ISP Write client Crossbar B */ 86 + #define TEGRA234_MEMORY_CLIENT_ISPWB 0x47 265 87 /* PCIE10r1 read clients */ 266 88 #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 267 89 /* PCIE7r1 read clients */ 268 90 #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 91 + /* XUSB_HOST read clients */ 92 + #define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a 93 + /* XUSB_HOST write clients */ 94 + #define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b 95 + /* XUSB read clients */ 96 + #define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c 97 + /* XUSB_DEV write clients */ 98 + #define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d 99 + /* TSEC Memory Return Data Client Description */ 100 + #define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54 101 + /* TSEC Memory Write Client Description */ 102 + #define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55 103 + /* XSPI writes */ 104 + #define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56 269 105 /* MGBE0 read client */ 270 106 #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 271 107 /* MGBEB read client */ ··· 298 90 #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b 299 91 /* MGBE0 write client */ 300 92 #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c 93 + /* OFAA client */ 94 + #define TEGRA234_MEMORY_CLIENT_OFAR 0x5d 95 + /* OFAA writes */ 96 + #define TEGRA234_MEMORY_CLIENT_OFAW 0x5e 301 97 /* MGBEB write client */ 302 98 #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f 99 + /* sdmmca memory read client */ 100 + #define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60 303 101 /* MGBEC write client */ 304 102 #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 305 103 /* sdmmcd memory read client */ 306 104 #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 105 + /* sdmmca memory write client */ 106 + #define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64 307 107 /* MGBED write client */ 308 108 #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 309 109 /* sdmmcd memory write client */ 310 110 #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 111 + /* SE Memory Return Data Client Description */ 112 + #define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68 113 + /* SE Memory Write Client Description */ 114 + #define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69 311 115 #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c 312 116 #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d 117 + /* DLA1ARDB1 read clients */ 118 + #define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e 119 + /* DLA1 writes */ 120 + #define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f 121 + /* VI FLACON read clients */ 122 + #define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71 123 + /* VI Write client */ 124 + #define TEGRA234_MEMORY_CLIENT_VI2W 0x70 125 + /* VI Write client */ 126 + #define TEGRA234_MEMORY_CLIENT_VIW 0x72 127 + /* NISO display read client */ 128 + #define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73 129 + /* NVDISPNISO writes */ 130 + #define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74 131 + /* XSPI client */ 132 + #define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75 133 + /* XSPI writes */ 134 + #define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76 135 + /* XSPI client */ 136 + #define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77 313 137 #define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 314 138 #define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 139 + /* Audio Processing (APE) engine read clients */ 140 + #define TEGRA234_MEMORY_CLIENT_APER 0x7a 141 + /* Audio Processing (APE) engine write clients */ 142 + #define TEGRA234_MEMORY_CLIENT_APEW 0x7b 143 + /* VI2FAL writes */ 144 + #define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c 145 + #define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e 146 + #define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f 147 + /* SE Memory Return Data Client Description */ 148 + #define TEGRA234_MEMORY_CLIENT_SESRD 0x80 149 + /* SE Memory Write Client Description */ 150 + #define TEGRA234_MEMORY_CLIENT_SESWR 0x81 151 + /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */ 152 + #define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82 153 + /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */ 154 + #define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83 155 + /* ETR read clients */ 156 + #define TEGRA234_MEMORY_CLIENT_ETRR 0x84 157 + /* ETR write clients */ 158 + #define TEGRA234_MEMORY_CLIENT_ETRW 0x85 159 + /* AXI Switch read client */ 160 + #define TEGRA234_MEMORY_CLIENT_AXISR 0x8c 161 + /* AXI Switch write client */ 162 + #define TEGRA234_MEMORY_CLIENT_AXISW 0x8d 163 + /* EQOS read client */ 164 + #define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e 165 + /* EQOS write client */ 166 + #define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f 167 + /* UFSHC read client */ 168 + #define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90 169 + /* UFSHC write client */ 170 + #define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91 171 + /* NVDISPLAY read client */ 172 + #define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92 315 173 /* BPMP read client */ 316 174 #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 317 175 /* BPMP write client */ ··· 386 112 #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 387 113 /* BPMPDMA write client */ 388 114 #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 115 + /* AON read client */ 116 + #define TEGRA234_MEMORY_CLIENT_AONR 0x97 117 + /* AON write client */ 118 + #define TEGRA234_MEMORY_CLIENT_AONW 0x98 119 + /* AONDMA read client */ 120 + #define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99 121 + /* AONDMA write client */ 122 + #define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a 123 + /* SCE read client */ 124 + #define TEGRA234_MEMORY_CLIENT_SCER 0x9b 125 + /* SCE write client */ 126 + #define TEGRA234_MEMORY_CLIENT_SCEW 0x9c 127 + /* SCEDMA read client */ 128 + #define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d 129 + /* SCEDMA write client */ 130 + #define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e 389 131 /* APEDMA read client */ 390 132 #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f 391 133 /* APEDMA write client */ 392 134 #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 135 + /* NVDISPLAY read client instance 2 */ 136 + #define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1 137 + #define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2 138 + /* MSS internal memqual MIU0 read clients */ 139 + #define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6 140 + /* MSS internal memqual MIU0 write clients */ 141 + #define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7 142 + /* MSS internal memqual MIU1 read clients */ 143 + #define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8 144 + /* MSS internal memqual MIU1 write clients */ 145 + #define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9 146 + /* MSS internal memqual MIU2 read clients */ 147 + #define TEGRA234_MEMORY_CLIENT_MIU2R 0xae 148 + /* MSS internal memqual MIU2 write clients */ 149 + #define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf 150 + /* MSS internal memqual MIU3 read clients */ 151 + #define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0 152 + /* MSS internal memqual MIU3 write clients */ 153 + #define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1 154 + /* MSS internal memqual MIU4 read clients */ 155 + #define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2 156 + /* MSS internal memqual MIU4 write clients */ 157 + #define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3 158 + #define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4 159 + #define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5 160 + #define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6 161 + #define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7 162 + #define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8 163 + #define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9 164 + #define TEGRA234_MEMORY_CLIENT_NVL2R 0xba 165 + #define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb 166 + /* VI FLACON read clients */ 167 + #define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc 168 + /* VIFAL write clients */ 169 + #define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd 170 + /* DLA0ARDA read clients */ 171 + #define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe 172 + /* DLA0 Falcon read clients */ 173 + #define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf 174 + /* DLA0 write clients */ 175 + #define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 176 + /* DLA0 write clients */ 177 + #define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 178 + /* DLA1ARDA read clients */ 179 + #define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 180 + /* DLA1 Falcon read clients */ 181 + #define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 182 + /* DLA1 write clients */ 183 + #define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 184 + /* DLA1 write clients */ 185 + #define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 186 + /* PVA0RDA read clients */ 187 + #define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 188 + /* PVA0RDB read clients */ 189 + #define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 190 + /* PVA0RDC read clients */ 191 + #define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 192 + /* PVA0WRA write clients */ 193 + #define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 194 + /* PVA0WRB write clients */ 195 + #define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca 196 + /* PVA0WRC write clients */ 197 + #define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb 198 + /* RCE read client */ 199 + #define TEGRA234_MEMORY_CLIENT_RCER 0xd2 200 + /* RCE write client */ 201 + #define TEGRA234_MEMORY_CLIENT_RCEW 0xd3 202 + /* RCEDMA read client */ 203 + #define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4 204 + /* RCEDMA write client */ 205 + #define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5 393 206 /* PCIE0 read clients */ 394 207 #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 395 208 /* PCIE0 write clients */ ··· 501 140 #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 502 141 /* PCIE5 write clients */ 503 142 #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 143 + /* ISP read client 1 for Crossbar A */ 144 + #define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4 145 + #define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5 146 + #define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6 147 + #define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7 148 + #define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8 149 + /* DLA0ARDA1 read clients */ 150 + #define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 151 + /* DLA1ARDA1 read clients */ 152 + #define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea 153 + /* PVA0RDA1 read clients */ 154 + #define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb 155 + /* PVA0RDB1 read clients */ 156 + #define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec 504 157 /* PCIE5r1 read clients */ 505 158 #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef 159 + #define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 160 + /* ISP read client for Crossbar A */ 161 + #define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2 162 + #define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4 163 + #define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5 164 + #define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6 165 + #define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7 166 + #define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8 167 + /* MSS internal memqual MIU5 read clients */ 168 + #define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc 169 + /* MSS internal memqual MIU5 write clients */ 170 + #define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd 171 + /* MSS internal memqual MIU6 read clients */ 172 + #define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe 173 + /* MSS internal memqual MIU6 write clients */ 174 + #define TEGRA234_MEMORY_CLIENT_MIU6W 0xff 175 + #define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 176 + #define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 506 177 507 178 #endif
+14
include/dt-bindings/power/tegra234-powergate.h
··· 4 4 #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ 5 5 #define __ABI_MACH_T234_POWERGATE_T234_H_ 6 6 7 + #define TEGRA234_POWER_DOMAIN_OFA 1U 7 8 #define TEGRA234_POWER_DOMAIN_AUD 2U 8 9 #define TEGRA234_POWER_DOMAIN_DISP 3U 9 10 #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U ··· 12 11 #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U 13 12 #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U 14 13 #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U 14 + #define TEGRA234_POWER_DOMAIN_XUSBA 10U 15 + #define TEGRA234_POWER_DOMAIN_XUSBB 11U 16 + #define TEGRA234_POWER_DOMAIN_XUSBC 12U 15 17 #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U 16 18 #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U 17 19 #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U ··· 23 19 #define TEGRA234_POWER_DOMAIN_MGBEB 18U 24 20 #define TEGRA234_POWER_DOMAIN_MGBEC 19U 25 21 #define TEGRA234_POWER_DOMAIN_MGBED 20U 22 + #define TEGRA234_POWER_DOMAIN_ISPA 22U 26 23 #define TEGRA234_POWER_DOMAIN_NVDEC 23U 24 + #define TEGRA234_POWER_DOMAIN_NVJPGA 24U 25 + #define TEGRA234_POWER_DOMAIN_NVENC 25U 26 + #define TEGRA234_POWER_DOMAIN_VI 28U 27 27 #define TEGRA234_POWER_DOMAIN_VIC 29U 28 + #define TEGRA234_POWER_DOMAIN_PVA 30U 29 + #define TEGRA234_POWER_DOMAIN_DLAA 32U 30 + #define TEGRA234_POWER_DOMAIN_DLAB 33U 31 + #define TEGRA234_POWER_DOMAIN_CV 34U 32 + #define TEGRA234_POWER_DOMAIN_GPU 35U 33 + #define TEGRA234_POWER_DOMAIN_NVJPGB 36U 28 34 29 35 #endif
+109 -1
include/dt-bindings/reset/tegra234-reset.h
··· 10 10 * @brief Identifiers for Resets controllable by firmware 11 11 * @{ 12 12 */ 13 + #define TEGRA234_RESET_ACTMON 1U 14 + #define TEGRA234_RESET_ADSP_ALL 2U 15 + #define TEGRA234_RESET_DSI_CORE 3U 16 + #define TEGRA234_RESET_CAN1 4U 17 + #define TEGRA234_RESET_CAN2 5U 18 + #define TEGRA234_RESET_DLA0 6U 19 + #define TEGRA234_RESET_DLA1 7U 20 + #define TEGRA234_RESET_DPAUX 8U 21 + #define TEGRA234_RESET_OFA 9U 22 + #define TEGRA234_RESET_NVJPG1 10U 13 23 #define TEGRA234_RESET_PEX1_CORE_6 11U 14 24 #define TEGRA234_RESET_PEX1_CORE_6_APB 12U 15 25 #define TEGRA234_RESET_PEX1_COMMON_APB 13U 16 26 #define TEGRA234_RESET_PEX2_CORE_7 14U 17 27 #define TEGRA234_RESET_PEX2_CORE_7_APB 15U 28 + #define TEGRA234_RESET_NVDISPLAY 16U 29 + #define TEGRA234_RESET_EQOS 17U 18 30 #define TEGRA234_RESET_GPCDMA 18U 31 + #define TEGRA234_RESET_GPU 19U 19 32 #define TEGRA234_RESET_HDA 20U 20 33 #define TEGRA234_RESET_HDACODEC 21U 34 + #define TEGRA234_RESET_EQOS_MACSEC 22U 35 + #define TEGRA234_RESET_EQOS_MACSEC_SECURE 23U 21 36 #define TEGRA234_RESET_I2C1 24U 22 37 #define TEGRA234_RESET_PEX2_CORE_8 25U 23 38 #define TEGRA234_RESET_PEX2_CORE_8_APB 26U ··· 45 30 #define TEGRA234_RESET_I2C7 33U 46 31 #define TEGRA234_RESET_I2C8 34U 47 32 #define TEGRA234_RESET_I2C9 35U 33 + #define TEGRA234_RESET_ISP 36U 34 + #define TEGRA234_RESET_MIPI_CAL 37U 35 + #define TEGRA234_RESET_MPHY_CLK_CTL 38U 36 + #define TEGRA234_RESET_MPHY_L0_RX 39U 37 + #define TEGRA234_RESET_MPHY_L0_TX 40U 38 + #define TEGRA234_RESET_MPHY_L1_RX 41U 39 + #define TEGRA234_RESET_MPHY_L1_TX 42U 40 + #define TEGRA234_RESET_NVCSI 43U 48 41 #define TEGRA234_RESET_NVDEC 44U 49 42 #define TEGRA234_RESET_MGBE0_PCS 45U 50 43 #define TEGRA234_RESET_MGBE0_MAC 46U 44 + #define TEGRA234_RESET_MGBE0_MACSEC 47U 45 + #define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48U 51 46 #define TEGRA234_RESET_MGBE1_PCS 49U 52 47 #define TEGRA234_RESET_MGBE1_MAC 50U 48 + #define TEGRA234_RESET_MGBE1_MACSEC 51U 49 + #define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52U 53 50 #define TEGRA234_RESET_MGBE2_PCS 53U 54 51 #define TEGRA234_RESET_MGBE2_MAC 54U 52 + #define TEGRA234_RESET_MGBE2_MACSEC 55U 55 53 #define TEGRA234_RESET_PEX2_CORE_10 56U 56 54 #define TEGRA234_RESET_PEX2_CORE_10_APB 57U 57 55 #define TEGRA234_RESET_PEX2_COMMON_APB 58U 56 + #define TEGRA234_RESET_NVENC 59U 57 + #define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60U 58 + #define TEGRA234_RESET_NVJPG 61U 59 + #define TEGRA234_RESET_LA 64U 60 + #define TEGRA234_RESET_HWPM 65U 61 + #define TEGRA234_RESET_PVA0_ALL 66U 62 + #define TEGRA234_RESET_CEC 67U 58 63 #define TEGRA234_RESET_PWM1 68U 59 64 #define TEGRA234_RESET_PWM2 69U 60 65 #define TEGRA234_RESET_PWM3 70U ··· 85 50 #define TEGRA234_RESET_PWM8 75U 86 51 #define TEGRA234_RESET_QSPI0 76U 87 52 #define TEGRA234_RESET_QSPI1 77U 53 + #define TEGRA234_RESET_I2S7 78U 54 + #define TEGRA234_RESET_I2S8 79U 55 + #define TEGRA234_RESET_SCE_ALL 80U 56 + #define TEGRA234_RESET_RCE_ALL 81U 57 + #define TEGRA234_RESET_SDMMC1 82U 58 + #define TEGRA234_RESET_RSVD_83 83U 59 + #define TEGRA234_RESET_RSVD_84 84U 88 60 #define TEGRA234_RESET_SDMMC4 85U 89 61 #define TEGRA234_RESET_MGBE3_PCS 87U 90 62 #define TEGRA234_RESET_MGBE3_MAC 88U 63 + #define TEGRA234_RESET_MGBE3_MACSEC 89U 64 + #define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90U 65 + #define TEGRA234_RESET_SPI1 91U 66 + #define TEGRA234_RESET_SPI2 92U 67 + #define TEGRA234_RESET_SPI3 93U 68 + #define TEGRA234_RESET_SPI4 94U 69 + #define TEGRA234_RESET_TACH0 95U 70 + #define TEGRA234_RESET_TACH1 96U 71 + #define TEGRA234_RESET_SPI5 97U 72 + #define TEGRA234_RESET_TSEC 98U 73 + #define TEGRA234_RESET_UARTI 99U 91 74 #define TEGRA234_RESET_UARTA 100U 92 - #define TEGRA234_RESET_VIC 113U 75 + #define TEGRA234_RESET_UARTB 101U 76 + #define TEGRA234_RESET_UARTC 102U 77 + #define TEGRA234_RESET_UARTD 103U 78 + #define TEGRA234_RESET_UARTE 104U 79 + #define TEGRA234_RESET_UARTF 105U 80 + #define TEGRA234_RESET_UARTJ 106U 81 + #define TEGRA234_RESET_UARTH 107U 82 + #define TEGRA234_RESET_UFSHC 108U 83 + #define TEGRA234_RESET_UFSHC_AXI_M 109U 84 + #define TEGRA234_RESET_UFSHC_LP_SEQ 110U 85 + #define TEGRA234_RESET_RSVD_111 111U 86 + #define TEGRA234_RESET_VI 112U 87 + #define TEGRA234_RESET_VIC 113U 88 + #define TEGRA234_RESET_XUSB_PADCTL 114U 89 + #define TEGRA234_RESET_VI2 115U 93 90 #define TEGRA234_RESET_PEX0_CORE_0 116U 94 91 #define TEGRA234_RESET_PEX0_CORE_1 117U 95 92 #define TEGRA234_RESET_PEX0_CORE_2 118U ··· 133 66 #define TEGRA234_RESET_PEX0_CORE_3_APB 124U 134 67 #define TEGRA234_RESET_PEX0_CORE_4_APB 125U 135 68 #define TEGRA234_RESET_PEX0_COMMON_APB 126U 69 + #define TEGRA234_RESET_RSVD_127 127U 70 + #define TEGRA234_RESET_NVHS_UPHY_PLL1 128U 136 71 #define TEGRA234_RESET_PEX1_CORE_5 129U 137 72 #define TEGRA234_RESET_PEX1_CORE_5_APB 130U 73 + #define TEGRA234_RESET_GBE_UPHY 131U 74 + #define TEGRA234_RESET_GBE_UPHY_PM 132U 75 + #define TEGRA234_RESET_NVHS_UPHY 133U 76 + #define TEGRA234_RESET_NVHS_UPHY_PLL0 134U 77 + #define TEGRA234_RESET_NVHS_UPHY_L0 135U 78 + #define TEGRA234_RESET_NVHS_UPHY_L1 136U 79 + #define TEGRA234_RESET_NVHS_UPHY_L2 137U 80 + #define TEGRA234_RESET_NVHS_UPHY_L3 138U 81 + #define TEGRA234_RESET_NVHS_UPHY_L4 139U 82 + #define TEGRA234_RESET_NVHS_UPHY_L5 140U 83 + #define TEGRA234_RESET_NVHS_UPHY_L6 141U 84 + #define TEGRA234_RESET_NVHS_UPHY_L7 142U 85 + #define TEGRA234_RESET_NVHS_UPHY_PM 143U 86 + #define TEGRA234_RESET_DMIC5 144U 87 + #define TEGRA234_RESET_APE 145U 88 + #define TEGRA234_RESET_PEX_USB_UPHY 146U 89 + #define TEGRA234_RESET_PEX_USB_UPHY_L0 147U 90 + #define TEGRA234_RESET_PEX_USB_UPHY_L1 148U 91 + #define TEGRA234_RESET_PEX_USB_UPHY_L2 149U 92 + #define TEGRA234_RESET_PEX_USB_UPHY_L3 150U 93 + #define TEGRA234_RESET_PEX_USB_UPHY_L4 151U 94 + #define TEGRA234_RESET_PEX_USB_UPHY_L5 152U 95 + #define TEGRA234_RESET_PEX_USB_UPHY_L6 153U 96 + #define TEGRA234_RESET_PEX_USB_UPHY_L7 154U 97 + #define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159U 98 + #define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160U 99 + #define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161U 100 + #define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162U 101 + #define TEGRA234_RESET_GBE_UPHY_L0 163U 102 + #define TEGRA234_RESET_GBE_UPHY_L1 164U 103 + #define TEGRA234_RESET_GBE_UPHY_L2 165U 104 + #define TEGRA234_RESET_GBE_UPHY_L3 166U 105 + #define TEGRA234_RESET_GBE_UPHY_L4 167U 106 + #define TEGRA234_RESET_GBE_UPHY_L5 168U 107 + #define TEGRA234_RESET_GBE_UPHY_L6 169U 108 + #define TEGRA234_RESET_GBE_UPHY_L7 170U 109 + #define TEGRA234_RESET_GBE_UPHY_PLL0 171U 110 + #define TEGRA234_RESET_GBE_UPHY_PLL1 172U 111 + #define TEGRA234_RESET_GBE_UPHY_PLL2 173U 138 112 139 113 /** @} */ 140 114