tjh.dev / kernel
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RDMA/irdma: Add support for V2 HMC resource management scheme

HMC resource initialization is updated to support V1 or V2 approach
based on the FW capability. In the V2 approach, driver receives the
assigned HMC resources count and verifies if it will fit in the given
local memory. If it doesn't fit, the driver load fails.

Signed-off-by: Vinoth Kumar Chandra Mohan <vinoth.kumar.chandra.mohan@intel.com>
Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com>
Link: https://patch.msgid.link/20250827152545.2056-11-tatyana.e.nikolova@intel.com
Tested-by: Jacob Moroni <jmoroni@google.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>

authored by

Vinoth Kumar Chandra Mohan and committed by
Leon Romanovsky 419afdd1 87f413b6

+130 -19
+118 -3
drivers/infiniband/hw/irdma/ctrl.c
··· 2902 2902 } 2903 2903 2904 2904 /** 2905 + * irdma_sc_get_decoded_ird_size_gen_3 - get decoded IRD size for GEN 3 2906 + * @ird_enc: IRD encoding 2907 + * IRD size defaults to a value of 4 in case of invalid input. 2908 + */ 2909 + static u16 irdma_sc_get_decoded_ird_size_gen_3(u8 ird_enc) 2910 + { 2911 + switch (ird_enc) { 2912 + case IRDMA_IRD_HW_SIZE_4096_GEN3: 2913 + return 4096; 2914 + case IRDMA_IRD_HW_SIZE_2048_GEN3: 2915 + return 2048; 2916 + case IRDMA_IRD_HW_SIZE_1024_GEN3: 2917 + return 1024; 2918 + case IRDMA_IRD_HW_SIZE_512_GEN3: 2919 + return 512; 2920 + case IRDMA_IRD_HW_SIZE_256_GEN3: 2921 + return 256; 2922 + case IRDMA_IRD_HW_SIZE_128_GEN3: 2923 + return 128; 2924 + case IRDMA_IRD_HW_SIZE_64_GEN3: 2925 + return 64; 2926 + case IRDMA_IRD_HW_SIZE_32_GEN3: 2927 + return 32; 2928 + case IRDMA_IRD_HW_SIZE_16_GEN3: 2929 + return 16; 2930 + case IRDMA_IRD_HW_SIZE_8_GEN3: 2931 + return 8; 2932 + case IRDMA_IRD_HW_SIZE_4_GEN3: 2933 + return 4; 2934 + default: 2935 + return 4; 2936 + } 2937 + } 2938 + 2939 + /** 2905 2940 * irdma_check_cqp_progress - check cqp processing progress 2906 2941 * @timeout: timeout info struct 2907 2942 * @dev: sc device struct ··· 3247 3212 struct irdma_hmc_fpm_misc *hmc_fpm_misc) 3248 3213 { 3249 3214 struct irdma_hmc_obj_info *obj_info; 3215 + u8 ird_encoding; 3250 3216 u64 temp; 3251 3217 u32 size; 3252 3218 u16 max_pe_sds; ··· 3323 3287 hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp); 3324 3288 hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp); 3325 3289 hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp); 3290 + if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, 3291 + dev->feature_info[IRDMA_FTN_FLAGS])) { 3292 + ird_encoding = (u8)FIELD_GET(IRDMA_QUERY_FPM_MAX_IRD, temp); 3293 + hmc_fpm_misc->ird = 3294 + irdma_sc_get_decoded_ird_size_gen_3(ird_encoding) / 2; 3295 + dev->hw_attrs.max_hw_ird = hmc_fpm_misc->ird; 3296 + dev->hw_attrs.max_hw_ord = hmc_fpm_misc->ird; 3297 + } 3326 3298 if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) 3327 3299 return 0; 3328 3300 irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC); ··· 5488 5444 avail_sds -= DIV_ROUND_UP(mrwanted, MAX_MR_PER_SD); 5489 5445 } 5490 5446 5447 + if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS]) && 5448 + pblewanted > avail_sds * MAX_PBLE_PER_SD) 5449 + ibdev_dbg(to_ibdev(dev), 5450 + "HMC: Warn: Resource version 2: pble wanted = 0x%x available = 0x%x\n", 5451 + pblewanted, avail_sds * MAX_PBLE_PER_SD); 5452 + 5491 5453 pblewanted = min(pblewanted, avail_sds * MAX_PBLE_PER_SD); 5492 5454 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; 5455 + } 5456 + 5457 + /** 5458 + * irdma_verify_commit_fpm_gen_3 - verify query fpm values 5459 + * @dev: sc device struct 5460 + * @max_pages: max local memory available 5461 + * @qpwanted: number of qp's wanted 5462 + */ 5463 + static int irdma_verify_commit_fpm_gen_3(struct irdma_sc_dev *dev, 5464 + u32 max_pages, 5465 + u32 qpwanted) 5466 + { 5467 + struct irdma_hmc_fpm_misc *hmc_fpm_misc; 5468 + u32 rrf_cnt, xf_cnt, timer_cnt, pages_needed; 5469 + struct irdma_hmc_info *hmc_info; 5470 + u32 rrffl_cnt = 0; 5471 + u32 xffl_cnt = 0; 5472 + u32 q1fl_cnt; 5473 + 5474 + hmc_info = dev->hmc_info; 5475 + hmc_fpm_misc = &dev->hmc_fpm_misc; 5476 + 5477 + rrf_cnt = roundup_pow_of_two(IRDMA_RRF_MULTIPLIER * qpwanted); 5478 + 5479 + if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) 5480 + rrffl_cnt = 5481 + hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / 5482 + hmc_fpm_misc->rrf_block_size; 5483 + 5484 + xf_cnt = roundup_pow_of_two(IRDMA_XF_MULTIPLIER * qpwanted); 5485 + 5486 + if (xf_cnt) 5487 + xffl_cnt = xf_cnt / hmc_fpm_misc->xf_block_size; 5488 + 5489 + timer_cnt = (round_up(qpwanted, 512) / 512 + 1) * 5490 + hmc_fpm_misc->timer_bucket; 5491 + 5492 + q1fl_cnt = hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; 5493 + 5494 + pages_needed = irdma_get_objs_pages(dev, hmc_info, IRDMA_LOC_MEM); 5495 + if (pages_needed > max_pages) { 5496 + ibdev_dbg(to_ibdev(dev), 5497 + "HMC: FAIL: SW counts rrf_cnt = %u rrffl_cnt = %u timer_cnt = %u", 5498 + rrf_cnt, rrffl_cnt, timer_cnt); 5499 + ibdev_dbg(to_ibdev(dev), 5500 + "HMC: FAIL: SW counts xf_cnt = %u xffl_cnt = %u q1fl_cnt = %u", 5501 + xf_cnt, xffl_cnt, q1fl_cnt); 5502 + 5503 + return -EINVAL; 5504 + } 5505 + 5506 + hmc_fpm_misc->max_sds -= pages_needed; 5507 + hmc_fpm_misc->loc_mem_pages -= pages_needed; 5508 + 5509 + return 0; 5493 5510 } 5494 5511 5495 5512 /** ··· 5567 5462 u32 rrf_cnt, xf_cnt, timer_cnt, pages_needed; 5568 5463 struct irdma_hmc_info *hmc_info; 5569 5464 u32 ird, ord; 5465 + 5466 + if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5467 + return irdma_verify_commit_fpm_gen_3(dev, max_pages, qpwanted); 5570 5468 5571 5469 hmc_info = dev->hmc_info; 5572 5470 hmc_fpm_misc = &dev->hmc_fpm_misc; ··· 5671 5563 hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt = 0; 5672 5564 hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].max_cnt = 0; 5673 5565 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt = 0; 5674 - hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt = 5675 - min(hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt, 5676 - (u32)IRDMA_FSIAV_CNT_MAX); 5566 + 5567 + if (!FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5568 + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt = 5569 + min(hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt, 5570 + (u32)IRDMA_FSIAV_CNT_MAX); 5571 + 5677 5572 for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) 5678 5573 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; 5679 5574 5680 5575 while (qpwanted >= IRDMA_MIN_QP_CNT) { 5681 5576 if (!irdma_set_loc_hmc_rsrc_gen_3(dev, loc_mem_pages, qpwanted)) 5682 5577 break; 5578 + 5579 + if (FIELD_GET(IRDMA_MANAGE_RSRC_VER2, dev->feature_info[IRDMA_FTN_FLAGS])) 5580 + return -EINVAL; 5683 5581 5684 5582 qpwanted /= 2; 5685 5583 if (mrte_loc == IRDMA_LOC_MEM) { ··· 5773 5659 hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt, 5774 5660 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt, 5775 5661 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); 5662 + 5776 5663 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt = 5777 5664 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt; 5778 5665 hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt =
+3
drivers/infiniband/hw/irdma/defs.h
··· 757 757 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0) 758 758 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0) 759 759 #define IRDMA_CQPSQ_RESUMEQP_QPID GENMASK(23, 0) 760 + #define IRDMA_MANAGE_RSRC_VER2 BIT_ULL(2) 760 761 761 762 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001 762 763 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005 ··· 910 909 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0) 911 910 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32) 912 911 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48) 912 + #define IRDMA_FEATURE_RSRC_MAX GENMASK_ULL(31, 0) 913 913 914 914 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32) 915 915 #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43) ··· 988 986 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(44, 32) 989 987 #define IRDMA_QUERY_FPM_MAX_PE_SDS_GEN3 GENMASK_ULL(47, 32) 990 988 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0) 989 + #define IRDMA_QUERY_FPM_MAX_IRD GENMASK_ULL(53, 50) 991 990 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32) 992 991 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32) 993 992 #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
+9 -16
drivers/infiniband/hw/irdma/type.h
··· 180 180 IRDMA_CQ_MAX_INCR = 3, 181 181 IRDMA_CEQ_MAX_INCR = 4, 182 182 IRDMA_SD_MAX_INCR = 5, 183 - IRDMA_QP_SMALL = 6, 184 - IRDMA_QP_MEDIUM = 7, 185 - IRDMA_QP_LARGE = 8, 186 - IRDMA_QP_XLARGE = 9, 187 - IRDMA_CQ_SMALL = 10, 188 - IRDMA_CQ_MEDIUM = 11, 189 - IRDMA_CQ_LARGE = 12, 190 - IRDMA_CQ_XLARGE = 13, 191 - IRDMA_CEQ_SMALL = 14, 192 - IRDMA_CEQ_MEDIUM = 15, 193 - IRDMA_CEQ_LARGE = 16, 194 - IRDMA_CEQ_XLARGE = 17, 195 - IRDMA_SD_SMALL = 18, 196 - IRDMA_SD_MEDIUM = 19, 197 - IRDMA_SD_LARGE = 20, 198 - IRDMA_SD_XLARGE = 21, 183 + IRDMA_MR_MAX_INCR = 6, 184 + IRDMA_Q1_MAX_INCR = 7, 185 + IRDMA_AH_MAX_INCR = 8, 186 + IRDMA_SRQ_MAX_INCR = 9, 187 + IRDMA_TIMER_MAX_INCR = 10, 188 + IRDMA_XF_MAX_INCR = 11, 189 + IRDMA_RRF_MAX_INCR = 12, 190 + IRDMA_PBLE_MAX_INCR = 13, 199 191 IRDMA_OBJ_1 = 22, 200 192 IRDMA_OBJ_2 = 23, 201 193 IRDMA_ENDPT_TRK = 24, ··· 607 615 u32 max_ceqs; 608 616 u32 max_sds; 609 617 u32 loc_mem_pages; 618 + u8 ird; 610 619 u32 xf_block_size; 611 620 u32 q1_block_size; 612 621 u32 ht_multiplier;