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riscv: add Zicfiss / Zicfilp extension CSR and bit definitions

The Zicfiss and Zicfilp extensions are enabled via b3 and b2 in
*envcfg CSRs. menvcfg controls enabling for S/HS mode. henvcfg
controls enabling for VS. senvcfg controls enabling for U/VU mode.

The Zicfilp extension extends *status CSRs to hold an 'expected
landing pad' bit. A trap or interrupt can occur between an indirect
jmp/call and target instruction. The 'expected landing pad' bit from
the CPU is recorded into the xstatus CSR so that when the supervisor
performs xret, the 'expected landing pad' state of the CPU can be
restored.

Zicfiss adds one new CSR, CSR_SSP, which contains the current shadow
stack pointer.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6
Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com>
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-4-b55691eacf4f@rivosinc.com
[pjw@kernel.org: grouped CSR_SSP macro with the other CSR macros; clarified patch description]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

authored by

Deepak Gupta and committed by
Paul Walmsley 41a2452c df117085

+14
+14
arch/riscv/include/asm/csr.h
··· 18 18 #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19 19 #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 20 21 + /* zicfilp landing pad status bit */ 22 + #define SR_SPELP _AC(0x00800000, UL) 23 + #define SR_MPELP _AC(0x020000000000, UL) 24 + #ifdef CONFIG_RISCV_M_MODE 25 + #define SR_ELP SR_MPELP 26 + #else 27 + #define SR_ELP SR_SPELP 28 + #endif 29 + 21 30 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22 31 #define SR_FS_OFF _AC(0x00000000, UL) 23 32 #define SR_FS_INITIAL _AC(0x00002000, UL) ··· 221 212 #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) 222 213 #define ENVCFG_CBZE (_AC(1, UL) << 7) 223 214 #define ENVCFG_CBCFE (_AC(1, UL) << 6) 215 + #define ENVCFG_LPE (_AC(1, UL) << 2) 216 + #define ENVCFG_SSE (_AC(1, UL) << 3) 224 217 #define ENVCFG_CBIE_SHIFT 4 225 218 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 226 219 #define ENVCFG_CBIE_ILL _AC(0x0, UL) ··· 331 320 332 321 #define CSR_STIMECMP 0x14D 333 322 #define CSR_STIMECMPH 0x15D 323 + 324 + /* zicfiss user mode csr. CSR_SSP holds current shadow stack pointer */ 325 + #define CSR_SSP 0x011 334 326 335 327 /* xtheadvector symbolic CSR names */ 336 328 #define CSR_VXSAT 0x9