Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Two clk driver fixes
- Use devm_kasprintf() to avoid overflows when forming clk names in
the Microchip PolarFire driver
- Fix the pretty broken Ingenic JZ4760 M/N/OD calculation to actually
work and find proper divisors"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: ingenic: jz4760: Update M/N/OD calculation algorithm
clk: microchip: mpfs-ccc: Use devm_kasprintf() for allocating formatted strings
+12
-16
+8
-10
drivers/clk/ingenic/jz4760-cgu.c
+8
-10
drivers/clk/ingenic/jz4760-cgu.c
···
58
58
unsigned long rate, unsigned long parent_rate,
59
59
unsigned int *pm, unsigned int *pn, unsigned int *pod)
60
60
{
61
-
unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 2;
61
+
unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1;
62
62
63
63
/* The frequency after the N divider must be between 1 and 50 MHz. */
64
64
n = parent_rate / (1 * MHZ);
···
66
66
/* The N divider must be >= 2. */
67
67
n = clamp_val(n, 2, 1 << pll_info->n_bits);
68
68
69
-
for (;; n >>= 1) {
70
-
od = (unsigned int)-1;
69
+
rate /= MHZ;
70
+
parent_rate /= MHZ;
71
71
72
-
do {
73
-
m = (rate / MHZ) * (1 << ++od) * n / (parent_rate / MHZ);
74
-
} while ((m > m_max || m & 1) && (od < 4));
75
-
76
-
if (od < 4 && m >= 4 && m <= m_max)
77
-
break;
72
+
for (m = m_max; m >= m_max && n >= 2; n--) {
73
+
m = rate * n / parent_rate;
74
+
od = m & 1;
75
+
m <<= od;
78
76
}
79
77
80
78
*pm = m;
81
-
*pn = n;
79
+
*pn = n + 1;
82
80
*pod = 1 << od;
83
81
}
84
82
+4
-6
drivers/clk/microchip/clk-mpfs-ccc.c
+4
-6
drivers/clk/microchip/clk-mpfs-ccc.c
···
164
164
165
165
for (unsigned int i = 0; i < num_clks; i++) {
166
166
struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
167
-
char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
167
+
char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i);
168
168
169
169
if (!name)
170
170
return -ENOMEM;
171
171
172
-
snprintf(name, 23, "%s_out%u", parent->name, i);
173
172
out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
174
173
out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
175
174
out_hw->reg_offset;
···
200
201
201
202
for (unsigned int i = 0; i < num_clks; i++) {
202
203
struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
203
-
char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
204
204
205
-
if (!name)
205
+
pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u",
206
+
strchrnul(dev->of_node->full_name, '@'), i);
207
+
if (!pll_hw->name)
206
208
return -ENOMEM;
207
209
208
210
pll_hw->base = data->pll_base[i];
209
-
snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
210
-
pll_hw->name = (const char *)name;
211
211
pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
212
212
pll_hw->parents,
213
213
&mpfs_ccc_pll_ops, 0);